Data transmission method, communication device and storage medium

Abstract

The invention provides a data transmission method, communication equipment and a storage medium. The data transmission method applied to first communication equipment comprises the following steps: acquiring a first bit sequence; performing convolutional coding on the first bit sequence to obtain a second bit sequence; performing repeated operation on the second bit sequence to obtain a third bit sequence; and transmitting the third bit sequence to a second communication device.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a data transmission method, communication device, and storage medium. Background Technology

[0002] In passive Internet of Things (IoT) technology, the complexity of the corresponding tag devices is very low due to the limited energy harvested. Existing passive tag devices do not employ channel coding technology, resulting in very small amounts of data that need to be transmitted and short transmission distances, hindering large-scale deployment.

[0003] In the future passive IoT, tags can transmit signals via energy reflection, resulting in very weak energy output. Therefore, it's crucial to ensure minimal energy consumption for these tags. However, to guarantee accurate and reliable reception of the signals, forward error correction coding is necessary; furthermore, to ensure receiver sensitivity, the coded data needs to be repeatedly transmitted. This added redundancy and repetition in information transmission necessitates an extremely low bit rate to ensure reliable transmission. Summary of the Invention

[0004] In view of this, embodiments of this application provide a data transmission method, communication device, and storage medium, which achieve extremely simplified transmission for tag devices while ensuring transmission reliability.

[0005] This application provides a data transmission method applied to a first communication device, including:

[0006] Obtain the first bit sequence;

[0007] The first bit sequence is convolutionally encoded to obtain the second bit sequence;

[0008] Repeat the operation on the second bit sequence to obtain the third bit sequence;

[0009] The third bit sequence is transmitted to the second communication device.

[0010] This application provides a data transmission method applied to a first communication device, including:

[0011] Obtain the first bit sequence;

[0012] The first bit sequence is convolutionally encoded to obtain the second bit sequence;

[0013] The second bit sequence is line-coded to obtain the fourth bit sequence;

[0014] The fourth bit sequence is transmitted to the second communication device.

[0015] This application provides a data transmission method applied to a first communication device, including:

[0016] Obtain the first bit sequence;

[0017] The first bit sequence is convolutionally encoded to obtain the second bit sequence;

[0018] Repeat the operation on the second bit sequence to obtain the third bit sequence;

[0019] The third bit sequence is line-coded to obtain the fifth bit sequence;

[0020] The fifth bit sequence is transmitted to the second communication device.

[0021] This application provides a data transmission method applied to a first communication device, including:

[0022] Obtain the first bit sequence;

[0023] The first bit sequence is convolutionally encoded to obtain the second bit sequence;

[0024] The second bit sequence is line-coded to obtain the fourth bit sequence;

[0025] Repeat the operation on the fourth bit sequence to obtain the third bit sequence;

[0026] The third bit sequence is transmitted to the second communication device.

[0027] This application provides a data transmission method applied to a second communication device, including:

[0028] Receive the third bit sequence sent by the first communication device;

[0029] The third bit sequence is de-repeated to obtain the second bit sequence;

[0030] The second bit sequence is convolutionally decoded to obtain the first bit sequence.

[0031] This application provides a data transmission method applied to a second communication device, including:

[0032] Receive the sixth bit sequence sent by the first communication device;

[0033] The sixth bit sequence is decoded to obtain the second bit sequence;

[0034] The second bit sequence is convolutionally decoded to obtain the first bit sequence.

[0035] This application provides a data transmission method applied to a second communication device, including:

[0036] Receive the fifth bit sequence sent by the first communication device;

[0037] The fifth bit sequence is decoded to obtain the third bit sequence;

[0038] The third bit sequence is de-repeated to obtain the second bit sequence;

[0039] The second bit sequence is convolutionally decoded to obtain the first bit sequence.

[0040] This application provides a data transmission method applied to a second communication device, including:

[0041] Receive the third bit sequence sent by the first communication device;

[0042] Perform a de-repetition operation on the third bit sequence to obtain the fourth bit sequence;

[0043] The fourth bit sequence is decoded to obtain the second bit sequence;

[0044] The second bit sequence is convolutionally decoded to obtain the first bit sequence.

[0045] This application provides a data transmission apparatus, applied to a first communication device, comprising:

[0046] The acquisition module is configured to acquire the first bit sequence;

[0047] A convolutional encoder is configured to perform convolutional encoding on the first bit sequence to obtain a second bit sequence; an interpolator is configured to perform a repeated operation on the second bit sequence to obtain a third bit sequence.

[0048] A transmitter configured to transmit the third bit sequence to a second communication device.

[0049] This application provides a data transmission apparatus, applied to a first communication device, comprising:

[0050] The acquisition module is configured to acquire the first bit sequence;

[0051] A convolutional encoder is configured to perform convolutional encoding on the first bit sequence to obtain a second bit sequence; a line encoder is configured to perform line encoding on the second bit sequence to obtain a fourth bit sequence; and a transmitter is configured to transmit the fourth bit sequence to a second communication device.

[0052] This application provides a data transmission apparatus, applied to a second communication device, comprising:

[0053] A receiver configured to receive a third bit sequence transmitted by a first communication device;

[0054] A restorer, configured to perform a deduplication operation on the third bit sequence to obtain a second bit sequence; a convolutional decoder, configured to perform convolutional decoding on the second bit sequence to obtain a first bit sequence. This application embodiment provides a data transmission apparatus, applied to a second communication device, comprising:

[0055] The receiver is configured to receive the fourth bit sequence transmitted by the first communication device;

[0056] A line decoder is configured to perform line decoding on the fourth bit sequence to obtain a second bit sequence; a convolutional decoder is configured to perform convolutional decoding on the second bit sequence to obtain a first bit sequence. This application provides a communication device, including: a memory and one or more processors; the memory is configured to store one or more programs;

[0057] When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any of the above embodiments.

[0058] This application provides a storage medium storing a computer program, which, when executed by a processor, implements the methods described in any of the above embodiments. Attached Figure Description

[0059] Figure 1 This is a structural block diagram of a wireless communication system provided in an embodiment of this application;

[0060] Figure 2 This is a block diagram illustrating an implementation of forward error correction coding provided in an embodiment of this application;

[0061] Figure 3 This is a flowchart of a data transmission method provided in an embodiment of this application;

[0062] Figure 4 This is a flowchart of another data transmission method provided in an embodiment of this application;

[0063] Figure 5 This is a schematic diagram of a data processing and transmission process provided in an embodiment of this application;

[0064] Figure 6 This is a schematic diagram of another data processing and transmission process provided in an embodiment of this application;

[0065] Figure 7 This is a schematic diagram of another data processing and transmission process provided in the embodiments of this application;

[0066] Figure 8 This is a schematic diagram illustrating an implementation of convolutional coding provided in an embodiment of this application;

[0067] Figure 9 This is a structural block diagram of a data transmission device provided in an embodiment of this application;

[0068] Figure 10 This is a structural block diagram of another data transmission device provided in the embodiments of this application;

[0069] Figure 11 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0070] The embodiments of this application will be described below with reference to the accompanying drawings. The examples given are for illustrative purposes only and are not intended to limit the scope of this application.

[0071] In digital communication systems, the transmitting end performs channel coding on the original information bit sequence (also referred to as the original bit sequence) to obtain the coded bit sequence. Then, the coded bit sequence is mapped into constellation modulation symbols, and finally, the obtained constellation modulation symbols are transmitted. In the channel, factors such as multipath propagation, motion, noise, and interference can all cause data transmission distortion. Channel coding refers to Forward Error Correction (FEC) coding, where FEC adds redundant information to the information bit sequence. The receiving end can reliably recover the original information bit sequence based on the corresponding FEC coding principle.

[0072] Convolutional coding is a potential minimalist label error correction coding scheme. However, traditional convolutional coding schemes add modules such as sub-block interleaving, bit collection, and bit selection to reduce performance loss caused by burst interference, which is insufficient to ensure minimal label implementation and reliable transmission. For example, in fourth-generation mobile communication, convolutional coding is used as the forward error correction coding scheme for the control channel. Its convolutional coding constraint length is 7, and it is implemented using 3 component codes. The bit sequence output by each component code is sub-block interleaved, and the interleaved bit sequences are collected sequentially into a circular buffer. Finally, the output bit sequence of the corresponding length is obtained through a bit selection method.

[0073] While interleaving can disperse the coded bits within the same grid in convolutional coding, improving its resistance to channel abrupt fading and interference, for passive IoT tags, minimizing device simplicity and energy consumption is paramount. Therefore, the sub-block interleaving, bit collection, and bit selection operations performed in convolutional coding schemes inevitably increase hardware complexity and energy consumption. These modules are highly detrimental to passive IoT tags.

[0074] Furthermore, to increase the coverage of tag devices, extremely low coding rates are required, such as below 1 / 6 or 1 / 8. This necessitates repeating the codewords output by convolutional coding. In traditional convolutional coding, due to operations like sub-block interleaving, bit collection, and bit selection, repetition can only be performed at the code block level. This can be achieved in two ways: first, by using a buffer to hold the output codewords and then repeatedly sending them; second, by repeatedly encoding the input bit sequence. Both methods either increase complexity or energy consumption. This is particularly unfriendly to passive IoT tag devices.

[0075] In view of this, this application proposes a data processing method and transmits the processed sequence.

[0076] Networks that automate wireless communication, such as the Internet of Things (IoT), are examples of wireless communication networks. Devices communicating through IoT networks (e.g., machine-type communication (MTC) devices) can include various types of sensors, water meters, electricity meters, product tags, and item data tags, etc. In some examples, IoT devices have low battery power, allowing for applications with very low data throughput but requiring minimal energy consumption to communicate for extended periods without battery replacement. In other examples, IoT devices do not require battery storage; they transmit signals directly to a receiver (base station) via backscattering. The tag collects energy and backscatters the signal back to the receiver; in this case, the device can be a passive IoT device. This device may be used in licensed spectrum, for example, to send signals to mobile communication base stations (e.g., node B or G node B), such as accessing an existing cellular network where the base station receives the data and transmits it to the appropriate destination. The device can also communicate using unlicensed spectrum. In some examples, these IoT devices (or UEs) use impedance networks to transmit data, with different impedance network parameters indicating different data signals. In some examples, these IoT devices perform forward error correction coding on the data to be transmitted to improve the reliability of data transmission. For example, by performing forward error correction coding on the raw data to be transmitted, coverage can be increased or transmission energy can be reduced. The forward error correction coding can employ some very simple coding methods, such as convolutional coding, Hamming coding, polar coding, or LDPC coding.

[0077] The following description provides examples but does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be appropriately omitted, substituted, or added to the examples. For example, the described methods may be performed in a different order than that described, and various steps may be added, omitted, or combined. Furthermore, features described for some examples may be combined with other examples.

[0078] Figure 1 This is a structural block diagram of a wireless communication system provided in an embodiment of this application. Figure 1According to various aspects of this application, an example of a wireless communication system 100 using forward error correction coding in cellular Internet of Things (IoT) communication is shown. In this example, the wireless communication system 100 includes a base station 110, various types of UEs (e.g., UE 120, UE 130, and UE 140), and a core network 150. The various types of UEs can be IoT devices used for various information collection, then forward error correction coding of the data before sending the data to the base station; the base station 110 communicates with each UE and is connected to the core network 150; the core network 150 can provide access authorization, user authentication, Internet Protocol (IP) connectivity, tracking, and other access, routing, or mobility management functions. In some examples, the base station 110 may be referred to as a base transceiver, wireless base station, access point, wireless transceiver, Node B, evolved Node B (eNB), general purpose node (gNB), home node B, home evolved Node B, reader, or some other suitable term. The wireless communication system 100 may include different types of base stations (e.g., macro cell base stations and / or small cell base stations).

[0079] Various types of UEs (or IoT devices) can be distributed throughout the wireless communication system 100, and each IoT device (or UE) can be fixed or mobile. The various types of UEs may also include, or be referred to by those skilled in the art, as mobile stations, user stations, mobile units, user units, radio units, remote units, mobile devices, radio devices, wireless communication devices, remote devices, mobile user stations, access terminals, mobile terminals, wireless terminals, remote terminals, handheld devices, user agents, mobile clients, clients, passive tags, or some other suitable term. Furthermore, the various types of UEs can also be cellular phones, personal digital assistants (PDAs), wireless modems, wireless communication devices, handheld devices, tablet computers, laptop computers, cordless phones, or wireless local loop (WLL) stations, etc. The various types of UEs can communicate with various types of base stations and network equipment (including macro eNBs, small cell eNBs, relay base stations, etc.).

[0080] Examples of applications for IoT devices include smart metering, inventory monitoring, water level monitoring, temperature monitoring, equipment monitoring, medical monitoring, wildlife monitoring, weather and geographic event monitoring, fleet management and tracking, remote security sensing, physical access control, and transaction-based business billing. The wireless communication system 100 may also include an IoT system or be part of an IoT system.

[0081] Figure 2 This is a block diagram illustrating the implementation of forward error correction coding provided in an embodiment of this application. Figure 2According to various aspects of this application, a block diagram illustrating the use of forward error correction coding in an IoT device is shown. The IoT device 200 may include a data processing module 210 and / or a transmitter 220. The IoT device may also include a processor and a memory for processing data, such as storing necessary parameter data and information bit sequences, performing forward error correction coding on the input information bit sequences, and transmitting the encoded data sequentially. Each component in the device can communicate with each other. The transmitter 220 may include a single antenna, or it may include multiple antennas.

[0082] In one embodiment, Figure 3 This is a flowchart illustrating a data transmission method provided in an embodiment of this application. This embodiment is applied to the case of performing convolutional encoding on tag devices in a passive Internet of Things (IoT) system. This embodiment can be executed by a first communication device. Figure 3 As shown, this embodiment includes: S310-S340.

[0083] S310, Obtain the first bit sequence.

[0084] In one example, the first bit sequence can be either the sequence after adding cyclic redundancy check (CRC) bits to the transport block or the sequence without CRC bits. In one example, if the first bit sequence is the sequence after adding CRC bits to the transport block, then the original bit sequence needs to be CRC encoded. In another example, if the first bit sequence is the sequence without CRC bits, then there is no need to perform CRC encoding on the original bit sequence; that is, the original bit sequence can be directly used as the first bit sequence.

[0085] S320. Perform convolutional encoding on the first bit sequence to obtain the second bit sequence.

[0086] In one example, the second bit sequence can also be referred to as the encoded bit sequence. In one example, a convolutional encoder can be configured in the first communication device, and the first bit sequence can be input into the convolutional encoder to obtain the second bit sequence after convolutional encoding.

[0087] S330. Repeat the operation on the second bit sequence to obtain the third bit sequence.

[0088] In one example, the third bit sequence can also be referred to as the repeating bit sequence.

[0089] S340, Transmit the third bit sequence to the second communication device.

[0090] In one embodiment, the first communication device transmits the generated repeating bit sequence to the second communication device.

[0091] In one embodiment, obtaining the first bit sequence includes: performing cyclic redundancy check (CRC) encoding on the original bit sequence to obtain the first bit sequence. In one example, if the first bit sequence is a sequence after adding CRC bits to the transport block, then CRC encoding on the original bit sequence is necessary to obtain the first bit sequence.

[0092] In one embodiment, the initial state of the convolutional coding register is determined by the first m bits of the first bit sequence; where m is equal to the constraint length of the convolutional coding minus one. In one example, the constraint length of the convolutional coding refers to the number of input bits that the convolutional encoder needs to reference when generating each output bit. Generally, the size of the constraint length of the convolutional coding has a certain impact on the error correction capability and coding efficiency of the convolutional code. In one example, the initial state of the convolutional coding register refers to the bit values ​​stored in the register before starting convolutional coding. In one example, before starting convolutional coding, the first communication device can obtain the bit values ​​of the first m bits of the first bit sequence, and then use the bit values ​​of the first m bits as the initial state of the convolutional coding register. In one example, the minimum value of the constraint length of the convolutional coding can be 7.

[0093] In one embodiment, before performing convolutional encoding on the first bit sequence to obtain the second bit sequence, the data transmission method applied to the first communication device further includes: placing the first m bits of the first bit sequence at the end of the first bit sequence to obtain an adjusted first bit sequence. In one example, the first communication device places the first m bits of the first bit sequence at the end of the first bit sequence, so that after performing convolutional encoding using the adjusted first bit sequence, the final state in the convolutionally encoded register is the same as the initial state.

[0094] In one embodiment, the initial state of the convolutional coding register is determined by the last m bits of the first bit sequence; where m is equal to the constraint length of the convolutional coding minus one. In one example, before starting convolutional coding, the first communication device may obtain the bit values ​​of the last m bits of the first bit sequence and then use the bit values ​​of the last m bits as the initial state of the convolutional coding register.

[0095] In one embodiment, the initial state of the convolutional coding register is set to all zeros. In one example, the bit values ​​stored in the convolutional coding register may be all zeros before convolutional coding begins.

[0096] In one embodiment, before performing convolutional encoding on the first bit sequence to obtain the second bit sequence, the data transmission method applied to the first communication device further includes: adding m bits all equal to zero after the first bit sequence to obtain an adjusted first bit sequence. In one example, if the initial state of the convolutional encoding register is set to all zeros, the first communication device can add m bits all equal to zero after the first bit sequence to obtain the adjusted first bit sequence.

[0097] In one embodiment, convolutional encoding of a first bit sequence to obtain a second bit sequence includes: convolutional encoding of the i-th bit in the adjusted first bit sequence to obtain a second bit sequence of length n bits; where i is a non-negative integer less than K, K is the length of the first bit sequence, and n is an integer greater than 1. In one example, if the initial state of the convolutional encoding register is determined by the first m bits or the last m bits of the first bit sequence, the first communication device can convolutionally encode the i-th bit in the adjusted first bit sequence to obtain a second bit sequence of length n bits, where i is a non-negative integer less than the length of the first bit sequence.

[0098] In one embodiment, convolutional encoding of a first bit sequence to obtain a second bit sequence includes: convolutional encoding of the i-th bit in the adjusted first bit sequence to obtain a second bit sequence of length n bits; where i is a non-negative integer less than the sum of K and m, K is the length of the first bit sequence, n is an integer greater than 1, and m is equal to the constraint length of the convolutional encoding minus one. In one example, if the initial state of the convolutional encoding register is determined by the first m bits or the last m bits of the first bit sequence, the first communication device can convolutionally encode the i-th bit in the adjusted first bit sequence to obtain a second bit sequence of length n bits, where i is a non-negative integer less than K+m.

[0099] In one embodiment, repeating the second bit sequence to obtain a third bit sequence includes: repeating the second bit sequence q times to obtain the third bit sequence; where q is an integer greater than 1. In one example, repeating the second bit sequence q times means repeating each bit in the second bit sequence q times to obtain the third bit sequence.

[0100] In one embodiment, the second bit sequence is repeated q times to obtain the third bit sequence, including:

[0101] Repeat each bit in the second bit sequence q times to obtain the third bit sequence; where the third bit sequence contains n*q bits; or,

[0102] Repeat all bits in the second bit sequence as a whole q times to obtain the third bit sequence. In one example, the first bit of the second bit sequence can be repeated q times, then the second bit q times, then the third bit q times, and so on, until the last bit of the second bit sequence is repeated q times. In another example, all bits in the second bit sequence can be directly repeated as a whole q times.

[0103] In one embodiment, before repeating the operation on the second bit sequence to obtain the third bit sequence, the data transmission method applied to the first communication device further includes: performing line coding on the second bit sequence to obtain a fourth bit sequence. Line coding can transform the signal output from a source or encoder into a digital signal suitable for channel transmission. In digital communication, line coding can optimize signal transmission in various ways, improving the overall performance and reliability of the communication system. In high-speed or long-distance transmission, line coding can help the receiving end better synchronize the signal with the transmitting end. In one example, the fourth bit sequence can also be referred to as the line-coded sequence. The first communication device can perform line coding on the second bit sequence to obtain the fourth bit sequence, and then repeat the operation on the line-coded fourth bit sequence to obtain the third bit sequence.

[0104] In one embodiment, repeating the operation on the second bit sequence to obtain the third bit sequence includes:

[0105] Repeat each bit in the fourth bit sequence q times to obtain the third bit sequence; or,

[0106] Repeating all bits in the fourth bit sequence as a whole q times yields the third bit sequence, which contains n*q bits. In one example, the first bit of the line-coded fourth bit sequence can be repeated q times, then the second bit q times, then the third bit q times, and so on, until the last bit of the line-coded fourth bit sequence is repeated q times. In another example, all bits in the line-coded fourth bit sequence can be directly repeated q times as a whole.

[0107] In one embodiment, after repeating the second bit sequence to obtain the third bit sequence, the data transmission method applied to the first communication device further includes: performing line encoding on the third bit sequence to obtain a fifth bit sequence. In one example, the first communication device may sequentially perform convolutional encoding and repetition operations on the first bit sequence to obtain the third bit sequence, and then perform line encoding on the third bit sequence to obtain the fifth bit sequence. In one example, the first communication device performs line encoding on the second bit sequence, which is a simpler encoding process than performing line encoding on the third bit sequence.

[0108] In one embodiment, transmitting the third bit sequence to the second communication device includes transmitting the fifth bit sequence to the second communication device. The first communication device performs line encoding on the third bit sequence to obtain the fifth bit sequence, and correspondingly, the first communication device directly transmits the fifth bit sequence to the second communication device.

[0109] In one embodiment, the line coding includes at least one of the following: dual-phase space FM0 coding; Miller coding; Manchester coding; pulse interval coding; mBnB coding.

[0110] In one embodiment, the value of q is determined by at least one of the following parameters: the length of the second bit sequence; the constraint length of the convolutional coding; the length of the first bit sequence; the code rate; and the number of CRC check bits.

[0111] In one embodiment, the value of q includes one of the following: 2, 3, 4, 5, 6, 7, 8, 12, 16, 24, 32, 48 and 64.

[0112] In one embodiment, the value of n includes one of the following: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 and 12.

[0113] In one embodiment, the constraint length of the convolutional coding includes one of the following values: 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11.

[0114] In one embodiment, Figure 4 This is a flowchart of another data transmission method provided in an embodiment of this application. This embodiment is applied to the case of receiving and processing data from tag devices in a passive Internet of Things (IoT) system. This embodiment can be executed by a second communication device. Figure 4 As shown, this embodiment includes:

[0115] S410: Receive the third bit sequence sent by the first communication device.

[0116] In one example, during the transmission of the third bit sequence from the first communication device to the second communication device, noise or interference may occur, causing distortion of the third bit sequence received by the second communication device. In this solution, the second communication device can receive the noisy third bit sequence.

[0117] S420. Perform a de-repetition operation on the third bit sequence to obtain the second bit sequence.

[0118] The process by which the second communication device de-repeates the third bit sequence can be understood as restoring the situation where the same bit is repeated multiple times in the third bit sequence to a state where it is retained only once. For example, this can be achieved by accumulating the repeated signals of the same bit.

[0119] S430. Perform convolution decoding on the second bit sequence to obtain the first bit sequence.

[0120] In one example, a convolutional decoder can be configured in a second communication device, and the second bit sequence can be input into the convolutional decoder to recover the first bit sequence.

[0121] In one embodiment, this is applied to the case of receiving and processing data from a tag device in a passive Internet of Things (IoT) system. This embodiment can be performed by a second communication device. This embodiment includes:

[0122] 1. Receive the fourth bit sequence sent by the first communication device.

[0123] In one example, during the transmission of the fourth bit sequence from the first communication device to the second communication device, noise or interference may occur, causing distortion of the fourth bit sequence received by the second communication device. In this solution, the second communication device can receive the noisy fourth bit sequence.

[0124] Second, the fourth bit sequence is decoded using line encoding to obtain the data sequence corresponding to the second bit sequence.

[0125] The process of the second communication device decoding the noisy fourth bit sequence using line coding can be understood as using the line coding decoding method to perform coding and obtain the data sequence corresponding to the second bit sequence.

[0126] Third, perform convolution decoding on the data sequence corresponding to the second bit sequence to obtain the first bit sequence.

[0127] In one example, a convolutional decoder can be configured in a second communication device, and the data sequence corresponding to the second bit sequence can be input into the convolutional decoder to recover the first bit sequence.

[0128] In one embodiment, this is applied to the case of receiving and processing data from a tag device in a passive Internet of Things (IoT) system. This embodiment can be performed by a second communication device. This embodiment includes:

[0129] 1. Receive the data sequence of the fifth bit sequence sent by the first communication device.

[0130] Second, the data sequence of the fifth bit sequence is decoded by line encoding to obtain the data sequence of the corresponding third bit sequence.

[0131] Third, perform a deduplication operation on the data sequence corresponding to the third bit sequence to obtain the data sequence corresponding to the second bit sequence.

[0132] Fourth, perform convolution decoding on the data sequence corresponding to the second bit sequence to obtain the corresponding first bit sequence, i.e., the information bit sequence.

[0133] In one embodiment, this is applied to the case of receiving and processing data from a tag device in a passive Internet of Things (IoT) system. This embodiment can be performed by a second communication device. This embodiment includes:

[0134] 1. Receive the data sequence of the third bit sequence sent by the first communication device.

[0135] Second, perform a deduplication operation on the data sequence of the third bit sequence to obtain the data sequence of the corresponding fourth bit sequence.

[0136] Third, perform line decoding on the data sequence corresponding to the fourth bit sequence to obtain the data sequence corresponding to the second bit sequence.

[0137] Fourth, perform convolution decoding on the data sequence corresponding to the second bit sequence to obtain the corresponding first bit sequence, i.e., the information bit sequence.

[0138] In the following example, taking the first communication device as the first transmission node and the second communication device as the second transmission node, the data processing and transmission process is explained. Also, in the following example, the first bit sequence is the information bit sequence, the second bit sequence is the encoded bit sequence, the third bit sequence is the repeated sequence, and the fourth and fifth bit sequences are both line-coded sequences. It should be noted that the fourth bit sequence is obtained by performing convolutional coding and line coding on the first bit sequence; the fifth bit sequence is obtained by sequentially performing convolutional coding, repetition operations, and line coding on the first bit sequence.

[0139] Example 1

[0140] Figure 5 This is a schematic diagram of a data processing and transmission process provided in an embodiment of this application. This embodiment is applied to the first transmission node. Figure 5As shown, this example includes the following steps:

[0141] S510, Obtain the information bit sequence.

[0142] S520. Perform convolutional encoding on the information bit sequence to obtain the encoded bit sequence.

[0143] S530. Repeat the encoded bit sequence q times to obtain the repeated sequence, where q is an integer greater than 1.

[0144] S540, Send the repeated sequence to the second transmission node.

[0145] In one possible implementation, the initial state of the register for convolutional coding is determined by the first m bits of the information bit sequence, where m is equal to the constraint length of the convolutional coding minus 1.

[0146] In one possible implementation, convolutional encoding of the information bit sequence includes: placing the first m bits of the information bit sequence at the end of the information bit sequence; and then performing convolutional encoding as follows: performing convolutional encoding on the i-th bit of the information bit sequence to obtain an encoded bit sequence [c0, c1, c2, ..., c] of length n bits. n-1 In the first m bits of the information bit sequence, i is a non-negative integer less than K, n is an integer greater than 1, and K is the length of the information bit sequence. Using the first m bits of the information bit sequence to initialize the initial state of the convolutional encoding register allows the UE to sequentially read data at the corresponding address positions and perform convolutional encoding, resulting in a simple and smooth operation. Especially when the information bit sequence contains CRC check bits, the original bits can be read sequentially, CRC check and convolutional encoding can be performed separately, and the convolutional encoding output can be sent out, thus eliminating the need for buffering and making the hardware extremely simple.

[0147] In one possible implementation, the initial state of the convolutional coding register is determined by the last m bits of the information bit sequence, where m is equal to the constraint length of the convolutional coding minus 1. In another possible implementation, convolutional coding of the information bit sequence includes: performing convolutional coding on the i-th bit of the information bit sequence to obtain an encoded bit sequence of length n bits [c0, c1, c2, ..., c...]. n-1 ], i is a non-negative integer less than K, n is an integer greater than 1, K is the length of the information bit sequence, and K is an integer greater than 0.

[0148] In one possible implementation, the initial state of the convolutional coding register is set to all zeros. In another possible implementation, convolutional coding of the information bit sequence includes: appending m bits all equal to zeros to the end of the information bit sequence; then performing convolutional coding as follows: performing convolutional coding on the i-th bit of the information bit sequence to obtain an encoded bit sequence of length n bits [c0, c1, c2, ..., c...]. n-1 ], i is a non-negative integer less than K+m, n is an integer greater than 1, K is the length of the information bit sequence, and K is an integer greater than 0.

[0149] In one possible implementation, the initial state of the convolutional coding register is determined by the number of CRC check bits. For example, when the number of CRC check bits in the information bit sequence is greater than 0, the initial state of the convolutional coding register is determined by the first m bits of the information bit sequence; when the number of CRC check bits in the information bit sequence is equal to 0, the initial state of the convolutional coding register is determined by the last m bits of the information bit sequence.

[0150] In one possible implementation, the encoded bit sequence is repeated q times to obtain a repeated sequence, including one of the following methods:

[0151] Method 1: Repeat each bit of the encoded bit sequence q times to obtain a repeated sequence of length n×q bits, which is {[c0, c0, ..., c0], [c1, c1, ..., c1], ..., [c n-1 c n-1 ... c n-1 ]};

[0152] Method 2: Repeat the encoded bit sequence q times to obtain a repeated sequence of length n×q bits, which is {[c0, c1, c2, ..., c...}. n-1 [c0, c1, c2, ..., c] n-1 ],...,[c0,c1,c2,...,c n-1 ]}.

[0153] Where n is equal to at least one of the following parameters: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12.

[0154] Where q is equal to at least one of the following parameters: 2, 3, 4, 5, 6, 7, 8, 12, 16, 24, 32, 48 and 64.

[0155] The constraint length of the convolutional coding includes at least one of the following: 2, 3, 4, 5, 7, 8, 9, 10, and 11.

[0156] The specific value of q is determined based on at least one of the following parameters: the length of the encoded bit sequence n, the constraint length v of the convolutional coding, the length of the information bit sequence K, the code rate, and the number of CRC check bits.

[0157] In one possible implementation, convolutional coding is performed using multiple component code generator polynomials. Convolutional coding can be implemented using multiple shift registers and multiple XOR gates, where every two adjacent shift registers are cascaded together. The output bit sequence of any component code in the convolutional coding is obtained by XORing the input bits with the state bits of a portion of the shift registers. Each component code generator polynomial corresponds to one component code output. For a convolutional code with n component code generator polynomials, an input of 1 bit yields an n-bit encoded bit sequence [c0, c1, c2, ..., cn]. n-1 ].

[0158] In a specific example, the encoded bit sequence is repeated q times to obtain a repeated sequence. The q-times repetition operation involves repeating each bit of the encoded bit sequence q times individually; that is, the encoded bit sequence [c0, c1, c2, ..., c...] is obtained by repeating the encoded bit sequence q times. n-1 After repetition, the resulting sequence of length n×q bits is {[c0, c0, ..., c0], [c1, c1, ..., c1], ..., [c n-1 c n-1 ... c n-1 This repetition method allows the receiver to quickly collect the soft information of each bit of the codeword corresponding to the convolutional coding, and then start calculating the branch metric, so the decoding delay at the receiver is very small.

[0159] In a specific example, the encoded bit sequence is repeated q times to obtain a repeated sequence. The operation of repeating q times means repeating the encoded bit sequence as a whole q times, that is, the encoded bit sequence [c0, c1, c2, ..., c...] n-1 After repetition, the resulting sequence of length n×q bits is {[c0, c1, c2, ..., c...}. n-1 [c0, c1, c2, ..., c] n-1 ],...,[c0,c1,c2,...,c n-1 This repetition method allows for a larger time diversity gain in data transmission, meaning that reception performance can be guaranteed even under sudden interference.

[0160] Example 2

[0161] Figure 6This is a schematic diagram of another data processing and transmission process provided in an embodiment of this application. This embodiment is applied to the first transmission node. This embodiment is based on the above... Figure 5 Based on this, line encoding is performed on the repeated bit sequence. For example... Figure 6 As shown, this example includes the following steps:

[0162] S610, Obtain the information bit sequence.

[0163] S620. Perform convolutional encoding on the information bit sequence to obtain the encoded bit sequence.

[0164] S630. Repeat the encoded bit sequence q times to obtain the repeated sequence, where q is an integer greater than 1.

[0165] S640. Perform line encoding on the repeated sequence to obtain the line-coded sequence.

[0166] S650, The line-encoded sequence is sent to the second transmission node.

[0167] In one possible implementation, the initial state of the register for convolutional coding is determined by the first m bits of the information bit sequence, where m is equal to the constraint length of the convolutional coding minus 1.

[0168] In one possible implementation, convolutional encoding of the information bit sequence includes: placing the first m bits of the information bit sequence at the end of the information bit sequence; and then performing convolutional encoding as follows: performing convolutional encoding on the i-th bit of the information bit sequence to obtain an encoded bit sequence [c0, c1, c2, ..., c] of length n bits. n-1 ], i is a non-negative integer less than K, n is an integer greater than 1, K is the length of the information bit sequence, and K is an integer greater than 0.

[0169] In one possible implementation, the initial state of the convolutional coding register is determined by the last m bits of the information bit sequence, where m is equal to the constraint length of the convolutional coding minus 1. In another possible implementation, convolutional coding of the information bit sequence includes: performing convolutional coding on the i-th bit of the information bit sequence to obtain an encoded bit sequence of length n bits [c0, c1, c2, ..., c...]. n-1 ], i is a non-negative integer less than K, n is an integer greater than 1, K is the length of the information bit sequence, and K is an integer greater than 0.

[0170] In one possible implementation, the initial state of the convolutional coding register is set to all zeros. In another possible implementation, convolutional coding of the information bit sequence includes: appending m bits all equal to zeros to the end of the information bit sequence; then performing convolutional coding as follows: performing convolutional coding on the i-th bit of the information bit sequence to obtain an encoded bit sequence of length n bits [c0, c1, c2, ..., c...]. n-1 ], i is a non-negative integer less than K+m, n is an integer greater than 1, K is the length of the information bit sequence, and K is an integer greater than 0.

[0171] In one possible implementation, the encoded bit sequence is repeated q times to obtain a repeated sequence, including one of the following methods:

[0172] Method 1: Repeat each bit of the encoded bit sequence q times to obtain a repeated sequence of length n×q bits, which is {[c0, c0, ..., c0], [c1, c1, ..., c1], ..., [c n-1 c n-1 ... c n-1 ]};

[0173] Method 2: Repeat the encoded bit sequence q times to obtain a repeated sequence of length n×q bits, which is {[c0, c1, c2, ..., c...}. n-1 [c0, c1, c2, ..., c] n-1 ],...,[c0,c1,c2,...,c n-1 ]}.

[0174] Line coding transforms signals from a source or encoder into digital signals suitable for channel transmission. In digital communication, line coding optimizes signal transmission in various ways, improving the overall performance and reliability of the communication system. Line coding helps the receiver better synchronize signals with the transmitter, especially in high-speed or long-distance transmission scenarios.

[0175] In one possible implementation, the above-mentioned line coding method may include at least one of the following: Bi-Phase Space Coding (FM0), Miller coding, Manchester coding, pulse interval encoding (PIE), and mBnB coding.

[0176] For ease of understanding, the line coding methods provided in the embodiments of this application will be described below.

[0177] FM0 encoding uses level changes within a bit window to represent the logical information of the corresponding bit, with a toggle occurring at the beginning of the bit window. For example, if a toggle occurs at the beginning of the bit window and remains unchanged throughout the window's duration, the corresponding bit's logical information is "1"; if a toggle occurs at the beginning of the bit window and then occurs in the middle of the window, the corresponding bit's logical information is "0". The bit window duration for FM0 encoding can be 1 μs, 8 μs, 16 μs, 25 μs, or 32 μs.

[0178] For example, assuming the input bit sequence is X = [1 0 0 0 1 1 1 0], then using FM0 encoding on the input bit sequence, the resulting line-coded sequence is Y = [0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1]. Here, '1' can be considered as a high-level bit, and '0' can be considered as a low-level bit.

[0179] Miller encoding uses level changes to represent the logical information of corresponding bits within a bit window duration. The encoding rules are as follows: a flip in the middle of the bit window represents a logical "1", and no flip in the middle represents a logical "0". Furthermore, the starting position of a bit window with logical "1" does not flip; in two consecutive bit windows with logical "0", the starting position of the second bit window flips, while the starting positions of the other bit windows do not flip.

[0180] For example, assuming the input bit sequence is X = [1 0 0 0 1 1 1 0], the line-coded sequence obtained by applying Miller encoding to the input bit sequence is Y = [1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 1].

[0181] Alternatively, Miller coding can be M-order subcarrier Miller coding, where each bit window duration of M-order subcarrier Miller coding contains M subcarrier periods. For example, M can be equal to at least one of the following: 1, 2, 4, 8, 16, 32, 48, 64, 96, and 128.

[0182] In the M-order subcarrier Miller coding, the parameter M can also be used to indicate the subcarrier frequency or data rate of the Miller coding, with the data rate reduced to 1 / M of the original. For example, if M equals 2, the data rate is reduced to 1 / M = 1 / 2 of the original. In the M-order subcarrier Miller coding, when M is greater than 1, it is actually the result of multiplying the coded data sequence output by the 1-order Miller coding with the subcarrier.

[0183] For example, if the input bit sequence is X = [1 0 0 0 1 1 1 0], then the first bit sequence is encoded using second-order subcarrier Miller coding, and the resulting line-coded sequence is Y = [1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 1 0 11 01 0 0 1 0 1 1 0 1 0 1 0 1 0].

[0184] Manchester encoding, also known as self-synchronizing code or phase encoding, uses signal changes to maintain synchronization between transmitting and receiving devices. Manchester encoding distinguishes between transmitted bits 0 and 1 based on changes in the transmitted level. For example, a high-to-low transition (output sequence [1 0]) represents bit 1, while a low-to-high transition (output sequence [0 1]) represents bit 0; or, a high-to-low transition (output sequence [1 0]) represents bit 0, and a low-to-high transition (output sequence [0 1]) represents bit 1. The code rate of this Manchester encoding is 1 / 2, meaning that for every 1 bit input, 2 bits can be encoded and output. For example, assuming the first bit sequence is [1 0 1 1], the second bit sequence obtained according to Manchester encoding is [1 0 0 1 1 0 1 0], or [0 1 10 0 1 0 1].

[0185] Furthermore, the code rate of this Manchester encoding can be equal to 1 / 4, meaning that for every 1 bit input, 4 bits can be encoded and output. For example, the output sequence [1 0 1 0] represents bit 1, while the output sequence [0 1 0 1] represents bit 0; or, the output sequence [1 0 1 0] represents bit 0, and the output sequence [0 1 0 1] represents bit 1.

[0186] Furthermore, the code rate of this Manchester encoding can be equal to 1 / 6, meaning that for every 1 bit input, 6 bits can be encoded as output. For example, the output sequence [1 0 1 0 1 0] represents bit 1, while the output sequence [0 1 0 1 0 1] represents bit 0; or, the output sequence [1 0 1 0 1 0] represents bit 0, and the output sequence [0 1 0 1 0 1] represents bit 1.

[0187] Furthermore, the code rate of this Manchester encoding can be equal to 1 / 8, meaning that for every 1 bit input, 8 bits can be encoded as output. For example, the output sequence [1 0 1 0 1 0 1 0] represents bit 1, while the output sequence [0 1 0 1 0 1 0 1] represents bit 0; or, the output sequence [1 0 1 0 1 0 1 0] represents bit 0, and the output sequence [0 1 0 1 0 1 0 1] represents bit 1.

[0188] Furthermore, the code rate of this Manchester encoding can be equal to 1 / z, meaning that for every 1 bit input, z bits can be encoded as output, where z is an even number greater than 0. Specifically, z can be equal to 8, 10, 12, 14, 16, 18, 20, 22, or 24. When the input bit is 1, the corresponding output sequence is [1 0] repeated z / 2 times; when the input bit is 0, the corresponding output sequence is [0 1] repeated z / 2 times; or, when the input bit is 0, the corresponding output sequence is [1 0] repeated z / 2 times; when the input bit is 1, the corresponding output sequence is [0 1] repeated z / 2 times.

[0189] PIE encoding, short for Pulse Interval Encoding, represents data by defining different time widths between the falling edges of pulses. Bit 1 is encoded as a short power-off pulse following a long full-power interval, while bit 0 is encoded as a short power-off pulse following a short full-power interval; bit 1 has a longer duration than bit 0. Generally, the full-power interval of pulse interval encoding can be used to charge or power the terminal. Therefore, using low-level and high-level pulses of equal duration to represent bit 0 ensures that the first communication node (e.g., an electronic tag) can receive at least 50% of the maximum power (even if the transmitted data contains long strings of zeros). If the full-power (high-level) time of bit 1 is three times longer than that of bit 0, then a randomly mixed binary data stream will provide approximately 67% of the peak power. For example, the output sequence corresponding to bit 1 is [1 1 1 0], and the output sequence corresponding to bit 0 is [1 0]. Assuming the first bit sequence is [1 0 1 1], the second bit sequence obtained according to PIE encoding is [1 1 1 0 1 0 1 1 1 0 1 1 1 0].

[0190] mBnB encoding involves dividing the input binary raw bitstream into groups of m binary codes, denoted as mB, called a codeword. Each codeword is then transformed into n binary codes, denoted as nB, and output in the same time slot. This encoding method transforms mB into nB, hence the name mBnB encoding, where m and n are positive integers, n > m, and typically n = m + 1. In specific examples, mBnB encoding can be 1B2B, 3B4B, 4B6B, 5B6B, 8B9B, 8B10B, or 17B18B.

[0191] Example 3

[0192] This embodiment is applied to the first transmission node to perform line encoding on the encoded bit sequence. This example includes the following steps:

[0193] Step 1: Obtain the information bit sequence.

[0194] Step 2: Perform convolutional encoding on the information bit sequence to obtain the encoded bit sequence.

[0195] Step 3: Perform line encoding on the encoded bit sequence to obtain the line-coded sequence.

[0196] Step 4: Send the line-encoded sequence to the second transmission node.

[0197] In one possible implementation, the information bit sequence is [b0, b1, b2, ..., bK-1], where K is the length of the information bit sequence and is a positive integer. Convolutional encoding is performed on the i-th bit of the information bit sequence to obtain an encoded bit sequence of length n bits [c0, c1, c2, ..., cn-1], where i is a non-negative integer less than K and n is a positive integer. Line encoding is then performed on the encoded bit sequence to obtain a line-coded sequence of length g bits [d0, d1, d2, ..., dg-1], where g is a positive integer.

[0198] In one possible implementation, the line coding method may include at least one of the following: Bi-Phase Space Coding (FM0), Miller coding, Manchester coding, pulse interval coding (PIE), and mBnB coding.

[0199] In one possible implementation, the line coding method is FM0 coding. If a flip occurs at the beginning of the bit window and remains unchanged during the duration of the bit window, the logical information of the corresponding bit is "1"; if a flip occurs at the beginning of the bit window and occurs in the middle of the bit window, the logical information of the corresponding bit is "0".

[0200] In one possible implementation, the line coding method is Miller coding. A flip at the middle position of a bit window represents logical information "1", and no flip at the middle position represents logical information "0". Furthermore, the starting position of a bit window with logical information "1" does not flip. In two consecutive bit windows with logical information "0", the starting position of the second bit window flips, while the starting positions of the other bit windows do not flip. In this case, Miller coding with subcarrier order M = 1 can be considered. In another possible implementation, the line coding method can be Miller coding of order M, where M is an integer greater than 0. For example, M can be equal to at least one of the following: 1, 2, 4, 6, 8, 10, 12, 16, 32, 48, 64, 96, and 128. M can be determined by downlink control signaling, or by the length of the information bit sequence, or by the code rate of convolutional coding, or by the number of CRC check bits, or by the modulation scheme. The modulation method may include at least one of the following: OOK modulation, BPSK modulation, and QPSK modulation. Using M-order Miller coding, by adjusting the M parameter, the spectral power of the transmitted data can be concentrated in a region with less interference, avoiding data collisions and interference between different user equipment, increasing the probability of successful data transmission, and thus ensuring the robustness of the communication system.

[0201] In one possible implementation, the line encoding method is Manchester encoding. In one example, a high-to-low transition (output sequence [1 0]) represents bit 1, and a low-to-high transition (output sequence

[01] ) represents bit 0. In another example, a high-to-low transition (output sequence [1 0]) represents bit 0, and a low-to-high transition (output sequence [0 1]) represents bit 1.

[0202] In one possible implementation, the line coding method is Manchester coding with a code rate of 1 / z, where z is an even number greater than 0. Specifically, z can be equal to 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, or 32. In one example, the output sequence corresponding to an input bit of 1 is [1 0] repeated z / 2 times, and the output sequence corresponding to an input bit of 0 is [0 1] repeated z / 2 times. In another example, the output sequence corresponding to an input bit of 0 is [1 0] repeated z / 2 times, and the output sequence corresponding to an input bit of 1 is [0 1] repeated z / 2 times. z can be determined by downlink control signaling, or by the length of the information bit sequence, or by the code rate of the convolutional coding, or by the number of CRC check bits, or by the modulation scheme. The modulation scheme can include at least one of the following: OOK modulation, BPSK modulation, or QPSK modulation. Using Manchester encoding can make data transmission more reliable, and it carries its own clock for transmitting signals, which facilitates synchronous reception at the receiving end, ensuring data synchronization and enhancing the robustness of communication.

[0203] Line coding transforms signals from a source or encoder into digital signals suitable for channel transmission. In digital communication, line coding optimizes signal transmission in various ways, improving the overall performance and reliability of the communication system. Line coding helps the receiver better synchronize signals with the transmitter, especially in high-speed or long-distance transmission scenarios.

[0204] Example 4

[0205] Figure 7 This is a schematic diagram of another data processing and transmission process provided in this application embodiment, which is applied to the first transmission node. This embodiment is based on the above... Figure 5 Based on this, line encoding is performed on the repeated bit sequence. For example... Figure 7 As shown, this example includes the following steps:

[0206] S710, Obtain the information bit sequence.

[0207] S720. Perform convolutional encoding on the information bit sequence to obtain the encoded bit sequence.

[0208] S730. Perform line encoding on the encoded bit sequence to obtain the line-coded sequence.

[0209] S740. Repeat the line-encoded sequence q times to obtain the repeated sequence, where q is an integer greater than 1.

[0210] S750, Send the repeated sequence to the second transmission node.

[0211] In one possible implementation, the initial state of the register for convolutional coding is determined by the first m bits of the information bit sequence, where m is equal to the constraint length of the convolutional coding minus 1.

[0212] In one possible implementation, convolutional encoding of the information bit sequence includes: placing the first m bits of the information bit sequence at the end of the information bit sequence; and then performing convolutional encoding as follows: performing convolutional encoding on the i-th bit of the information bit sequence to obtain an encoded bit sequence [c0, c1, c2, ..., c] of length n bits. n-1 ], i is a non-negative integer less than K, n is an integer greater than 1, K is the length of the information bit sequence, and K is an integer greater than 0.

[0213] In one possible implementation, the initial state of the convolutional coding register is determined by the last m bits of the information bit sequence, where m is equal to the constraint length of the convolutional coding minus 1. In another possible implementation, convolutional coding of the information bit sequence includes: performing convolutional coding on the i-th bit of the information bit sequence to obtain an encoded bit sequence of length n bits [c0, c1, c2, ..., c...]. n-1 ], i is a non-negative integer less than K, n is an integer greater than 1, K is the length of the information bit sequence, and K is an integer greater than 0.

[0214] In one possible implementation, the initial state of the convolutional coding register is set to all zeros. In another possible implementation, convolutional coding of the information bit sequence includes: appending m bits all equal to zeros to the end of the information bit sequence; then performing convolutional coding as follows: performing convolutional coding on the i-th bit of the information bit sequence to obtain an encoded bit sequence of length n bits [c0, c1, c2, ..., c...]. n-1 ], i is a non-negative integer less than K+m, n is an integer greater than 1, K is the length of the information bit sequence, and K is an integer greater than 0.

[0215] Among them, the encoded bit sequence [c0, c1, c2, ..., c n-1 After line coding, the resulting sequence is [d0, d1, d2, ..., d...]. g-1 ].

[0216] In one possible implementation, the line-encoded sequence [d0, d1, d2, ..., d...] is... g-1 The sequence can be obtained by repeating it q times, including one of the following methods:

[0217] Method 1: Repeat each bit of the line-encoded sequence q times to obtain a repeated sequence of length g×q bits, which is {[d0, d0, ..., d0], [d1, d1, ..., d1], ..., [d0, ..., ... g-1 d g-1 ... d g-1 ]};

[0218] Method 2: Repeat the encoded bit sequence q times to obtain a repeated sequence of length g×q bits, which is {[d0, d1, d2, ..., d...}. g-1 ]、[d0、d1、d2、...、d g-1 ],...,[d0,d1,d2,...,d g-1 ]}.

[0219] In one example, the line-encoded sequence [d0, d1, d2, ..., d... g-1 Repeating this process q times yields a repeating sequence, with each bit being repeated. The resulting repeating sequence is {[d0, d0, ..., d0], [d1, d1, ..., d1], ..., [d0, ..., ... g-1 d g-1 ... d g-1 ]}.

[0220] In one example, the line-encoded sequence [d0, d1, d2, ..., d... g-1 Repeat q times to obtain the repeated sequence. Repeat by block to obtain the repeated sequence as {[d0, d1, d2, ..., d...}. g-1 ]、[d0、d1、d2、...、d g-1 ],...,[d0,d1,d2,...,d g-1 ]}.

[0221] Example 5

[0222] In this example, the information bit sequence consists of K bits. The processing of the information bit sequence includes the following steps:

[0223] Step 1: Obtain the information bit sequence, which consists of K bits. In one example, the information bit sequence can be the sequence after adding cyclic redundancy check (CRC) bits to the transport block, or it can be a sequence without CRC bits. This information bit sequence is set as [a0, a1, a2, ..., a...]. K-1 ].

[0224] Step 2: Perform convolutional encoding on the information bit sequence to obtain the encoded bit sequence.

[0225] Figure 8This is a schematic diagram illustrating an implementation of convolutional coding provided in an embodiment of this application. For example... Figure 8 As shown, an example of convolutional coding is illustrated in accordance with various aspects of this disclosure. The constraint length of the convolutional coding is v = 7, in which case the number of shift registers required is 7 - 1 = 6 (i.e., m = 6), and the highest power of the component code generator polynomial is 6, including the following four component code generator polynomials (i.e., n = 4, the four component code generator polynomials correspond to the following octal values: 133, 171, 165, and 123):

[0226] g0(D)=1+D 2 +D 3 +D 5 +D 6 ;

[0227] g1(D) = 1 + D 1 +D 2 +D 3 +D 6 ;

[0228] g2(D)=1+D 1 +D 2 +D 4 +D 6 ;

[0229] g3(D) = 1 + D 2 +D 5 +D 6 ;

[0230] like Figure 8 The system includes six registers: s0, s1, s2, s3, s4, and s5. A total of 15 XOR gates are required. The 0th component code requires 4 XOR gates, the 1st component code requires 4 XOR gates, the 2nd component code requires 4 XOR gates, and the 3rd component code requires 3 XOR gates.

[0231] In this example, the information bit sequence [a0, a1, a2, ..., a] is first processed before convolutional coding. k-1 The first m bits (i.e., bits 0 to (m-1)) of the [] are placed in m registers of the convolutional encoding, i.e., s0 = a m-1 s1=a m-2 ... s m-1 = a0, where m = v-1. That is, the initial state of the register of the convolutional coding is determined by the first m bits of the information bit sequence, where m is equal to the constraint length of the convolutional coding minus 1. In this example, m equals 6.

[0232] Furthermore, the information bit sequence [a0, a1, a2, ..., a] is... K-1The first m bits of [b0, b1, b2, ..., bm] are placed at the end of the information bit sequence, thus obtaining the input information bit sequence as [b0, b1, b2, ..., bm]. w-1 ], that is, b i =a i+m i equals 0, 1, ..., wm-1; and b j =a j-k+m j equals wm, w-m+1, ..., w-1. That is, the input information bit sequence is [b0, b1, b2, ..., b...]. w-1 ] = [a m a m+1 a m+2 ... a K-1 a0, a1, ..., a m-1 Here, m can be considered as the number of registers in the convolutional coding, v is the constraint length of the convolutional coding, and m = v-1. w equals k. Then the input information bit sequence is [b0, b1, b2, ..., b...]. w-1 The input bits are fed into the convolutional coding process bit by bit. Each input bit corresponds to an output sequence of n encoded bits [c0, c1, c2, ..., c]. n-1 ], where n is an integer greater than 1. The input information bit sequence [b0, b1, b2, ..., b...] is... w-1 Bit by bit, the data enters the convolutional encoding. Therefore, the initial and final states of the convolutional encoding are both [s0 = a]. m-1 s1=a m-2 ... s m-1 =a0].

[0233] In another example, the initial values ​​of the m registers in the convolutional coding are s0 = a0, s1 = a1, ..., s m-1 =a m-1 And, the input information bit sequence [a0, a1, a2, ..., a...] K-1 The first m bits of [b0, b1, b2, ..., bm] are placed at the end of the information bit sequence, resulting in the input information bit sequence [b0, b1, b2, ..., bm]. w-1 ] = [a m a m+1 a m+2 ... a K-1 a m-1 [b0, b1, b2, ..., b0]. The input information bit sequence [b0, b1, b2, ..., b0] will be used. w-1 If each bit is fed into the convolutional encoding, then the initial and final states of the convolutional encoding are both [s0 = a0, s1 = a1, ..., s...]. m-1 =a m-1 ].

[0234] In another example, all m=6 registers of the convolutional encoding are initialized to 0 before encoding, and the input information bit sequence is [b0, b1, b2, ..., b...]. w-1 ], w = k + v - 1, where b i =a i i equals 0, 1, ..., k-1; b j =0, j equals k, k+1, ..., k+v-2. The input information bit sequence is [b0, b1, b2, ..., b...]. w-1 The input bits are fed into the convolutional coding process bit by bit. Each input bit corresponds to an output sequence of n encoded bits [c0, c1, c2, ..., c]. n-1 ], where n is an integer greater than 1.

[0235] In another example, before encoding, all m=6 registers of the convolutional encoding are initialized to be equal to the last m bits of the input information bit sequence, which is [b0, b1, b2, ..., b...]. w-1 ], w = k, where bi = ai, i equals 0, 1, ..., k-1. The input information bit sequence is [b0, b1, b2, ..., b...]. w-1 The input bits are fed into the convolutional coding process bit by bit. Each input bit corresponds to an output sequence of n encoded bits [c0, c1, c2, ..., c]. n-1 ], where n is an integer greater than 1.

[0236] Step 3: Repeat the encoded bit sequence q times to obtain a repeated sequence, where q is an integer greater than 1. Assume the repeated sequence is [d0, d1, d2, ..., d...]. v-1 ].

[0237] In one example, the encoded bit sequence [c0, c1, c2, ..., c...] n-1 The process is repeated q times to obtain the repeated sequence. The method for repeating q times is as follows: each bit of the encoded bit sequence is repeated q times to obtain a repeated sequence of length n×q bits, which is [d0, d1, d2, ..., d...]. v-1 ]={[c0,c0,...,c0],[c1,c1,...,c1],...,[c n-1 c n-1 ... c n-1 ]}, v equals n×q. In this case, the repetition method uses bit-by-bit repetition.

[0238] In another example, the encoded bit sequence [c0, c1, c2, ..., c...]n-1 The process is repeated q times to obtain the repeated sequence. The method for repeating q times is as follows: each bit of the encoded bit sequence is repeated q times to obtain a repeated sequence of length n×q bits, which is [d0, d1, d2, ..., d...]. v-1 ] = {[c0, c1, c2, ..., c n-1 [c0, c1, c2, ..., c] n-1 ],...,[c0,c1,c2,...,c n-1 ]}, v equals n×q. In this case, the repetition method uses block repetition.

[0239] Step 4: Send the repeated sequence to the second transmission node.

[0240] In one possible implementation, the number of component codes n in the convolutional coding can be equal to 2, then it can be implemented as follows: Figure 6 The first two component code generator polynomials g0(D) and g1(D) shown are used for convolutional coding. Alternatively, n can be equal to 3, in which case the following can be used: Figure 6 The first two component code generator polynomials g0(D), g1(D), and g2(D) shown are used for convolutional encoding.

[0241] In one possible implementation, the number of repetitions q can be equal to 2; or, the number of repetitions q can be equal to 3; or, the number of repetitions q can be equal to 4; or, the number of repetitions q can be equal to 5; or, the number of repetitions q can be equal to 6; or, the number of repetitions q can be equal to 8.

[0242] Example 6

[0243] The difference between Example 6 and Example 5 is that the repeated sequence is further line-coded to obtain the line-coded sequence, where the line coding adopts one of the following methods: FM0 coding, Miller coding, Manchester coding, pulse interval coding, and mBnB coding.

[0244] For example, this example includes the following steps:

[0245] Step 1: Obtain the information bit sequence;

[0246] Step 2: Perform convolutional encoding on the information bit sequence to obtain the encoded bit sequence;

[0247] Step 3: Repeat the encoded bit sequence q times to obtain the repeated sequence, where q is an integer greater than 1;

[0248] Step 4: Perform line encoding on the repeated sequence to obtain the line-coded sequence;

[0249] Step 5: Send the line-encoded sequence to the second transmission node.

[0250] Suppose that repeating the encoded bit sequence q times yields a repeated sequence [d0, d1, d2, ..., dn]. v-1 The line-coded sequence obtained by performing line coding on the repeated sequence is [e0, e1, e2, ..., e]. g-1 ] where g is an integer greater than v.

[0251] In a specific example, Manchester encoding is used for line coding. A high-to-low transition represents bit 1, and a low-to-high transition represents bit 0; or, a high-to-low transition represents bit 0, and a low-to-high transition represents bit 1, meaning the code rate of this Manchester encoding is 1 / 2. Therefore, the length g of the line-coded sequence obtained after line coding is equal to 2 × v. In one example, the code rate of this Manchester encoding can be 1 / 4. In this case, the output corresponding to an input bit of 0 is [0 1 0 1], and the output corresponding to an input bit of 1 is [1 0 1 0]; or, the output corresponding to an input bit of 1 is [0 1 0 1], and the output corresponding to an input bit of 0 is [1 0 1 0]. In one example, the Manchester encoding code rate can be 1 / 6. In this case, the output corresponding to an input bit of 0 is [0 1 0 101], and the output corresponding to an input bit of 1 is [1 0 1 0 1 0]; or, the output corresponding to an input bit of 1 is [0 10 1 0 1], and the output corresponding to an input bit of 0 is [1 0 1 0 1 0]. In another example, the Manchester encoding code rate can be 1 / 8. In this case, the output corresponding to an input bit of 0 is [0 1 0 1 0 1 0 1], and the output corresponding to an input bit of 1 is [1 0 1 0 1 0 1 0]; or, the output corresponding to an input bit of 1 is [0 1 0 1 0 1 0 1], and the output corresponding to an input bit of 0 is [1 0 1 0 1 0 1 0]. In one example, the code rate of this Manchester encoding can be 1 / z, where z is an even number greater than 0. Specifically, z can be equal to 8, 10, 12, 14, 16, 18, 20, 22, or 24. The output sequence corresponding to an input bit of 1 is [1 0] repeated z / 2 times, and the output sequence corresponding to an input bit of 0 is [0 1] repeated z / 2 times; or, the output sequence corresponding to an input bit of 0 is [1 0] repeated g / 2 times, and the output sequence corresponding to an input bit of 1 is [0 1] repeated z / 2 times.

[0252] In a specific example, the line encoding uses FM0 encoding. For instance, if a flip occurs at the beginning of the bit window and remains unchanged throughout the window's duration, the corresponding bit's logical information is "1"; if a flip occurs at the beginning of the bit window and then again in the middle, the corresponding bit's logical information is "0". Therefore, the length g of the line-encoded sequence is equal to 2 × v. If the FM0 encoding has a tail bit, the length g of the line-encoded sequence will be greater than 2 × v.

[0253] In a specific example, Miller encoding is used for line coding. For instance, a flip in the middle of a bit window represents logic "1", while no flip in the middle represents logic "0". The starting position of a bit window with logic "1" does not flip. In two consecutive bit windows with logic "0", the starting position of the second bit window flips, while the starting positions of the other bit windows do not flip. Therefore, the length g of the line-coded sequence obtained after line coding is equal to 2 × v. Alternatively, Miller encoding can be M-order subcarrier Miller encoding, where each bit window duration in M-order subcarrier Miller encoding contains M subcarrier periods. For M-order subcarrier Miller encoding, the length g of the line-coded sequence obtained after line coding is equal to 2 × v × M. If the Miller encoding has a tail bit, the length g of the line-coded sequence will be greater than 2 × v × M.

[0254] In a specific example, the line encoding uses mBnB encoding. For example, m equals 4, n equals 6; or m equals 2, n equals 4; or m equals 1, n equals 3; or m equals 2, n equals 5; or m equals 2, n equals 6; or m equals 3, n equals 6; or m equals 4, n equals 8; or m equals 5, n equals 10. Then, the length g of the line-encoded sequence obtained after line encoding is equal to v / m×n.

[0255] Example 7

[0256] The difference between Example 7 and Example 6 is that, after convolutionally encoding the information bit sequence to obtain the encoded bit sequence, the encoded bit sequence is then line-coded to obtain the line-coded sequence, and this line-coded sequence is repeated q times to obtain the repeated sequence. The line coding uses one of the following methods: FM0 coding, Miller coding, Manchester coding, pulse-interval coding, or mBnB coding.

[0257] For example, this example includes the following steps:

[0258] Step 1: Obtain the information bit sequence;

[0259] Step 2: Perform convolutional encoding on the information bit sequence to obtain the encoded bit sequence;

[0260] Step 3: Perform line encoding on the encoded bit sequence to obtain the line-coded sequence;

[0261] Step 4: Repeat the line-encoded sequence q times to obtain the repeated sequence, where q is an integer greater than 1;

[0262] Step 5: Send the repeated sequence to the second transmission node.

[0263] Among them, the encoded bit sequence [c0, c1, c2, ..., c n-1 After line coding, the resulting sequence is [d0, d1, d2, ..., d...]. g-1 In one example, the line-encoded sequence [d0, d1, d2, ..., d] g-1 The sequence is obtained by repeating the sequence q times. The following method is used: Each bit of the line-coded sequence is repeated q times to obtain a repeated sequence of length g×q bits, which is [e0, e1, e2, ..., e...]. h-1 ]={[d0, d0, ..., d0], [d1, d1, ..., d1], ..., [d g-1 d g-1 ... d g-1 ]}; where h equals g×q. By repeating bits in the sequence after line coding, the receiver can quickly collect the bits within the coding grid of the line code, thus enabling rapid decoding and facilitating line coding decoding and convolutional decoding. Furthermore, transmission is relatively simple, which is highly advantageous for passive tag-less user equipment.

[0264] In one example, the line-encoded sequence [d0, d1, d2, ..., d... g-1 The sequence is repeated q times to obtain a repeating sequence. The following method is used: the bit sequence after line encoding is repeated q times as a whole to obtain a repeating sequence of length g×q bits, which is [e0, e1, e2, ..., e...]. h-1 ] = {[d0, d1, d2, ..., d g-1 ]、[d0、d1、d2、...、d g-1 ],...,[d0,d1,d2,...,d g-1 ]}; where h equals g×q. By repeating bits in blocks in the sequence after line coding, the receiver can quickly collect the bits within the coding grid of the convolutional coding, facilitating both line coding and convolutional coding decoding. Furthermore, transmission is relatively simple, which is highly advantageous for passive tagless user equipment.

[0265] In one example, the line-encoded sequence [d0, d1, d2, ..., d... g-1 The sequence is repeated q times to obtain the repeated sequence. The following method is used: the bit sequence after line encoding is repeated q times in blocks of Y bits, resulting in a repeated sequence of length g×q bits, [e0, e1, e2, ..., e...]. h-1 ] = {[d0, d1, ..., d} Y-1 ]、[d0、d1、...、d Y-1 ]、...[d Y d Y+1 ... d 2Y-1 ]、[d Y d Y+1 ... d 2Y-1 [...}; where h equals g × q, and Y equals the number of bits output by the line coding, where Y is an integer greater than 1. In one example, Manchester coding with a code rate of 1 / z has Y equal to z; subcarrier Miller coding with an order of M has Y = 2 × M. By repeating the bits within the line-coded grid in the sequence after line coding, the receiver can quickly collect the bits within the line-coded grid, thus enabling rapid decoding and facilitating line coding decoding and convolutional decoding. Furthermore, transmission is relatively simple, which is highly advantageous for passive tag-based user equipment.

[0266] Example 8

[0267] Example 8 illustrates the process of performing CRC encoding on the original bit sequence to obtain the first bit sequence (i.e., the information bit sequence). For example, this example includes the following steps:

[0268] Step 1: Obtain the original bit sequence;

[0269] Step 2: Perform cyclic redundancy check (CRC) encoding on the original bit sequence to obtain the CRC-encoded bit sequence (i.e., the information bit sequence).

[0270] The Cyclic Redundancy Check (CRC) coding includes: performing operations on the original bit sequence based on generator polynomials to obtain a CRC check bit sequence; merging the original bit sequence and the CRC check bit sequence yields the CRC-encoded bit sequence (i.e., the information bit sequence). The CRC coding includes A generator polynomials, where the number of CRC check bits corresponding to the A generator polynomials are L0, L1, ..., L... A-1 , where L i <L 1+iLet i be an integer greater than 1, where i is equal to 0, 1, ..., A-2. A is an integer greater than 1, and i is greater than 0. A can be equal to 2, 3, 4, 5, or 6. The number of CRC check bits corresponds to the highest power in the CRC generator polynomial, i.e., the length of the CRC check bit sequence.

[0271] In one example, the A generator polynomials are nested, meaning that nested generator polynomials are those whose generator polynomials can be determined based on the generator polynomial of the longer CRC check bit sequence. For example, if the generator polynomial of the longer CRC check bit sequence (let's call it L1) is the first generator polynomial, and the generator polynomial of the shorter CRC check bit sequence (let's call it L0) is the second generator polynomial, then the second generator polynomial is equal to the remainder polynomial obtained by dividing the first generator polynomial by the first target polynomial. The first target polynomial is equal to a monomial of degree L0+1 (i.e., D). L0+1 Alternatively, the second generator polynomial is equal to the quotient polynomial obtained by dividing the first generator polynomial by the second objective polynomial, where the second objective polynomial is equal to the monomial of degree L1-L0 (i.e., D). L1-L0 ).

[0272] In one example, the Cyclic Redundancy Check (CRC) code includes A = 2 generator polynomials, and the CRC check bit sequence lengths L0 and L1 corresponding to A = 2 generator polynomials are {6, 16}, respectively. In a specific example, the generator polynomial with a CRC check bit sequence length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 10 +D 11 +D 12 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 13 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 10 +D 11 +D 13 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 9 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 10 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 9 +D 12 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D9 +D 13 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 12 +D 13 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 8 +D 9 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 8 +D 10 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 9 +D 11 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 13 +D 14 +D 15 +D 16Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 9 +D 11 +D 12 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 10 +D 11 +D 13 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 9 +D 12 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D7 +D 9 +D 12 +D 13 +D 14 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 8 +D 9 +D 10 +D 12 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 9 +D 10 +D 11 +D 12 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 12 +D 13 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 10 +D 11 +D 12 +D 13 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 9 +D 14 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 9 +D 11 +D 14 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 8 +D 9 +D 13 +D 14 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 9 +D 11 +D 13 +D 14 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 9 +D 10 +D12 +D 13 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 10 +D 11 +D 12 +D 14 +D 15 +D 16 Alternatively, the generator polynomial for the corresponding CRC check bit sequence with a length of 6 is: g(D) = 1 + D 5 +D 6 The corresponding generator polynomial for the CRC check bit sequence with a length of 16 is: g(D) = 1 + D 5 +D 6 +D 7 +D 8 +D 9 +D 10 +D 13 +D 14 +D 15 +D 16 .

[0273] In one example, the Cyclic Redundancy Check (CRC) code includes A = 2 generator polynomials, and the CRC check bit sequence lengths L0 and L1 corresponding to A = 2 generator polynomials are {6, 16}, respectively. That is, it includes CRC6 and CRC16. CRC6 corresponds to a CRC generator polynomial with a CRC check bit sequence length of 6, and CRC16 corresponds to a CRC generator polynomial with a CRC check bit sequence length of 16. In a specific example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 4 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 3 +D 4 +D 10 +D 15 +D16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 4 +D 5 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 2 +D 3 +D 6 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 4 +D 6 +D 7 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 2 +D 3 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 4 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 3 +D 5 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D5 +D 6 The CRC16 expression is: g(D) = 1 + D 5 +D 6 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 2 +D 7 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 3 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 3 +D 4 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 2 +D 5 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 6 +D 7 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6The CRC16 expression is: g(D) = 1 + D 5 +D 8 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 6 +D 8 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 3 +D 5 +D 6 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 3 +D 5 +D 7 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 3 +D 6 +D 7 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 2 +D 3 +D 4 +D 6 +D 7 +D 10 +D15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 3 +D 4 +D 5 +D 6 +D 7 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 4 +D 5 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 2 +D 3 +D 5 +D 6 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 3 +D 4 +D 5 +D 6 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 6 +D 7 +D 8 +D 10 +D 15 +D 16In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 3 +D 4 +D 6 +D 7 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 4 +D 5 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 3 +D 5 +D 7 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 3 +D 4 +D 6 +D 7 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D6 The CRC16 expression is: g(D) = 1 + D 4 +D 5 +D 6 +D 7 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 3 +D 8 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 2 +D 3 +D 4 +D 8 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 4 +D 5 +D 8 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 4 +D 6 +D 8 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 4 +D5 +D 7 +D 8 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 2 +D 6 +D 7 +D 8 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 3 +D 4 +D 5 +D 6 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 3 +D 4 +D 5 +D 6 +D 7 +D 8 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D 6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 4 +D 5 +D 6 +D 7 +D 9 +D 10 +D 15 +D 16 In another example, the generator polynomial of CRC6 is: g(D) = 1 + D 5 +D6 The CRC16 expression is: g(D) = 1 + D 1 +D 2 +D 3 +D 5 +D 7 +D 8 +D 9 +D 10 +D 15 +D 16 .

[0274] In one example, the Cyclic Redundancy Check (CRC) code includes A = 2 generator polynomials, and the CRC check bit sequence lengths L0 and L1 corresponding to A = 2 generator polynomials are {5, 16} respectively. The generator polynomial of CRC5 is g(D) = 1 + D. 3 +D5. For simplicity, CRC16 represents the CRC generator polynomial with a CRC check bit sequence length of 16. In one example, CRC16 is 1+D5. 3 +D 5 +D 10 +D 16 In one example, CRC16 is 1+D. 3 +D 5 +D 6 +D 8 +D 9 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 8 +D 10 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 10 +D 11 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 11 +D 12 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 10 +D 11 +D 12 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D7 +D 8 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 9 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 11 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 9 +D 11 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 12 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 9 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 10 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 9 +D 10 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 12 +D 13 +D14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 9 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 10 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 8 +D 9 +D 10 +D 11 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 8 +D 9 +D 10 +D 12 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 10 +D 11 +D 12 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 9 +D 10 +D 11 +D 12 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 8 +D 9 +D12 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 9 +D 10 +D 12 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 9 +D 11 +D 12 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 9 +D 11 +D 12 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 10 +D 11 +D 12 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 9 +D 10 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 9 +D 10 +D 12 +D 14 +D16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 8 +D 11 +D 12 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 9 +D 10 +D 11 +D 12 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 10 +D 13 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 9 +D 10 +D 13 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 9 +D 12 +D 13 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 10 +D 12 +D 13 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 8 +D 10 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D3 +D 5 +D 6 +D 9 +D 10 +D 11 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 8 +D 10 +D 12 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 10 +D 11 +D 12 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 10 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 10 +D 11 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 11 +D 12 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 11 +D 12 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D10 +D 11 +D 12 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 10 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 8 +D 9 +D 10 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 8 +D 11 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 9 +D 11 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 13 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 10 +D 13 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 12 +D13 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 9 +D 10 +D 11 +D 12 +D 13 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 8 +D 11 +D 12 +D 13 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 8 +D 10 +D 11 +D 12 +D 13 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 8 +D 9 +D 10 +D 12 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 8 +D 10 +D 12 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 8 +D 9 +D10 +D 12 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 8 +D 9 +D 10 +D 12 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 8 +D 10 +D 11 +D 12 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 9 +D 10 +D 11 +D 12 +D 13 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 8 +D 10 +D 11 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 9 +D10 +D 11 +D 12 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 7 +D 10 +D 11 +D 12 +D 13 +D 14 +D 15 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 7 +D 9 +D 10 +D 11 +D 12 +D 13 +D 14 +D 15 +D 16 .

[0275] In one example, the Cyclic Redundancy Check (CRC) code includes A = 2 generator polynomials, and the CRC check bit sequence lengths L0 and L1 corresponding to A = 2 generator polynomials are {5, 16} respectively. The generator polynomial of CRC5 is g(D) = 1 + D. 3 +D5. In one example, CRC16 is g(D) = 1 + D 7 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 4 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 4 +D 5 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 4 +D 6 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D3 +D 5 +D 7 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 6 +D 7 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 8 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 4 +D 8 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 4 +D 5 +D 8 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 4 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 4 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 5 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 7 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D3 +D 4 +D 5 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 4 +D 6 +D 7 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 5 +D 8 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 5 +D 6 +D 7 +D 8 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 5 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 5 +D 6 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 4 +D 5 +D 6 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 5 +D 7 +D9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 4 +D 5 +D 7 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 6 +D 7 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 6 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 5 +D 6 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 4 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 5 +D 6 +D 10 +D 11 +D14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 4 +D 5 +D 6 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 5 +D 7 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 4 +D 5 +D 7 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 6 +D 7 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 4 +D 5 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 6 +D 8 +D 10 +D 11 +D 14 +D 16In one example, CRC16 is g(D) = 1 + D 3 +D 5 +D 6 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 4 +D 5 +D 6 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 7 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 7 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 6 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 7 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 5 +D 7 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 4 +D5 +D 7 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 5 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 4 +D 5 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 6 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 5 +D 6 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 5 +D 7 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 4 +D 5 +D 6 +D 7 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D2 +D 3 +D 4 +D 6 +D 7 +D 8 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 4 +D 5 +D 6 +D 7 +D 8 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 4 +D 6 +D 7 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 4 +D 5 +D 6 +D 7 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 4 +D 5 +D 6 +D 7 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 4 +D 5 +D 6 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D1 +D 2 +D 4 +D 5 +D 7 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 4 +D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 4 +D 5 +D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 3 +D 4 +D 5 +D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 4 +D 5 +D 6 +D 7 +D 10 +D 11 +D 14 +D 16In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 4 +D 5 +D 6 +D 7 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 4 +D 6 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 5 +D 6 +D 7 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 5 +D 6 +D 7 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 4 +D 5 +D 6 +D 7 +D 8 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 5 +D 6 +D 9 +D 10 +D 11 +D 14 +D16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 5 +D 7 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 5 +D 6 +D 7 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 4 +D 5 +D 6 +D 7 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 4 +D 6 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 3 +D 4 +D 6 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 2 +D 3 +D 5 +D 6 +D 8 +D 9 +D 10 +D 11 +D14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 7 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 5 +D 6 +D 7 +D 8 +D 9 +D 10 +D 11 +D 14 +D 16 In one example, CRC16 is g(D) = 1 + D 1 +D 2 +D 3 +D 4 +D 5 +D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 16 .

[0276] In one example, the Cyclic Redundancy Check (CRC) code contains at least one CRC generator polynomial from any of the examples above.

[0277] Example 9

[0278] Example 9 illustrates the process of convolutionally encoding an information bit sequence to obtain the encoded bit sequence. For example, this example includes the following steps:

[0279] Step 1: Obtain the information bit sequence.

[0280] Step 2: Perform convolutional encoding on the information bit sequence to obtain the encoded bit sequence.

[0281] In one embodiment, the constraint length of the convolutional coding is v = 4, in which case the required number of shift registers can be 4 - 1 = 3, and the highest power of the component code generator polynomial is 3. The convolutional coding includes at least two generator polynomials, and these at least two generator polynomials are at least two of the following: 1 + D 1 +D 3 1+D 1 +D2 +D 3 and 1+D 2 +D 3 The corresponding octal values ​​are 15, 17, and 13.

[0282] In one example, the convolutional coding includes two component code generator polynomials (i.e., n = 2 component code generator polynomials corresponding to octal values ​​13 and 17 respectively): 1 + D 2 +D 3 and 1+D 1 +D 2 +D 3 .

[0283] In another example, the convolutional coding includes two component code generator polynomials (i.e., n = 2 component code generator polynomials corresponding to octal values ​​of 15 and 17 respectively): 1 + D 1 +D 3 and 1+D 1 +D 2 +D 3 .

[0284] In another example, the convolutional coding includes two component code generator polynomials (i.e., n = 2 component code generator polynomials corresponding to octal values ​​of 15 and 13 respectively): 1 + D 1 +D 3 and 1+D 2 +D 3 .

[0285] In one embodiment, the convolutional coding includes three component code generator polynomials (i.e., n = 3 component code generator polynomials). In one example, the three component code generator polynomials are: 1 + D 1 +D 3 1+D 1 +D 2 +D 3 1+D 2 +D 3 The corresponding octal values ​​are 15, 17, and 13. In another example, the generator polynomial for the three component codes is 1 + D. 1 +D 3 1+D 1 +D 2 +D 3 1+D 1 +D 3 The corresponding octal values ​​are 15, 17, and 15. In another example, the generator polynomial for the three component codes is 1 + D. 2 +D 3 1+D 1 +D 2 +D 3 1+D2 +D 3 The corresponding octal values ​​are 13, 17, and 13.

[0286] In one embodiment, the convolutional coding includes four component code generator polynomials (i.e., n = 4 component code generator polynomials). In one example, the four component code generator polynomials are: 1 + D 2 +D 3 1+D 1 +D 2 +D 3 1+D 1 +D 3 1+D 2 +D 3 The corresponding octal values ​​are 13, 17, 15, and 13. In another example, the generator polynomial for the three component codes is 1 + D. 2 +D 3 1+D 1 +D 2 +D 3 1+D 1 +D 3 1+D 1 +D 3 The corresponding octal values ​​are 13, 17, 15, and 15. In another example, the generator polynomial for the three component codes is: 1 + D 1 +D 3 1+D 1 +D 2 +D 3 1+D 2 +D 3 1+D 2 +D 3 The corresponding octal values ​​are 15, 17, 13, and 13. In another example, the generator polynomial for the three component codes is 1 + D. 1 +D 3 1+D 1 +D 2 +D 3 1+D 2 +D 3 1+D 1 +D 3 The corresponding octal values ​​are 15, 17, 13, and 15.

[0287] In one embodiment, the convolutional coding includes five component code generator polynomials (i.e., n = 5 component code generator polynomials). In one example, the five component code generator polynomials are: g0(D) = 1 + D 1 +D 3 g1(D) = 1 + D 1 +D 2+D 3 g2(D)=1+D 2 +D 3 g3(D) = 1 + D 1 +D 3 g4(D) = 1 + D 1 +D 2 +D 3 The corresponding octal values ​​are 15, 17, 13, 15, and 17. In another example, the generator polynomial for the five component codes is: g0(D) = 1 + D 1 +D 3 g1(D) = 1 + D 1 +D 2 +D 3 g2(D)=1+D 2 +D 3 g3(D) = 1 + D 2 +D 3 g4(D) = 1 + D 1 +D 2 +D 3 The corresponding octal values ​​are 15, 17, 13, 13, and 17. In another example, the generator polynomial for the five component codes is: g0(D) = 1 + D 2 +D 3 g1(D) = 1 + D 1 +D 2 +D 3 g2(D)=1+D 1 +D 3 g3(D) = 1 + D 1 +D 3 g4(D) = 1 + D 1 +D 2 +D 3 The corresponding octal values ​​are 13, 17, 15, 15, and 17. In another example, the generator polynomial for the five component codes is: g0(D) = 1 + D 2 +D 3 g1(D) = 1 + D 1 +D 2 +D 3 g2(D)=1+D 1 +D 3 g3(D) = 1 + D 2 +D 3 g4(D) = 1 + D 1 +D 2 +D 3 The corresponding octal values ​​are 13, 17, 15, 13, and 17.

[0288] In one embodiment, the convolutional coding includes six component code generator polynomials (i.e., n = six component code generator polynomials). In one example, the six component code generator polynomials are: g0(D) = 1 + D 2 +D 3 g1(D) = 1 + D 1 +D 2 +D 3 g2(D)=1+D 1 +D 3 g3(D) = 1 + D 2 +D 3 g4(D) = 1 + D 1 +D 2 +D 3 g5(D) = 1 + D 1 +D 3 The corresponding octal values ​​are 13, 17, 15, 13, 17, 15. In another example, the generator polynomial for the 6 component codes is: g0(D) = 1 + D 2 +D 3 g1(D) = 1 + D 1 +D 2 +D 3 g2(D)=1+D 1 +D 3 g3(D) = 1 + D 1 +D 3 g4(D) = 1 + D 1 +D 2 +D 3 g5(D) = 1 + D 2 +D 3 The corresponding octal values ​​are: 13, 17, 15, 15, 17, 13. In another example, the generator polynomial for the 6 component codes is: g0(D) = 1 + D 1 +D 3 g1(D) = 1 + D 1 +D 2 +D 3 g2(D)=1+D 2 +D 3 g3(D) = 1 + D 2 +D 3 g4(D) = 1 + D 1 +D 2 +D 3 g5(D) = 1 + D 1 +D 3 The corresponding octal values ​​are: 15, 17, 13, 13, 17, 15. In another example, the generator polynomial for the 6 component codes is: g0(D) = 1 + D 1 +D3 g1(D) = 1 + D 1 +D 2 +D 3 g2(D)=1+D 2 +D 3 g3(D) = 1 + D 1 +D 3 g4(D) = 1 + D 1 +D 2 +D 3 g5(D) = 1 + D 2 +D 3 The corresponding octal values ​​are: 15, 17, 13, 15, 17, 13.

[0289] In one embodiment, Figure 9 This is a structural block diagram of a data transmission device provided in an embodiment of this application. This embodiment is applied to a first communication device. Figure 9 As shown, the data transmission device in this embodiment includes: an acquisition module 910, a convolution encoder 920, an interpolator 930, and a transmitter 940.

[0290] The acquisition module 910 is configured to acquire the first bit sequence.

[0291] The convolutional encoder 920 is configured to perform convolutional encoding on the first bit sequence to obtain the second bit sequence.

[0292] Interpolator 930 is configured to repeat the operation on the second bit sequence to obtain the third bit sequence.

[0293] Transmitter 940 is configured to transmit a third bit sequence to a second communication device.

[0294] In one embodiment, obtaining the first bit sequence includes:

[0295] The original bit sequence is encoded using Cyclic Redundancy Check (CRC) to obtain the first bit sequence.

[0296] In one embodiment, the initial state of the register for convolutional coding is determined by the first m bits of the first bit sequence; where m is equal to the constraint length of the convolutional coding minus one.

[0297] In one embodiment, before performing convolutional encoding on the first bit sequence to obtain the second bit sequence, the data transmission method applied to the first communication device further includes:

[0298] The first m bits of the first bit sequence are placed at the end of the first bit sequence to obtain the adjusted first bit sequence.

[0299] In one embodiment, the initial state of the register for convolutional coding is determined by the last m bits of the first bit sequence; where m is equal to the constraint length of the convolutional coding minus one.

[0300] In one embodiment, the initial state of the registers for convolutional coding is set to 0.

[0301] In one embodiment, before performing convolutional encoding on the first bit sequence to obtain the second bit sequence, the data transmission method applied to the first communication device further includes:

[0302] Add m bits, all equal to zero, after the first bit sequence to obtain the adjusted first bit sequence.

[0303] In one embodiment, convolutional encoding is performed on the first bit sequence to obtain the second bit sequence, including:

[0304] Convolutional encoding is performed on the i-th bit in the adjusted first bit sequence to obtain a second bit sequence of length n bits; where i is a non-negative integer less than K, K is the length of the first bit sequence, and n is an integer greater than 1.

[0305] In one embodiment, convolutional encoding is performed on the first bit sequence to obtain the second bit sequence, including:

[0306] Perform convolutional encoding on the i-th bit in the adjusted first bit sequence to obtain a second bit sequence of length n bits; where i is a non-negative integer less than the sum of K and m, K is the length of the first bit sequence, n is an integer greater than 1, and m is equal to the constraint length of the convolutional encoding minus one.

[0307] In one embodiment, repeating the operation on the second bit sequence to obtain the third bit sequence includes:

[0308] Repeat the second bit sequence q times to obtain the third bit sequence; where q is an integer greater than 1.

[0309] In one embodiment, the second bit sequence is repeated q times to obtain the third bit sequence, including:

[0310] Repeat each bit in the second bit sequence q times to obtain the third bit sequence; where the third bit sequence contains n*q bits; or,

[0311] Repeat all bits in the second bit sequence as a whole q times to obtain the third bit sequence.

[0312] In one embodiment, before repeating the operation on the second bit sequence to obtain the third bit sequence, the data transmission method applied to the first communication device further includes:

[0313] The second bit sequence is line-coded to obtain the fourth bit sequence.

[0314] In one embodiment, repeating the operation on the second bit sequence to obtain the third bit sequence includes:

[0315] Repeat each bit in the fourth bit sequence q times to obtain the third bit sequence; or,

[0316] Repeat all bits in the fourth bit sequence as a whole q times to obtain the third bit sequence; the third bit sequence contains n*q bits.

[0317] In one embodiment, after repeating the operation on the second bit sequence to obtain the third bit sequence, the data transmission method applied to the first communication device further includes:

[0318] The third bit sequence is line-coded to obtain the fifth bit sequence.

[0319] In one embodiment, transmitting the third bit sequence to the second communication device includes:

[0320] The fifth bit sequence is transmitted to the second communication device.

[0321] In one embodiment, the line coding includes at least one of the following: dual-phase space FM0 coding; Miller coding; Manchester coding; pulse interval coding; mBnB coding.

[0322] In one embodiment, the value of q is determined by at least one of the following parameters: the length of the second bit sequence; the constraint length of the convolutional coding; the length of the first bit sequence; the code rate; and the number of CRC check bits.

[0323] In one embodiment, the value of q includes one of the following: 2, 3, 4, 5, 6, 7, 8, 12, 16, 24, 32, 48 and 64.

[0324] In one embodiment, the value of n includes one of the following: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 and 12.

[0325] In one embodiment, the constraint length of the convolutional coding includes one of the following values: 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11.

[0326] The data transmission device provided in this embodiment is configured to achieve... Figure 3 The data transmission method applied to the first communication device in the illustrated embodiment is similar in principle and technical effect to the data transmission device provided in this embodiment, and will not be described again here.

[0327] In one embodiment, this application also provides a data transmission device, which is applied to a first communication device. The data transmission device in this embodiment includes: an acquisition module, a convolutional encoder, a line encoder, and a transmitter.

[0328] The acquisition module is configured to acquire the first bit sequence;

[0329] A convolutional encoder is configured to perform convolutional encoding on the first bit sequence to obtain a second bit sequence;

[0330] A line encoder is configured to perform line encoding on the second bit sequence to obtain a fourth bit sequence;

[0331] A transmitter configured to transmit the fourth bit sequence to a second communication device.

[0332] The data transmission device provided in this embodiment is configured to implement the data transmission method applied to the first communication device described above. The implementation principle and technical effects of the data transmission device provided in this embodiment are similar, and will not be repeated here.

[0333] In one embodiment, this application also provides a data transmission apparatus, which is applied to a second communication device. The data transmission apparatus in this embodiment includes a receiver, a line decoder, and a convolutional decoder.

[0334] The receiver is configured to receive the fourth bit sequence transmitted by the first communication device;

[0335] A line decoder is configured to perform line decoding on the fourth bit sequence to obtain a second bit sequence;

[0336] A convolutional decoder is configured to perform convolutional decoding on the second bit sequence to obtain a first bit sequence.

[0337] The data transmission device provided in this embodiment is configured to implement the data transmission method applied to the second communication device described above. The implementation principle and technical effects of the data transmission device provided in this embodiment are similar, and will not be repeated here.

[0338] In one embodiment, Figure 10 This is a structural block diagram of another data transmission device provided in an embodiment of this application. This embodiment is applied to a second communication device. Figure 10 As shown, the data transmission device in this embodiment includes: a receiver 1010, a restorer 1020, and a convolutional decoder 1030.

[0339] Receiver 1010 is configured to receive the third bit sequence sent by the first communication device;

[0340] The restorer 1020 is configured to perform a deduplication operation on the third bit sequence to obtain the second bit sequence;

[0341] The convolutional decoder 1030 is configured to perform convolutional decoding on the second bit sequence to obtain the first bit sequence.

[0342] The data transmission device provided in this embodiment is configured to achieve... Figure 4 The data transmission method applied to the second communication device in the illustrated embodiment is similar in principle and technical effect to the data transmission device provided in this embodiment, and will not be described again here.

[0343] In one embodiment, Figure 11 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Figure 11 As shown, the device provided in this application includes: a processor 1110, a memory 1120, and a communication module 1130. The device may contain one or more processors 1110. Figure 11 Taking a processor 1110 as an example. The number of memory units 1120 in this device can be one or more. Figure 11 Taking a memory 1120 as an example, the processor 1110, memory 1120, and communication module 1130 of this device can be connected via a bus or other means. Figure 11 Taking a bus connection as an example, the communication module 1130 may include a transmitter and a receiver. In this embodiment, the device can be a first communication device or a second communication device. In one example, if the communication device is a first communication device, i.e., a transmitter, the communication device includes a transmitter and can be used to send data to a second communication device, which is a receiver. The transmitted signal can be obtained by adjusting the impedance parameters of the impedance network module. In another example, if the communication device is a second communication device, i.e., a receiver, the communication device includes a receiver and can be used to receive data sent by the first communication device, which is the transmitter.

[0344] Memory 1120, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, and modules, such as program instructions / modules corresponding to the devices in any embodiment of this application (e.g., the acquisition module 910, convolution encoder 920, interpolator 930, and transmitter 940 in a data transmission apparatus). Memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created according to the use of the device, etc. Furthermore, memory 1120 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, memory 1120 may further include memory remotely located relative to processor 1110, and these remote memories can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. In one example, memory 710 may include a data storage unit and a data encoding processing unit, wherein the data storage unit may be used as a local cache for information bit sequences, some other signaling parameters, and / or encoded bit sequences. The data encoding processing unit performs convolutional encoding and repetition operations on the information bit sequence to obtain the repeated sequence.

[0345] When the communication device is a first communication device, the device provided above can be configured to execute the data transmission method applied to the first communication device provided in any of the above embodiments, and has corresponding functions and effects.

[0346] When the communication device is a second communication device, the device provided above can be configured to execute the data transmission method for the second communication device provided in any of the above embodiments, and has the corresponding functions and effects.

[0347] This application also provides a storage medium containing computer-executable instructions. When executed by a computer processor, the computer-executable instructions are used to perform a data transmission method applied to a first communication device. The method includes: acquiring a first bit sequence; performing convolutional encoding on the first bit sequence to obtain a second bit sequence; performing a repeated operation on the second bit sequence to obtain a third bit sequence; and transmitting the third bit sequence to a second communication device.

[0348] This application also provides a storage medium containing computer-executable instructions. When executed by a computer processor, the computer-executable instructions are used to perform a data transmission method applied to a second communication device. The method includes: receiving a third bit sequence sent by a first communication device; performing a deduplication operation on the third bit sequence to obtain a second bit sequence; and performing convolutional decoding on the second bit sequence to obtain a first bit sequence.

[0349] Those skilled in the art will understand that the term user equipment covers any suitable type of wireless user equipment, such as mobile phones, portable data processing devices, portable web browsers, or vehicle-mounted mobile stations.

[0350] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0351] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0352] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on memory. Memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Video Disc (DVD) or Compact Disk (CD)), etc. Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and processors based on multi-core processor architectures.

[0353] This application also provides a computer program product, including a computer program that, when executed by a processor, can implement the data transmission method provided in any embodiment of this application.

[0354] In the implementation of the computer program product, computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0355] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data transmission method, characterized in that, Applied to a first communication device, including: Obtain the first bit sequence; The first bit sequence is convolutionally encoded to obtain the second bit sequence; Repeat the operation on the second bit sequence to obtain the third bit sequence; The third bit sequence is transmitted to the second communication device.

2. The method according to claim 1, characterized in that, The process of obtaining the first bit sequence includes: The original bit sequence is encoded using Cyclic Redundancy Check (CRC) to obtain the first bit sequence.

3. The method according to claim 1, characterized in that, The initial state of the register for the convolutional coding is determined by the first m bits of the first bit sequence; where m is equal to the constraint length of the convolutional coding minus one.

4. The method according to claim 3, characterized in that, Before performing convolutional encoding on the first bit sequence to obtain the second bit sequence, the method further includes: The first m bits of the first bit sequence are placed at the end of the first bit sequence to obtain the adjusted first bit sequence.

5. The method according to claim 1, characterized in that, The initial state of the register for the convolutional coding is determined by the last m bits of the first bit sequence; where m is equal to the constraint length of the convolutional coding minus one.

6. The method according to claim 1, characterized in that, The initial state of the registers for the convolutional encoding is set to 0.

7. The method according to claim 6, characterized in that, Before performing convolutional encoding on the first bit sequence to obtain the second bit sequence, the method further includes: Add m bits, all equal to zero, after the first bit sequence to obtain the adjusted first bit sequence.

8. The method according to any one of claims 3-5, characterized in that, The step of performing convolutional encoding on the first bit sequence to obtain the second bit sequence includes: The i-th bit in the adjusted first bit sequence is convolutionally encoded to obtain a second bit sequence of length n bits; where i is a non-negative integer less than K, K is the length of the first bit sequence, and n is an integer greater than 1.

9. The method according to claim 6 or 7, characterized in that, The step of performing convolutional encoding on the first bit sequence to obtain the second bit sequence includes: The i-th bit in the adjusted first bit sequence is convolutionally encoded to obtain a second bit sequence of length n bits; where i is a non-negative integer less than the sum of K and m, K is the length of the first bit sequence, n is an integer greater than 1, and m is equal to the constraint length of the convolutional encoding minus one.

10. The method according to claim 1, characterized in that, The step of repeating the second bit sequence to obtain the third bit sequence includes: The second bit sequence is repeated q times to obtain the third bit sequence; wherein q is an integer greater than 1.

11. The method according to claim 10, characterized in that, The step of repeating the second bit sequence q times to obtain the third bit sequence includes: Repeat each bit in the second bit sequence q times to obtain the third bit sequence; wherein the third bit sequence contains n*q bits; or, Repeat all bits in the second bit sequence as a whole q times to obtain the third bit sequence.

12. The method according to claim 1, characterized in that, Before repeating the operation on the second bit sequence to obtain the third bit sequence, the method further includes: The second bit sequence is line-coded to obtain the fourth bit sequence.

13. The method according to claim 12, characterized in that, The step of repeating the second bit sequence to obtain the third bit sequence includes: Repeat each bit in the fourth bit sequence q times to obtain the third bit sequence; or, Repeat all bits in the fourth bit sequence as a whole q times to obtain the third bit sequence; wherein the third bit sequence contains n*q bits.

14. The method according to claim 1, characterized in that, After repeating the operation on the second bit sequence to obtain the third bit sequence, the method further includes: The third bit sequence is line-coded to obtain the fifth bit sequence.

15. The method according to claim 14, characterized in that, The step of transmitting the third bit sequence to the second communication device includes: The fifth bit sequence is transmitted to the second communication device.

16. The method according to any one of claims 12-14, characterized in that, The line coding includes at least one of the following: dual-phase space FM0 coding; Miller coding; Manchester coding; pulse interval coding; mBnB coding.

17. The method according to claim 10, 11 or 13, characterized in that, The value of q is determined by at least one of the following parameters: the length of the second bit sequence; the constraint length of the convolutional coding; the length of the first bit sequence; the code rate; and the number of CRC check bits.

18. The method according to claim 10, 11 or 13, characterized in that, The value of q includes one of the following: 2, 3, 4, 5, 6, 7, 8, 12, 16, 24, 32, 48 and 64.

19. The method according to claim 8, characterized in that, The value of n includes one of the following: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 and 12.

20. The method according to claim 1, characterized in that, The constraint length of the convolutional encoding includes one of the following values: 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11.

21. A data transmission method, characterized in that, Applied to a second communication device, including: Receive the third bit sequence sent by the first communication device; The third bit sequence is de-repeated to obtain the second bit sequence; The second bit sequence is convolutionally decoded to obtain the first bit sequence.

22. A communication device, characterized in that, include: Memory, and one or more processors; The memory is configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors perform the method as described in any one of claims 1-20 or 21 above.

23. A storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1-20 or 21.

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