Master-slave integrated MVB simulation test device based on FPGA and MCU

Abstract

The application discloses a master-slave integrated MVB simulation test device based on FPGA and MCU, a device body is internally provided with an FPGA chip, an MCU chip and an MVB communication physical layer circuit; the FPGA chip is internally integrated with an MVB master logic unit and an MVB slave logic unit; the MCU chip is in communication connection with the master logic unit and the MVB slave logic unit; the MVB communication physical layer circuit is used for realizing conversion between a logic level signal output by the FPGA chip and an EMD signal of the MVB bus. The MVB master logic control unit sends an MVB master frame according to a port traversal table stored in a port table unit; after the MVB slave logic data and state control unit obtains sending control right of the MVB sending control unit, the MVB slave logic unit sends or receives data with the MVB bus. The application reduces the number of devices and cable connections, shortens the deployment time of a test system and shortens the single test time.

Description

Technical Field

[0001] This invention relates to the field of MVB simulation test equipment technology, and in particular to a master-slave integrated MVB simulation test equipment based on FPGA and MCU. Background Technology

[0002] Traditional MVB testing systems consist of multiple independent devices, including an MVB master station, MVB repeater devices, MVB slave devices, MVB cables, and the system under test (DUT). The MVB master station controls the communication of the entire MVB network. First, the MVB master station sends an MVB master frame. Then, all MVB slave devices and the DUT receive the MVB master frame. The polled MVB slave devices communicate with the DUT via MVB cables to acquire test data, and this process is repeated periodically. This testing system requires multiple independent devices, has complex cabling, and is costly. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a master-slave integrated MVB simulation test device based on FPGA and MCU, as well as an MVB simulation test method.

[0004] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows: Firstly, a master-slave integrated MVB simulation test device based on FPGA and MCU, comprising: a device body, wherein an FPGA chip, an MCU chip and an MVB communication physical layer circuit are disposed within the device body; the FPGA chip integrates an MVB master logic unit and an MVB slave logic unit; the MCU chip forms a communication connection with the MVB master logic unit and the MVB slave logic unit;

[0005] The input terminal of the MVB communication physical layer circuit is connected to the FPGA chip; the output terminal of the MVB communication physical layer circuit is connected to the MVB-EMD interface; the MVB communication physical layer circuit is used to convert the logic level signal output by the FPGA chip to the EMD signal of the MVB bus; the MVB-EMD interface is used to connect to an external MVB bus.

[0006] The MVB main logic control unit in the MVB main logic unit controls the MVB sending Manchester encoding and framing sending unit to send the MVB main frame to the MVB communication physical layer circuit according to the port traversal table stored in the port table unit. After the MVB main frame is sent, the MVB main logic control unit releases the sending control right of the MVB sending control unit to the MVB slave logic data and status control unit in the MVB slave logic unit.

[0007] After obtaining the transmission control of the MVB transmission control unit from the logic data and status control unit, the MVB sends or receives data from the logic unit and the MVB bus.

[0008] Preferably, the MCU chip communicates with an external host computer via an Ethernet interface to receive data sent by the host computer and upload simulation test data.

[0009] Preferred,

[0010] The MVB main logic unit includes a UART transceiver unit, a data packet assembly and command parsing unit, a command operation unit, a main transmission control unit, a transmission FIFO unit, an MVB main logic control unit, an MVB transmission Manchester encoding and framing transmission unit, a port table unit, and a receive FIFO unit.

[0011] The UART transceiver unit is connected to the communication interface of the MCU chip and is used to receive data transmitted by the MCU chip. The data received from the MCU chip includes MVB main logic unit configuration information and main unit control instructions.

[0012] The data packet and command parsing unit is used to parse the MVB main logic unit configuration information and main unit control instructions received by the UART transceiver unit;

[0013] The command operation unit is used to generate operation instructions based on the parsed MVB main logic unit configuration information, and to start or stop the MVB main logic control unit based on the main unit control instructions.

[0014] The port table unit is used to store the port traversal table obtained by converting the configuration information of the MVB main logic unit.

[0015] The transmission FIFO unit is used to buffer the MVB main frame data to be transmitted;

[0016] The main transmit control unit is used to control the transmit FIFO unit to transmit data to the UART transceiver unit;

[0017] Preferably, the UART transceiver unit communicates with the MCU chip. The data received by the UART transceiver unit is transmitted to the command operation unit through the data packet assembly and command parsing unit. After the MVB main logic control unit is started, the MVB main logic control unit updates the MVB main logic unit configuration information to the port table unit.

[0018] Preferred,

[0019] The MVB slave logic unit includes an application access unit, a read FIFO unit, a write FIFO unit, a debugging unit, a port time update unit, a device control unit, a data storage unit, an application access memory interface unit, an MVB slave logic data and status control unit, a memory access control unit, a TX buffer unit, a slave logic MVB transmit Manchester encoding and framing transmission unit, an MVB receive RX unit, and an RX buffer unit.

[0020] The application access unit is connected to the communication interface of the MCU chip and is used to interact with the MCU chip for data exchange.

[0021] The write FIFO unit is used to cache the data to be sent from the MCU chip to the MVB slave logic data and status control unit; the data memory unit is used to store the MVB slave logic unit configuration information and interaction data.

[0022] The MVB uses the logic data and status control unit to control the transmission of data between the data storage unit and other units, and to match the port information in the MVB master frame.

[0023] The logical MVB sending Manchester encoding and framing unit is used to encode the data to be sent in Manchester and then frame it before transmitting it to the MVB communication physical layer circuit.

[0024] The MVB receiving RX unit is used to decode and error-check the MVB main frame received by the MVB communication physical layer circuit, and store the checked data to the data memory unit.

[0025] The read FIFO unit is used to cache the interactive data uploaded to the MCU chip;

[0026] The port time update unit is used to update the interaction period of the MVB slave logic unit port;

[0027] The debugging unit is used to debug the running status of the MVB slave logic unit;

[0028] The memory access control unit is used to control read and write access to the data memory unit;

[0029] The TX buffer unit is used to cache the slave frame data to be encoded.

[0030] Preferred,

[0031] The application access control unit communicates with the MCU chip and parses the received data, sending it to the write FIFO unit. The MVB updates the data memory from the logic data and status control unit and sends it to the MVB bus through the logic MVB send Manchester encoding and framing unit. Data received from the MVB bus is decoded by the MVB receive RX unit and stored in the data memory unit. The MVB controls the data to be transmitted to the MCU chip via the application access unit.

[0032] Preferred,

[0033] The MVB communication physical layer circuit includes a transformer T6, a differential operational amplifier chip U5, an operational amplifier chip U6, a pre-emphasis signal transmission chip U8, and a level conversion chip U7.

[0034] One side of transformer T6 is connected to the MVB-EMD interface, and the other side of transformer T6 is connected to the input of differential operational amplifier U5. The output of differential operational amplifier U5 is connected to the input of operational amplifier U6. The output of operational amplifier U6 is connected to pin B of pre-emphasis signal transmitting chip U8. Pin A of pre-emphasis signal transmitting chip U8 is grounded. Pin RO of pre-emphasis signal transmitting chip U8 is connected to pin B of level conversion chip U7. Pin A of level conversion chip U7 is connected to pin VREFB1N0 of FPGA chip. Pin DE of pre-emphasis signal transmitting chip U8 is connected to pin IO_VB1N0_3 of FPGA chip. Pin DI of pre-emphasis signal transmitting chip U8 is connected to pin IO_VB1N0_2 of FPGA chip.

[0035] Preferred,

[0036] The device body also includes a power supply circuit, an LED circuit, a DIP switch circuit, an FPGA configuration circuit, a USB circuit, a serial port debugging circuit, and an SD card circuit.

[0037] The power supply circuit is used to provide operating power for the FPGA chip, MCU chip and various peripheral circuits;

[0038] The LED circuit is used to indicate the operating status and communication status of the device;

[0039] The DIP switch circuit is used to set the hardware parameters of the device;

[0040] The FPGA configuration circuit is used for programming and configuring the FPGA chip.

[0041] The USB circuit is used to enable USB data interaction between the device and external devices;

[0042] The serial port debugging circuit is used for serial port debugging of the device;

[0043] The SD card circuit is used to expand data storage capacity and store simulation test logs.

[0044] Secondly, an MVB simulation test method is provided, which uses the aforementioned master-slave integrated MVB simulation test equipment based on FPGA and MCU. The MVB communication physical layer circuit in the master-slave integrated MVB simulation test equipment is connected to the MVB bus through the MVB-EMD interface; several systems under test to be tested are connected to the MVB bus.

[0045] The testing method includes the following steps:

[0046] The first step is that the MCU chip sends the MVB main logic unit configuration information to the UART transceiver unit of the MVB main logic unit;

[0047] The MCU chip sends the MVB slave logic unit configuration information to the application access unit of the MVB slave logic unit;

[0048] The second step is to convert the MVB main logic unit configuration information into a port traversal table and store it in the port table unit.

[0049] From the logic data and status control unit, MVB stores logical configuration information into the data storage module;

[0050] The third step is for the MCU chip to send a master unit control command to start the MVB main logic control unit.

[0051] After the MVB main logic control unit starts, the MVB bus enters the running state. The MVB main logic control unit reads the port numbers that need to be traversed from the port table in sequence, and sends the MVB main frame to the MVB bus through the MVB Manchester encoding and framing unit.

[0052] After the MVB main frame is sent, the MVB main logic control unit releases the sending control of the MVB sending control unit to the MVB slave logic data and status control unit.

[0053] Step 4: All systems under test on the MVB bus receive the MVB master frame. The MVB slave logic data and status control unit obtains the transmission control right of the MVB transmission control unit. The MVB receive RX unit receives the MVB master frame and sends it to the MVB slave logic data and status control unit. The MVB slave logic data and status control unit traverses the port configuration table of the data storage device. If a matching port is found, it prepares to receive or send data.

[0054] If the matched port is the source port, the MVB reads the corresponding port data from the logic data and status control unit and sends it to the logic MVB sending Manchester encoding and framing unit for framing and encoding, and then sends it to the MVB bus.

[0055] If the matched port is the destination port, the MVB receives the next packet of slave frame data from the logical data and status control unit and updates the corresponding port table in the data memory.

[0056] Step 5: The MCU chip communicates with the application access module to write or read data from the data storage and transmit it to the host computer.

[0057] The beneficial effects of the present invention are: the master-slave integrated MVB simulation test device of the present invention realizes the functions of the MVB master logic unit and the MVB slave logic unit on a single FPGA chip, and performs time-division control on the communication data.

[0058] The master-slave integrated MVB simulation test equipment of this invention simplifies system complexity compared to traditional MVB test systems composed of multiple independent devices: by integrating the master station, slave station, and repeater into a single device, this invention reduces the number of devices and cable connections, shortens the deployment time of the test system, and lowers costs by eliminating the hardware and maintenance costs of multiple independent devices. Configuration and data parsing are achieved through a host computer, eliminating the need for testers to manually operate multiple devices, thus shortening the duration of a single test. Attached Figure Description

[0059] Figure 1 This is a logical functional block diagram of the MVB simulation test device of the present invention;

[0060] Figure 2 This is a hardware functional block diagram of the MVB simulation test equipment of the present invention;

[0061] Figure 3 This is a circuit schematic diagram of the MVB communication physical layer circuit of the present invention;

[0062] Figure 4 This is a structural diagram of the MVB simulation test equipment of the present invention;

[0063] Figure 5 This is a schematic diagram showing the connection between the MVB simulation test equipment of the present invention and the system under test;

[0064] Figure 6 This is a diagram showing the ports configured in the simulation test and the corresponding port data interaction communication test information.

[0065] Figure 7This is a diagram illustrating how the host computer parses data into application-layer information and displays it.

[0066] Figure 8 This is a partial pin connection of the PFGA chip of the present invention. Figure 1 ;

[0067] Figure 9 This is a partial pin connection of the PFGA chip of the present invention. Figure 2 ;

[0068] Figure 10 This is a partial pin connection of the MVU chip of the present invention. Figure 1 ;

[0069] Figure 11 This is a partial pin connection of the MVU chip of the present invention. Figure 2 . Detailed Implementation

[0070] The present invention will now be described in further detail with reference to the accompanying drawings and preferred embodiments. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0071] 1. Overall Implementation Overview

[0072] The master-slave integrated MVB simulation test equipment in this embodiment adopts the core architecture of "FPGA+MCU", which is suitable for the field of train communication technology and can be directly applied to the simulation test scenario of on-board rail transit communication system.

[0073] like Figure 4 As shown, the device body has a structural dimension of 150mm×110mm×45mm, making it compact and easy to install and deploy in vehicle-mounted testing environments. The device integrates core functional modules and peripheral auxiliary circuits internally, and has standardized interfaces externally, which can quickly establish connections with the host computer on the PC and the system under test (such as vehicle-mounted rail transit communication systems) to meet convenient testing needs.

[0074] like Figure 2 As shown, the device body contains an FPGA chip, an MCU chip, and an MVB communication physical layer circuit; the FPGA chip integrates an MVB master logic unit and an MVB slave logic unit; the MCU chip forms a communication connection with the MVB master logic unit and the MVB slave logic unit.

[0075] The input terminal of the MVB communication physical layer circuit is connected to the FPGA chip; the output terminal of the MVB communication physical layer circuit is connected to the MVB-EMD interface. The MVB communication physical layer circuit is used to convert the logic level signal output by the FPGA chip to the EMD signal of the MVB bus; the MVB-EMD interface is used to connect to an external MVB bus.

[0076] like Figure 2 As shown, the device also includes a power supply circuit, an LED circuit, a DIP switch circuit, an FPGA configuration circuit, a USB circuit, a serial port debugging circuit, and an SD card circuit.

[0077] The power supply circuit is used to provide operating power to the FPGA chip, MCU chip and various peripheral circuits;

[0078] LED circuits are used to indicate the operating and communication status of equipment;

[0079] DIP switch circuits are used to set the hardware parameters of the device;

[0080] The FPGA configuration circuit is used for programming and configuring the FPGA chip;

[0081] USB circuitry is used to enable USB data exchange between the device and external devices.

[0082] The serial port debugging circuit is used for serial port debugging of the device;

[0083] The SD card circuit is used to expand data storage capacity and store simulation test logs.

[0084] 2. Detailed Description of Equipment Hardware Structure

[0085] The core chip module in this embodiment includes an FPGA chip and an MCU chip. These two chips enable data interaction and control command transmission, jointly completing the MVB master-slave logic function and system scheduling. The MCU chip can be a commonly used microcontroller chip, such as... Figure 10 , Figure 11 As shown, the MCU chip used is LPC1788FBD144.

[0086] like Figure 1 , Figure 8 , Figure 9 As shown, the FPGA chip is the core carrier for implementing the MVB master and slave logic functions, and it integrates the MVB master logic unit and the MVB slave logic unit.

[0087] like Figure 1As shown, the MVB main logic unit includes a UART transceiver unit, a data packet assembly and command parsing unit, a command operation unit, a main transmission control unit, a transmission FIFO unit, an MVB main logic control unit, an MVB transmission Manchester encoding and framing transmission unit, a port table unit, and a receive FIFO unit.

[0088] The UART transceiver unit is connected to the communication interface of the MCU chip and is used to receive data transmitted by the MCU chip. The data received from the MCU chip includes MVB main logic unit configuration information and main unit control instructions.

[0089] The data packet and command parsing unit is used to parse the MVB main logic unit configuration information and main unit control instructions received by the UART transceiver unit.

[0090] The command operation unit is used to generate operation instructions based on the parsed MVB main logic unit configuration information, and to start or stop the MVB main logic control unit based on the main unit control instructions.

[0091] The port table unit is used to store the port traversal table obtained by converting the configuration information of the MVB main logic unit.

[0092] The MVB main logic control unit is the core control unit, responsible for controlling the periodic communication of the MVB bus according to the port traversal table stored in the port table unit. The port traversal table stored in the port table unit is generated by converting the MVB main logic unit configuration information issued by the MCU chip. The design of 1 millisecond time interval and 1024 millisecond cycle period ensures the regularity and stability of MVB main frame transmission.

[0093] The MVB master logic control unit controls the MVB sending Manchester encoding and framing sending unit to send MVB master frames to the MVB communication physical layer circuit according to the port traversal table stored in the port table unit. After the MVB master frame is sent, the MVB master logic control unit releases the sending control right of the MVB sending control unit to the MVB slave logic data and status control unit in the MVB slave logic unit. Then, after the MVB slave logic data and status control unit obtains the sending control right of the MVB sending control unit, the MVB slave logic unit can send or receive data with the MVB bus.

[0094] The transmit FIFO unit is used to buffer the MVB main frame data to be transmitted.

[0095] The main transmit control unit controls the transmit FIFO unit to transmit data to the UART transceiver unit. The MCU chip sends control data to the MVB main logic control unit. After receiving the control data, the MVB main logic control unit sends response data to the command operation unit. The command operation unit transmits the response data to the transmit FIFO unit, and the main transmit control unit controls the transmit FIFO unit to transmit data to the UART transceiver unit.

[0096] The UART transceiver unit communicates with the MCU chip. The data received by the UART transceiver unit is transmitted to the command operation unit through the data packet assembly and command parsing unit, and is updated to the port table unit by the MVB main logic control unit. The MVB main logic control unit controls the operation of the MVB bus according to the data in the port table unit.

[0097] like Figure 1 As shown, the MVB slave logic unit includes an application access unit, a read FIFO unit, a write FIFO unit, a debugging unit, a port time update unit, a device control unit, a data storage unit, an application access memory interface unit, an MVB slave logic data and status control unit, a memory access control unit, a TX buffer unit, a slave logic MVB transmit Manchester encoding and framing transmission unit, an MVB receive RX unit, and an RX buffer unit.

[0098] The application access unit is connected to the communication interface of the MCU chip and is used to interact with the MCU chip for data exchange.

[0099] The write FIFO unit is used to cache the data to be sent from the MCU chip to the MVB slave logic data and status control unit; the data memory unit is used to store the MVB slave logic unit configuration information and interaction data.

[0100] The MVB uses the logic data and status control unit to control the transmission of data between the data storage unit and other units, and to match the port information in the MVB master frame.

[0101] The logical MVB sending Manchester encoding and framing unit is used to encode and frame the data to be sent and then transmit it to the MVB communication physical layer circuit.

[0102] The MVB receive RX unit is used to decode and error-check the MVB master frames received by the MVB communication physical layer circuit to ensure the accuracy of data transmission, and to store the checked data in the data memory unit; the read FIFO unit is used to buffer the interactive data uploaded to the MCU chip; the port time update unit is used to update the interaction cycle of the MVB slave logic unit port; the debug unit is used to debug the operating status of the MVB slave device; the memory access control unit is used to control the read and write access to the data memory unit; and the TX buffer unit is used to buffer the slave frame data to be encoded.

[0103] The application access control unit communicates with the MCU chip and parses the received data, sending it to the write FIFO unit. The MVB updates the data memory from the logic data and status control unit and sends it to the MVB bus through the logic MVB send Manchester encoding and framing unit. Data received from the MVB bus is decoded by the MVB receive RX unit and stored in the data memory unit. The MVB controls the data to be transmitted to the MCU chip via the application access unit.

[0104] The MVB slave logic unit is centered around the MVB slave logic data and status control unit, which is responsible for matching the port information in the MVB master frame and controlling the reception and transmission of data.

[0105] like Figure 2 As shown, the MVB communication physical layer circuit has two sets (corresponding to MVB communication physical layer circuit 1 and MVB communication physical layer circuit 2), forming a redundant design.

[0106] like Figure 3 As shown, the MVB communication physical layer circuit is used for level signal conversion between the MVB transmit control unit of the FPGA chip in the simulation test equipment and the MVB bus. Its function is to convert the CMOS logic level of the FPGA chip into the EMD signal level of the MVB bus. Figure 3 As shown, the MVB communication physical layer circuit includes transformer T6, differential operational amplifier chip U5, operational amplifier chip U6, pre-emphasized signal transmitter chip U8, and level conversion chip U7. The circuit uses transformer T6 to achieve electrical signal isolation, thus enabling long-distance transmission. Differential operational amplifier U5 provides high-impedance input, ensuring signal attenuation remains within standard ranges even with multiple nodes. Operational amplifier U6 controls the voltage threshold to prevent signal interference. Level conversion chip U7 converts the CMOS logic level output from the FPGA chip to the EMD signal level of the MVB bus, and also performs signal relay functionality.

[0107] The transformer T6 side is connected to the MVB-EMD interface. Figure 3 MVB_A_N port, Figure 3 The other side of transformer T6 is connected to the input of differential operational amplifier U5 (MVB_A_P port). The output of differential operational amplifier U5 is connected to the input of operational amplifier U6. The output of operational amplifier U6 is connected to pin B of pre-emphasis signal transmitting chip U8. Pin A of pre-emphasis signal transmitting chip U8 is grounded. Pin RO of pre-emphasis signal transmitting chip U8 is connected to pin B of level conversion chip U7. Pin A of level conversion chip U7 is connected to pin VREFB1N0 of FPGA chip. Pin DE of pre-emphasis signal transmitting chip U8 is connected to pin IO_VB1N0_3 of FPGA chip. Pin DI of pre-emphasis signal transmitting chip U8 is connected to pin IO_VB1N0_2 of FPGA chip.

[0108] An MVB simulation testing method employs the aforementioned master-slave integrated MVB simulation testing equipment based on FPGA and MCU, such as... Figure 5 As shown, the MVB communication physical layer circuit in the master-slave integrated MVB simulation test equipment is connected to the MVB bus through the MVB-EMD interface; several systems under test to be tested are connected to the MVB bus.

[0109] The testing method includes the following steps:

[0110] The first step is that the MCU chip sends the MVB main logic unit configuration information to the UART transceiver unit of the MVB main logic unit;

[0111] The MCU chip sends the MVB slave logic unit configuration information to the application access unit of the MVB slave logic unit;

[0112] The second step is to convert the MVB main logic unit configuration information into a port traversal table and store it in the port table unit.

[0113] From the logic data and status control unit, MVB stores logical configuration information into the data storage module;

[0114] The third step is for the MCU chip to send a master unit control command to start the MVB main logic control unit.

[0115] After the MVB main logic control unit starts, the MVB bus enters the running state. The MVB main logic control unit reads the port numbers that need to be traversed from the port table in sequence, and sends the MVB main frame to the MVB bus through the MVB Manchester encoding and framing unit.

[0116] After the MVB main frame is sent, the MVB main logic control unit releases the sending control of the MVB sending control unit to the MVB slave logic data and status control unit.

[0117] Step 4: All systems under test on the MVB bus receive the MVB master frame. The MVB slave logic data and status control unit obtains the transmission control right of the MVB transmission control unit. The MVB receive RX unit receives the MVB master frame and sends it to the MVB slave logic data and status control unit. The MVB slave logic data and status control unit traverses the port configuration table of the data storage device. If a matching port is found, it prepares to receive or send data.

[0118] If the matched port is the source port, the MVB reads the corresponding port data from the logic data and status control unit and sends it to the logic MVB sending Manchester encoding and framing unit for framing and encoding, and then sends it to the MVB bus.

[0119] If the matched port is the destination port, the MVB receives the next packet of slave frame data from the logical data and status control unit and updates the corresponding port table in the data memory.

[0120] Step 5: The MCU chip communicates with the application access module to write or read data from the data storage and transmit it to the host computer.

[0121] Simulation test environment such as Figure 5 As shown, it consists of four parts: a host computer, a master-slave integrated MVB simulation test device, MVB cables, and the system under test. The host computer configures the MVB master logic unit configuration information and MVB slave logic unit configuration information of the MVB simulation test device, and performs communication data exchange. The entire simulation test is controlled by the host computer via Ethernet.

[0122] Step 1: Connect the master-slave integrated MVB simulation test device to the host computer via USB cable and Ethernet cable. Connect the master-slave integrated MVB simulation test device to the MVB bus, and connect several systems under test to the MVB bus.

[0123] Step 2: Configure the MVB simulation test equipment through the host computer. The configuration information includes the MVB master logic unit configuration information and the MVB slave logic unit configuration information.

[0124] The MVB main logic unit configuration information includes the port table of the MVB main logic unit and the main port update cycle;

[0125] MVB slave logic unit configuration information includes the MVB slave logic unit's port table, unit address, and slave port update cycle.

[0126] Step 3: The host computer sends the configuration information to the MVB simulation test device via Ethernet and controls the operation of the MVB simulation test device. For example... Figure 6As shown, the following ports are configured: 0x0195, 0x0893, 0x00b1, 0x0005, 0x0006, 0x00a0, 0x00b0, 0x0a92, 0x0a93, 0x0192, 0x0892, 0x0193, and 0x0194.

[0127] Step 4: After the MVB simulation test equipment is running, if... Figure 7 As shown, the host computer interacts with the system under test through the MVB simulation test equipment, and parses the data into application layer information according to the communication protocol. The host computer receives the interactive data uploaded by the MVB simulation test equipment, parses it into application layer information, and displays it.

[0128] Step 5: The operation of the MVB simulation test equipment is completed under the control of the host computer. That is, the host computer sends a stop command to the MCU chip, the MCU chip transmits the stop command to the MVB main logic unit, and the MVB main logic control unit in the MVB main logic unit stops working.

[0129] like Figure 1 As shown, to achieve the master-slave integrated design of the MVB simulation test system, the core is to implement the functions of the MVB master device logic circuit and the MVB slave device logic circuit on a single FPGA chip, and to perform time-division control of the communication data. Then, combined with an MCU chip, communication and configuration with the host computer are realized, and the MVB communication physical layer circuit realizes the conversion and relay functions of logic level signals and EMD signals.

[0130] The above description is merely a specific embodiment of the present invention. Various examples and illustrations do not constitute a limitation on the substantive content of the present invention. Those skilled in the art can modify or transform the specific embodiments described above after reading the specification without departing from the essence and scope of the invention.

Claims

1. A master-slave integrated MVB simulation and testing device based on FPGA and MCU, characterized in that: include: The device body contains an FPGA chip, an MCU chip, and an MVB communication physical layer circuit. The FPGA chip integrates an MVB master logic unit and an MVB slave logic unit. The MCU chip forms a communication connection with the MVB master logic unit and the MVB slave logic unit. The input terminal of the MVB communication physical layer circuit is connected to the FPGA chip; the output terminal of the MVB communication physical layer circuit is connected to the MVB-EMD interface; the MVB communication physical layer circuit is used to convert the logic level signal output by the FPGA chip to the EMD signal of the MVB bus; the MVB-EMD interface is used to connect to an external MVB bus. The MCU chip sends the MVB main logic unit configuration information to the UART transceiver unit of the MVB main logic unit; it converts the MVB main logic unit configuration information into a port traversal table and stores it in the port table unit. The MVB main logic control unit in the MVB main logic unit controls the MVB sending Manchester encoding and framing sending unit to send the MVB main frame to the MVB communication physical layer circuit according to the port traversal table stored in the port table unit. After the MVB main frame is sent, the MVB main logic control unit releases the sending control right of the MVB sending control unit to the MVB slave logic data and status control unit in the MVB slave logic unit. After obtaining the transmission control of the MVB transmission control unit from the logic data and status control unit, the MVB sends or receives data from the logic unit and the MVB bus.

2. The master-slave integrated MVB simulation test device based on FPGA and MCU according to claim 1, characterized in that: The MCU chip communicates with an external host computer via an Ethernet interface to receive data sent by the host computer and upload simulation test data.

3. The master-slave integrated MVB simulation test device based on FPGA and MCU according to claim 1, characterized in that: The MVB main logic unit includes a UART transceiver unit, a data packet assembly and command parsing unit, a command operation unit, a main transmission control unit, a transmission FIFO unit, an MVB main logic control unit, an MVB transmission Manchester encoding and framing transmission unit, a port table unit, and a receive FIFO unit. The UART transceiver unit is connected to the communication interface of the MCU chip and is used to receive data transmitted by the MCU chip. The data received from the MCU chip includes MVB main logic unit configuration information and main unit control instructions. The data packet and command parsing unit is used to parse the MVB main logic unit configuration information and main unit control instructions received by the UART transceiver unit. The command operation unit is used to generate operation instructions based on the parsed MVB main logic unit configuration information, and to start or stop the MVB main logic control unit based on the main unit control instructions. The port table unit is used to store the port traversal table obtained by converting the configuration information of the MVB main logic unit. The transmission FIFO unit is used to buffer the MVB main frame data to be transmitted; The main transmit control unit is used to control the transmit FIFO unit to transmit data to the UART transceiver unit.

4. The master-slave integrated MVB simulation test device based on FPGA and MCU according to claim 3, characterized in that: The UART transceiver unit communicates with the MCU chip. The data received by the UART transceiver unit is transmitted to the command operation unit through the data packet assembly and command parsing unit. After the MVB main logic control unit is started, the MVB main logic control unit updates the MVB main logic unit configuration information to the port table unit.

5. The master-slave integrated MVB simulation test device based on FPGA and MCU according to claim 1, characterized in that: The MVB slave logic unit includes an application access unit, a read FIFO unit, a write FIFO unit, a debugging unit, a port time update unit, a device control unit, a data storage unit, an application access memory interface unit, an MVB slave logic data and status control unit, a memory access control unit, a TX buffer unit, a slave logic MVB transmit Manchester encoding and framing transmission unit, an MVB receive RX unit, and an RX buffer unit. The application access unit is connected to the communication interface of the MCU chip and is used to interact with the MCU chip for data exchange. The write FIFO unit is used to cache the data to be sent from the MCU chip to the MVB slave logic data and status control unit; the data memory unit is used to store the MVB slave logic unit configuration information and interaction data. The MVB uses the logic data and status control unit to control the transmission of data between the data storage unit and other units, and to match the port information in the MVB master frame. The logical MVB sending Manchester encoding and framing unit is used to encode the data to be sent in Manchester and then frame it before transmitting it to the MVB communication physical layer circuit. The MVB receiving RX unit is used to decode and error-check the MVB main frame received by the MVB communication physical layer circuit, and store the checked data to the data memory unit. The read FIFO unit is used to cache the interactive data uploaded to the MCU chip; The port time update unit is used to update the interaction period of the MVB slave logic unit port; The debugging unit is used to debug the running status of the MVB slave logic unit; The memory access control unit is used to control read and write access to the data memory unit; The TX buffer unit is used to cache the slave frame data to be encoded.

6. The master-slave integrated MVB simulation test device based on FPGA and MCU according to claim 5, characterized in that: The application access control unit communicates with the MCU chip and parses the received data, sending it to the write FIFO unit. The MVB updates the data memory from the logic data and status control unit and sends it to the MVB bus through the logic MVB send Manchester encoding and framing unit. Data received from the MVB bus is decoded by the MVB receive RX unit and stored in the data memory unit. The MVB controls the data to be transmitted to the MCU chip via the application access unit.

7. The master-slave integrated MVB simulation and testing device based on FPGA and MCU according to claim 1, characterized in that: The MVB communication physical layer circuit includes a transformer T6, a differential operational amplifier chip U5, an operational amplifier chip U6, a pre-emphasis signal transmission chip U8, and a level conversion chip U7. One side of transformer T6 is connected to the MVB-EMD interface, and the other side of transformer T6 is connected to the input of differential operational amplifier U5. The output of differential operational amplifier U5 is connected to the input of operational amplifier U6. The output of operational amplifier U6 is connected to pin B of pre-emphasis signal transmitting chip U8. Pin A of pre-emphasis signal transmitting chip U8 is grounded. Pin RO of pre-emphasis signal transmitting chip U8 is connected to pin B of level conversion chip U7. Pin A of level conversion chip U7 is connected to pin VREFB1N0 of FPGA chip. Pin DE of pre-emphasis signal transmitting chip U8 is connected to pin IO_VB1N0_3 of FPGA chip. Pin DI of pre-emphasis signal transmitting chip U8 is connected to pin IO_VB1N0_2 of FPGA chip.

8. The master-slave integrated MVB simulation test device based on FPGA and MCU according to claim 1, characterized in that: The device body also includes a power supply circuit, an LED circuit, a DIP switch circuit, an FPGA configuration circuit, a USB circuit, a serial port debugging circuit, and an SD card circuit. The power supply circuit is used to provide operating power for the FPGA chip, MCU chip and various peripheral circuits; The LED circuit is used to indicate the operating status and communication status of the device; The DIP switch circuit is used to set the hardware parameters of the device; The FPGA configuration circuit is used for programming and configuring the FPGA chip. The USB circuit is used to enable USB data interaction between the device and external devices; The serial port debugging circuit is used for serial port debugging of the device; The SD card circuit is used to expand data storage capacity and store simulation test logs.

9. An MVB simulation testing method, characterized in that: The master-slave integrated MVB simulation test equipment based on FPGA and MCU as described in claim 1 is used. The MVB communication physical layer circuit in the master-slave integrated MVB simulation test equipment is connected to the MVB bus through the MVB-EMD interface; several systems under test to be tested are connected to the MVB bus. The testing method includes the following steps: The first step is that the MCU chip sends the MVB main logic unit configuration information to the UART transceiver unit of the MVB main logic unit; The MCU chip sends the MVB slave logic unit configuration information to the application access unit of the MVB slave logic unit; The second step is to convert the MVB main logic unit configuration information into a port traversal table and store it in the port table unit. The logic unit configuration information of the MVB is stored in the data storage module from the logic data and status control unit. The third step is for the MCU chip to send a master unit control command to start the MVB main logic control unit. After the MVB main logic control unit starts, the MVB bus enters the running state. The MVB main logic control unit reads the port numbers that need to be traversed from the port table in sequence, and sends the MVB main frame to the MVB bus through the MVB Manchester encoding and framing unit. After the MVB main frame is sent, the MVB main logic control unit releases the sending control of the MVB sending control unit to the MVB slave logic data and status control unit. Step 4: All systems under test on the MVB bus receive the MVB master frame. The MVB slave logic data and status control unit obtains the transmission control right of the MVB transmission control unit. The MVB receive RX unit receives the MVB master frame and sends it to the MVB slave logic data and status control unit. The MVB slave logic data and status control unit traverses the port configuration table of the data storage device. If a matching port is found, it prepares to receive or send data. If the matched port is the source port, the MVB reads the corresponding port data from the logic data and status control unit and sends it to the logic MVB sending Manchester encoding and framing unit for framing and encoding, and then sends it to the MVB bus. If the matched port is the destination port, the MVB receives the next packet of slave frame data from the logical data and status control unit and updates the corresponding port table in the data memory. Step 5: The MCU chip communicates with the application access module to write or read data from the data storage and transmit it to the host computer.

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