Address mapping method and device of logic unit, equipment and medium

Abstract

The invention provides an address mapping method and device of a logic unit, equipment and a medium, and relates to the technical field of chips. The method comprises the following steps: analyzing a bit stream file to obtain a corresponding relationship between a frame address corresponding to each configuration frame and a physical coordinate; identifying each key configuration bit according to the configuration bit identification file, and determining a configuration bit address of each key configuration bit in the configuration memory; determining a physical coordinate range of each logic unit in the FPGA according to the layout information, and determining a target frame address corresponding to the physical coordinate range based on the corresponding relationship; and determining a necessary bit based on the target frame address, and constructing an address mapping library according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bit. According to the method, the address mapping accuracy can be ensured while the address mapping efficiency of the logic unit is ensured, so that a reliable reference basis can be provided for tasks such as accurate fault analysis and radiation protection of the FPGA.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically, to an address mapping method, apparatus, device, and medium for logic units. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs), as highly flexible integrated circuits, occupy a pivotal position in many fields of today's digital age. From high-speed data processing in communications and real-time computing in image processing systems, to complex mission control in aerospace and precise control in industrial automation, FPGAs, with their reconfigurability and powerful parallel processing capabilities, provide efficient and customized solutions for various systems.

[0003] For tasks such as precise fault analysis and radiation protection in FPGAs, it is often necessary to clarify the mapping relationship between the physical location of each logic unit in the FPGA and its corresponding configuration memory location. However, currently, technicians can usually only infer some mapping relationships by consulting scattered documents, making it difficult to guarantee mapping efficiency and accuracy. Summary of the Invention

[0004] The problem addressed by this invention is how to improve the efficiency and accuracy of address mapping for logic units.

[0005] To address the above problems, this invention provides an address mapping method for logic units, comprising: The acquired bitstream file of the FPGA is parsed to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the configuration memory of the FPGA; wherein, the physical coordinates are used to indicate the area covered by the logic unit controlled by the corresponding configuration frame in the FPGA; Identify each key configuration bit in all configuration frames based on the obtained configuration bit identifier file, and determine the configuration bit address of each key configuration bit in the configuration memory; wherein, the configuration bit address includes the frame address, intra-frame word offset, and intra-word bit offset corresponding to the key configuration bit; Based on the obtained FPGA layout information, the physical coordinate range of each logic unit in the FPGA is determined, and the target frame address corresponding to the physical coordinate range is determined based on the correspondence. Based on the target frame address, the necessary bits are obtained by determining each of the key configuration bits used to control the logic unit, and an address mapping library for the logic unit is constructed according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bits.

[0006] Optionally, parsing the acquired FPGA bitstream file to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the FPGA's configuration memory includes: Retrieve the synchronization words in the bitstream file in a forward-to-back order; When the synchronization word is retrieved and the instruction information following the synchronization word is a frame address write command, the information following the frame address write command is used as the frame address; According to the preset bit field definition rules corresponding to the configuration memory, the physical region description corresponding to the frame address is determined, the physical region description is converted into the physical coordinates, and the frame address is associated with the corresponding physical coordinates to obtain the correspondence.

[0007] Optionally, the step of identifying each key configuration bit in all the configuration frames according to the acquired configuration bit identifier file, and determining the configuration bit address of each key configuration bit in the configuration memory, includes: The configuration bit corresponding to the preset identifier in the configuration bit identifier file is used as the key configuration bit, and the frame address, the intra-frame word offset and the intra-word bit offset corresponding to the key configuration bit are determined according to the preset mapping relationship to obtain the configuration bit address.

[0008] Optionally, determining the physical coordinate range of each logic unit within the FPGA based on the obtained FPGA layout information includes: Extract a set of constraint coordinates corresponding to each logical unit from the layout information, and obtain the physical coordinate range based on the set of constraint coordinates.

[0009] Optionally, determining the target frame address corresponding to the physical coordinate range based on the correspondence includes: The physical coordinates within the specified physical coordinate range are taken as the target physical coordinates; The frame address corresponding to the target physical coordinates is determined based on the correspondence, and the target frame address is obtained.

[0010] Optionally, determining the necessary bits for each of the key configuration bits used to control the logic unit based on the target frame address includes: The key configuration bit that is the same as the target frame address is used as the necessary bit.

[0011] Optionally, the address mapping library includes the physical coordinate range corresponding to the logical unit, and the configuration bit address of each necessary bit corresponding to the physical coordinate range.

[0012] In this invention, by parsing the acquired bitstream file of the FPGA, the correspondence between the frame address and physical coordinates of each configuration frame in the FPGA's configuration memory is obtained. This facilitates a coarse-grained association between the logical storage address (i.e., frame address) of the configuration frame and the physical address (i.e., physical coordinates) of the logic unit controlled by the configuration frame on the FPGA. A preliminary mapping between logical storage addresses and physical addresses is established at the configuration frame level, providing a foundation for subsequent refined address mapping. Simultaneously, this invention identifies each key configuration bit in all configuration frames based on the acquired configuration bit identifier file and determines the configuration bit address of each key configuration bit in the configuration memory. This not only accurately focuses on the key configuration bits that significantly influence the control of the logic units but also helps to determine the precise logical storage location of each key configuration bit in the configuration memory, providing crucial positioning information for constructing the address mapping library of the logic units. Based on this, this invention determines the physical coordinate range of each logic unit in the FPGA based on the acquired FPGA layout information and determines the target frame address corresponding to the physical coordinate range based on the correspondence. This invention facilitates the accurate definition of the actual coverage area of ​​logic units within an FPGA, and further utilizes the correspondence to associate the physical coordinate range of the logic unit with the target frame address corresponding to the relevant configuration frame in the configuration memory, enabling rapid location of the configuration frame controlling a specific logic unit. Furthermore, based on the target frame address, the invention determines the necessary bits for each key configuration bit used to control the logic unit, and combines the physical coordinate range of the logic unit with the configuration bit addresses of the necessary bits to construct an address mapping library for the logic unit. This achieves a fine-grained mapping between the physical address (i.e., physical coordinate range) of the logic unit in the FPGA and the corresponding logical storage address (i.e., configuration bit address) of each key configuration bit (i.e., necessary bit) controlling that physical area. While ensuring the efficiency of logic unit address mapping, it also ensures the accuracy of the address mapping, thereby providing a reliable reference for tasks such as accurate fault analysis and radiation protection of the FPGA.

[0013] The present invention also provides an address mapping device for logic units, comprising: The parsing module is used to parse the acquired bitstream file of the FPGA to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the configuration memory of the FPGA; wherein, the physical coordinates are used to indicate the area covered by the logic unit controlled by the corresponding configuration frame in the FPGA. The identification module is used to identify each key configuration bit in all the configuration frames according to the acquired configuration bit identifier file, and to determine the configuration bit address of each key configuration bit in the configuration memory; wherein, the configuration bit address includes the frame address, intra-frame word offset and intra-word bit offset corresponding to the key configuration bit; The determination module is used to determine the physical coordinate range of each logic unit in the FPGA based on the obtained layout information of the FPGA, and to determine the target frame address corresponding to the physical coordinate range based on the correspondence. The mapping module is used to determine the necessary bits for each of the key configuration bits used to control the logic unit based on the target frame address, and to construct the address mapping library of the logic unit according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bit.

[0014] The address mapping device for logic units provided by this invention has essentially the same advantages as the address mapping method for logic units compared to the prior art, and will not be elaborated further here.

[0015] The present invention also provides an electronic device, including a memory and a processor; The memory is used to store computer programs; The processor is used to implement the address mapping method of the logical units as described above when executing the computer program.

[0016] The address mapping method between the electronic device and the logic unit provided by this invention has essentially the same advantages as the prior art, and will not be elaborated further here.

[0017] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the address mapping method of the logic unit as described above.

[0018] The address mapping method between the computer-readable storage medium and the logical unit provided by this invention has essentially the same advantages as the prior art, and will not be repeated here. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the address mapping method for a logical unit according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the address mapping device for a logic unit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0020] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the accompanying drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0021] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0022] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments"; the term "optionally" means "optional embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this invention are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0023] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0024] like Figure 1 As shown in the figure, an address mapping method for a logic unit provided by an embodiment of the present invention includes the following steps: S1: Parse the obtained bitstream file of the FPGA to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the FPGA configuration memory; wherein, the physical coordinates are used to indicate the area covered by the logic unit controlled by the corresponding configuration frame in the FPGA.

[0025] Specifically, in this embodiment, the FPGA bitstream file refers to a binary file used for programming and configuring the FPGA, which may include all configuration information of the FPGA configuration memory. The configuration frame in this embodiment refers to a basic storage unit of the configuration memory; each configuration frame is typically used to control a specific logic unit in the FPGA. The physical coordinates in this embodiment refer to the location region on the FPGA chip used to define the logic unit controlled by the configuration frame (such as the logic chip corresponding to the physical coordinates).

[0026] Optionally, the acquired bitstream file of the FPGA is parsed to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the FPGA's configuration memory, including: Retrieve synchronization words from the bitstream file in front-to-back order; When a synchronization word is retrieved and the instruction information following the synchronization word is a frame address write command, the information following the frame address write command is used as the frame address; Based on the preset bit field definition rules corresponding to the configuration memory, the physical region description corresponding to the frame address is determined, the physical region description is converted into physical coordinates, and the frame address is associated with the corresponding physical coordinates to obtain the correspondence.

[0027] Specifically, in this embodiment, the synchronization word refers to a set of binary codes in the bitstream file that serves a specific identifying function, used to mark the start position of a specific information segment, facilitating accurate identification and processing of subsequent content. Different instruction information typically follows the synchronization word in the bitstream file, such as frame address write commands, configuration frame write commands, etc. Synchronization words can be searched in the bitstream file from front to back. When a synchronization word is found and the instruction information following it is a frame address write command, the information after the frame address write command can be used as the frame address. For example, after finding the synchronization word "10101010", subsequent instruction information is read. If the instruction information corresponds to a frame address write command (assuming its encoding is "0011"), then the information read afterward is the frame address.

[0028] In one embodiment, the preset bit field definition rules can represent the structural rules determined during the FPGA design phase, used to specify the attribute descriptions represented by different bit segments in the configuration memory. The frame address can be 32 bits, and different bit segments can contain different attribute descriptions. For example, a certain bit segment can indicate which half of the chip (i.e., the FPGA) the physical resource (such as a logic unit) controlled by the configuration frame represented by the frame address is located in, the type of physical resource (such as CLB, BRAM, IOB, etc.), or the row number and column number of the physical resource on the chip. After obtaining the frame address, the physical region description (such as the logical row number and logical column number) corresponding to the frame address can be determined according to the preset bit field definition rules. Through the device layout topology data or physical resource mapping table provided by the FPGA manufacturer, the physical region description is converted into the corresponding physical coordinate range (such as row coordinates and column coordinates), and the frame address is associated with the corresponding physical coordinates to obtain the correspondence, providing a basis for the subsequent accurate construction of the address mapping relationship of each logic unit.

[0029] S2: Identify each key configuration bit in all configuration frames based on the obtained configuration bit identifier file, and determine the configuration bit address of each key configuration bit in the configuration memory; wherein, the configuration bit address includes the frame address, intra-frame word offset and intra-word bit offset corresponding to the key configuration bit.

[0030] Specifically, in this embodiment, the configuration bit identifier file can be an EBD file. After the FPGA implementation is complete, the EBD file can be generated using design tools. The EBD file provides the tag type corresponding to each configuration bit in ASCII format. The tag type is stored in character form; the character "1" indicates a critical configuration tag, meaning that the configuration bit corresponding to that character is used to control a specific function of the logic unit. The character "0" indicates a non-critical configuration tag, meaning that the character is unrelated to the function control of the logic unit. Each critical configuration bit in all configuration frames can be identified based on the tag type corresponding to the character.

[0031] Optionally, based on the obtained configuration bit identifier file, each key configuration bit in all configuration frames is identified, and the configuration bit address of each key configuration bit in the configuration memory is determined, including: The configuration bit corresponding to the preset identifier in the configuration bit identifier file is taken as the key configuration bit, and the frame address, intra-frame word offset and intra-word bit offset corresponding to the key configuration bit are determined according to the preset mapping relationship to obtain the configuration bit address.

[0032] In one embodiment, the configuration bit corresponding to a preset identifier (e.g., the character "1") in the configuration bit identifier file can be used as the key configuration bit. Based on this, since there is a preset mapping relationship (e.g., linear correlation) between the logical storage address of the configuration bit in the configuration memory (i.e., the configuration bit address) and the EBD line number, the frame address, intra-frame word offset, and intra-word bit offset corresponding to the key configuration bit can be determined according to the preset mapping relationship and the position of the key configuration bit in the EBD, thereby determining the configuration bit address corresponding to the key configuration bit. For example, if each line of the EBD file consists of 32 characters (0 or 1), each corresponding to 32 bits of a configuration word, the frame address of each key configuration bit, the word offset within the frame (i.e., which 32-bit word), and the bit offset within the word (i.e., which position in the word) can be obtained to obtain the configuration bit address of the key configuration bit in the configuration memory. In this way, the key configuration bits that can affect the function of the logic unit, as well as the detailed addresses of each key configuration bit in the configuration memory, can be quickly extracted.

[0033] S3: Based on the obtained FPGA layout information, determine the physical coordinate range of each logic unit in the FPGA, and determine the target frame address corresponding to the physical coordinate range based on the correspondence.

[0034] Specifically, the layout information referred to in this embodiment represents information such as the specific location distribution of each logic unit on the chip in the FPGA. For example, in FPGA design tools (such as Vivado), after the implementation stage (including placement and routing) is completed, detailed placement and routing results will be automatically generated (which records the location attribute information corresponding to each logic unit), thereby obtaining the layout information.

[0035] Optionally, based on the obtained FPGA layout information, the physical coordinate range of each logic unit within the FPGA is determined, including: Extract a set of constraint coordinates corresponding to each logical unit from the layout information, and obtain the physical coordinate range based on the set of constraint coordinates.

[0036] In one embodiment, after obtaining the layout information, a set of constraint coordinates corresponding to each logical unit in the layout information can be extracted (the user pre-specifies the constraint area by setting pblock), and the physical coordinate range can be obtained based on this set of constraint coordinates. For example, assuming that the row coordinates are represented by X, the column coordinates are represented by Y, and the constraint coordinates include X30Y50 and X35Y50, then the physical coordinate range is the area covered by X30Y50 to X35Y50.

[0037] Optionally, determining the target frame address corresponding to the physical coordinate range based on the correspondence includes: Use the physical coordinates within the physical coordinate range as the target physical coordinates; The frame address corresponding to the target's physical coordinates is determined based on the correspondence, thus obtaining the target frame address.

[0038] Specifically, in this embodiment, after determining the physical coordinate range corresponding to each logic unit, the physical coordinates within that range can be obtained. The frame addresses corresponding to each physical coordinate are then obtained based on the correspondence, and these frame addresses are used as target frame addresses. In this way, the frame address of the configuration frame containing the configuration bit used to control the actual physical coordinate position of the logic unit can be quickly located, providing a data foundation for further determining the configuration bit addresses of the key configuration bits controlling the logic unit.

[0039] S4: Based on the target frame address, determine the necessary bits for each key configuration bit used to control the logic unit, and construct the address mapping library of the logic unit according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bit.

[0040] Optionally, the necessary bits are obtained by determining the key configuration bits for the control logic unit based on the target frame address, including: The critical configuration bits that are the same as the target frame address are designated as necessary bits.

[0041] Specifically, the frame address of the configuration frame obtained from parsing the bitstream file has a unique correspondence with the frame address in the configuration bit address corresponding to the key configuration bit. After obtaining the target frame address, the necessary bits for each key configuration bit used to control the logic unit can be determined based on the target frame address. For example, it can be determined whether the frame address in the configuration bit address of the key configuration bit is the same as the target frame address. When they are the same, the corresponding key configuration bit can be used as the necessary bit. Based on this, an address mapping library for the logic unit can be constructed according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bit.

[0042] Optionally, the address mapping library includes the physical coordinate range corresponding to the logical unit, and the configuration bit address of each necessary bit corresponding to the physical coordinate range.

[0043] In one embodiment, after determining the target frame address corresponding to the physical coordinate range of the logic unit, the necessary bits for controlling the logic unit can be obtained by determining the key configuration bits based on the target frame address. Furthermore, by associating the physical coordinate range corresponding to the logic unit with the configuration bit addresses of the necessary bits determined based on the physical coordinate range, an address mapping library can be constructed.

[0044] In this embodiment, by parsing the acquired bitstream file of the FPGA, the correspondence between the frame address and physical coordinates of each configuration frame in the FPGA's configuration memory is obtained. This facilitates a coarse-grained association between the logical storage address (i.e., frame address) of the configuration frame and the physical address (i.e., physical coordinates) of the logic unit controlled by the configuration frame on the FPGA. A preliminary mapping between logical storage addresses and physical addresses is established at the configuration frame level, providing a foundation for subsequent refined address mapping. Simultaneously, this embodiment identifies each key configuration bit in all configuration frames based on the acquired configuration bit identifier file and determines the configuration bit address of each key configuration bit in the configuration memory. This not only accurately focuses on the key configuration bits that significantly influence the control of the logic units but also helps to determine the precise logical storage location of each key configuration bit in the configuration memory, providing crucial positioning information for constructing the address mapping library of the logic units. Based on this, this embodiment determines the physical coordinate range of each logic unit in the FPGA according to the acquired FPGA layout information and determines the target frame address corresponding to the physical coordinate range based on the correspondence. This approach facilitates the accurate definition of the actual coverage area of ​​logic units within the FPGA. Furthermore, by leveraging the correspondence, the physical coordinate range of the logic unit is associated with the target frame address corresponding to the relevant configuration frame in the configuration memory, enabling rapid location of the configuration frame controlling a specific logic unit. Further, this embodiment determines the necessary bits for each key configuration bit used to control the logic unit based on the target frame address. Combining the physical coordinate range of the logic unit and the configuration bit addresses of the necessary bits, an address mapping library for the logic unit is constructed. This achieves a refined mapping between the physical address (i.e., physical coordinate range) of the logic unit in the FPGA and the corresponding logical storage address (i.e., configuration bit address) of each key configuration bit (i.e., necessary bit) controlling that physical area. While ensuring the efficiency of the logic unit address mapping, it also ensures the accuracy of the address mapping, thereby providing a reliable reference for tasks such as accurate fault analysis and radiation protection of the FPGA.

[0045] like Figure 2 As shown, an embodiment of the present invention provides an address mapping device 200 for a logic unit, comprising: The parsing module 210 is used to parse the acquired bitstream file of the FPGA to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the configuration memory of the FPGA; wherein, the physical coordinates are used to indicate the area covered by the logic unit controlled by the corresponding configuration frame in the FPGA. The identification module 220 is used to identify each key configuration bit in all the configuration frames according to the acquired configuration bit identifier file, and determine the configuration bit address of each key configuration bit in the configuration memory; wherein, the configuration bit address includes the frame address, intra-frame word offset and intra-word bit offset corresponding to the key configuration bit; The determination module 230 is used to determine the physical coordinate range of each logic unit in the FPGA based on the obtained layout information of the FPGA, and to determine the target frame address corresponding to the physical coordinate range based on the correspondence. The mapping module 240 is used to determine the necessary bits for each of the key configuration bits used to control the logic unit based on the target frame address, and to construct the address mapping library of the logic unit according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bit.

[0046] The address mapping device and address mapping method for logic units provided in this embodiment can produce basically the same technical effects, and will not be described in detail here.

[0047] like Figure 3 As shown, an electronic device 300 provided in this embodiment of the invention includes a memory 310 and a processor 320; the memory 310 is used to store a computer program; the processor 320 is used to implement the address mapping method of the logic unit as described above when the computer program is executed.

[0048] Alternatively, an electronic device 300 includes a memory 310 and a processor 320 coupled to the memory 310; the memory 310 is configured to store a computer program; and the processor 320 is configured to perform the following operations when the computer program is executed: The acquired bitstream file of the FPGA is parsed to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the configuration memory of the FPGA; wherein, the physical coordinates are used to indicate the area covered by the logic unit controlled by the corresponding configuration frame in the FPGA; Identify each key configuration bit in all configuration frames based on the obtained configuration bit identifier file, and determine the configuration bit address of each key configuration bit in the configuration memory; wherein, the configuration bit address includes the frame address, intra-frame word offset, and intra-word bit offset corresponding to the key configuration bit; Based on the obtained FPGA layout information, the physical coordinate range of each logic unit in the FPGA is determined, and the target frame address corresponding to the physical coordinate range is determined based on the correspondence. Based on the target frame address, the necessary bits are obtained by determining each of the key configuration bits used to control the logic unit, and an address mapping library for the logic unit is constructed according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bits.

[0049] The address mapping method between the electronic device and the logic unit provided in this embodiment can produce basically the same technical effect, and will not be described again here.

[0050] This invention provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the address mapping method for logical units as described above.

[0051] Alternatively, a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to perform the following operations: The acquired bitstream file of the FPGA is parsed to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the configuration memory of the FPGA; wherein, the physical coordinates are used to indicate the area covered by the logic unit controlled by the corresponding configuration frame in the FPGA; Identify each key configuration bit in all configuration frames based on the obtained configuration bit identifier file, and determine the configuration bit address of each key configuration bit in the configuration memory; wherein, the configuration bit address includes the frame address, intra-frame word offset, and intra-word bit offset corresponding to the key configuration bit; Based on the obtained FPGA layout information, the physical coordinate range of each logic unit in the FPGA is determined, and the target frame address corresponding to the physical coordinate range is determined based on the correspondence. Based on the target frame address, the necessary bits are obtained by determining each of the key configuration bits used to control the logic unit, and an address mapping library for the logic unit is constructed according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bits.

[0052] The address mapping method between the computer-readable storage medium and the logic unit provided in this embodiment can produce basically the same technical effect, and will not be described again here.

[0053] The present invention will now be described an electronic device 300 that can serve as a server or client of the present invention, which is an example of a hardware device that can be applied to various aspects of the present invention. Electronic device 300 is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic device 300 can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0054] Electronic device 300 includes a computing unit that can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) or a computer program loaded from a storage unit into random access memory (RAM). The RAM may also store various programs and data required for device operation. The computing unit, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0055] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. In this application, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention according to actual needs. Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units can be implemented in hardware or as software functional units.

[0056] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. A method for address mapping of logical units, characterized in that, include: The acquired bitstream file of the FPGA is parsed to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the configuration memory of the FPGA; wherein, the physical coordinates are used to indicate the area covered by the logic unit controlled by the corresponding configuration frame in the FPGA; Identify each key configuration bit in all configuration frames based on the obtained configuration bit identifier file, and determine the configuration bit address of each key configuration bit in the configuration memory; wherein, the configuration bit address includes the frame address, intra-frame word offset, and intra-word bit offset corresponding to the key configuration bit; Based on the obtained FPGA layout information, the physical coordinate range of each logic unit in the FPGA is determined, and the target frame address corresponding to the physical coordinate range is determined based on the correspondence. Based on the target frame address, the necessary bits are obtained by determining each of the key configuration bits used to control the logic unit, and an address mapping library for the logic unit is constructed according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bits.

2. The address mapping method for logic units according to claim 1, characterized in that, The step of parsing the acquired FPGA bitstream file to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the FPGA's configuration memory includes: Retrieve the synchronization words in the bitstream file in a forward-to-back order; When the synchronization word is retrieved and the instruction information following the synchronization word is a frame address write command, the information following the frame address write command is used as the frame address; According to the preset bit field definition rules corresponding to the configuration memory, the physical region description corresponding to the frame address is determined, the physical region description is converted into the physical coordinates, and the frame address is associated with the corresponding physical coordinates to obtain the correspondence.

3. The address mapping method for logic units according to claim 1, characterized in that, The step of identifying each key configuration bit in all configuration frames based on the acquired configuration bit identifier file, and determining the configuration bit address of each key configuration bit in the configuration memory, includes: The configuration bit corresponding to the preset identifier in the configuration bit identifier file is used as the key configuration bit, and the frame address, the intra-frame word offset and the intra-word bit offset corresponding to the key configuration bit are determined according to the preset mapping relationship to obtain the configuration bit address.

4. The address mapping method for logic units according to claim 1, characterized in that, The step of determining the physical coordinate range of each logic unit in the FPGA based on the obtained FPGA layout information includes: Extract a set of constraint coordinates corresponding to each logical unit from the layout information, and obtain the physical coordinate range based on the set of constraint coordinates.

5. The address mapping method for logic units according to claim 1, characterized in that, Determining the target frame address corresponding to the physical coordinate range based on the correspondence includes: The physical coordinates within the specified physical coordinate range are taken as the target physical coordinates; The frame address corresponding to the target physical coordinates is determined based on the correspondence, and the target frame address is obtained.

6. The address mapping method for logic units according to claim 1, characterized in that, The step of determining the necessary bits for each of the key configuration bits used to control the logic unit based on the target frame address includes: The key configuration bit that is the same as the target frame address is used as the necessary bit.

7. The address mapping method for logic units according to any one of claims 1-6, characterized in that, The address mapping library includes the physical coordinate range corresponding to the logical unit, and the configuration bit address of each necessary bit corresponding to the physical coordinate range.

8. An address mapping device for a logic unit, characterized in that, include: The parsing module is used to parse the acquired bitstream file of the FPGA to obtain the correspondence between the frame address and physical coordinates of each configuration frame in the configuration memory of the FPGA; wherein, the physical coordinates are used to indicate the area covered by the logic unit controlled by the corresponding configuration frame in the FPGA. The identification module is used to identify each key configuration bit in all the configuration frames according to the acquired configuration bit identifier file, and to determine the configuration bit address of each key configuration bit in the configuration memory; wherein, the configuration bit address includes the frame address, intra-frame word offset and intra-word bit offset corresponding to the key configuration bit; The determination module is used to determine the physical coordinate range of each logic unit in the FPGA based on the obtained layout information of the FPGA, and to determine the target frame address corresponding to the physical coordinate range based on the correspondence. The mapping module is used to determine the necessary bits for each of the key configuration bits used to control the logic unit based on the target frame address, and to construct the address mapping library of the logic unit according to the physical coordinate range corresponding to the logic unit and the configuration bit address corresponding to the necessary bit.

9. An electronic device, characterized in that, Including memory and processor; The memory is used to store computer programs; The processor is configured to implement the address mapping method for logical units as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the address mapping method for logical units as described in any one of claims 1 to 7.

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