Semiconductor device

Abstract

A semiconductor device includes a capacitor including a lower electrode, an upper electrode, and a dielectric layer between the lower electrode and the upper electrode, where at least one of the lower electrode and the upper electrode includes a nanolayer piezoelectric electrode, where the nanolayer piezoelectric electrode includes a plurality of first material layers and a plurality of second material layers that are alternately arranged, where the first material layers and the second material layers are alternately arranged. The plurality of first material layers includes indium oxide (In2O3), where the plurality of second material layers includes vanadium oxide (V2O5), where each of the plurality of first material layers includes a plurality of layers, and where each of the plurality of second material layers includes a single layer.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0060762, filed on May 8, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a capacitor. Background Technology

[0003] As semiconductor device dimensions shrink, the size of capacitors used in dynamic random access memory (DRAM) devices and similar devices is also decreasing. With smaller capacitor sizes, leakage current may increase. Accordingly, a high-k dielectric material that can be used as a dielectric layer is needed. Summary of the Invention

[0004] A semiconductor device including a capacitor is provided, which exhibits reduced leakage current and relatively high capacitance even in the high-frequency region by employing a novel electrode material with a high work function.

[0005] According to one aspect of this disclosure, a semiconductor device includes a capacitor comprising: a lower electrode; an upper electrode; and a dielectric layer between the lower electrode and the upper electrode, wherein at least one of the lower electrode and the upper electrode comprises a nanolaminated electrode comprising a plurality of alternating first material layers and a plurality of second material layers, wherein the plurality of first material layers comprises indium oxide (In2O3), wherein the plurality of second material layers comprises vanadium oxide (V2O5), wherein each of the plurality of first material layers comprises multiple layers, and wherein each of the plurality of second material layers comprises a single layer.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a capacitor including: a lower electrode; an upper electrode; and a dielectric layer between the lower electrode and the upper electrode, wherein at least one of the lower electrode and the upper electrode includes a nanolaminated electrode comprising a plurality of alternating first material layers and a plurality of second material layers, wherein the plurality of first material layers comprises indium oxide (In2O3), wherein the plurality of second material layers comprises vanadium oxide (V2O5), and wherein the work function of the nanolaminated electrode is in the range of 5.2 eV to 5.5 eV.

[0007] According to one aspect of this disclosure, a semiconductor device includes: a substrate; a contact structure on the substrate; a lower electrode on the contact structure, the lower electrode having a cylindrical shape and including a first nanolaminated electrode; a dielectric layer on the lower electrode; and an upper electrode on the dielectric layer, wherein the first nanolaminated electrode includes a plurality of alternating first material layers and a plurality of second material layers, wherein the plurality of first material layers include indium oxide (In2O3), wherein the plurality of second material layers include vanadium oxide (V2O5), wherein each of the plurality of first material layers includes multiple layers, and wherein each of the plurality of second material layers includes a single layer. Attached Figure Description

[0008] The above and other aspects and features of specific embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This shows a cross-sectional view of a semiconductor device according to one or more embodiments;

[0010] Figure 2A It shows Figure 1 A cross-sectional view of the lower electrode;

[0011] Figure 2B It shows Figure 1 A cross-sectional view of the upper electrode;

[0012] Figure 3 This shows a cross-sectional view of a semiconductor device according to one or more embodiments;

[0013] Figure 4 This shows a cross-sectional view of a semiconductor device according to one or more embodiments;

[0014] Figure 5 This shows a cross-sectional view of a semiconductor device according to one or more embodiments;

[0015] Figure 6 This is a timing diagram illustrating a method for manufacturing a nanolaminated electrode according to one or more embodiments;

[0016] Figure 7A This is a schematic flowchart illustrating the first material layer deposition cycle;

[0017] Figure 7B This is a schematic flowchart illustrating the deposition cycle of the second material layer;

[0018] Figure 8 This is an X-ray diffraction (XRD) analysis curve of a nanolaminated electrode according to one or more embodiments;

[0019] Figure 9 This is a graph showing the resistivity, carrier mobility, and carrier concentration of a nanolaminated electrode according to one or more embodiments;

[0020] Figure 10 This is a graph showing the binding energy of a nanolaminated electrode according to one or more embodiments, measured by ultraviolet photoelectron spectroscopy (UPS).

[0021] Figure 11 These are scanning electron microscope images of capacitors from comparative examples;

[0022] Figure 12 These are scanning electron microscope images of capacitors according to one or more embodiments;

[0023] Figure 13 This is a graph showing the capacitance of a capacitor relative to frequency according to one or more embodiments;

[0024] Figure 14 It is a graph showing the capacitance of a capacitor in the high-frequency region according to one or more embodiments;

[0025] Figure 15 It is a schematic performance diagram of the capacitor based on the comparative example;

[0026] Figure 16 This is a schematic performance diagram of a capacitor according to one or more embodiments;

[0027] Figure 17 This is a graph showing the current density of a capacitor relative to voltage according to one or more embodiments;

[0028] Figure 18 This shows a cross-sectional view of a semiconductor device according to one or more embodiments;

[0029] Figure 19 It shows Figure 18 A magnified view of region A;

[0030] Figure 20 This shows a cross-sectional view of a semiconductor device according to one or more embodiments;

[0031] Figure 21 This illustrates a cross-sectional view of a semiconductor device according to one or more embodiments; and

[0032] Figure 22 This is a cross-sectional view of a semiconductor device according to one or more embodiments. Detailed Implementation

[0033] In the following description, embodiments will be illustrated with reference to the accompanying drawings. In the drawings, the same elements are designated by the same reference numerals, and therefore, repeated descriptions will be omitted.

[0034] In the specification, the horizontal direction may include a first horizontal direction (X direction) and a second horizontal direction (Y direction) that intersect each other. The direction that intersects the first horizontal direction (X direction) and the second horizontal direction (Y direction) may be referred to as the vertical direction (Z direction). In the specification, the vertical horizontal may be referred to as the height horizontal along any configured vertical direction (Z direction).

[0035] As used in this article, multiple “units,” “modules,” “components,” and “blocks” can be implemented as a single component, or a single “unit,” “module,” “component,” and “block” can include multiple components.

[0036] It will be understood that when a component is referred to as being “connected” or “attached” to another component, it can be directly or indirectly connected to that other component.

[0037] Furthermore, when a component "comprises" or "includes" an element, the component may also include other elements without excluding them, unless there is a specific description to the contrary.

[0038] Throughout the description, when one component is "on" another component, it includes not only the case where the component is in contact with the other component, but also the case where there are other components between the two components.

[0039] As used herein, the expressions “at least one of a, b, or c” and “at least one of a, b, and c” mean “only a”, “only b”, “only c”, “both a and b”, “both a and c”, “both b and c”, and “all a, b, and c”.

[0040] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, this disclosure should not be limited by these terms. These terms are used only to distinguish one element from another.

[0041] As used in this article, the singular forms “a,” “one,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0042] For ease of description, identification codes may be used with respect to any methods or processes described herein, but are not intended to indicate the order of each step or operation. Each step or operation may be performed in a different order than that described, unless the context clearly indicates otherwise. One or more steps or operations may be omitted unless the context of this disclosure clearly indicates otherwise.

[0043] Figure 1 This is a cross-sectional view of a semiconductor device 1 according to one or more embodiments. Figure 2A It shows Figure 1 A cross-sectional view of the lower electrode 20. Figure 2B It shows Figure 1 A cross-sectional view of the upper electrode 40.

[0044] refer to Figure 1 The semiconductor device 1 may include a substrate 10, a lower electrode 20, a dielectric layer 30, and an upper electrode 40. The lower electrode 20, the dielectric layer 30, and the upper electrode 40 may constitute a capacitor. For example, the lower electrode 20, the dielectric layer 30, and the upper electrode 40 may constitute a capacitor having a metal-insulator-metal (MIM) structure.

[0045] In one or more embodiments, the lower electrode 20 may include, as referenced Figure 2A The nanolaminated electrode NE may include a plurality of alternating first material layers 22 and a plurality of second material layers 24.

[0046] In one or more embodiments, the plurality of first material layers 22 may include indium oxide. For example, the plurality of first material layers 22 may include indium oxide (In2O3). For example, the plurality of first material layers 22 may be formed using an atomic layer deposition (ALD) process, and each of the plurality of first material layers 22 may have a first thickness t11 of 1.5 nanometers to 11.5 nanometers.

[0047] In one or more embodiments, each of the plurality of first material layers 22 may have a multilayer structure formed by stacking a plurality of monolayers. As used herein, the term “monolayer” may refer to a single layer of material continuously connected by performing a unit cycle in an ALD process for stacking an atomic layer, an island-shaped particle, or an island-shaped aggregate.

[0048] For example, each of the plurality of first material layers 22 can be formed by repeating the first material layer deposition cycle of the ALD process "m" times, where m can be a natural number equal to or greater than 2 (e.g., 25, 50, 75, 100, 125 or 150).

[0049] In one or more embodiments, the plurality of second material layers 24 may include vanadium oxide. For example, the plurality of second material layers 24 may include vanadium oxide (V₂O₅). For example, each of the plurality of second material layers 24 may be formed using an ALD process. The thickness of each of the plurality of second material layers 24 in the vertical direction (Z-direction) may be less than the thickness of each of the plurality of first material layers 22 in the vertical direction (Z-direction). For example, each of the plurality of second material layers 24 may have a second thickness t₁₂ of 0.005 nm to 0.015 nm.

[0050] In one or more embodiments, each of the plurality of second material layers 24 may have a single-layer structure. In one or more embodiments, each of the plurality of second material layers 24 may include, for example: Figure 2A The diagram shows a continuously connected single layer. In one or more embodiments, each of the plurality of second material layers 24 may include island-shaped particles or aggregates disposed on the top surface of each of the plurality of first material layers 22. For example, each of the plurality of second material layers 24 may be formed by repeating the second material layer deposition cycle of the ALD process "n" times, where n may be a natural number from 1 to 5 (e.g., 1). The number of repetitions of the second material layer deposition cycle may be less than the number of repetitions of the first material layer deposition cycle. However, the number of repetitions of the first material layer deposition cycle and the number of repetitions of the second material layer deposition cycle are not limited to the numbers described and can be determined by taking into account the ratio of indium oxide and vanadium oxide included in the nanolaminated electrode NE.

[0051] The lower electrode 20 can be formed by repeating a first material layer deposition cycle for forming each of the plurality of first material layers 22 and a second material layer deposition cycle for forming each of the plurality of second material layers 24 in a certain proportion. The first and second material layer deposition cycles can be repeatedly performed. For example, a first material layer deposition cycle is performed such that the first material layer 22 has a first thickness t11, and then a second material layer deposition cycle is performed such that the second material layer has a second thickness t12, and then a first material layer deposition cycle is performed such that the first material layer 22 has a first thickness t11, and then a second material layer deposition cycle is performed such that the second material layer has a second thickness t12. Accordingly, the lower electrode 20 can have a thickness t10 of 10 nanometers to 50 nanometers.

[0052] In one or more embodiments, dielectric layer 30 may comprise a metal oxide as a high-k material. In one or more embodiments, dielectric layer 30 may comprise titanium oxide. In other embodiments, dielectric layer 30 may comprise at least one of zirconium oxide, hafnium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanum oxide.

[0053] The upper electrode 40 may include, as referenced Figure 2B The nanolaminated electrode NE can include a plurality of alternating first material layers 42 and a plurality of second material layers 44. The plurality of first material layers 42 can be configured similarly to the plurality of first material layers 22, and the plurality of second material layers 44 can be configured similarly to the plurality of second material layers 24.

[0054] For example, each of the plurality of first material layers 42 can be formed using an ALD process and can have a first thickness t21 of 1.5 nm to 11.5 nm. For example, each of the plurality of second material layers 44 can be formed using an ALD process and can have a second thickness t22 of 0.005 nm to 0.015 nm. The upper electrode 40 can have a thickness t20 of 10 nm to 50 nm.

[0055] In one or more embodiments, Figure 2A and Figure 2B The nanolaminated electrode NE shown can have a work function of 5.2 eV to 5.5 eV. Because the nanolaminated electrode NE has a stacked structure of indium oxide and vanadium oxide with a relatively high work function, according to the comparative example, the nanolaminated electrode NE can have a higher work function than electrodes including, for example, titanium nitride (TiN) (e.g., 4.5 eV).

[0056] In one or more embodiments, Figure 2A and Figure 2B The X-ray diffraction analysis of the nanolaminated electrode NE shows a first peak (211) originating from the plane of indium oxide with a cubic structure, a second peak (222) originating from the plane, and a third peak (400) originating from the plane of indium oxide. In the X-ray diffraction analysis of the indium oxide (In₂O₃) electrode according to the comparative example, the nanolaminated electrode NE and the indium oxide electrode can have substantially the same first and third peaks. The second peak of the nanolaminated electrode NE can be lower than that of the indium oxide electrode. For example, the second peak of the nanolaminated electrode NE can be lower than 30.76° and higher than 30.66°. This is likely because the ionic radius of vanadium atoms (approximately 0.79 Å) is smaller than that of indium atoms (approximately 0.8 Å), and therefore, vanadium atoms can occupy unoccupied interstitial positions of indium atoms, resulting in lattice contraction of the indium oxide crystal.

[0057] In one or more embodiments, Figure 2A and Figure 2B The nanolaminated electrode NE shown can have a carrier concentration equal to or higher than that of the indium oxide electrode, and can have a carrier mobility equal to or higher than that of the indium oxide electrode. Furthermore, Figure 2Aand Figure 2B The nanolaminated electrode NE can have a resistivity equal to or lower than that of the indium oxide electrode. For example, the resistivity of the nanolaminated electrode NE can be 0.1 to 1 times that of the indium oxide electrode.

[0058] In one or more embodiments, the lower electrode 20, the dielectric layer 30, and the upper electrode 40 may constitute a MIM-type capacitor, and each of the lower electrode 20 and the upper electrode 40 may include a nanolaminated electrode NE. In one or more embodiments, the lower electrode 20 and the upper electrode 40 may include a nanolaminated electrode NE.

[0059] In one or more embodiments, the lower electrode 20 may include a nanolaminated electrode NE, and the upper electrode 40 may not include the nanolaminated electrode NE, but may include at least one metal selected from metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), or tungsten (W); conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), or tungsten nitride (WN); and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), or strontium ruthenium oxide (SrRuO3). For example, the upper electrode 40 may include silver oxide (AgO).

[0060] In other embodiments, the lower electrode 20 may not include the nanolaminated electrode NE, and may include at least one metal selected from metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), or tungsten (W); conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), or tungsten nitride (WN); and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), or strontium ruthenium oxide (SrRuO3). For example, the lower electrode 20 may include silver oxide (AgO). The upper electrode 40 may include the nanolaminated electrode NE.

[0061] The nanolaminated electrode NE can have a higher work function than electrodes according to comparative examples (e.g., titanium nitride (TiN) electrodes), and can have a higher carrier concentration, higher carrier mobility, and lower resistivity than electrodes according to comparative examples (e.g., indium oxide (In2O3) electrodes). The work function, carrier concentration, carrier mobility, and resistivity of the nanolaminated electrode NE will be described in detail below.

[0062] A capacitor comprising a lower electrode 20, a dielectric layer 30, and an upper electrode 40 can have a relatively high capacitance value across the entire frequency range from low to high frequencies. When a capacitor is defined as having a first capacitance at 1 kHz and a second capacitance at 1 MHz, in one or more embodiments, the second capacitance can be greater than 40% of the first capacitance. For example, the second capacitance can be greater than 50% of the first capacitance.

[0063] Furthermore, since the nanolaminated electrode NE has a relatively high work function, the capacitor can have a relatively low leakage current by increasing the potential barrier between the nanolaminated electrode NE and the dielectric to effectively block the leakage path of the current.

[0064] Figure 3 This is a cross-sectional view of a semiconductor device 2 according to one or more embodiments. Except that the semiconductor device 2 includes a first lower electrode 20_1 and a second lower electrode 20_2, the semiconductor device 2 is similar to a reference... Figure 1 , Figure 2A and Figure 2B The semiconductor device 1 described is similar, and therefore, the differences from semiconductor device 1 will be described in detail.

[0065] refer to Figure 3 The semiconductor device 2 may include a substrate 10, a first lower electrode 20_1, a second lower electrode 20_2, a dielectric layer 30, and an upper electrode 40. The first lower electrode 20_1, the second lower electrode 20_2, the dielectric layer 30, and the upper electrode 40 may constitute a capacitor. For example, the first lower electrode 20_1, the second lower electrode 20_2, the dielectric layer 30, and the upper electrode 40 may constitute a MIM capacitor.

[0066] The first lower electrode 20_1 may be located on the substrate 10, and the second lower electrode 20_2 may be located on the first lower electrode 20_1. The second lower electrode 20_2 may be located between the first lower electrode 20_1 and the dielectric layer 30.

[0067] In one or more embodiments, the first lower electrode 20_1 may not include, as referenced Figure 2AThe nanolaminated electrode NE may include at least one metal selected from metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), or tungsten (W); conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), or tungsten nitride (WN); and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), or strontium ruthenium oxide (SrRuO3). For example, the first lower electrode 20_1 may include a monolayer electrode (e.g., an electrode including titanium nitride (TiN)). In one or more embodiments, the second lower electrode 20_2 may include as referenced Figure 2A The nanolaminated electrode NE. Each of the first lower electrode 20_1 and the second lower electrode 20_2 may have a thickness of 10 nanometers to 50 nanometers in the vertical direction (Z direction).

[0068] Figure 4 This is a cross-sectional view of a semiconductor device 3 according to one or more embodiments. Except that the semiconductor device 3 includes a first upper electrode 40_1 and a second upper electrode 40_2, the semiconductor device 3 is similar to a reference... Figure 1 , Figure 2A and Figure 2B The semiconductor device 1 described is similar, and therefore, the differences from semiconductor device 1 will be described in detail.

[0069] refer to Figure 4 The semiconductor device 3 may include a substrate 10, a lower electrode 20, a dielectric layer 30, a first upper electrode 40_1, and a second upper electrode 40_2. The lower electrode 20, the dielectric layer 30, the first upper electrode 40_1, and the second upper electrode 40_2 may constitute a capacitor. For example, the lower electrode 20, the dielectric layer 30, the first upper electrode 40_1, and the second upper electrode 40_2 may constitute a MIM capacitor.

[0070] The first upper electrode 40_1 may be located on the dielectric layer 30, and the second upper electrode 40_2 may be located on the first upper electrode 40_1. The first upper electrode 40_1 may be located between the dielectric layer 30 and the second upper electrode 40_2.

[0071] In one or more embodiments, the first upper electrode 40_1 may include, as referenced Figure 2B The nanolaminated electrode NE is described above. In one or more embodiments, the second upper electrode 40_2 may not include, as referenced... Figure 2BThe nanolaminated electrode NE may include at least one metal selected from metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), or tungsten (W); conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), or tungsten nitride (WN); and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), or strontium ruthenium oxide (SrRuO3). For example, the second upper electrode 40_2 may include a monolayer electrode (e.g., an electrode including titanium nitride (TiN)). Each of the first upper electrode 40_1 and the second upper electrode 40_2 may have a thickness of 10 nanometers to 50 nanometers in the vertical direction (Z direction).

[0072] Figure 5 This is a cross-sectional view showing a semiconductor device 4 according to one or more embodiments. Except that the semiconductor device 4 includes a first lower electrode 20_1, a second lower electrode 20_2, a first upper electrode 40_1, and a second upper electrode 40_2, the semiconductor device 4 is similar to a reference... Figure 1 , Figure 2A and Figure 2B The semiconductor device 1 described is similar, and therefore, the differences from semiconductor device 1 will be described in detail.

[0073] refer to Figure 5 The semiconductor device 4 may include a substrate 10, a first lower electrode 20_1, a second lower electrode 20_2, a dielectric layer 30, a first upper electrode 40_1, and a second upper electrode 40_2. The first lower electrode 20_1, the second lower electrode 20_2, the dielectric layer 30, the first upper electrode 40_1, and the second upper electrode 40_2 may constitute a capacitor. For example, the first lower electrode 20_1, the second lower electrode 20_2, the dielectric layer 30, the first upper electrode 40_1, and the second upper electrode 40_2 may constitute a MIM capacitor.

[0074] The first lower electrode 20_1 may be located on the substrate 10, and the second lower electrode 20_2 may be located on the first lower electrode 20_1. The second lower electrode 20_2 may be located between the first lower electrode 20_1 and the dielectric layer 30.

[0075] In one or more embodiments, the first lower electrode 20_1 may not include, as referenced Figure 2A The nanolaminated electrode NE is described above. For example, the first lower electrode 20_1 may include a monolayer electrode (e.g., an electrode comprising titanium nitride (TiN)). In one or more embodiments, the second lower electrode 20_2 may include, as referenced... Figure 2AThe nanolaminated electrode NE. Each of the first lower electrode 20_1 and the second lower electrode 20_2 may have a thickness of 10 nanometers to 50 nanometers in the vertical direction (Z direction).

[0076] The first upper electrode 40_1 may be located on the dielectric layer 30, and the second upper electrode 40_2 may be located on the first upper electrode 40_1. The first upper electrode 40_1 may be located between the dielectric layer 30 and the second upper electrode 40_2.

[0077] In one or more embodiments, the first upper electrode 40_1 may include, as referenced Figure 2B The nanolaminated electrode NE is described above. In one or more embodiments, the second upper electrode 40_2 may not include, as referenced... Figure 2B The nanolaminated electrode NE is described above. For example, the second upper electrode 40_2 may include a monolayer electrode (e.g., an electrode comprising titanium nitride (TiN)). Each of the first upper electrode 40_1 and the second upper electrode 40_2 may have a thickness of 10 nanometers to 50 nanometers in the vertical direction (Z direction).

[0078] refer to Figure 3 The described capacitor includes a first lower electrode 20_1, a second lower electrode 20_2, a dielectric layer 30, and an upper electrode 40, and a reference electrode. Figure 4 The description includes a lower electrode 20, a dielectric layer 30, a first upper electrode 40_1 and a second upper electrode 40_2, and a reference. Figure 5 The capacitor described, comprising a first lower electrode 20_1, a second lower electrode 20_2, a dielectric layer 30, a first upper electrode 40_1, and a second upper electrode 40_2, can have a relatively high capacitance value across the entire frequency range from low frequency to high frequency, and can have a relatively low leakage current due to the nanolaminated electrode NE having a relatively high work function.

[0079] Figure 6 This is a timing diagram illustrating a method DP for manufacturing a nanolaminated electrode according to one or more embodiments. Figure 7A This schematically illustrates the flowchart of the first material layer deposition cycle DP_A. Figure 7B This schematically illustrates the flowchart of the second material layer deposition cycle DP_B.

[0080] refer to Figure 6 , Figure 7A and Figure 7BThe method for fabricating nanolaminated electrodes (DP) can be based on atomic layer deposition (ALD) processes. For example, a first material layer deposition cycle DP_A and a second material layer deposition cycle DP_B can be sequentially performed on a substrate in a reaction chamber, and the nanolaminated electrode can be formed by repeating the first material layer deposition cycle DP_A and the second material layer deposition cycle DP_B. The first material layer deposition cycle DP_A and the second material layer deposition cycle DP_B can be collectively referred to as the material layer-to-material layer deposition cycle.

[0081] For example, a nanolaminated electrode can be formed by sequentially executing the first period DP_A1 of the first material layer, the first period DP_B1 of the second material layer, the second period DP_A2 of the first material layer, the second period DP_B2 of the second material layer, and then executing the k-th period DP_Ak of ​​the first material layer and the k-th period DP_Bk of the second material layer. Figure 6 As shown. That is, the material layer can be repeated k times for the deposition cycle. The number of times the material layer is repeated for the deposition cycle can be determined by taking into account the total thickness of the nanolaminated electrode and the growth rate of each of the first and second material layers in the deposition cycle.

[0082] like Figure 7A As shown, the first material layer deposition cycle DP_A may include a unit cycle, which sequentially includes a first metal source supply operation containing indium (operation S12), a first cleaning operation (operation S14), a first oxygen source supply operation (operation S16), and a second cleaning operation (operation S18). The first material layer deposition cycle DP_A may include an operation that repeats the unit cycle m times (operation S20), where the unit cycle sequentially includes the first metal source supply operation (operation S12), the first cleaning operation (operation S14), the first oxygen source supply operation (operation S16), and the second cleaning operation (operation S18). For example, m may be 25 to 150, or 50 to 125, or 60 to 100. For example, m may be 25, 50, 75, 100, 125, or 150.

[0083] In one or more embodiments, during the first metal source supply operation (operation S12), a first metal source may be supplied to the reaction chamber, and the first metal source may be an organometallic precursor including indium. The first metal source may include at least one selected from trimethylindium (In(CH3)3, TMIn), [1,1,1-trimethyl-N-(trimethylsilyl)silaneamine]indium (InCA-1), [3-(dimethylamino)propyl]dimethylindium (DADI), and cyclopentadienylindium (InCp). In one or more embodiments, the first metal source may be, but is not limited to, DADI. For example, the first metal source supply operation (operation S12) may be performed for a duration of 0.5 seconds to 3 seconds.

[0084] Next, in the first cleaning operation (operation S14), the remaining first metal source that is not adsorbed on the substrate can be cleaned and / or removed. In the first cleaning operation (operation S14), for example, an argon source including argon gas (Ar) can be supplied for a period of 10 to 20 seconds.

[0085] In the first oxygen source supply operation (operation S16), a first oxygen source may be supplied to the reaction chamber, and the first oxygen source may include at least one of hydrogen peroxide, oxygen, ozone, and oxygen plasma. The first oxygen source may also be referred to as a reactant. In the first oxygen source supply operation (operation S16), a reaction may occur between the first metal source adsorbed on the substrate and the first oxygen source to form a first material layer comprising indium oxide. For example, the first oxygen source supply operation (operation S16) may be performed for a duration of 0.5 seconds to 20 seconds.

[0086] Next, in the second cleaning operation (operation S18), the remaining first oxygen source that is not adsorbed on the substrate can be cleaned and / or removed. In the second cleaning operation (operation S18), for example, after exposure to an argon source including argon gas (Ar) for 3 to 7 seconds, an argon source can be supplied for 20 to 40 seconds.

[0087] For example, an indium oxide layer with a thickness of about 0.07 nm to about 0.08 nm can be formed for a unit cycle comprising a first metal source supply operation (operation S12), a first scavenging operation (operation S14), a first oxygen source supply operation (operation S16), and a second scavenging operation (operation S18). In the first material layer deposition cycle DP_A, when the number of repetitions m per unit cycle is less than 25, the first material layer (indium oxide) may be difficult to form to a sufficiently large thickness for crystallization, and when m is greater than 150, the first material layer (indium oxide) may form to an excessively large thickness. Therefore, the nanolaminated electrode may have a relatively high resistivity or a relatively low carrier concentration and carrier mobility.

[0088] like Figure 7B As shown, the second material layer deposition cycle DP_B can include a unit cycle, which sequentially includes a second metal source supply operation containing vanadium (operation S32), a first scavenging operation (operation S34), a second oxygen source supply operation (operation S36), and a second scavenging operation (operation S38). The second material deposition cycle DP_B can also include an operation that repeats the unit cycle n times (operation S40), where the unit cycle sequentially includes the second metal source supply operation (operation S32), the first scavenging operation (operation S34), the second oxygen source supply operation (operation S36), and the second scavenging operation (operation S38). Here, n can be 1 to 5 (e.g., 1).

[0089] In one or more embodiments, during the second metal source supply operation (operation S32), a second metal source may be supplied to the reaction chamber, and the second metal source may be an organometallic precursor including vanadium. The second metal source may include at least one of tetrakis(dimethylamino)vanadium, tetrakis(ethylmethylamino)vanadium (TEMAV), triisopropylvanadium oxide (VOIP), triisopropoxide vanadium (VTIP), VCl3, and VCl4. However, this is merely an example, and the second metal source is not limited to the materials described above. In one or more embodiments, the second metal source may be, but is not limited to, VTIP. For example, the second metal source supply operation (operation S32) may be performed for a duration of 0.5 seconds to 5 seconds.

[0090] Next, in the first cleaning operation (operation S34), any remaining second metal source that is not adsorbed on the substrate can be cleaned and / or removed. In the first cleaning operation (operation S34), for example, an argon source including argon gas (Ar) can be supplied for a period of 10 to 20 seconds.

[0091] In the second oxygen source supply operation (operation S36), a second oxygen source can be supplied to the reaction chamber, and the second oxygen source may include at least one of hydrogen peroxide, oxygen, ozone, and oxygen plasma. The second oxygen source may also be referred to as a reactant. In the second oxygen source supply operation (operation S36), a reaction can occur between the second metal source adsorbed on the first material layer and the second oxygen source to form a second material layer comprising vanadium oxide. For example, a monolayer of vanadium oxide can be formed on the first material layer. For example, the second oxygen source supply operation (operation S36) can be performed for a duration of 0.5 seconds to 20 seconds.

[0092] Next, in the second cleaning operation (operation S38), any remaining second oxygen source not adsorbed on the substrate can be cleaned and / or removed. In the second cleaning operation (operation S38), for example, after exposure to an argon source including argon gas (Ar) for 3 to 7 seconds, an argon source can be supplied for 20 to 40 seconds.

[0093] For example, a vanadium oxide layer with a thickness of 0.005 nm to 0.015 nm can be formed for a unit cycle comprising a second metal source supply operation (operation S32), a first scavenging operation (operation S34), a second oxygen source supply operation (operation S36), and a second scavenging operation (operation S38). Here, "n" (as described in operation S40) can be 1 to 5 (e.g., 1).

[0094] In one or more embodiments, the vanadium oxide layer may be formed as a single layer continuously connected on the top surface of the indium oxide layer, or it may be formed as island-shaped particles or aggregates located on the top surface of the indium oxide layer.

[0095] When the ratio (m:n) of the number of repetitions of the first material layer deposition cycle DP_A to the number of repetitions of the second material layer deposition cycle DP_B is in the range of 25:1 to 150:1, the nanolaminated electrode can be formed with high work function, high carrier concentration, high carrier mobility and low resistivity.

[0096] In the following text, referring to Experimental Example 1 regarding the ratio (m:n) of the number of repetitions of the first material layer deposition cycle DP_A to the number of repetitions of the second material layer deposition cycle DP_B, we will... Figures 8 to 10 The description details the change in electrical properties of the nanolaminated electrode as a function of the ratio of the number of repetitions of the first material layer deposition cycle DP_A to the number of repetitions of the second material layer deposition cycle DP_B.

[0097] Experimental Example 1

[0098] A nanolaminated electrode with a thickness of approximately 20 nm was formed by repeating a first material layer deposition cycle DP_A and a second material layer deposition cycle DP_B on a substrate in an ALD device at ratios of 150:1, 100:1, 75:1, 50:1, and 25:1. An indium oxide layer with a thickness of approximately 0.076 nm can be formed by performing one first material layer deposition cycle DP_A, and a vanadium oxide layer with a thickness of approximately 0.01 nm can be formed by performing one second material layer deposition cycle DP_B. As a comparative example, a monolayer electrode of indium oxide (In₂O₃) was formed by performing only the first material layer deposition cycle DP_A.

[0099] Table 1:

[0100] Table 2:

[0101] Figure 8 This is an X-ray diffraction analysis curve of a nanolaminated electrode according to one or more embodiments.

[0102] refer to Figure 8 X-ray diffraction analysis curves of Examples 1 to 5 and X-ray diffraction analysis curves of comparative examples. Figure 1The following are shown. Referring to the X-ray diffraction analysis curves of Examples 1 to 5, a first peak (211), a second peak (222), and a third peak (400) originating from the plane of indium oxide having a cubic crystal structure are shown. It was found that in the comparative example and Examples 1 to 5, the first and third peaks have substantially the same or similar values, but the second peak has different values. It was found that the second peak has a smaller value in Examples 1 to 5 compared to the comparative example. For example, the second peak was found to have a value of 30.74° in Example 1, approximately 30.74° in Example 2, approximately 30.72° in Example 3, approximately 30.72° in Example 4, approximately 30.70° in Example 5, and approximately 30.76° in the comparative example. This is likely because in Examples 1 to 5, the ionic radius of vanadium atoms (approximately 0.79 Å) is smaller than that of indium atoms (approximately 0.8 Å), and therefore, vanadium atoms can occupy unoccupied interstitial positions of indium atoms, resulting in lattice contraction of the indium oxide crystal. Accordingly, as the proportion of vanadium oxide increases, the second peak can shift to a lower angle.

[0103] Figure 9 The graph shows the resistivity, carrier mobility, and carrier concentration of a nanolaminated electrode according to one or more embodiments.

[0104] refer to Figure 9 It was found that the resistivity, carrier mobility, and carrier concentration of Examples 1 to 5 were equal to or better than those of the comparative examples. Specifically, Example 3, with an In2O3:V2O5 ratio of 75:1, was found to have the lowest resistivity (e.g., 4.08 × 10⁻⁶). -4 The highest carrier concentration (Ω•cm) and the highest carrier mobility (52.1 cm⁻¹) were observed. 2 / V•s). In Examples 1 to 3, it was found that as the In₂O₃:V₂O₅ ratio changed from 150:1 to 75:1 (i.e., as the vanadium oxide content increased), the resistivity decreased, and the carrier concentration and carrier mobility increased. In Examples 3 to 5, it was found that as the In₂O₃:V₂O₅ ratio changed from 75:1 to 25:1 (i.e., as the vanadium oxide content increased), the resistivity increased, and the carrier concentration and carrier mobility decreased. This may be because vanadium oxide causes amorphization of indium oxide, or due to the scattering effect caused by excess vanadium oxide leading to a decrease in carrier concentration and carrier mobility.

[0105] Figure 10 This is a graph showing the binding energy of a nanolaminated electrode according to one or more embodiments, measured by ultraviolet photoelectron spectroscopy (UPS).

[0106] refer to Figure 10 The binding energies of Examples 1 to 5 are shown together with those of Comparative Example 1 (Indium oxide (In2O3)), Comparative Example 2 (Indium tin oxide (ITO)), and Comparative Example 3 (Titanium nitride (TiN)). Table 3 shows the work functions of Examples 1 to 5, Comparative Example 1, and Comparative Example 2 calculated based on the binding energies measured by UPS.

[0107] Table 3:

[0108] As shown in Table 3, it was found that the binding energy decreased and the work function increased with increasing vanadium oxide content. Furthermore, the work functions of Examples 1 to 5 were found to be 5.2 eV to 5.5 eV, which are higher than those of Comparative Examples 1 to 3.

[0109] Figure 11 The image is a scanning electron microscope image of a capacitor based on a comparative example. Figure 12 This is a scanning electron microscope image of a capacitor according to an embodiment.

[0110] refer to Figure 11 The comparison example capacitor was found to contain titanium nitride (TiN) as the bottom electrode, titanium oxide (TiO2) as the dielectric layer, and silver (Ag) as the top electrode. (Reference) Figure 12 It was found that the capacitor according to the embodiment includes a nanolaminated electrode (In2O3:V2O5) as the lower electrode, titanium oxide (TiO2) as the dielectric layer, and silver (Ag) as the upper electrode. This finding is consistent with... Figure 11 The lower electrode of the comparative example is similar, according to Figure 12 The lower electrode (nanolaminated electrode) of the embodiment is a continuous material layer covering the entire substrate and is formed to a uniform thickness. Furthermore, it was found that the interface between the lower electrode (nanolaminated electrode) and the dielectric layer according to the embodiment has good interface characteristics, with no interface defects (e.g., voids or seams).

[0111] The capacitor described below according to the comparative example, and according to Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 The capacitors in the embodiments respectively have capacitors according to the comparative example, and capacitors according to... Figure 11 and Figure 12 The configuration of the capacitor in the embodiment.

[0112] Figure 13 This is a graph showing the capacitance of a capacitor relative to frequency according to an embodiment. Figure 14 This is a graph showing the capacitance of the capacitor in the high-frequency region according to an embodiment.

[0113] refer to Figure 13 and Figure 14 The capacitor according to the comparative example has a high capacitance of 750 pF to 800 pF in the low-frequency region of about 1 kHz, but the capacitance decreases with increasing frequency. The capacitor according to the comparative example also has a capacitance of 200 pF to 250 pF in the high-frequency region of about 1 MHz. On the other hand, the capacitor according to the embodiment (including a nanolaminated electrode) has a high capacitance of 800 pF to 850 pF in the low-frequency region of about 1 kHz, and the capacitance decreases with increasing frequency, but the decrease is relatively slow compared to the capacitor according to the comparative example. The capacitor according to the embodiment also has a capacitance of 450 pF to 500 pF in the high-frequency region of 1 MHz. It was found that in the high-frequency region (e.g., 1 MHz), the capacitance of the capacitor according to the embodiment is 1.5 to 2.5 times that of the capacitor according to the comparative example.

[0114] Typically, in the low-frequency region, the equivalent series resistance component refers to the value corresponding to the dielectric loss due to dielectric relaxation. As the frequency increases, the effects of series resistance and inductance become dominant, and therefore, the capacitance decreases, and the equivalent series resistance is affected by the losses due to electrodes.

[0115] The capacitor according to the embodiment has a dielectric loss factor of 0.1 to 0.2 at 1 MHz (e.g., about 0.115), while the capacitor according to the comparative example has a dielectric loss factor of about 1.46 at 1 MHz. Accordingly, the capacitor according to the embodiment is found to have a significantly lower dielectric loss factor than the capacitor according to the comparative example. This is likely due to the relatively low resistivity (i.e., relatively low series resistance) and relatively high carrier concentration and mobility of the nanolaminated electrodes included in the capacitor according to the embodiment. It can be assumed that the capacitor according to the embodiment has a relatively high capacitance value due to the significantly lower dielectric loss factor.

[0116] Figure 15 The schematic performance diagram EB_1 is based on the capacitor of the comparative example. Figure 16 EB_2 is a schematic performance diagram of a capacitor according to an embodiment.

[0117] refer to Figure 15In the capacitor according to the comparative example, the work function WF1 of the lower electrode (TiN) is approximately 4.5 eV, the conduction band EC of the dielectric layer (TiO2) is approximately 4.2 eV, and the difference between the work function WF1 of the lower electrode (TiN) and the conduction band EC of the dielectric layer (TiO2) is relatively small. Correspondingly, the band shift BO_1 at the interface between the lower electrode and the dielectric layer can have a relatively small value. When the band shift at the interface between the lower electrode and the dielectric layer is small, leakage current due to thermionic emission may occur.

[0118] refer to Figure 16 In the capacitor according to the embodiment, the work function WF2 of the lower electrode (In2O3:V2O5) is 5.2 eV to 5.5 eV, the conduction band EC of the dielectric layer (TiO2) is about 4.2 eV, and the difference between the work function WF2 of the lower electrode (In2O3:V2O5) and the conduction band EC of the dielectric layer (TiO2) is relatively large. Accordingly, the band shift BO_2 at the interface between the lower electrode and the dielectric layer can have a relatively large value. When the band shift at the interface between the lower electrode and the dielectric layer is large, leakage current due to thermionic emission can be significantly reduced or prevented.

[0119] Figure 17 This is a graph showing the current density of the capacitor relative to the voltage according to an embodiment.

[0120] refer to Figure 17 The capacitor in the comparison example was found to have a capacitance of 4.77 × 10⁻⁶ at 1V. -6 The leakage current density, while the capacitor in the example has 4.10 × 10⁻⁶ at 1V. -9 The leakage current density is lower, and therefore, the leakage current density of the capacitor according to the embodiment is 1800 times or more lower than that of the capacitor according to the comparative example.

[0121] The narrow bandgap of titanium oxide used as a dielectric layer may result in a large leakage current due to Schottky emission at the interface between the dielectric layer and the electrode. However, because the nanolaminated electrode included in the capacitor according to the embodiment has a relatively high work function as described above, the potential barrier between the electrode and the dielectric layer can be increased to effectively block the leakage path of the current, thereby reducing the leakage current of the capacitor.

[0122] Figure 18 This is a cross-sectional view of a semiconductor device 100 according to one or more embodiments. Figure 19 It shows Figure 18 A magnified view of region A.

[0123] refer to Figure 18 and Figure 19The semiconductor device 100 may include a dynamic random access memory (DRAM) device and may include a unit transistor formed on a substrate 110 and a capacitor CAP electrically connected to the unit transistor.

[0124] A lower insulating layer 112 may be located on a substrate 110, and a contact structure 114 may be located on the substrate 110 to penetrate the lower insulating layer 112. The contact structure 114 may include a conductive material. An etch stop film 116 having an opening through which the top surface of the contact structure 114 is exposed may be located on the lower insulating layer 112.

[0125] A capacitor CAP may be located on an etch stop film 116. The capacitor CAP may include a lower electrode 120, a dielectric layer 130, and an upper electrode 140. The lower electrode 120 may have a cylindrical shape, with its bottom sidewalls surrounded by the etch stop film 116, and its bottom surface located on the top surface of the contact structure 114. The lower electrode 120 may have a relatively large height in the vertical direction or a large aspect ratio, and a support member 118 may be located on the sidewalls of the lower electrode 120. The dielectric layer 130 may be conformally located on the inner and outer walls of the lower electrode 120. The upper electrode 140 may be located on the dielectric layer 130 to cover the lower electrode 120.

[0126] In one or more embodiments, the lower electrode 120 may include a plurality of alternating first material layers 122 and a plurality of second material layers 124. The lower electrode 120 may have a similar shape to the reference electrode. Figure 2A The structure of the described nanolaminated electrode NE is similar to that of other structures. For example, the plurality of first material layers 122 may comprise a multilayer containing indium oxide, and the plurality of second material layers 124 may comprise a monolayer containing vanadium oxide.

[0127] In one or more embodiments, dielectric layer 130 may comprise a metal oxide as a high-k material. In one or more embodiments, dielectric layer 130 may comprise titanium oxide. In other embodiments, dielectric layer 130 may comprise at least one of zirconium oxide, hafnium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium oxide, scandium oxide, and lanthanum oxide.

[0128] In one or more embodiments, the upper electrode 140 may include a plurality of alternating first material layers 142 and a plurality of second material layers 144. The upper electrode 140 may have a reference [material layer]. Figure 2B The structure of the described nanolaminated electrode NE is similar to that of other structures. For example, the plurality of first material layers 142 may comprise a multilayer containing indium oxide, and the plurality of second material layers 144 may comprise a monolayer containing vanadium oxide.

[0129] Figure 20This is a cross-sectional view of a semiconductor device 100A according to one or more embodiments.

[0130] refer to Figure 20 The lower electrode 120 may be a nanolaminated electrode comprising a plurality of alternating first material layers 122 and a plurality of second material layers 124, and the upper electrode 140A may comprise at least one selected from metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo) or tungsten (W), conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN) or tungsten nitride (WN), and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2) or strontium ruthenium oxide (SrRuO3).

[0131] Figure 21 This is a cross-sectional view of a semiconductor device 100B according to one or more embodiments.

[0132] refer to Figure 21 The lower electrode 120A may have a cylindrical shape located on the top surface of the contact structure 114 and extending in the vertical direction. The dielectric layer 130 may be conformally located on the top surface and sidewalls of the lower electrode 120A.

[0133] In one or more embodiments, the lower electrode 120A may include an integrated material layer extending in a vertical direction, and the lower electrode 120A may include a reference. Figure 2A The nanolaminated electrode NE is described. Based on a manufacturing method according to one or more embodiments, the lower electrode 120A can be formed by: forming a molded insulating layer with openings in a columnar shape on a substrate, and using a reference... Figure 6 , Figure 7A and Figure 7B The described manufacturing method forms a reference in this opening. Figure 2A The nanolaminated electrode NE is described.

[0134] In other embodiments, the lower electrode 120A may include a base pillar extending in a vertical direction and an electrode layer conformally located on the sidewalls and top surface of the base pillar. The base pillar may include at least one metal selected from metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), or tungsten (W); conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), or tungsten nitride (WN); and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), or strontium ruthenium oxide (SrRuO3). The electrode layer may include a reference electrode. Figure 2A The nanolaminated electrode NE is described.

[0135] Figure 22 This is a cross-sectional view of a semiconductor device 200 according to one or more embodiments.

[0136] refer to Figure 22 The semiconductor device 200 may be a global shutter type image sensor, comprising a plurality of photoelectric conversion regions PD formed on a semiconductor substrate 210, and a capacitor CAP located on the front surface of the semiconductor substrate 210. A transfer gate TG may extend into the semiconductor substrate 210 and may be configured to control photoelectrons stored in the photoelectric conversion regions PD. Pixel transistors may also be formed on the front surface of the semiconductor substrate 210, and the pixel transistors may be electrically connected to the capacitor CAP, such that charge transferred from the photoelectric conversion regions PD of each pixel is stored in the capacitor CAP. The capacitor CAP may include a lower electrode 220, a dielectric layer 230, and an upper electrode 240, and at least one of the lower electrode 220 and the upper electrode 240 may include a reference electrode. Figures 1 to 3 The nanolaminated electrode NE is described. The front wiring layer FL may be located on the front surface of the semiconductor substrate 210, the front insulating layer FI may cover the front wiring layer FL and the capacitor CAP, and the color filter CF and the microlens ML may be located on the rear surface of the semiconductor substrate 210.

[0137] As described above, one or more embodiments have been shown in the accompanying drawings and described in the specification. While specific terminology has been used to describe one or more embodiments, this is for the purpose of explaining the technical ideas of this disclosure only and is not intended to limit the meaning and scope of this disclosure as set forth in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be implemented accordingly. Accordingly, the true technical scope of this disclosure should be determined by the technical spirit of the appended claims.

[0138] Although this disclosure has been specifically shown and described with reference to one or more embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Capacitors, including: Lower electrode; upper electrode; and A dielectric layer is located between the lower electrode and the upper electrode. Wherein, at least one of the lower electrode and the upper electrode includes a nanolaminated electrode, the nanolaminated electrode comprising a plurality of alternating first material layers and a plurality of second material layers. The plurality of first material layers include indium oxide (In2O3). The plurality of second material layers include vanadium oxide (V₂O₅). Each of the plurality of first material layers comprises multiple layers, and Each of the plurality of second material layers comprises a single layer.

2. The semiconductor device according to claim 1, wherein, The lower electrode includes: The first lower electrode; and The second lower electrode is located on top of the first lower electrode. The first lower electrode does not include the nano-laminated electrode. The first lower electrode comprises at least one selected from metal, conductive metal nitride, or conductive metal oxide, and The second lower electrode includes the nanolaminated electrode.

3. The semiconductor device according to claim 1, wherein, The upper electrode includes: The first upper electrode; and The second upper electrode is located on the first upper electrode. Wherein, the first upper electrode includes the nanolaminated electrode, wherein the second upper electrode does not include the nanolaminated electrode, and wherein the second upper electrode includes at least one selected from metal, conductive metal nitride, or conductive metal oxide.

4. The semiconductor device according to claim 1, wherein, Each of the plurality of first material layers comprises 25 to 150 single layers.

5. The semiconductor device according to claim 1, wherein, The plurality of first material layers are included in the nanolaminated electrode in a proportion of 66 wt% to 68 wt%, and The plurality of second material layers are included in the nanolaminated electrode in a proportion of 0.6 wt% to 0.8 wt%.

6. The semiconductor device according to claim 1, wherein, The work function of the nanolaminated electrode is in the range of 5.2 eV to 5.5 eV.

7. The semiconductor device according to claim 1, wherein, The capacitor has a first capacitance at 1 kHz and a second capacitance at 1 MHz, and The second capacitor is 40% larger than the first capacitor.

8. The semiconductor device according to claim 1, wherein, The thickness of the nanolaminated electrode is in the range of 10 nanometers to 50 nanometers.

9. The semiconductor device according to claim 1, wherein, The dielectric layer comprises a high-k metal oxide.

10. The semiconductor device according to claim 1, wherein, In the X-ray diffraction analysis results, the peaks of the plane originating from the crystal structure of the nanolaminated electrode are greater than 30.66° and less than 30.76°.

11. A semiconductor device, comprising: Capacitors, including: Lower electrode; upper electrode; and A dielectric layer is located between the lower electrode and the upper electrode. Wherein, at least one of the lower electrode and the upper electrode includes a nanolaminated electrode, the nanolaminated electrode comprising a plurality of alternating first material layers and a plurality of second material layers. The plurality of first material layers include indium oxide (In2O3). The plurality of second material layers include vanadium oxide (V₂O₅), and The work function of the nanolaminated electrode is in the range of 5.2 eV to 5.5 eV.

12. The semiconductor device according to claim 11, wherein, Each of the plurality of first material layers comprises multiple layers, and Each of the plurality of second material layers comprises a single layer.

13. The semiconductor device according to claim 11, wherein, The plurality of first material layers are included in the nanolaminated electrode in a proportion of 66 wt% to 68 wt%, and The plurality of second material layers are included in the nanolaminated electrode in a proportion of 0.6 wt% to 0.8 wt%.

14. The semiconductor device according to claim 11, wherein, The first thickness of each of the plurality of first material layers is in the range of 1.5 nanometers to 11.5 nanometers, and The second thickness of each of the plurality of second material layers is in the range of 0.005 nanometers to 0.015 nanometers.

15. The semiconductor device according to claim 11, wherein, The capacitor has a first capacitance at a frequency of 1 kHz and a second capacitance at a frequency of 1 MHz. The second capacitor is 50% larger than the first capacitor.

16. The semiconductor device according to claim 11, wherein, The dielectric loss factor of the nanolaminated electrode at 1 MHz is in the range of 0.1 to 0.

2.

17. A semiconductor device, comprising: Substrate; A contact structure on the substrate; The lower electrode, on the contact structure, has a cylindrical shape and includes a first nanolaminated electrode; Dielectric layer, on the lower electrode; as well as The upper electrode is located on the dielectric layer. The first nanolaminated electrode comprises multiple alternating first material layers and multiple second material layers. The plurality of first material layers include indium oxide (In2O3). The plurality of second material layers include vanadium oxide (V₂O₅). Each of the plurality of first material layers comprises multiple layers, and Each of the plurality of second material layers comprises a single layer.

18. The semiconductor device according to claim 17, wherein, Each of the plurality of first material layers comprises 25 to 150 single layers.

19. The semiconductor device according to claim 17, wherein, The upper electrode includes a second nanolaminated electrode, which comprises alternating third material layers and multiple fourth material layers. The plurality of third material layers include indium oxide (In2O3). The plurality of fourth material layers include vanadium oxide (V₂O₅). Each of the plurality of third material layers comprises multiple layers, and Each of the plurality of fourth material layers comprises a single layer.

20. The semiconductor device according to claim 19, wherein, Each of the plurality of third material layers comprises 25 to 150 single layers.

Images