Method for improving connection and filling of SEG inner and outer base regions
By forming a polycrystalline layer at the junction of the base region and the outer base region and then etching it away, the stress increase and undercut problems caused by germanium-silicon crystal deposition are solved, thereby improving the RF electrical performance of HBT devices.
Patent Information
- Application Number
- CN202510956916.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-10
- Publication Date
- 2025-11-11
AI Technical Summary
In semiconductor device manufacturing, germanium-silicon crystal deposition is prone to occur at the junction of the base region and the outer base region of heterojunction bipolar transistor devices. This leads to a reduction in the undercut area space, increased stress at the junction, warping, and increased resistance, which affects the radio frequency electrical performance of the device.
By forming a polycrystalline layer at the junction of the inner and outer base regions and removing the polycrystalline layer using highly selective etching gas, the deposition process of the epitaxial layer is optimized, ensuring that germanium-silicon grows only from bottom to top in the bottom single crystal region, thus avoiding the deposition of germanium-silicon crystals at the junction.
The stress problem at the junction of the base region and the outer base region was improved, the shape of the undercut region was optimized, and the RF electrical characteristics of the HBT device were enhanced, including a significant increase in current amplification factor and characteristic frequency.
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Figure CN120936048A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and in particular to a method for improving the connection and filling of the inner and outer base regions of a SEG. Background Technology
[0002] In the field of semiconductor device manufacturing, the base region of the 55-nanometer-level bipolar complementary metal-oxide-semiconductor (BiCMOS) platform is epitaxially grown from germanium (Ge) silicon (Si). Among them, the selective epitaxy of Germanium silicon (SEG) process is simple and easy to integrate.
[0003] like Figure 1 As shown, in the related technology, a single-crystal germanium-silicon layer 201 is epitaxially formed inside and outside the base region 204. However, germanium-silicon crystal 203 is easily deposited at the junction of the base region 204 and the outer base region 205. The deposition of germanium-silicon crystal 203 reduces the space of the lateral etching (undercut) region, which restricts the subsequent deposition of silicon cap layer 202.
[0004] like Figure 2 , Figure 3 As shown, on the other hand, the formation of germanium-silicon crystal 203 will cause increased stress at the connection between base region 204 and outer base region 205, warping of the undercut region, and even pitting. At the same time, the formation of germanium-silicon crystal 203 will also cause increased resistance at the connection, affecting the radio frequency (RF) electrical performance of the device. Summary of the Invention
[0005] This application provides a method for improving the connection and filling of the inner and outer base regions of SEG, which can solve the problem of germanium-silicon crystal deposition at the connection between the base region and the outer base region in related technologies.
[0006] On one hand, embodiments of this application provide a method for improving the connectivity and filling of the SEG inner and outer base regions, including: Provide a wafer substrate; An epitaxial site region is formed on the surface of the wafer substrate. The epitaxial site region includes an outer base region and an inner base region. Both the outer base region and the inner base region have openings. The openings of the outer base region and the inner base region are connected in an inverted "T" shape. An epitaxial layer is formed to fill the inner base region, and the formation of the epitaxial layer also includes forming a polycrystalline layer at the junction of the inner base region and the outer base region; The polycrystalline layer is removed by etching through the opening in the outer base region; A protective layer is formed to cover the epitaxial layer.
[0007] In some embodiments, the epitaxial layer comprises a single-crystal germanium-silicon layer.
[0008] In some embodiments, the thickness of the epitaxial layer is 200 to 400 angstroms.
[0009] In some embodiments, the temperature at which the epitaxial layer is deposited is between 600 and 700 degrees Celsius.
[0010] In some embodiments, the process chamber pressure for depositing the epitaxial layer is 6 Torr to 20 Torr.
[0011] In some embodiments, the deposition rate for forming the epitaxial layer is from 10 angstroms per minute to 30 angstroms per minute.
[0012] In some embodiments, the etching removal of the polycrystalline layer through the opening in the outer base region includes: The polycrystalline layer is removed by etching with a highly selective etching gas.
[0013] In some embodiments, the highly selective etching gas includes hydrogen chloride.
[0014] In some embodiments, the gas flow rate for removing the polycrystalline layer by etching with a highly selective etching gas is from 100 standard cubic meters per minute to 300 standard cubic meters per minute.
[0015] In some embodiments, the pressure at which the polycrystalline layer is removed by etching with a highly selective etching gas is 10 Torr to 100 Torr.
[0016] In some embodiments, the temperature at which the polycrystalline layer is removed by etching with a highly selective etching gas is 600 to 800 degrees Celsius.
[0017] In some embodiments, the protective layer includes a silicon layer.
[0018] The technical solution of this application has at least the following advantages: By etching away the polycrystalline layer at the junction of the outer and inner base regions, the growth of germanium-silicon crystals in the outer base region is essentially eliminated, solving the problem of excessive stress at the junction of the inner and outer base regions in related technologies. At the same time, the shape of the undercut region is optimized, thereby improving the overall RF electrical characteristics of the HBT device. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0020] Figure 1 These are cross-sectional views of the base region and outer base region of an HBT device in related technologies; Figure 2 This is a TEM image of the overall structure of an HBT device in related technologies; Figure 3 This is a TEM image of the undercut region of an HBT device in related technologies; Figure 4 This is a flowchart of an exemplary embodiment of the improved method provided in this application; Figure 5 This is a cross-sectional view of a wafer substrate and epitaxial site region provided in an exemplary embodiment of this application; Figure 6 This is a cross-sectional view of the structure after the epitaxial layer is formed, provided in an exemplary embodiment of this application; Figure 7 This is a cross-sectional view of the structure after etching to remove the polycrystalline layer, provided in an exemplary embodiment of this application; Figure 8 This is a cross-sectional view of the structure after the protective layer has been generated, provided in an exemplary embodiment of this application; Figure 9 This is a TEM image of an HBT device manufactured using the improved method provided in an exemplary embodiment of this application; Figure 10 This is a TEM image of the undercut region of an HBT device manufactured using the improved method provided in an exemplary embodiment of this application; Figure 11 This is a comparison chart of the current amplification factor of an HBT device manufactured using the improved method provided in an exemplary embodiment of this application; Figure 12 This is a comparison diagram of the characteristic frequencies of an HBT device manufactured using the improved method provided in an exemplary embodiment of this application. Detailed Implementation
[0021] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0024] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0025] refer to Figure 4 It presents a flowchart of an improved method provided by an exemplary embodiment of this application, such as... Figure 4 As shown, it includes: Step S101: Provide a wafer substrate.
[0026] refer to Figure 5 It presents a cross-sectional structural diagram of a wafer substrate and epitaxial site region provided in an exemplary embodiment of this application, such as... Figure 5 As shown, it includes: For example, a wafer substrate 301 is provided, and impurities and oxide layers on the surface of the wafer substrate 301 are removed by cleaning.
[0027] Step S102: An epitaxial site region is formed on the surface of the wafer substrate. The epitaxial site region includes an outer base region and an inner base region. Both the outer base region and the inner base region have openings. The openings of the outer base region and the inner base region are connected in an inverted "T" shape.
[0028] like Figure 5As shown, for example, by standardizing the process parameters such as photolithography, etching, and doping, the consistency of wafer substrate 301 processing is ensured, providing a qualified wafer substrate 301 for epitaxial growth. After completion, an epitaxial site region is formed on the surface of the wafer substrate 301. The epitaxial site region includes an outer base region 303 and an inner base region 302. Both the outer base region 303 and the inner base region 302 have openings. The width of the opening in the outer base region 303 is smaller than the width of the opening in the inner base region 302. The two openings are connected in an inverted "T" shape. Both the inner base region 302 and the outer base region 303 are filled with germanium-silicon material. Due to the discontinuity of their structures, an undercut structure appears at the connection between the inner base region 302 and the outer base region 303. Figure 5 (Not shown in the image).
[0029] Step S103: Form an epitaxial layer to fill the inner base region. The epitaxial layer formation process also includes forming a polycrystalline layer at the junction of the inner base region and the outer base region.
[0030] Optionally, the epitaxial layer may include a single-crystal germanium-silicon layer.
[0031] The thickness of the epitaxial layer is 200 to 400 angstroms.
[0032] The temperature at which the epitaxial layer is formed is between 600 and 700 degrees Celsius.
[0033] The process chamber pressure for depositing the epitaxial layer is between 6 Torr and 20 Torr.
[0034] The deposition rate for forming the epitaxial layer ranges from 10 angstroms per minute to 30 angstroms per minute.
[0035] refer to Figure 6 It presents a cross-sectional view of the structure after the epitaxial layer is formed, as provided in an exemplary embodiment of this application, such as... Figure 6 As shown, it includes: For example, an epitaxial layer 304 is deposited in the inner base region 302 by chemical vapor deposition. The epitaxial layer 304 is a single-crystal germanium-silicon layer with a thickness of 300 angstroms. The temperature during the deposition of the epitaxial layer 304 is 650 degrees Celsius, the pressure during the deposition of the epitaxial layer 304 is 14 Torr, and the deposition rate of the epitaxial layer 304 is 20 angstroms per minute. The combination of temperature, pressure and rate can reduce diffusion during the deposition of single-crystal germanium-silicon. However, the undercut structure acts as a "trap" during the deposition process. Some germanium-silicon epitaxial layers will still diffuse due to the high temperature during the deposition process and diffuse to unintended areas. For example, they are collected by the undercut structure at the junction of the inner base region 302 and the outer base region 303, forming a polycrystalline layer 305 at the junction of the inner base region 302 and the outer base region 303. The polycrystalline layer 305 is a germanium-silicon polycrystalline layer.
[0036] Step S104: Remove the polycrystalline layer by etching through the opening in the outer base region.
[0037] Optionally, removing the polycrystalline layer by etching through an opening in the outer base region includes: The polycrystalline layer at the junction of the outer base region and the inner base region is removed by highly selective etching gas.
[0038] Among them, the highly selective etching gas includes hydrogen chloride.
[0039] The gas flow rate for removing the polycrystalline layer by highly selective etching gas is 100 standard cubic meters per minute to 300 standard cubic meters per minute.
[0040] The pressure for removing the polycrystalline layer by highly selective etching gas is 10 Torr to 100 Torr.
[0041] The temperature for removing the polycrystalline layer by etching with highly selective etching gas is 600 to 800 degrees Celsius.
[0042] refer to Figure 7 It presents a cross-sectional view of the structure after etching and removal of the polycrystalline layer according to an exemplary embodiment of this application, such as... Figure 7 As shown, it includes: For example, a mask layer is used to protect the surface and sidewalls of the outer base region 303. Through the opening of the outer base region 303, the polycrystalline layer 305 at the connection with the inner base region 302 is etched downwards and removed by etching with highly selective hydrogen chloride gas. In germanium-silicon crystals, the bond energy between germanium atoms and chlorine is significantly lower than that between silicon and chlorine, making germanium atoms more susceptible to attack by chlorine free radicals and detach from the crystal lattice. At this time, the hydrogen chloride gas flow rate during the highly selective gas etching process is 200 standard cubic meters per minute, the pressure is 50 Torr, and the temperature is 650 degrees Celsius. The low temperature of 650 degrees Celsius during the highly selective gas etching process can suppress the reactivity of silicon atoms, allowing germanium atoms to still react efficiently and achieve highly selective etching. The low pressure of 50 Torr can reduce gas phase collisions and enhance surface reaction control. After etching, germanium-silicon can be grown from bottom to top only in the single crystal region at the bottom of the inner base region 302. At the same time, the removal of the polycrystalline layer 305 by etching makes the undercut region smoother.
[0043] Step S105: Form a protective layer to cover the epitaxial layer.
[0044] Optionally, the protective layer may include a silicon layer.
[0045] refer to Figure 8 It presents a cross-sectional view of the structure after the protective layer is generated, as provided in an exemplary embodiment of this application, such as... Figure 8 As shown, it includes: For example, a protective layer 306 is deposited on the surface of the epitaxial layer 304, and the protective layer 306 is a silicon layer.
[0046] refer to Figure 9 It presents a TEM image of an HBT device fabricated using the improved method provided in an exemplary embodiment of this application, such as... Figure 9 As shown, after the method provided in this application is improved, the deposition rate of germanium-silicon in the epitaxial layer 303 is precisely controlled by pressure, and a high-selectivity etching step is added after the germanium-silicon deposition, so that germanium-silicon grows from bottom to top only in the bottom single crystal region, and almost no germanium-silicon crystals grow at the connection of the outer base region 303.
[0047] refer to Figure 10 It presents a TEM image of the undercut region of an HBT device fabricated using the improved method provided in an exemplary embodiment of this application, such as... Figure 10 As shown, the pitting corrosion in the undercut area has been significantly improved, and the overall surface is smooth without any warping.
[0048] refer to Figure 11 It presents a comparison graph of the current amplification factor (β) of an HBT device manufactured using the improved method provided in an exemplary embodiment of this application, such as... Figure 11 As shown, the current amplification factor of the HBT device in the related technology is about 100, which is improved to 1800 after optimization, resulting in a significant improvement.
[0049] refer to Figure 12 It presents a comparison graph of the characteristic frequency (Ft) of an HBT device fabricated using the improved method provided in an exemplary embodiment of this application, such as... Figure 12 As shown, the characteristic frequency value of the HBT device in the related technology is about 50, which is improved to about 225 after optimization, resulting in a significant overall improvement.
[0050] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for improving the connection and filling of the inner and outer base regions of a SEG, characterized in that, include: Provide a wafer substrate; An epitaxial site region is formed on the surface of the wafer substrate. The epitaxial site region includes an outer base region and an inner base region. Both the outer base region and the inner base region have openings. The openings of the outer base region and the inner base region are connected in an inverted "T" shape. An epitaxial layer is formed to fill the inner base region, and the formation of the epitaxial layer also includes forming a polycrystalline layer at the junction of the inner base region and the outer base region; The polycrystalline layer is removed by etching through the opening in the outer base region; A protective layer is formed to cover the epitaxial layer.
2. The method as described in claim 1, characterized in that, The epitaxial layer includes a single-crystal germanium-silicon layer.
3. The method as described in claim 2, characterized in that, The thickness of the epitaxial layer is 200 to 400 angstroms.
4. The method as described in claim 3, characterized in that, The temperature at which the epitaxial layer is deposited is between 600 and 700 degrees Celsius.
5. The method as described in claim 4, characterized in that, The process chamber pressure for depositing the epitaxial layer is 6 Torr to 20 Torr.
6. The method as described in claim 5, characterized in that, The deposition rate for forming the epitaxial layer is from 10 angstroms per minute to 30 angstroms per minute.
7. The method as described in claim 1, characterized in that, The step of etching away the polycrystalline layer through the opening in the outer base region includes: The polycrystalline layer is removed by etching with a highly selective etching gas.
8. The method as described in claim 7, characterized in that, The highly selective etching gas includes hydrogen chloride.
9. The method as described in claim 7, characterized in that, The gas flow rate for removing the polycrystalline layer by etching with highly selective etching gas is 100 standard cubic meters per minute to 300 standard cubic meters per minute.
10. The method as described in claim 7, characterized in that, The pressure at which the polycrystalline layer is removed by etching with a highly selective etching gas is 10 Torr to 100 Torr.
11. The method as described in claim 7, characterized in that, The temperature at which the polycrystalline layer is removed by etching with a highly selective etching gas is 600 to 800 degrees Celsius.
12. The method as described in claim 1, characterized in that, The protective layer includes a silicon layer.