Super junction insulated gate bipolar transistor

Abstract

The embodiment of the invention provides a super junction insulated gate bipolar transistor. The transistor comprises a cellular area located in the center and a terminal area located on the periphery of the cellular area, multiple sets of column areas which are arranged side by side are formed in an epitaxial area corresponding to the terminal area, the conduction type of the column areas is opposite to that of the epitaxial area, the column areas extend in the thickness direction of the epitaxial area, and the extension depths of the column areas in each set are consistent. The extension depth of each group of column regions is reduced along with the increase of the distance with the cellular region, the width of the column regions is smaller than that of the cellular region, and the minimum interval between the column regions in the epitaxial region corresponding to the terminal region and the column regions in the epitaxial region corresponding to the cellular region is smaller than the width of the cellular region. According to the super junction insulated gate bipolar transistor provided by the embodiment of the invention, larger withstand voltage can be realized without increasing the terminal area, and the terminal utilization rate of a device is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a superjunction insulated gate bipolar transistor. Background Technology

[0002] Silicon carbide superjunction insulated gate bipolar transistors (IGBTs) have advantages such as high voltage withstand capability, low conduction loss and high-speed switching characteristics.

[0003] In related technologies, relatively little attention has been paid to the terminal structure of superjunction IGBTs, and field limiting loops are usually used to ensure the voltage withstand capability of the terminal structure.

[0004] However, in the process of realizing this application, the inventors discovered at least the following problems in the related technology: the above-mentioned field limiting loop method will occupy a large amount of terminal area. Summary of the Invention

[0005] This application provides a superjunction insulated gate bipolar transistor to achieve a higher withstand voltage with the same terminal area.

[0006] In a first aspect, embodiments of this application provide a superjunction insulated gate bipolar transistor, characterized in that it includes: a cell region located at the center, and a terminal region located around the cell region;

[0007] Multiple sets of pillar regions are formed in parallel in the epitaxial region corresponding to the terminal region; the conductivity type of the pillar regions is opposite to that of the epitaxial region.

[0008] The column region extends along the thickness direction of the epitaxial region; the extension depth of each column region in each group is consistent, and the extension depth of each column region in each group decreases as the distance from the cell region increases; the width of the column region is less than the width of the cell region; the minimum interval between the column region in the epitaxial region corresponding to the terminal region and the column region in the epitaxial region corresponding to the cell region is less than the width of the cell region.

[0009] In one possible design, a terminal main junction and a terminal ring region are formed above the plurality of pillar regions in the epitaxial region; the conductivity type of the terminal ring region is opposite to that of the epitaxial region.

[0010] In one possible design, the field limiting rings in the terminal ring region are distributed at equal intervals, or the inner ring lines of the field limiting rings in the terminal ring region are equally spaced.

[0011] In one possible design, the distance between the pillar region farthest from the cell region in the epitaxial region corresponding to the terminal region and the field limiting ring farthest from the cell region in the terminal ring region is greater than or equal to 20 micrometers and less than or equal to 30 micrometers.

[0012] In one possible design, the distance between the lower surface of the terminal ring region and the upper surface of the column region is greater than or equal to 1 micrometer and less than or equal to 2 micrometers.

[0013] In one possible design, the spacing between the plurality of column regions increases as the distance from the cell region increases.

[0014] In one possible design, the depth of the column region is greater than 40 micrometers.

[0015] In one possible design, the coordinates of the feature points corresponding to the multiple sets of column regions are elliptical; the feature point is the midpoint of the column region that is farthest from the cell region in the corresponding column region group.

[0016] In one possible design, the distance between the column region and the lower surface of the extension region is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0017] In one possible design, the width of the column region is in a preset ratio to the width of the cell region, wherein the preset ratio is less than or equal to 2 / 3 and greater than or equal to 1 / 3.

[0018] In one possible design, the terminal region also includes a silicon carbide substrate located below the epitaxial region.

[0019] Secondly, embodiments of this application provide a method for determining the termination structure of a superjunction insulated-gate bipolar transistor, including:

[0020] Obtain the size of the terminal area, and determine the first number of column areas that can be constructed in the extension area corresponding to the terminal area based on the size of the terminal area, the width and spacing of the column areas;

[0021] The first number of column areas are divided into a second number of column area groups; each column area group contains an equal number of column areas.

[0022] A target coordinate system is established with the width direction of the column area as the first coordinate axis direction and the depth direction of the column area as the second coordinate axis direction;

[0023] For each column group, the coordinate value of the center line of the width of the column group that is farthest from the cell region in the column group is determined as the first coordinate value of the column group. Based on the preset curve formula constructed based on the target coordinate system and the first coordinate value, the second coordinate value of the column group on the second coordinate axis is determined.

[0024] The terminal structure is determined based on the first and second coordinate values ​​corresponding to each column group.

[0025] Thirdly, embodiments of this application provide a device for determining the termination structure of a superjunction insulated-gate bipolar transistor, comprising:

[0026] The acquisition module is used to acquire the size of the terminal area and determine the first number of column areas that can be constructed in the extension area corresponding to the terminal area based on the size of the terminal area, the width and spacing of the column areas.

[0027] The partitioning module is used to divide the first number of column areas into a second number of column area groups; each column area group contains an equal number of column areas.

[0028] A module is established to create a target coordinate system with the width direction of the column area as the first coordinate axis direction and the depth direction of the column area as the second coordinate axis direction.

[0029] The determination module is used to determine the coordinate value of the center line of the width of the column that is farthest from the cell in each column group as the first coordinate value of the column group, and to determine the second coordinate value of the column group on the second coordinate axis according to the preset curve formula constructed based on the target coordinate system and the first coordinate value.

[0030] The determining module is further configured to determine the terminal structure based on the first coordinate value and the second coordinate value corresponding to each column group.

[0031] Thirdly, embodiments of this application provide a device for determining the termination structure of a superjunction insulated gate bipolar transistor, comprising: at least one processor and a memory;

[0032] The memory stores computer-executed instructions;

[0033] The at least one processor executes the computer execution instructions stored in the memory, causing the at least one processor to perform the method described in the second aspect above and various possible designs of the second aspect.

[0034] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the methods described in the second aspect above and various possible designs of the second aspect.

[0035] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the methods described in the second aspect above and various possible designs of the second aspect.

[0036] The superjunction insulated-gate bipolar transistor (SGBB) provided in this embodiment includes a central cell region and a terminal region surrounding the cell region. Multiple sets of pillar regions are formed in parallel within the epitaxial region corresponding to the terminal region. The conductivity type of the pillar regions is opposite to that of the epitaxial region. The pillar regions extend along the thickness direction of the epitaxial region, and the extension depth of each pillar region within each group is consistent. The extension depth of each group of pillar regions decreases as the distance from the cell region increases. The width of the pillar regions is smaller than the width of the cell region. The minimum spacing between the pillar regions in the epitaxial region corresponding to the terminal region and the pillar regions in the epitaxial region corresponding to the cell region is smaller than the width of the cell region. By optimizing the arrangement of the multiple pillar regions in the terminal region, the SGBB provided in this embodiment can improve the breakdown voltage of the device within the same terminal area. Specifically, the decrease in the extension depth of the pillar regions within the terminal region as the distance from the cell region increases effectively optimizes the electric field distribution, reduces electric field concentration, and thus improves the breakdown voltage performance of the device. In addition, the width of the pillar region is designed to be smaller than the width of the cell region, and the minimum spacing between pillar regions is smaller than the width of the cell region. This not only enhances the electric field buffering capability of the terminal region, but also achieves greater withstand voltage without increasing the terminal area, thereby increasing the terminal utilization rate of the device. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0038] Figure 1 A schematic diagram of the terminal region of a superjunction insulated gate bipolar transistor provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of the first terminal structure of the superjunction + field confinement ring in the related technology;

[0040] Figure 3 A schematic diagram of the second terminal structure of a superjunction + field confinement ring based on elliptic curve arrangement provided in an embodiment of this application;

[0041] Figure 4This is a schematic diagram of the electric field distribution of the first terminal structure of the superjunction + field confinement ring in the related technology;

[0042] Figure 5 A schematic diagram of the electric field distribution of the second terminal structure based on an elliptic curve arrangement of a superjunction and a field-limiting ring, provided in an embodiment of this application.

[0043] Figure 6 This is a schematic diagram of the electric field distribution curves at the bottom of the field limiting ring along the X-axis direction for the first and second terminal structures.

[0044] Figure 7 A schematic diagram of the breakdown curves for the first and second terminal structures;

[0045] Figure 8 This is a flowchart illustrating the method for determining the termination structure of a superjunction insulated gate bipolar transistor provided in an embodiment of this application.

[0046] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments.

[0047] Figure label:

[0048] 1-Substrate region; 2-Buffer layer; 3-Epipolar region; 4-Pillar region; 5-Terminal main junction; 6-Oxide layer; 7-Field confinement ring. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] It should be noted that the superjunction insulated gate bipolar transistor provided in this application can be used in the field of semiconductor technology, or in any field other than semiconductor technology. The application field of the superjunction insulated gate bipolar transistor provided in this application is not limited.

[0051] Silicon carbide (SiC) devices possess advantages such as high voltage withstand capability, low on-resistance, faster switching speed, higher operating temperature, better heat dissipation, and good radiation resistance, leading to their widespread application in power electronic circuits. SiC devices include Insulated Gate Bipolar Transistors (IGBTs), Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and Junction Field-Effect Transistors (JFETs).

[0052] For silicon carbide superjunction IGBTs, the following advantages are available:

[0053] High voltage withstand capability: Silicon carbide has a high critical breakdown electric field. Compared with traditional silicon-based IGBTs, silicon carbide superjunction IGBTs can withstand higher voltages without breakdown. This makes them excellent in high-voltage applications, such as high-voltage direct current transmission and high-voltage frequency converters, meeting the high-voltage handling requirements of these systems.

[0054] Low conduction loss: The superjunction structure design optimizes the on-resistance of the device. Combined with the low resistivity and high electron mobility of silicon carbide material, this results in even lower resistance for the silicon carbide superjunction IGBT in the on-state, thus reducing conduction losses. This helps improve power conversion efficiency and reduce energy waste during transmission and conversion. For long-term power systems, this can significantly reduce energy consumption and operating costs.

[0055] High-speed switching characteristics: Silicon carbide materials have fast carrier migration speeds, and the superjunction structure also facilitates rapid charge exchange and switching operations, enabling silicon carbide superjunction IGBTs to have faster switching speeds. In high-frequency applications, such as switching power supplies and photovoltaic inverters, higher switching frequencies can be achieved, reducing the use of external components such as filters, shrinking equipment size, and increasing power density.

[0056] There is relatively little attention paid to the termination structure of superjunction IGBTs in related technologies. Field limiting loops are usually used to ensure the voltage withstand capability of the termination structure.

[0057] However, the above-mentioned field limiting loop method will occupy a large amount of terminal area, resulting in the terminal area accounting for 50% to 80% of the chip area. Under the same defect density, an excessively large terminal area will encounter more defects, leading to terminal failure.

[0058] To address the aforementioned technical problems, the inventors of this application have discovered that a superjunction + field-limiting ring approach can be used to improve the voltage withstand capability of the termination structure. Furthermore, by optimizing the arrangement of the pillar regions, a higher voltage withstand capability can be achieved within the same termination area, increasing the device's termination utilization rate. Based on this, this application provides a superjunction insulated-gate bipolar transistor.

[0059] Figure 1 This is a schematic diagram of the terminal region of a superjunction insulated-gate bipolar transistor provided in an embodiment of this application. Figure 1 As shown, a superjunction insulated gate bipolar transistor includes: a cell region (not shown) located at the center, and a terminal region located around the cell region.

[0060] Multiple sets of pillar regions 4 are formed in parallel in the epitaxial region 3 corresponding to the terminal region; the conductivity type of the pillar regions 4 is opposite to that of the epitaxial region 3.

[0061] The column region 4 extends along the thickness direction of the extension region 3; the extension depth of each column region 4 in each group is consistent, and the extension depth of each column region 4 decreases as the distance from the cell region increases; the width of the column region 4 is less than the width of the cell region; the minimum interval between the column region 4 in the extension region 3 corresponding to the terminal region and the column region 4 in the extension region 3 corresponding to the cell region is less than the width of the cell region.

[0062] In this embodiment, as Figure 1 As shown, substrate 1 can be a P-type substrate (P-Sub), epitaxial region 3 can be an N-type epitaxial region (N-epi), pillar region 4 can be a P-type pillar region (Ppillar 4), the main junction 5 can be formed by P-type doping, oxide layer 6 is formed by isolation deposition on the terminal region, and field confinement ring 7 can be P-type implanted. The substrate can be a silicon carbide substrate.

[0063] The superjunction insulated gate bipolar transistor provided in this application improves the breakdown voltage of the device within the same termination area by optimizing the arrangement of multiple pillar regions 4 in the termination region. Specifically, the extension depth of the pillar regions 4 in the termination region decreases as the distance from the cell region increases, which effectively optimizes the electric field distribution and reduces electric field concentration, thereby improving the breakdown voltage performance of the device. In addition, the width of the pillar regions 4 is designed to be smaller than the width of the cell region, and the minimum spacing between the pillar regions 4 is smaller than the width of the cell region. This not only enhances the electric field buffering capability of the termination region but also achieves a higher breakdown voltage without increasing the termination area, thus increasing the device's termination utilization rate.

[0064] In some embodiments, a terminal main junction 5 and a terminal ring region are formed above multiple sets of pillar regions 4 in the epitaxial region 3; the conductivity type of the terminal ring region is opposite to that of the epitaxial region 3. The superjunction insulated gate bipolar transistor provided in this application, by forming a terminal main junction 5 and a terminal ring region above multiple sets of pillar regions 4 in the epitaxial region 3, can further improve the device's breakdown voltage performance and reliability. Specifically, the conductivity type of the terminal ring region is opposite to that of the epitaxial region 3, which can effectively form a more uniform electric field distribution in the terminal region, reduce electric field concentration, and thus improve the device's breakdown voltage capability. Furthermore, the introduction of the terminal main junction 5 provides an additional buffer layer 2 for the electric field, further enhancing the electric field modulation capability of the terminal region. Through these structural optimizations, the superjunction insulated gate bipolar transistor not only exhibits superior performance under high voltage conditions but also achieves greater breakdown voltage without increasing device size, increasing the device's terminal utilization rate.

[0065] In some embodiments, the field limiting rings 7 in the termination ring region are equally spaced, or the spacing between the inner loops of the field limiting rings 7 in the termination ring region is equal. The superjunction insulated gate bipolar transistor provided in this application, by designing the field limiting rings 7 to be equally spaced in the termination ring region, or by making the spacing between the inner loops of the field limiting rings 7 equal, can further optimize the electric field distribution and improve the device's breakdown voltage performance. The equally spaced field limiting rings 7 design helps to form a uniform electric field gradient in the termination region, thereby effectively reducing electric field concentration and lowering the risk of breakdown. Furthermore, the design with equal spacing between the inner loops ensures a smooth transition of the electric field between the rings, further improving the accuracy and stability of electric field control. Through these design optimizations, the superjunction insulated gate bipolar transistor exhibits higher reliability and longer lifespan in high-voltage applications, achieving a higher breakdown voltage with the same termination area and increasing the device's termination utilization.

[0066] In this embodiment, the field limiting rings 7 can be distributed in several ways. In one possible implementation, they can be distributed with equal spacing, meaning the interval between adjacent field limiting rings 7 is equal. In another possible implementation, the sum of the ring width and the ring spacing can be set to be equal. These can be adjusted according to actual conditions in practical applications; this embodiment does not impose any limitations on this.

[0067] In some embodiments, the spacing between the pillar region 4, which is farthest from the cell region in the epitaxial region 3 corresponding to the termination region, and the field limiting ring 7, which is farthest from the cell region in the termination ring region, is greater than or equal to 20 micrometers (μm) and less than or equal to 30 micrometers. The superjunction insulated-gate bipolar transistor provided in this application, by setting the spacing between the last pillar region 4 in the epitaxial region 3 corresponding to the termination region and the last field limiting ring 7 in the termination ring region to 20 to 30 micrometers, can effectively optimize the electric field distribution of the device and improve its withstand voltage performance. This spacing range ensures a reasonable transition of the electric field between the termination region and the field limiting ring 7, reducing electric field concentration and thus lowering the risk of breakdown. Furthermore, this spacing design provides sufficient electric field buffer space without increasing the device size, enhancing the stability and reliability of the device under high-voltage conditions. Through these optimization measures, the superjunction insulated-gate bipolar transistor exhibits superior performance and longer lifespan in power electronic applications requiring high withstand voltage performance, achieving higher withstand voltage with the same termination area and increasing the device's termination utilization rate.

[0068] Specifically, the last column region 4 (the column region 4 furthest from the cell region) in the terminal region has a larger gap from the last field limiting ring 7 (the field limiting ring 7 furthest from the cell region) and the cell region. The gap between the last column region 4 and the last field limiting ring 7 in the terminal region ranges from 20 micrometers to 30 micrometers, and can be adjusted according to the actual situation.

[0069] In some embodiments, the distance between the lower surface of the termination ring region and the upper surface of the pillar region 4 is greater than or equal to 1 micrometer and less than or equal to 2 micrometers. The superjunction insulated gate bipolar transistor provided in this application, by setting the distance between the termination ring region and the pillar region 4 to 1 to 2 micrometers, can effectively optimize the electric field distribution and improve the device's breakdown voltage performance. This distance setting ensures a smooth transition of the electric field between the termination ring region and the pillar region 4, reducing electric field concentration and thus lowering the risk of breakdown. Furthermore, this distance range provides sufficient electric field buffer space, enhancing the stability and reliability of the device under high voltage conditions, while achieving a higher breakdown voltage with the same termination area, increasing the device's termination utilization rate.

[0070] Specifically, the upper part of column 4 is not connected to the terminal ring region, with an interval range of 1μm to 2μm.

[0071] In some embodiments, the spacing between the plurality of pillar regions 4 increases with the distance from the cell region. The superjunction insulated gate bipolar transistor provided in this application, by designing the spacing between the plurality of pillar regions 4 to increase with the distance from the cell region, can effectively optimize the electric field distribution and improve the device's withstand voltage performance. As the spacing between the pillar regions 4 gradually increases, the electric field distribution in the termination region becomes more uniform, reducing electric field concentration and thus lowering the risk of breakdown. It can provide better electric field buffering without increasing the overall device size, enhancing the device's stability and reliability under high voltage conditions. Furthermore, the gradually increasing spacing helps to form a smoother electric field gradient in the termination region, improving the overall performance and lifespan of the device, achieving a higher withstand voltage with the same termination area, and increasing the device's termination utilization rate.

[0072] In this embodiment, the width of column area 4 can be uniform, and the spacing between adjacent column areas 4 can gradually increase, such as... Figure 1 As shown, the distance between the first column area 4 and the second column area 4 is S1, and the distance between the (N-1)th column area 4 and the Nth column area 4 is SN-1 = S1 + (N-1) × f, where 0.01 < f < 0.1.

[0073] In some embodiments, to improve reliability, a minimum limit can be set for the depth of pillar region 4; specifically, the depth of pillar region 4 can be greater than 40 micrometers. The superjunction insulated gate bipolar transistor provided in this application significantly improves the device's breakdown voltage and current carrying capacity by designing the depth of pillar region 4 to be greater than 40 micrometers. A deeper pillar region 4 helps to form a more uniform electric field distribution inside the device, reducing electric field concentration and thus lowering the risk of breakdown. Furthermore, increasing the depth of pillar region 4 can increase the current channel capacity of the device, enhancing its stability and reliability under high current conditions. This design achieves a higher breakdown voltage with the same termination area, increasing the device's termination utilization.

[0074] In some embodiments, the coordinates of the feature points corresponding to the multiple sets of pillar regions 4 are elliptically distributed; the feature point is the midpoint of the pillar region 4 farthest from the cell region in the corresponding set of pillar regions 4. The superjunction insulated gate bipolar transistor provided in this application optimizes the electric field distribution and improves the withstand voltage performance by designing the coordinates of the feature points corresponding to the multiple sets of pillar regions 4 as elliptical. The feature point is the midpoint of the pillar region 4 farthest from the cell region in the corresponding set of pillar regions 4. The elliptical distribution design helps to form a more uniform electric field gradient in the terminal region, reducing electric field concentration and thus reducing the risk of breakdown. This distribution method can effectively regulate the expansion of the electric field in different directions, enhancing the stability and reliability of the device under high voltage conditions. Furthermore, the elliptical distribution design can provide better electric field buffering without increasing the overall device size, improving the overall performance and lifespan of the device, achieving a higher withstand voltage with the same terminal area, and increasing the terminal utilization rate of the device.

[0075] Specifically, such as Figure 1 As shown, an X-axis (first coordinate axis) and a Y-axis (second coordinate axis) can be established. The left boundary of the first column 4 in the terminal region (i.e., the column 4 closest to the cell region) is the starting position of the X-axis, and the upper surface of column 4 is the starting position of the Y-axis. The width of column 4 is marked along the X-axis direction, and the depth of column 4 is marked along the Y-axis direction.

[0076] It can be based on the elliptic formula: x 2 / a 2 +y 2 / b 2 =1 determines the arrangement and distribution of each column region 4. Here, 'a' is the difference between the width of the terminal region and 'm', where 'm' ranges from 100μm to 150μm, and 'b' is the length of each column region 4 within the cell region. The depth 'y' of each group of column regions 4 can be obtained based on the x-coordinate of the same feature point as input. For example, the depth 'y' of the group of column regions 4 can be obtained by using the x-coordinate of the perpendicular bisector of the widest side of the last column region 4 (the column region 4 furthest from the cell region).

[0077] In some embodiments, the distance between the pillar region 4 and the lower surface of the epitaxial region 3 is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer. The superjunction insulated gate bipolar transistor provided in this application, by setting the distance between the pillar region 4 and the lower surface of the epitaxial region 3 to be greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer, can effectively optimize the electric field distribution of the device and improve its breakdown voltage performance. This setting ensures the formation of an appropriate electric field buffer between the pillar region 4 and the lower surface of the epitaxial region 3, reducing electric field concentration and thus lowering the risk of breakdown. Furthermore, this distance range helps to achieve a higher breakdown voltage with the same termination area, increasing the device's termination utilization.

[0078] Specifically, such as Figure 1 As shown, the lower part of column 4 is not connected to buffer layer 2, with a spacing of 0.5 to 1 μm.

[0079] In some embodiments, the width of the pillar region 4 is in a preset ratio to the width of the cell region, where the preset ratio is less than or equal to 2 / 3 and greater than or equal to 1 / 3. The superjunction insulated gate bipolar transistor provided in this application, by setting the width of the pillar region 4 to the width of the cell region in a preset ratio less than or equal to 2 / 3 and greater than or equal to 1 / 3, effectively optimizes the electric field distribution and conduction performance of the device. This design ensures a reasonable electric field transition between the cell region and the pillar region 4, reducing electric field concentration and thus lowering the risk of breakdown. Furthermore, an appropriate width ratio helps maintain a good current path without significantly increasing the device size, enhancing the stability and reliability of the device under high voltage and high current conditions. By optimizing the width ratio of the pillar region 4 to the cell region, this design improves the overall performance and lifespan of the device, achieving a higher withstand voltage within the same terminal area and increasing the terminal utilization rate of the device.

[0080] In this embodiment, the width of pillar region 4 can be set to half the width of the cell region. By setting the width of pillar region 4 to half the width of the cell region, the electric field distribution and conduction performance of the device can be effectively optimized. This width ratio design ensures a reasonable electric field transition between the cell region and pillar region 4, reducing electric field concentration and thus lowering the risk of breakdown. Through this ratio setting, the electric field can be more uniformly distributed in the termination region, enhancing the stability and reliability of the device under high voltage conditions. In addition, this design helps maintain a good current path, improving the device's conduction efficiency and overall performance.

[0081] In some embodiments, the termination region further includes a silicon carbide substrate located beneath the epitaxial region. In this embodiment, the termination region design using a silicon carbide substrate can significantly improve the thermal, electrical, and mechanical properties of the device, making it perform better in high-power, high-frequency, and high-temperature environments.

[0082] In some embodiments, the termination region further includes a substrate region 1, a buffer layer 2, and an oxide layer 6; the oxide layer 6 is formed on the upper surface of the epitaxial region 3; the buffer layer 2 is formed on the lower surface of the epitaxial region 3; and the substrate region 1 is formed on the lower surface of the buffer layer 2. The superjunction insulated-gate bipolar transistor provided in this application significantly improves the electrical performance and structural stability of the device by introducing a substrate region 1, a buffer layer 2, and an oxide layer 6 into the termination region. The oxide layer 6, formed on the upper surface of the epitaxial region 3, provides excellent electric field passivation, reducing the impact of surface defects on the electric field distribution, thereby reducing the risk of breakdown. The buffer layer 2, located on the lower surface of the epitaxial region 3, plays a role in adjusting stress and buffering the electric field, further optimizing the electric field distribution and enhancing the stability of the device under high-voltage conditions. The substrate region 1, formed on the lower surface of the buffer layer 2, provides mechanical support for the entire structure and also helps in the effective dissipation of heat. Through this multi-layer structure design, a greater withstand voltage is achieved with the same termination area, increasing the device's termination utilization rate.

[0083] In this embodiment, substrate region 1 can be a P-type silicon carbide substrate, epitaxial region 3 can be an N-type epitaxial layer, pillar region 4 can be a P-type pillar region 4, terminal main junction 5 can be formed by P-type doping, oxide layer 6 is formed by isolation deposition on the terminal region, and field confinement ring 7 can be P-type implanted.

[0084] The following combination Figures 2 to 7 The drug resistance of the superjunction insulated-gate bipolar transistor provided in the embodiments of this application will be described similarly. Figure 2 This is a schematic diagram of the first terminal structure of a superjunction + field-limiting ring in related technologies. Figure 3 This is a schematic diagram of the second terminal structure of a superjunction with field confinement ring based on elliptic curve arrangement provided in an embodiment of this application. Figure 4 This is a schematic diagram of the electric field distribution of the first terminal structure of the superjunction + field confinement ring in related technologies. Figure 5 This is a schematic diagram of the electric field distribution of the second terminal structure based on an elliptic curve arrangement superjunction + field confinement ring provided in an embodiment of this application. Figure 6 This is a schematic diagram of the electric field distribution curves at the bottom of the field limiting ring along the X-axis direction for the first and second terminal structures. Figure 7 This is a schematic diagram of the breakdown curves of the first terminal structure and the second terminal structure.

[0085] like Figure 2 and Figure 3 As shown, the width of the P-type doped pillars in both the first and second terminal structures is the same, at 3.6 μm, and the cell size is 7.2 μm. The first terminal structure uses the same arrangement of pillars as the cell, with a total of 36 P-pillars. The second terminal structure is calculated with a terminal length of 400 μm, a = 275 μm, b = 146 μm, S1 = 3.6, and f = 0.02, and then substituted into the elliptic formula x.2 / a 2 +y 2 / b 2 Calculating with =1, we find there are a total of 33 P-column regions, arranged as follows: Figure 3 As shown.

[0086] observe Figure 4 and Figure 5 It can be found that, Figure 5 The depletion line distribution is closer to an ellipsoid, and the electric field under each field-limiting loop is greater than that of the previous one. Figure 4 should be higher, Figure 6 The electric field distribution curves along the X-direction at the bottom of the field-limiting loops for both structures show that the electric field in each field-limiting loop of the second terminal structure is larger than that of the first terminal structure. While the electric field in the first terminal structure tends to concentrate in the last loop, the second terminal structure optimizes the electric field distribution. Therefore, from... Figure 7 As can be seen, the device's withstand voltage has increased from 4300V to 6000V, representing a 39% increase in withstand voltage while using the same terminal area.

[0087] Figure 8 This is a flowchart illustrating the method for determining the termination structure of a superjunction insulated-gate bipolar transistor provided in an embodiment of this application. Figure 8 As shown, the method includes:

[0088] 801. Obtain the size of the terminal area. Based on the size of the terminal area, the width and spacing of the column areas, determine the first number of column areas that can be constructed in the extension area corresponding to the terminal area.

[0089] For example, such as Figure 1 As shown, the width of column area 4 can be uniform, and the spacing between adjacent column areas 4 can gradually increase, such as... Figure 1 As shown, the distance between the first column section 4 and the second column section 4 is S1, and the distance between the (N-1)th column section 4 and the Nth column section 4 is S. N-1 =S1+(N-1)×f, where 0.01<f<0.1.

[0090] In some embodiments, the plurality of column regions include a first column region and a second column region; the first column region is the column region in the terminal region that is closest to the cell region, and the second column region is adjacent to the first column region; the first interval between the first column region and the second column region is related to the width of the cell region; the interval between each adjacent column region is an increasing arithmetic sequence.

[0091] 802. Divide the first number of column areas into a second number of column area groups; each column area group contains an equal number of column areas.

[0092] For example, after confirming the number of P-column areas, the total number of P-column areas, i.e., the first number, can be divided by the second number (e.g., 5) to divide the area into 5 regions, with each region having the same number of column areas.

[0093] 803. Establish a target coordinate system with the width direction of the column area as the first coordinate axis direction and the depth direction of the column area as the second coordinate axis direction.

[0094] Specifically, such as Figure 1 As shown, an X-axis (first coordinate axis) and a Y-axis (second coordinate axis) can be established. The left boundary of the first column 4 in the terminal region (i.e., the column 4 closest to the cell region) is the starting position of the X-axis, and the upper surface of column 4 is the starting position of the Y-axis. The width of column 4 is marked along the X-axis direction, and the depth of column 4 is marked along the Y-axis direction.

[0095] 804. For each column group, determine the coordinate value of the center line of the width of the column group that is farthest from the cell region in the column group as the first coordinate value of the column group. Based on the preset curve formula constructed based on the target coordinate system and the first coordinate value, determine the second coordinate value of the column group on the second coordinate axis.

[0096] For example, it can be based on the ellipse formula: x 2 / a 2 +y 2 / b 2 =1 determines the arrangement and distribution of each column region 4. Here, 'a' is the difference between the width of the terminal region and 'm', where 'm' ranges from 100μm to 150μm, and 'b' is the length of each column region 4 within the cell region. The depth 'y' of each group of column regions 4 can be obtained based on the x-coordinate of the same feature point as input. For example, the depth 'y' of the group of column regions 4 can be obtained by using the x-coordinate of the perpendicular bisector of the widest side of the last column region 4 (the column region 4 furthest from the cell region).

[0097] 805. Determine the terminal structure based on the first and second coordinate values ​​corresponding to each column group.

[0098] Specifically, after determining the first and second coordinate values ​​(equivalent to the column depth), the arrangement of each column can be determined, thereby determining the terminal structure.

[0099] To ensure reliability, steps 801 to 804 can be iterated to ensure that the second coordinate value, i.e. the depth, corresponding to each column region is greater than 40 micrometers.

[0100] In some embodiments, the preset curve formula is the ellipse formula.

[0101] The method for determining the termination structure of a superjunction insulated gate bipolar transistor (SGB) provided in this embodiment optimizes the electric field distribution in the termination region and improves the overall performance of the device through a series of precise steps. First, by obtaining the dimensions of the termination region and the width and spacing of the pillar regions, the number of pillar regions that can be constructed in the epitaxial region is determined, ensuring the basic accuracy of the design. Next, the pillar regions are divided into equal groups to facilitate subsequent coordinate system construction and electric field optimization. By establishing a target coordinate system and using the elliptic formula to determine the coordinate values ​​of each pillar group, a more uniform electric field distribution can be achieved within the termination region, reducing electric field concentration and lowering the risk of breakdown. Finally, the termination structure is determined based on the coordinate values ​​of each pillar group, ensuring a smooth electric field transition and high voltage withstand capability of the device. This not only improves the stability and reliability of the device under high voltage conditions but also achieves a higher voltage withstand capability within the same termination area, increasing the device's termination utilization rate.

[0102] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A superjunction insulated gate bipolar transistor, characterized in that, include: The cell region located at the center, and the terminal region located around the cell region; Multiple sets of pillar regions are formed in parallel in the epitaxial region corresponding to the terminal region; the conductivity type of the pillar regions is opposite to that of the epitaxial region. The column region extends along the thickness direction of the epitaxial region; the extension depth of each column region in each group is consistent, and the extension depth of each column region in each group decreases as the distance from the cell region increases; the width of the column region is less than the width of the cell region; the minimum interval between the column region in the epitaxial region corresponding to the terminal region and the column region in the epitaxial region corresponding to the cell region is less than the width of the cell region.

2. The transistor according to claim 1, characterized in that, In the epitaxial region, a terminal main junction and a terminal ring region are formed above the multiple sets of pillar regions; the conductivity type of the terminal ring region is opposite to that of the epitaxial region.

3. The transistor according to claim 2, characterized in that, The field limiting rings in the terminal ring area are distributed at equal intervals, or the inner ring lines of the field limiting rings in the terminal ring area are equally spaced.

4. The transistor according to claim 2, characterized in that, The distance between the column region farthest from the cell region in the epitaxial region corresponding to the terminal region and the field limiting ring farthest from the cell region in the terminal ring region is greater than or equal to 20 micrometers and less than or equal to 30 micrometers.

5. The transistor according to claim 2, characterized in that, The distance between the lower surface of the terminal ring region and the upper surface of the column region is greater than or equal to 1 micrometer and less than or equal to 2 micrometers.

6. The transistor according to any one of claims 1-5, characterized in that, The spacing between the plurality of column regions increases as the distance from the cell region increases.

7. The transistor according to any one of claims 1-5, characterized in that, The depth of the column region is greater than 40 micrometers.

8. The transistor according to any one of claims 1-5, characterized in that, The coordinates of the feature points corresponding to the multiple groups of column regions are elliptical; the feature point is the midpoint of the column region that is farthest from the cell region in the corresponding column region group.

9. The transistor according to any one of claims 1-5, characterized in that, The distance between the column region and the lower surface of the epitaxial region is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

10. The transistor according to any one of claims 1-5, characterized in that, The width of the column region is in a preset ratio to the width of the cell region, wherein the preset ratio is less than or equal to 2 / 3 and greater than or equal to 1 / 3.

11. The transistor according to any one of claims 1-5, characterized in that, The terminal region also includes a silicon carbide substrate located below the epitaxial region.

Images