Manufacturing method of semiconductor device and product thereof

Abstract

The invention relates to a semiconductor device, which comprises a semiconductor substrate unit, a two-dimensional material layer, two single crystals and two metal electrode layers, wherein the two-dimensional material layer is formed on the semiconductor substrate unit and consists of a transition metal disulfide. The single crystals are arranged on the two-dimensional material layer at intervals. Each single crystal is composed of a first metal material or an intermetallic compound composed of the first metal material and a second metal material. The metal electrode layers are made of the second metal material, and each metal electrode layer is in contact with the corresponding single crystal. In the invention, the first metal material has a first melting point, the second metal material has a second melting point, and the first melting point is lower than the second melting point. The invention also provides a manufacturing method of the semiconductor device. By means of the single crystals of the first metal materials or the single crystals of the intermetallic compounds on the two-dimensional material layer, the contact resistance can be reduced, and the current density can be improved.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a method for manufacturing a semiconductor device and the product thereof. Background Technology

[0002] Transition metal dichalcogenides (TMDs), with their two-dimensional layered structure consisting of only molecular layers, can transition from an indirect bandgap in three-dimensional structures to a direct bandgap. When fabricated into field-effect transistors (FETs), they exhibit excellent on / off current ratios, thus attracting significant attention in recent years. Common TMDs include two-dimensional semiconductor materials such as molybdenum disulfide (MoS2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), and tungsten diselenide (WSe2).

[0003] See Figure 1 Taiwan Patent No. TW202109882 (hereinafter referred to as Case 1) discloses a conventional semiconductor device 1, which includes a substrate 11, a semiconductor two-dimensional material (e.g., MoS2) layer 12 disposed on the substrate 11, a source film structure 13S and a drain film structure 13D respectively disposed on a source region 12S and a drain region 12D of the semiconductor two-dimensional material layer 12, a gate dielectric layer 14 extending along a channel region 12C of the semiconductor two-dimensional material layer 12 and partially exposing the source film structure 13S and the drain film structure 13D, and a gate electrode 15 disposed on the gate dielectric layer 14. The source electrode layer structure 13S and the drain electrode layer structure 13D each have a sequentially stacked conductive two-dimensional material layer 131S and 131D containing group IV elements, a discrete metal layer 132S and 132D, and an electrode metal layer 133S and 133D. Each conductive two-dimensional material layer 131S and 131D is made of germanene or stanene. Each discrete metal layer 132S and 132D can be made of a metallic material such as aluminum (Al), bismuth (Bi), cadmium (Cd), chromium (Cr), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), or tungsten (W) that does not form an alloy with the conductive two-dimensional material layers 131S and 131D. Each electrode metal layer 133S and 133D can be made of metal materials such as indium (In), lead (Pb), copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), cobalt (Co), rhodium (Rh), iron (Fe), ruthenium (Ru), manganese (Mn), molybdenum (Mo), vanadium (V), titanium (Ti), zirconium (Zr), hafnium (Hf), or magnesium (Mg), which can form alloys with each conductive two-dimensional material layer 131S and 131D.

[0004] However, the current density of TMDs transistors is often limited by contact resistance (Rc). This is because during the fabrication of TMDs transistors, the two-dimensional semiconductor material is easily damaged and defects are generated by the high energy during the fabrication of the contact electrode metal layer, which in turn triggers the pinning effect of the Fermi level, ultimately making it impossible to effectively reduce the Schottky barrier.

[0005] As explained above, improving the manufacturing process and structure of semiconductor devices to effectively reduce contact resistance and increase current density is a problem that needs to be solved by relevant companies in this technical field. Summary of the Invention

[0006] The first objective of this invention is to provide a method for manufacturing a semiconductor device that can effectively reduce contact resistance and increase current density.

[0007] The method for manufacturing the semiconductor device of the present invention includes the following steps: step (a), step (b), step (c), and step (d).

[0008] Step (a) involves forming a two-dimensional material layer composed of transition metal dichalcogenides on a semiconductor substrate unit.

[0009] Step (b) involves forming two spaced-apart lower metal layers, each composed of a first metal material, on the two-dimensional material layer.

[0010] Step (c) involves forming an upper metal layer made of a second metal material on each of the lower metal layers, so that each upper metal layer and the lower metal layer form a double-layer structure.

[0011] Step (d) involves selectively annealing the bilayer structure and then cooling it to room temperature.

[0012] In this invention, the first metallic material has a first melting point, and the second metallic material has a second melting point, wherein the first melting point is lower than the second melting point.

[0013] In each bilayer structure, the first metal material and the second metal material are alloyed during the selective annealing process, and after cooling to room temperature, a single crystal of the first metal material and a metal electrode layer of the second metal material are precipitated. The single crystal of the first metal material is spaced apart on the two-dimensional material layer, and the metal electrode layer of each second metal material is in contact with the single crystal of the corresponding first metal material. Alternatively, in each bilayer structure, a portion of the second metal material and a portion of the first metal material generate an intermetallic compound during the selective annealing process, and the remaining portion of the second metal material and the intermetallic compound in each bilayer structure, after cooling to room temperature, respectively form a metal electrode layer of the second metal material and a single crystal of the intermetallic compound. The single crystal of the intermetallic compound is spaced apart on the two-dimensional material layer, and the metal electrode layer of each second metal material is in contact with the single crystal of the corresponding intermetallic compound.

[0014] In the method for manufacturing the semiconductor device of the present invention, the first metal material is selected from Bi, Sb, In, Sn, or Pb, and the second metal material is selected from Au, Ni, Pt, Pd, Ti, or Al. However, under certain conditions, when the first metal material is Bi or Sn, the second metal material excludes Al; when the first metal material is Pb, the second metal material excludes Ni, Ti, and Al.

[0015] In the method for manufacturing the semiconductor device of the present invention, the first metal material is Bi, and the second metal material is Au or Ni.

[0016] In the method for manufacturing the semiconductor device of the present invention, the first metal material is Bi, the second metal material is Ni, each single crystal of the intermetallic compound is Bi3Ni, each single crystal of the intermetallic compound has a plurality of Bi3Ni layers stacked along the thickness direction of the two-dimensional material layer, and each metal electrode layer of the second metal material is respectively formed on the upper surface of each single crystal of the intermetallic compound.

[0017] In the method for manufacturing the semiconductor device of the present invention, in step (d), the remaining portion of the first metal material in each double-layer structure forms a Bi contact layer after cooling to room temperature. Each Bi contact layer is sandwiched between the Bi3Ni layer of the single crystal of the corresponding intermetallic compound and the two-dimensional material layer.

[0018] In the method for manufacturing the semiconductor device of the present invention, the lower metal layer of each double-layer structure has a first thickness between 1 nm and 20 nm.

[0019] In the method for manufacturing the semiconductor device of the present invention, the upper metal layer of each double-layer structure has a second thickness between 10 nm and 100 nm.

[0020] The method for manufacturing the semiconductor device of the present invention involves selective annealing performed by laser annealing from above the bilayer structure, wherein the laser used in the laser annealing technique has a predetermined wavelength range between 800 nm and 1 mm.

[0021] The method for manufacturing a semiconductor device according to the present invention includes a semiconductor substrate unit comprising a doped semiconductor substrate and a dielectric layer formed on the doped semiconductor substrate.

[0022] A second object of the present invention is to provide a semiconductor device obtained by the aforementioned manufacturing method.

[0023] The semiconductor device of the present invention includes a semiconductor substrate unit, a two-dimensional material layer formed on the semiconductor substrate unit and composed of a transition metal dichalcogenide, two single crystals, and two metal electrode layers. The single crystals are spaced apart on the two-dimensional material layer. Each single crystal is composed of a first metal material or a mesometallic compound composed of the first metal material and a second metal material. The metal electrode layers are composed of the second metal material, and each metal electrode layer contacts its corresponding single crystal. In this invention, the first metal material has a first melting point, and the second metal material has a second melting point, wherein the first melting point is lower than the second melting point.

[0024] In the semiconductor device of the present invention, the first metal material is selected from Bi, Sb, In, Sn, or Pb, and the second metal material is selected from Au, Ni, Pt, Pd, Ti, or Al. However, under certain conditions, when the first metal material is Bi or Sn, the second metal material excludes Al; when the first metal material is Pb, the second metal material excludes Ni, Ti, and Al.

[0025] In the semiconductor device of the present invention, the first metal material is Bi, and the second metal material is Au or Ni.

[0026] In the semiconductor device of the present invention, the first metal material is Bi, the second metal material is Ni, each single crystal of the intermetallic compound is Bi3Ni, each single crystal has a plurality of Bi3Ni layers stacked along the thickness direction of the two-dimensional material layer, and each metal electrode layer of the second metal material is respectively formed on the upper surface of each single crystal of the intermetallic compound.

[0027] The semiconductor device of the present invention further includes two Bi contact layers, each of which is sandwiched between a Bi3Ni layer of a single crystal of a corresponding intermetallic compound and the two-dimensional material layer.

[0028] The semiconductor device of the present invention includes a semiconductor substrate unit comprising a doped semiconductor substrate and a dielectric layer formed on the doped semiconductor substrate.

[0029] The beneficial effects of the present invention are that the single crystals of each first metal material or each monometallic compound located on the two-dimensional material layer help to reduce contact resistance and increase current density. Attached Figure Description

[0030] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:

[0031] Figure 1 This is a schematic diagram illustrating a conventional semiconductor device disclosed in early publication No. TW202109882 of the Taiwan Patent Application.

[0032] Figures 2A to 2D Each of these is a schematic diagram illustrating a step (a), a step (b), a step (c), and a step (d) of a first embodiment of the manufacturing method of the semiconductor device of the present invention.

[0033] Figures 3A to 3H Each is a schematic diagram illustrating the detailed process of step (a) of the manufacturing method of the first embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram illustrating the process of implementing step (d) in the manufacturing method of the first embodiment of the present invention and the resulting semiconductor device;

[0035] Figure 5 This is a schematic diagram illustrating a second embodiment of the method for manufacturing a semiconductor device according to the present invention, the process of carrying out step (d), and the resulting semiconductor device;

[0036] Figure 6 This is a schematic diagram illustrating a third embodiment of the method for manufacturing a semiconductor device according to the present invention, the process of carrying out step (d), and the resulting semiconductor device;

[0037] Figure 7 It is a Raman spectrum;

[0038] Figure 8A and Figure 8B Each is a cross-sectional image obtained by a transmission electron microscope (hereinafter referred to as TEM), illustrating a microscopic image of a semiconductor device obtained in a specific example 1 (E1) of the manufacturing method of the present invention;

[0039] Figure 9 It is a cross-sectional image of a high-resolution transmission electron microscope (hereinafter referred to as HRTEM), illustrating a Bi single crystal of the semiconductor device of this specific example 1 (E1) of the present invention;

[0040] Figure 10A It is a current density versus gate voltage (Vg) curve, illustrating a comparison of the transfer characteristics of the semiconductor device of this specific example 1 (E1) of the present invention with those of a semiconductor device of comparative example 1 (CE1).

[0041] Figure 10B It is a total resistance (R) total The relationship between channel length (L) is used to illustrate the comparison of the electrical characteristics of the semiconductor device of this specific example 1 (E1) and the semiconductor device of this comparative example 1 (CE1), and its y-intercept is twice the contact resistance (2Rc).

[0042] Figure 11 It is a grazing-incidence x-ray diffraction (GIXRD) pattern illustrating the crystal structure of a semiconductor device obtained by a specific example 3 (E3) of the manufacturing method of the present invention, and the semiconductor devices obtained by the manufacturing methods of comparative example 2 (CE2) and comparative example 3 (CE3).

[0043] Figure 12A This is a TEM cross-sectional image, illustrating a microscopic image of the semiconductor device obtained by the method of Comparative Example 2 (CE2);

[0044] Figure 12B This is a TEM cross-sectional image illustrating a microscopic image of a semiconductor device obtained by the method of Comparative Example 4 (CE4).

[0045] Figure 13A It is a TEM cross-sectional image with a partially magnified TEM cross-sectional image inserted in the lower right corner, illustrating a microscopic image of a semiconductor device obtained in a specific example 2 (E2) of the manufacturing method of the present invention;

[0046] Figure 13B yes Figure 13A A magnified cross-sectional image illustrating a Bi3Ni single crystal of the semiconductor device of this specific example 2 (E2) of the present invention;

[0047] Figure 14 This is a TEM cross-sectional image illustrating the contact between a Bi contact layer and a MoS2 two-dimensional material layer in the semiconductor device of this specific example 3 (E3) of the present invention.

[0048] Figure 15A It is a drain current versus gate voltage (hereinafter referred to as Id-Vg) curve, illustrating the comparison of the transfer characteristics of the semiconductor device of Comparative Example 2 (CE2) and the semiconductor device of Comparative Example 4 (CE4);

[0049] Figure 15B It is an Id-Vg curve graph, which illustrates the comparison of the transmission characteristics of the semiconductor device of Comparative Example 2 (CE2) and the semiconductor device of Specific Example 2 (E2) of the present invention;

[0050] Figure 15C It is an Id-Vg curve graph, illustrating the comparison of the transmission characteristics of the semiconductor device of Comparative Example 2 (CE2) and the semiconductor device of Specific Example 3 (E3) of the present invention;

[0051] Figure 16A This is a graph showing the relationship between total resistance and channel length, illustrating the contact resistance of the semiconductor device in Comparative Example 2 (CE2).

[0052] Figure 16B This is a graph showing the relationship between total resistance and channel length, illustrating the contact resistance of the semiconductor device in this specific example 3 (E3) of the present invention.

[0053] Figure 17A and Figure 17B The graphs are respectively the drain current density versus gate voltage (Vg) curves, illustrating the comparison of the transfer characteristics of the semiconductor device of Comparative Example 2 (CE2) after undergoing different annealing temperatures;

[0054] Figure 18A and Figure 18B The graphs are respectively the drain current density versus gate voltage (Vg) curves, illustrating the comparison of the transfer characteristics of the semiconductor device of this specific example 3 (E3) after undergoing different annealing temperatures;

[0055] Figure 19A and Figure 19B The graphs are respectively the drain current density versus gate voltage (Vg) curves, illustrating the comparison of the transfer characteristics of the semiconductor device of this specific example 1 (E1) after undergoing different annealing temperatures;

[0056] Figure 20 It is self Figure 17A , Figure 17B , Figure 18A , Figure 18B and Figure 19A , Figure 19B The obtained graph shows the relationship between the current density and the annealing temperature.

[0057] Figure 21A This is a drain current density versus gate voltage (Vg) graph, illustrating a comparison of the transfer characteristics of the semiconductor device in Comparative Example 2 (CE2) and Specific Example 3 (E3) of the present invention; and

[0058] Figure 21B It is a drain current density versus drain voltage (Vd) curve, illustrating the output characteristics of the semiconductor device of this specific example 3 (E3) of the present invention. Detailed Implementation

[0059] Before the invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0060] See Figures 2 and 3. Figure 4 The present invention discloses a method for manufacturing a semiconductor device and a product thereof, and a first embodiment thereof. The method for manufacturing the first embodiment of the present invention includes the following steps: step (a), step (b), step (c), and step (d).

[0061] like Figure 2A As shown, step (a) involves forming a two-dimensional material layer 3 composed of a transition metal dichalcogenide (TMD) on a semiconductor substrate unit 2. The semiconductor substrate unit 2 includes a doped semiconductor substrate 21 and a dielectric layer 22 formed on the doped semiconductor substrate 21. In this first embodiment of the invention, the doped semiconductor substrate 21 and the dielectric layer 22 are illustrated using a heavily phosphorus (P)-doped N-type silicon substrate and a silicon dioxide (SiO2) layer as examples, but are not limited thereto. The TMDs applicable to this first embodiment of the invention can be selected from MoS2, WS2, MoSe2, or WSe2. In this first embodiment of the invention, the TMDs are illustrated using the N-type semiconductor material MoS2 as an example, but are not limited thereto. Specifically, the N-type silicon substrate and the silicon dioxide layer are used as a bottom gate and a gate dielectric layer, respectively, of the semiconductor device finally completed by the method in this first embodiment of the invention, while the two-dimensional material layer 3 is used as a channel layer of the semiconductor device.

[0062] In step (a) of the first embodiment of the present invention, the two-dimensional material layer 3 is transmitted via... Figures 3A to 3H The wet transfer method shown is used to form the semiconductor substrate unit 2. Specifically, the two-dimensional material layer 3 is first formed on a sapphire substrate 301 by chemical vapor deposition (CVD). Figure 3A (As shown). Next, as... Figure 3B As shown, a polymethyl methacrylate (PMMA) layer 302 is coated onto the sapphire substrate 301, on which the two-dimensional material layer 3 is formed, using a spin coating method. Subsequently, the sapphire substrate 301 coated with the PMMA layer 302 is immersed in a 1M potassium hydroxide (KOH) aqueous solution 303, causing the KOH aqueous solution 303 to etch from the periphery of the PMMA layer 302 toward the two-dimensional material layer 3. After the periphery of the PMMA layer 302 detaches from the sapphire substrate 301, the two-dimensional material layer 3 gradually detaches from the sapphire substrate 301 due to surface tension and the buoyancy contributed by the KOH aqueous solution 303 (see [link to documentation]). Figure 3D Next, the two-dimensional material layer 3, covered with the PMMA layer 302, is placed in a deionized water 304 (see [link]). Figure 3E After that, the semiconductor substrate unit 2 is placed in the deionized water 304 to retrieve the two-dimensional material layer 3 covered by the PMMA layer 302 (see [link]). Figure 3F Subsequently, the PMMA layer 302, the two-dimensional material layer 3, and the semiconductor substrate unit 2 are placed together on a heating plate (not shown) and dried at 100°C (e.g., Figure 3G Next, the PMMA layer 302, the two-dimensional material layer 3, and the semiconductor substrate unit 2 are sequentially immersed in acetone at 60°C for 10 minutes to remove the PMMA layer 302 (see [link]). Figure 3H The acetone is removed by immersion in isopropanol (IPA) and then dried with nitrogen (N2) to complete step (a).

[0063] like Figure 2B As shown, step (b) involves forming two spaced-apart lower metal layers 61 on the two-dimensional material layer 3, each composed of a first metal material.

[0064] like Figure 2C As shown, step (c) involves forming an upper metal layer 62 made of a second metal material on each of the lower metal layers 61, so that each upper metal layer 62 and the lower metal layer 61 form a double-layer structure 6.

[0065] like Figure 2D As shown, step (d) involves applying selective annealing to the bilayer structure 6 and then cooling it to room temperature. This selective annealing is performed from above the bilayer structure 6 using a laser annealing technique. The laser used in this technique has a predetermined wavelength range between 800 nm and 1 mm. It should be noted that selective annealing means that the thermal energy of the laser within this predetermined wavelength range can be absorbed by the lower metal layer 61 and the upper metal layer 62 of each bilayer structure 6, but not by the two-dimensional material layer 3. Therefore, during selective annealing, each bilayer structure 6 undergoes a phase transformation due to the thermal energy of the laser, while the two-dimensional material layer 3, partially covered by each bilayer structure 6, is not damaged by the thermal energy of the laser.

[0066] In this invention, the first metallic material has a first melting point, and the second metallic material has a second melting point, wherein the first melting point is lower than the second melting point. The first metallic material applicable to this invention is selected from Bi, Sb, In, Sn, or Pb, and the second metallic material is selected from Au, Ni, Pt, Pd, Ti, or Al. However, conditionally, when the first metallic material is Bi or Sn, Al is excluded from the second metallic material; when the first metallic material is Pb, Ni, Ti, and Al are excluded from the second metallic material.

[0067] In some embodiments, the lower metal layer 61 of each double-layer structure 6 has a first thickness between 1 nm and 20 nm, and the upper metal layer 62 of each double-layer structure 6 has a second thickness between 10 nm and 100 nm. In some embodiments, the first thickness of each lower metal layer 61 is between 2 nm and 12 nm, and the second thickness of each upper metal layer 62 is between 35 nm and 75 nm. In this first embodiment of the invention, the first metal material is Bi, and the second metal material is Au.

[0068] Please see Figure 4 In detail, the first metal material and the second metal material in each of the double-layer structures 6 are alloyed during the selective annealing process, and after cooling to room temperature, a single crystal 41 of the first metal material (Bi) and a metal electrode layer 5 of the second metal material (Au) are precipitated respectively, thereby obtaining the semiconductor device of the first embodiment of the present invention. The single crystal 41 of the first metal material is spaced apart on the two-dimensional material layer 3, and the metal electrode layer 5 of each of the second metal materials is in contact with the single crystal 41 of the corresponding first metal material. Thus, it can be seen that the single crystal 41 of each of the first metal materials (Bi) is composed of the first metal material, and the metal electrode layer 5 is composed of the second metal material (Au).

[0069] It should be further explained here that the thickness of the lower metal layer (Bi) 61 in each of the double-layer structures 6 in the first embodiment determines the position of the single crystal precipitated after selective annealing and cooling to room temperature. Specifically, when the first thickness of each lower metal layer 61 is relatively thick, after selective annealing and cooling to room temperature, single crystals 41 of the first metal material (Bi) tend to precipitate on a periphery and an upper surface (e.g., the metal electrode layer 5 of the corresponding second metal material (Au)). Figure 4 (As shown). When the first thickness of each lower metal layer 61 is relatively thin, after selective annealing and cooling to room temperature, the single crystal 41 of the first metal material (Bi) tends to precipitate on the lower surface of the metal electrode layer 5 of the corresponding second metal material (Au) to directly contact the two-dimensional material layer 3.

[0070] See Figure 5 A second embodiment of the method for manufacturing the semiconductor device and its product is substantially the same as the first embodiment, except that the second metal material is Ni. Specifically, a portion of the second metal material and a portion of the first metal material in each double-layer structure 6 are used to form a dielectric metal compound during the selective annealing process. After cooling to room temperature, a remaining portion of the second metal material and the dielectric metal compound respectively form a metal electrode layer 5 of the second metal material and a single crystal 42 of the dielectric metal compound. The single crystal 42 of the dielectric metal compound is spaced apart on the two-dimensional material layer 3, and the metal electrode layer 5 of each second metal material is in contact with its corresponding single crystal 42 of the dielectric metal compound. Therefore, each single crystal 42 of the dielectric metal compound is a dielectric metal compound composed of the portion of the first metal material and the portion of the second metal material.

[0071] In detail, each single crystal 42 of the intermetallic compound is Bi3Ni. Each single crystal 42 of the intermetallic compound has multiple Bi3Ni layers (not shown) stacked along a thickness direction of the two-dimensional material layer 3, and each metal electrode layer 5 of the second metal material is correspondingly formed on an upper surface of each single crystal (Bi3Ni) 42 of the intermetallic compound.

[0072] See Figure 6 A third embodiment of the method for manufacturing the semiconductor device and its product is generally the same as the second embodiment, except that in step (d), a remaining portion of the first metal material in each double-layer structure 6 forms a Bi contact layer 43 after cooling to room temperature. Each Bi contact layer 43 is sandwiched between the Bi3Ni layer of the corresponding monometallic compound single crystal 42 and the two-dimensional material layer 3.

[0073] The present invention provides the following comparative examples and specific examples based on the manufacturing method of the embodiments, and the microstructure and electrical properties detection results of the semiconductor devices obtained by the manufacturing method.

[0074] <Concrete example 1 (E1)>

[0075] A specific example 1 (E1) of the method for manufacturing the semiconductor device of the present invention is implemented according to the first embodiment. First, a two-dimensional MoS2 material layer in this specific example 1 (E1) is formed on a heavily phosphorus-doped N-type silicon substrate by the wet transfer method. Next, a patterned photoresist layer is formed on the MoS2 two-dimensional material layer on the heavily phosphorus-doped N-type silicon substrate by a photolithography process to partially expose two spaced-apart regions of the MoS2 two-dimensional material layer. Then, an electron beam evaporation apparatus is used to deposit a 5×10 -6Up to 1.2×10 -5 Under the operating pressure of torr, a 10 nm Bi layer and a 50 nm Au layer were sequentially deposited on two regions of the MoS2 two-dimensional material layer exposed outside the patterned photoresist layer. Next, the patterned photoresist layer was removed to obtain the two-layer structure of Example 1 (E1). Finally, using a [material name - likely a product name] purchased from Pennsylvania, USA... The DiamondE-1000 CO2 laser annealing apparatus applies selective annealing to each bilayer structure. The selective annealing parameters for this specific example (E1) are summarized in Table 1 below. In this specific example (E1) of the present invention, the MoS2 two-dimensional material layer is used as a channel layer of the semiconductor device, and the length of the channel layer is 17.0 μm, 3 μm, 6 μm, 9 μm, and 12 μm.

[0076] Table 1

[0077]

[0078] <Comparative Example 1 (CE1)>

[0079] A comparative example 1 (CE1) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of specific example 1 (E1), except that the selective annealing is not performed in comparative example 1 (CE1).

[0080] <Concrete example 2 (E2)>

[0081] A specific example 2 (E2) of the method for manufacturing the semiconductor device of the present invention is implemented according to the second embodiment. In this specific example 2 (E2), before depositing a Bi layer with a double-layer structure, a shutter of the electron beam evaporation apparatus is used to shield the underside of a two-dimensional MoS2 material layer. Specifically, after the shutter shields the underside of the MoS2 material layer, the power supply of an electron gun in the electron beam evaporation apparatus is turned on to generate an electron beam that bombards a Bi bulk material in a crucible, causing a bismuth oxide (BiOx) film formed on a surface of the Bi bulk material to deposit on the shutter. After the bismuth oxide film on the surface of the Bi bulk material is completely ejected, the shutter is removed, allowing the Bi bulk material to continue being bombarded by the electron beam, thereby depositing a 10 nm Bi layer on the MoS2 two-dimensional material layer. This avoids the deposition of a BiOx layer on the MoS2 two-dimensional material layer in this specific example 2 (E2) that would affect electrical performance. Next, a 30 nm Ni layer was deposited on the Bi layer in Example 2 (E2). Finally, selective annealing of Example 2 (E2) was performed using selective annealing parameters that were substantially the same as those in Example 1 (E1). The output power and scan speed of Example 2 (E2) during selective annealing were 80 W and 5 cm / sec, respectively. In Example 2 (E2) of the present invention, the MoS2 two-dimensional material layer is used as a channel layer of the semiconductor device, and the length of the channel layer is 3.0 μm, 150 nm, 200 nm, 300 nm, and 500 nm.

[0082] <Concrete example 3 (E3)>

[0083] A specific example 3 (E3) of the method for manufacturing the semiconductor device of the present invention is implemented according to the third embodiment and is substantially the same as that of specific example 2 (E2), except that the scan speed of specific example 3 (E3) during selective annealing is 7 cm / sec.

[0084] <Comparative Example 2 (CE2)>

[0085] A comparative example 2 (CE2) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of specific example 2 (E2), except that the selective annealing is not performed in comparative example 2 (CE2).

[0086] Comparative Example 3 (CE3)

[0087] Comparative Example 3 (CE3) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of Specific Example 2 (E2), except that Comparative Example 3 (CE3) uses a rapid thermal annealing (RTA) technique instead of selective annealing. In Comparative Example 3 (CE3), the RTA technique involves heating to 400°C at a heating rate of 10°C / sec for 60 seconds.

[0088] <Comparative Example 4 (CE4)>

[0089] A comparative example 4 (CE4) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of comparative example 3 (CE3), except that comparative example 4 (CE) is heated to 300°C for 30 seconds when performing an RTA technique.

[0090] <Concrete example 4 (E4)>

[0091] A specific example 4 (E4) of the method for manufacturing the semiconductor device of the present invention is generally the same as that of specific example 2 (E2), except that a 50 nm Au layer is deposited on a Bi layer.

[0092] Depend on Figure 7 The Raman spectra shown indicate that the signal peak positions of the MoS2 two-dimensional material layer in Comparative Example 1 (CE1) are similar to those in Specific Example 1 (E1). This demonstrates that the MoS2 two-dimensional material layer in Specific Example (E1) was not damaged by the CO2 laser after selective annealing, and therefore the signal peak positions of the MoS2 two-dimensional material layer in Specific Example (E1) are similar to those in Comparative Example 1 (CE1).

[0093] The TEM cross-sectional image in Figure 8 shows the relationship with... Figure 9 The HRTEM cross-sectional image shows that, after selective annealing, the Bi in the bilayer structure of this specific example 1 (E1) is precipitated on the side of Au (see...). Figure 8A ) and the upper surface (see Figure 8B Furthermore, the precipitated Bi is a single crystal (see...). Figure 9 It should be noted here that the image shown in the TEM cross-section ( Figure 8A , Figure 8B Bi and Au in the sample were obtained by analysis using an energy dispersive spectrometer (EDS) integrated into a TEM device.

[0094] In addition, by Figure 10A The electrical data shown indicate that the current density of this specific example (E1) is approximately 42% higher than that of the comparative example (CE1).

[0095] The Id-Vg curves corresponding to each channel length of the semiconductor devices in Specific Example 1 (E1) and Comparative Example 1 (CE1) are shown (not shown in the figure; only the Id-Vg curve of the semiconductor device with a channel length of 17 μm is shown, as follows). Figure 10AThe contact resistance (Rc) obtained by calculating the Id-Vd curve (not shown in the figure) and the Id-Vd curve (not shown in the figure) using the transfer length method (TLM) is displayed on the graph. Figure 10B The required carrier concentration for TLM is 8.64 × 10⁻⁶. 12 / cm 2 .Depend on Figure 10B It can be seen that the contact resistance (Rc) of Comparative Example 1 (CE1) is as high as 46.5kΩ·μm, while the contact resistance (Rc) of Specific Example 1 (E1) is only 35kΩ·μm.

[0096] Figure 11 The diagrams shown are GIXRD images of Example 3 (E3), Comparative Example 2 (CE2), and Comparative Example 3 (CE3) of the present invention; wherein, the incident angle of an X-ray incident on Example 3 (E3), Comparative Example 2 (CE2), and Comparative Example 3 (CE3) is set to 0.5 degrees. Figure 11 It can be seen that Comparative Example 2 (CE2), which did not undergo selective annealing, only showed diffraction peaks of Ni, indicating that Comparative Example 2 (CE2) only contained Ni crystalline phase; Comparative Example 3 (CE3), which underwent RTA at 400°C for 60 seconds, showed diffraction peaks of both Ni and BiNi, indicating that Comparative Example 3 (CE3) contained both Ni and BiNi crystalline phases; while Specific Example 3 (E3), which underwent selective annealing at a scan speed of 7 cm / sec and an output power of 80 W, only showed diffraction peaks of Bi3Ni, indicating that the bilayer structure of Specific Example 3 (E3) transformed into the Bi3Ni crystalline phase after CO2 laser annealing.

[0097] Depend on Figure 12A As shown in the TEM cross-sectional image, Comparative Example 2 (CE2) has Bi and Ni sequentially stacked on SiO2, and... Figure 12B As shown in the TEM cross-sectional image, Comparative Example 4 (CE4) has BiNi and Ni sequentially stacked on a MoS2 two-dimensional material layer on SiO2. It should be noted that when the inventors captured the TEM cross-sectional image of the semiconductor device in Comparative Example 2 (CE2), they did not capture the area showing the MoS2 two-dimensional material layer. Therefore, Figure 12A The MoS2 two-dimensional material layer of the semiconductor device of Comparative Example 2 (CE2) is not shown, but will be described here as well.

[0098] Further by Figure 13A and Figure 13BThe TEM cross-sectional image shown reveals that in Example 2 (E2), selective annealing was performed at a scan speed of 5 cm / sec and an output power of 80 W. A Bi3Ni single crystal composed of multiple Bi3Ni layers is sequentially stacked on a MoS2 two-dimensional material layer. Calculations show that the spacing between two adjacent Bi3Ni layers in the Bi3Ni single crystal of Example 2 (E2) is approximately 0.242 nm. Furthermore, from... Figure 14 As shown in the TEM cross-sectional image, in this specific example 3 (E3), selective annealing was performed at a scan speed of 7 cm / sec and an output power of 80 W, Bi and a Bi3Ni single crystal composed of multiple Bi3Ni layers were sequentially stacked on a MoS2 two-dimensional material layer. Figure 13A , Figure 13B and Figure 14 The results show that in Example 2 (E2), where selective annealing was performed at a slower scan speed (5 cm / sec), the Bi in its bilayer structure completely formed the Bi3Ni single crystal with Ni. In Example 3 (E3), where selective annealing was performed at a faster scan speed (7 cm / sec), the Bi in its bilayer structure only partially formed the Bi3Ni single crystal with Ni, leaving residual Bi in contact with the MoS2 two-dimensional material layer. It is worth noting that the melting point of the Bi3Ni single crystals formed after CO2 laser annealing in Examples 2 (E2) and 3 (E3) is higher than that of Bi in Comparative Example 2 (CE2). Therefore, it can be inferred that the semiconductor devices of Examples 2 (E2) and 3 (E3) have higher thermal stability than Comparative Example 2 (CE2). The results of the thermal stability and electrical tests of the semiconductor devices of the present invention will be described later. Similarly, the results shown in the TEM cross-sectional image (…) Figure 12A , Figure 12B , Figure 13A and Figure 14 Ni, Bi, BiNi, Bi3Ni and MoS2 in the sample were obtained by TEM-EDS analysis.

[0099] Depend on Figure 15A , Figure 15B and Figure 15C The electrical analysis results can be calculated, and the carrier mobility (μFE) of the semiconductor device (BiNi contact) in Comparative Example 4 (CE4) is 12.8 cm⁻¹. 2 / V·s decreased to 8.3cm 2 / V·s(see Figure 15A In the semiconductor device of specific example 2 (E2) (Bi3Ni contact), a decrease in μFE from 14.3 to 10.1 cm⁻¹ was also observed. 2 / V·s(see Figure 15BIn contrast, the semiconductor device (Bi3Ni / Bi contact) of this specific example (E3) exhibits stable mobility from 19.5 to 20.3 cm⁻¹. 2 The values ​​remain similar between / V·s (see...) Figure 15C ).

[0100] The Id-Vg curves corresponding to each channel length of the semiconductor devices in Specific Example 3 (E3) and Comparative Example 2 (CE2) are shown (not shown in the figure; only the Id-Vg curves for a 500nm channel length are displayed, such as...). Figure 15C The contact resistance (Rc) calculated by TLM from the Id-Vd curve (not shown in the figure) and the Id-Vd curve (not shown in the figure) is displayed on [the graph]. Figure 16A as well as Figure 16B The required carrier concentration for TLM is 1.43 × 10⁻⁶. 13 / cm 2 .Depend on Figure 16A and Figure 16B It can be seen that the contact resistance (Rc) of Comparative Example 2 (CE2) and Specific Example 3 (E3) are similar, at 177 Ω·μm and 174 Ω·μm respectively.

[0101] The thermal stability and electrical test results of the semiconductor devices of Comparative Example 2 (CE2), Specific Example 3 (E3), and Specific Example 1 (E1) of the present invention are respectively shown in... Figure 17A , Figure 17B , Figure 18A , Figure 18B and Figure 19A , Figure 19B Specifically, the semiconductor devices of Comparative Example 2 (CE2), Specific Example 3 (E3), and Specific Example 1 (E1) were each subjected to a 5-minute RTA at different temperatures within a temperature range of 200°C to 500°C in a nitrogen atmosphere, and then an IV measurement was performed after each heating cycle.

[0102] Depend on Figure 17A and Figure 17B As can be seen from the display, the semiconductor device of Comparative Example 2 (CE2) has a drain voltage (hereinafter referred to as V). DS The slope of the linear region of the Id-Vg curve obtained under the condition of 1V decreases as the temperature of the RTA increases, indicating that the contact resistance (Rc) of the semiconductor device in Comparative Example 2 (CE2) increases with the temperature of the RTA. Furthermore, Figure 17A It was also observed that after one RTA at 400°C, the on / off ratio of the semiconductor device of Comparative Example 2 (CE2) dropped to below one order of magnitude, indicating that the electrical properties of Comparative Example 2 (CE2) had significantly decreased after the RTA at 400°C.

[0103] Depend on Figure 18A and Figure 18B As can be seen from the diagram, the semiconductor device in this specific example 3 (E3) is in V DS While the slope of the linear region of the Id-Vg curve obtained at 1V decreases with increasing RTA temperature, the slope of the linear region of the Id-Vg curve for the semiconductor device of Example 3 (E3) remains stable when the RTA temperature reaches 300°C. Even after a single RTA at 500°C, the semiconductor device of Example 3 (E3) maintains an on / off ratio of four orders of magnitude (see [link to RTA]). Figure 18A This confirms that the Bi3Ni single crystal in the semiconductor device of this specific example 3 (E3) provides excellent thermal stability for its electrical performance.

[0104] Depend on Figure 19A and Figure 19B As can be seen from the diagram, the semiconductor device in this specific example 1 (E1) is in V DS The slope of the linear region of the Id-Vg curve obtained under the condition of 1V decreases significantly with increasing RTA temperature, and Figure 19A It also shows that after one RTA at 350°C, the on / off ratio of the semiconductor device in this specific example (E1) is less than an order of magnitude.

[0105] Depend on Figure 20 It can be seen that the semiconductor device of this specific example 3 (E3) after sequentially undergoing RTA at 200°C, 250°C and 300°C still maintains a conduction current density of about 2.5 μA / μm and shows no decreasing trend. In contrast, the semiconductor devices of Comparative Example 2 (CE2) and Specific Example 1 (E1) after sequentially undergoing RTA at 200°C, 250°C and 300°C only retain about 50% and 21% of the conduction current density, respectively.

[0106] Depend on Figure 21A It can be seen that the carrier mobility and conduction current density of Comparative Example 2 (CE2) without selective annealing and Specific Example 3 (E3) with selective annealing performed at a scan speed of 7 cm / sec and an output power of 80 W are similar. It is noteworthy that the critical voltage (Vth) and sub-threshold swing (SS) of Comparative Example 2 (CE2) without selective annealing are -4.7 V and 1680 mV / dec, respectively. However, after selective annealing at a scan speed of 7 cm / sec and an output power of 80 W (i.e., Specific Example 3 (E3)), the critical voltage (Vth) and SS shift positively to -0.7 V and decrease to 1020 mV / dec, respectively. This can be attributed to the selective annealing of Specific Example 3 (E3). Furthermore, from Figure 21BIt can be seen that the output characteristics of the semiconductor device of this specific example 3 (E3) of the present invention exhibit clear ohmic contact behavior at gate voltages between 0V and 35V.

[0107] In summary, the method for manufacturing the semiconductor device and its product of the present invention, by means of the single crystals 41 of each first metal material (Bi) located on the two-dimensional material layer 3, can help reduce the contact resistance (Rc) and increase the current density, and the single crystals (Bi3Ni) 42 of each dielectric metal compound can also help improve the thermal stability of the semiconductor device, so the purpose of the present invention can indeed be achieved.

[0108] The above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the claims and description of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Includes the following steps: Step (a): A two-dimensional material layer composed of transition metal dichalcogenides is formed on a semiconductor substrate unit; Step (b) involves forming two spaced-apart lower metal layers, each composed of a first metal material, on the two-dimensional material layer. Step (c) involves forming an upper metal layer made of a second metal material on each lower metal layer, thereby forming a double-layer structure with each lower metal layer. Step (d): The double-layer structure is selectively annealed and then cooled to room temperature; Wherein, the first metallic material has a first melting point, and the second metallic material has a second melting point, wherein the first melting point is lower than the second melting point; In each of the two-layer structures, the first metal material and the second metal material are alloyed during selective annealing, and after cooling to room temperature, single crystals of the first metal material and metal electrode layers of the second metal material are precipitated respectively. The single crystals of the first metal material are spaced apart on the two-dimensional material layers, and the metal electrode layers of each second metal material are in contact with their respective single crystals of the first metal material; or In each of the bilayer structures, the portion of the second metal material and the portion of the first metal material are converted into a mesometallic compound during the selective annealing process. After cooling to room temperature, the remaining portion of the second metal material and the mesometallic compound respectively form a metal electrode layer of the second metal material and a single crystal of the mesometallic compound. The single crystal of the mesometallic compound is spaced apart on the two-dimensional material layer, and the metal electrode layer of each second metal material is in contact with the single crystal of the corresponding mesometallic compound.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The first metallic material is selected from Bi, Sb, In, Sn, or Pb, and the second metallic material is selected from Au, Ni, Pt, Pd, Ti, or Al. However, under certain conditions, when the first metallic material is Bi or Sn, the second metallic material excludes Al; when the first metallic material is Pb, the second metallic material excludes Ni, Ti, and Al.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that: The first metallic material is Bi, and the second metallic material is Au or Ni.

4. The method for manufacturing a semiconductor device according to claim 2, characterized in that: The first metallic material is Bi, the second metallic material is Ni, each single crystal of the intermetallic compound is Bi3Ni, each single crystal of the intermetallic compound has multiple Bi3Ni layers stacked along the thickness direction of the two-dimensional material layer, and each metal electrode layer of the second metallic material is respectively formed on the upper surface of each single crystal of the intermetallic compound.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that: In step (d), the remaining portion of the first metal material in each bilayer structure forms a Bi contact layer after cooling to room temperature. Each Bi contact layer is sandwiched between the Bi3Ni layer of the corresponding monometallic compound single crystal and the two-dimensional material layer.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that: Each double-layer structure has a lower metal layer with a first thickness between 1 nm and 20 nm.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that: Each double-layer structure has an upper metal layer with a second thickness between 10 nm and 100 nm.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The selective annealing is performed by laser annealing from above the bilayer structure, and the laser used in this laser annealing technique has a predetermined wavelength range between 800 nm and 1 mm.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The semiconductor substrate unit includes a doped semiconductor substrate and a dielectric layer formed on the doped semiconductor substrate.

10. A semiconductor device, characterized in that: Include: Semiconductor substrate unit; A two-dimensional material layer is formed on the semiconductor substrate unit and is composed of transition metal dichalcogenides; Two single crystals are spaced apart on the two-dimensional material layer. Each single crystal is composed of a first metallic material or a mesometallic compound composed of the first metallic material and a second metallic material. Two metal electrode layers are made of the second metal material, and each metal electrode layer is in contact with its corresponding single crystal. The first metallic material has a first melting point, and the second metallic material has a second melting point, wherein the first melting point is lower than the second melting point.

11. The semiconductor device according to claim 10, characterized in that: The first metallic material is selected from Bi, Sb, In, Sn, or Pb, and the second metallic material is selected from Au, Ni, Pt, Pd, Ti, or Al. However, under certain conditions, when the first metallic material is Bi or Sn, the second metallic material excludes Al; when the first metallic material is Pb, the second metallic material excludes Ni, Ti, and Al.

12. The semiconductor device according to claim 11, characterized in that: The first metallic material is Bi, and the second metallic material is Au or Ni.

13. The semiconductor device according to claim 11, characterized in that: The first metallic material is Bi, the second metallic material is Ni, each single crystal of the intermetallic compound is Bi3Ni, each single crystal has multiple Bi3Ni layers stacked along the thickness direction of the two-dimensional material layer, and each metal electrode layer of the second metallic material is respectively formed on the upper surface of each single crystal of the intermetallic compound.

14. The semiconductor device according to claim 13, characterized in that: The semiconductor device further includes two Bi contact layers, each of which is sandwiched between a Bi3Ni layer of a corresponding monometallic compound single crystal and the two-dimensional material layer.

15. The semiconductor device according to claim 10, characterized in that: The semiconductor substrate unit includes a doped semiconductor substrate and a dielectric layer formed on the doped semiconductor substrate.

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