Method for forming semiconductor device, and semiconductor structure

Abstract

A method of the present disclosure includes forming a stack including channel layers interleaved by sacrificial layers; patterning the stack to form a fin structure; forming a dummy gate stack over the channel region of the fin structure; recessing the source / drain region of the fin-shaped structure to form a trench; removing the sacrificial layer in the channel region to release the channel layer as a channel member; forming a dielectric dummy layer filling a space between the channel members; forming a source / drain feature in the trench; removing the dummy gate stack; removing the dielectric dummy layer to release the channel member; trimming the channel member to reduce a thickness of the channel member; and forming a gate structure to wrap around the channel member. The embodiment of the invention relates to a method for forming a semiconductor device and a semiconductor structure.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices and semiconductor structures. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, as the geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) shrinks, the functional density (i.e., the number of interconnect devices per unit chip area) typically increases. This scaling-down process generally provides numerous benefits through increased yield efficiency and reduced associated costs. However, this scaling-down process also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology advances to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCE). Multi-gate devices generally refer to devices with a gate structure, or a portion thereof, positioned above more than one side of the channel region. Gate-all-around (GAA) transistors are an example of multi-gate devices and have become a popular and promising candidate for high-performance and low-leakage applications. The gate structure of a GAA transistor can extend partially or entirely around the channel region to provide access to both sides or more of the channel region. As GAA devices continue to expand, challenges arise. While existing structures and fabrication techniques are generally sufficient for their intended use, they are not entirely satisfactory in every aspect. Summary of the Invention

[0004] One embodiment of this application relates to a method for forming a semiconductor device, comprising: forming a stack over a substrate, the stack including a plurality of channel layers interleaved by a plurality of sacrificial layers; patterning the stack to form a fin structure; forming isolation members on the sidewalls of the fin structure; forming a dummy gate stack over a channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; after depositing the gate spacer layer, recessing the source / drain regions of the fin structure to form source / drain trenches; removing the sacrificial layers in the channel regions to release the channel layers as channel members; depositing a dielectric dummy layer to fill the space between the channel members; forming source / drain members in the source / drain regions; after forming the source / drain members, removing the dummy gate stack; removing the dielectric dummy layer to release the channel members; after removing the dielectric dummy layer, trimming the channel members to reduce the thickness of the channel members in the channel regions; and forming a gate structure to surround each of the channel members.

[0005] Another aspect of the embodiments of this application relates to a method for forming a semiconductor device, comprising:

[0006] A fin-like structure is formed over a substrate, the fin-like structure comprising multiple silicon layers interleaved with multiple silicon-germanium layers, wherein multiple mixed layers containing germanium-doped silicon are formed between two adjacent silicon layers and the silicon-germanium layers; a dummy gate stack is formed over a channel region of the fin-like structure; a gate spacer layer is deposited over the dummy gate stack; after depositing the gate spacer layer, the source / drain regions of the fin-like structure are recessed to form source / drain trenches; the silicon-germanium layers in the channel regions are selectively removed to expose the mixed layers; an oxide layer is deposited in the space between the silicon layers; source / drain components are formed in the source / drain trenches; the dummy gate stack is removed; the oxide layer is selectively removed; the mixed layers are removed from the channel regions; and a gate structure is formed to surround each of the silicon layers.

[0007] Another aspect of this application relates to a semiconductor structure comprising: a plurality of nanostructures suspended above a substrate; a gate structure that surrounds each of the nanostructures; a gate spacer layer disposed on the sidewalls of the gate structure; source / drain components adjacent to the nanostructures; an internal spacer component disposed between the gate structure and the source / drain components; and a germanium-containing hybrid layer that is vertically stacked between the internal spacer component and the nanostructures. Attached Figure Description

[0008] The invention will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figure 1 A flowchart illustrating a method for forming a semiconductor device according to one or more aspects of this disclosure is shown.

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 , Figure 34 and Figure 35 The following are shown in accordance with one or more aspects of this disclosure: Figure 1 A partial cross-sectional view of the work-in-process (WIP) structure during the manufacturing process of the method. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the invention. These are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for brevity and clarity, but does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] For ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein may be interpreted accordingly.

[0013] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass numbers within a reasonable range, taking into account variations inherent during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having characteristics related to the numerical value, a numerical value or range encompasses a reasonable range including said value, such as within + / 20% of said value. For example, a material layer with a thickness of "about 5 nm" can cover a size range of 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / -15%.

[0014] This disclosure generally relates to GAA transistors and methods for their fabrication. GAA transistors can be fabricated using a replacement gate process, in which a dummy gate stack is first formed as a placeholder, which is then replaced with a functional gate structure. In some replacement gate processes, sacrificial material in the nanostructure of the GAA transistor is removed after the formation of epitaxial source / drain components. Ideally, due to the difference in material composition, the high etch selectivity between the sacrificial material (e.g., SiGe) and the nanostructure (e.g., Si) should protect the nanostructure from etch loss during sacrificial material removal. However, during annealing processes (e.g., annealing processes during the formation of shallow trench isolation (STI) components and / or epitaxial source / drain components), atoms other than silicon (e.g., Ge) in the sacrificial material may diffuse into the nanostructure as impurities. The diffusion of impurities reduces etch selectivity. Therefore, the nanostructure may suffer etch loss during sacrificial material removal. Furthermore, impurities diffused into the nanostructure lattice may cause lattice distortion due to atomic size mismatch, potentially introducing strain and defects. These defects act as trap states within the bandgap, also known as interface traps. Interface traps can trap and release charge carriers, leading to threshold voltage fluctuations and deterioration of device uniformity.

[0015] This disclosure provides a method for forming a GAA transistor. In an example process, a fin structure having a channel layer and a sacrificial layer is formed over a substrate. Impurities (e.g., Ge) in the sacrificial layer may diffuse into the surface portion of the channel layer. The surface portion of the channel layer may also be referred to as a hybrid layer because it contains silicon and impurities other than silicon. The hybrid layer has a relatively low germanium concentration compared to the sacrificial layer, which includes a relatively high germanium concentration (also referred to as mole fraction or germanium atomic percentage (Ge%)). After forming a dummy gate stack over the channel region of the fin structure, at least one gate spacer is formed over the dummy gate stack. The source / drain regions of the fin structure are recessed. The sacrificial layer is removed in a selective etching process to release the channel layer as a channel member. The selective etching process is tuned to have a high etch contrast between the sacrificial layer and the channel layer. Due to the difference in germanium concentration, the hybrid layer may be retained in the surface portion of the channel member. Then, in a suitable deposition process (e.g., atomic layer deposition (ALD) process), a dielectric dummy layer is deposited to surround each channel member. Then, the dielectric dummy layer is selectively and partially recessed to form internal spacer recesses between multiple channel members. An internal spacer layer is deposited over the internal spacer recesses. The deposited internal spacer layer is etched to form internal spacer components. Source / drain components are then formed over the source / drain recesses. After selectively removing the dummy gate stack, the dielectric dummy layer is selectively removed to re-release the channel members. The channel members are further trimmed to remove the mixing layer, thereby substantially eliminating interface traps introduced by impurities. A gate structure is then formed to surround each channel member.

[0016] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure from a work-in-process (WIP) structure according to embodiments of the present disclosure. Method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some of the described steps may be replaced, eliminated, or shifted for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2-35 Description method 100, which is based on Figure 1 Partial cross-sectional views of the WIP structure 200 of an embodiment of method 100 at different stages of manufacturing. Since the WIP structure 200 will be fabricated into a semiconductor structure or semiconductor device, the WIP structure 200 is also referred to herein as a semiconductor structure 200 or a semiconductor device 200. For the avoidance of doubt, Figures 2-35 The X, Y, and Z directions are perpendicular to each other. Throughout this disclosure, unless otherwise expressly stated, the same reference numerals denote the same features or steps.

[0017] refer to Figure 1 and Figure 2 Method 100 includes block 102, wherein a stack 204 of alternating semiconductor layers is formed over semiconductor device 200. (As...) Figure 2 As shown, semiconductor device 200 includes a substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Depending on design requirements known in the art, substrate 202 may include various doping configurations. In embodiments where the semiconductor device is p-type, an n-type doping distribution (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doping distribution (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. In addition, the substrate 202 may optionally include an epi-layer that can be strained to enhance performance, and may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0018] In some embodiments, the stack 204 above the substrate 202 includes a channel layer 208 of a first semiconductor composition, which is interleaved with a sacrificial layer 206 of a second semiconductor composition. Alternatively, the sacrificial layer 206 and the channel layer 208 may be interleaved. The first and second semiconductor compositions may be different. In some embodiments, the sacrificial layer 206 comprises silicon-germanium (SiGe) or germanium-tin (GeSn), while the channel layer 208 comprises silicon (Si). It should be noted that, as... Figure 2 As shown, three (3) sacrificial layers 206 and three (3) channel layers 208 are arranged alternately, which is for illustrative purposes only and is not intended to limit the scope specifically described in the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the performance requirements of the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0019] The sacrificial layer 206 and the channel layer 208 in the stack 204 can be deposited using molecular beam epitaxy (MBE), vapor phase deposition (VPE), and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, while the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the Ge% in the sacrificial layer 206 may be not less than about 20%, for example, about 30% or higher. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially dopant-free (i.e., having about 0 atoms / cm²). 3 To approximately 1x10 17 atoms / cm 3 (the concentration of non-intrinsic dopants), wherein, for example, no intentional doping is performed during the epitaxial growth of the stack 204.

[0020] refer to Figure 1 and Figure 3 Method 100 includes a frame 104 in which a fin structure 212 is formed from a stack 204 and a substrate 202. To pattern the stack 204, a hard mask layer may be deposited over the stack 204 to form an etching mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer disposed above the pad oxide layer. The fin structure 212 may be patterned from the stack 204 and the substrate 202 using photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. Figure 3As shown, the etching process at frame 104 forms a trench extending vertically through a portion of the stack 204 and the substrate 202. The trench defines a fin structure 212. In some embodiments, a dual-patterning or multi-patterning process can be used to define the fin structure, with a spacing, for example, smaller than that achievable using a single direct lithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a lithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the fin structure 212 can then be patterned using the remaining spacers or mandrels by etching a portion of the stack 204 and the substrate 202. Figure 3 As shown, the fin-like structure 212 extends vertically along the Z direction and longitudinally along the X direction. Figure 3 As shown, the fin structure 212 includes a fin base 212B (or base / protrusion) patterned from the substrate 202 and a patterned stack 204 disposed directly above the fin base 212B. In some cases, the width of the fin structure 212, measured along the Y direction, can be between about 3 nm and about 20 nm.

[0021] refer to Figure 1 and Figure 4 Method 100 includes a frame 108, wherein an isolation member 214 is formed around the fin base 212B of the fin structure 212. Figure 4 In some embodiments shown, isolation member 214 is disposed on the sidewall of fin base 212B. In some embodiments, isolation member 214 may be formed in a trench to isolate fin structure 212 from adjacent fin structures. Isolation member 214 may also be referred to as shallow trench isolation (STI) member 214. For example, in some embodiments, a dielectric layer is first deposited over substrate 202 to fill the trench. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by chemical mechanical polishing (CMP). The planarized dielectric layer is further recessed or pulled back by dry etching, wet etching, and / or combinations thereof to form Figure 4 The STI component 214 is shown. After the recess, the fin structure 212 rises above the STI component 214, while the STI component 214 remains on the sidewall of the fin base 212B. In the illustrated embodiment, the top surface of the STI component 214 has a recessed profile. The center point of the recessed profile of the STI component 214 is located below the top surface of the fin base 212B.

[0022] In some embodiments, the formation of the STI component 214 may include heat treatment to cure the dielectric material of the STI component 214. The heat treatment may induce germanium atoms in the sacrificial layer 206 to diffuse into the adjacent channel layer 208, thereby inducing a mixed layer 209 between the adjacent channel layer 208 and the sacrificial layer 206, such as... Figure 4 As shown. A hybrid layer 209 is also formed between the bottommost sacrificial layer 206 and the top of the substrate 202. In some embodiments of method 100, the heat treatment during the formation of the STI component 214 may be optional and / or omitted, but method 100 may still have one or more other heat treatments in subsequent processes, such as during the formation of the epitaxial source / drain components, to induce the hybrid layer 209. The heat treatment accelerates the diffusion of germanium atoms from the sacrificial layer 206 into the channel layer 208, thereby forming the hybrid layer 209 between them. The hybrid layer 209 is silicon-rich and includes a small amount of germanium. In some embodiments, the Ge% in the hybrid layer 209 may range from about 0.02% to about 5%. The Ge% in the hybrid layer 209 is less than the Ge% in the sacrificial layer 206, for example, the ratio of the Ge% in the hybrid layer 209 to the Ge% in the sacrificial layer 206 is between about 1:100 and about 1:10. In some embodiments, the thickness of the hybrid layer 209 may range from about 0.1 nm to about 0.6 nm.

[0023] refer to Figure 1 and Figure 5 Method 100 includes frame 110, wherein a semiconductor pad 210 is deposited over a fin structure 212. After forming the STI component 214, the semiconductor pad 210 may be deposited over the semiconductor device 200, including over the STI component 214, over the top surface of the fin structure 212, and on the sidewalls of the fin structure 212. The semiconductor pad 210 serves to protect the sidewalls of the sacrificial layer 206, as it may suffer adverse damage during manufacturing. In some embodiments, the semiconductor pad 210 may comprise silicon (Si). In some embodiments, the semiconductor pad 210 may be deposited using PVD, CVD, or atomic layer deposition (ALD).

[0024] refer to Figure 1 and Figure 6-7 Method 100 includes block 112, wherein a dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. The dummy gate stack 220 serves as a placeholder for various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 7 It is along Figure 6 A cross-sectional view of line AA in [the image]. In [the image], as shown... Figure 7In some embodiments shown, a dummy gate stack 220 is formed above a fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 7 As shown, the channel region 212C is disposed along the X direction between the two source / drain regions 212SD. The source / drain region, or "S / D region," as used herein, can refer to a region that provides a source and / or drain for one or more devices. It can also refer to the source or drain of one or more devices.

[0025] The formation of the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning these layers. (See reference) Figure 6 A dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be deposited over the semiconductor device 200. The dummy dielectric layer 216 can be formed on the fin structure 212 using chemical vapor deposition (CVD), algebraic liquid deposition (ALD), oxygen plasma oxidation (APOD), or other suitable processes. In the illustrated embodiment, the dummy dielectric layer 216 is formed using an AOD process, which substantially oxidizes the semiconductor pad 210 to form the dummy dielectric layer 216. In some cases, the dummy dielectric layer 216 may comprise silicon oxide. Subsequently, a dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using a CVD, ALD, or other suitable process. In some cases, the dummy electrode layer 218 may comprise polysilicon. For patterning purposes, a gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using a CVD, ALD, or other suitable process. The gate top hard mask layer 222, dummy electrode layer 218, and dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, such as Figure 7 As shown. For example, the patterning process may include photolithography (e.g., photolithography or electron beam lithography) and etching. The photolithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. The photolithography process forms a patterned photoresist layer. Then, in the etching process, the patterned photoresist layer is used as an etching mask to pattern the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 located above the silicon oxide layer 223. Figure 7As shown, the dummy gate stack 220 is patterned such that it is disposed only above the channel region 212C and not above the source / drain region 212SD.

[0026] refer to Figure 1 and Figure 8 Method 100 includes block 114, wherein a gate spacer layer 226 is deposited over a semiconductor device 200, including over a dummy gate stack 220. In some embodiments, the gate spacer layer 226 is conformally deposited over the semiconductor device 200, including over the top surface and sidewalls of the dummy gate stack 220. The term “conformal” may be used herein to describe a situation where the thickness of the various regions is substantially uniform. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon carbon oxide, silicon carbonitride, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using processes such as CVD, subatmospheric CVD (SACVD), ALD, or other suitable processes.

[0027] refer to Figure 1 and Figure 9-10 Method 100 includes block 116, wherein the source / drain regions 212SD of the fin structure 212 are anisotropically recessed to form source / drain trenches 228. Anisotropic etching may include dry etching or a suitable etching process that etches the source / drain regions 212SD and a portion of the substrate 202. The resulting source / drain trenches 228 extend vertically through the depth of the stack 204 and partially into the substrate 202. The exemplary dry etching process of block 116 may be implemented using oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases and / or plasmas and / or combinations thereof. Figure 9 As shown, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the stack 204 into the substrate 202, the source / drain trench 228 includes a bottom surface and lower sidewalls defined in the substrate 202. It is noteworthy that while the sidewalls of the sacrificial layer 206 and the channel layer 208 are illustrated as substantially vertical, in some embodiments, the sidewalls may have a tapered profile (as shown in region 229', as an alternative embodiment of region 229), such that the width of the channel layer 208 (and the width of the subsequently formed dielectric dummy layer 230 and the width of the subsequently formed gate structure 250 in the space reserved in the sacrificial layer 206) gradually increases from top to bottom as measured along the X direction in the figure. Reference Figure 10It includes a partial cross-sectional view of two adjacent source / drain regions 212SD. (See attached image.) Figure 10 As shown, above the source / drain region 212SD, most of the fin structure 212 is etched away, and the top surface of the fin base 212B is exposed in the source / drain region 212SD. Because the etching rate of the gate spacer layer 226 is slower than that of the fin structure 212, the gate spacer layer 226 in the source / drain region 212SD is higher than the top surface of the fin base 212B.

[0028] refer to Figure 1 and Figure 11 Method 100 includes block 118, wherein a plurality of channel layers 208 in a channel region are released as channel members 2080. After forming source / drain trenches 228, sacrificial layers 206 interleaved with the channel layers 208 in the channel region 212C are selectively removed. The selective removal of sacrificial layers 206 releases the channel layers 208 to form the channel members 2080. Depending on the design, the channel members 2080 may take the form of nanowires, nanorods, nanosheets, or other nanostructures. The selective removal of sacrificial layers 206 creates spaces between and around adjacent channel members 2080. The selective removal of sacrificial layers 206 can be achieved by a selective dry etching process. Example selective dry etching processes may include the use of one or more fluorine (F) gases. In some embodiments, the fluorine-containing gases may include fluorine (F2), hydrogen fluoride (HF), chlorine trifluoride (ClF3), fluorine radicals (F*), and nitrogen trifluoride radicals (NF3*). In some embodiments, the sacrificial layer 206 can be etched using a vapor-phase etching process with a fluorinated gas (e.g., F2, HF, and ClF3). In some embodiments, the sacrificial layer 206 can be etched using a radical phase etching process with free radicals (e.g., F*, H*, and NF3*) generated from a fluorinated gas using a remote plasma system. Dry etching processes can produce byproducts such as silicon tetrafluoride (SiF4) and germanium tetrafluoride (GeF4). In some embodiments, the flow rate of the fluorinated gas ranges from about 100 standard cubic centimeters per minute (sccm) to about 500 sccm. In some embodiments, the dry etching process can be performed at a temperature of about -20°C to about 150°C and a pressure of about 100 mTorr to about 1000 mTorr. In some embodiments, due to the difference in germanium concentration, the mixed layer 209 is substantially retained after the removal of the sacrificial layer 206, thus creating a certain etching contrast between the sacrificial layer 206 and the mixed layer 209.

[0029] refer to Figure 1 and Figure 12Method 100 includes block 120, wherein a dielectric dummy layer 230 is deposited around channel member 2080 and over source / drain trench 228. The dielectric dummy layer 230 may be an oxide, such as silicon oxide in some embodiments, and may be deposited using ALD, flowable chemical vapor deposition (FCVD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition processes. The dielectric dummy layer 230 fills the spaces between channel members 2080 and covers the sidewalls of channel members 2080. In the illustrated embodiment, to improve gap-filling capability without leaving voids underneath, the deposition of the dielectric dummy layer 230 may include an ALD process to first form a thin dielectric layer, followed by an FCVD process to form a thick dielectric layer over the thin dielectric layer. The combination of ALD and FCVD processes improves gap-filling capability without affecting production throughput. Furthermore, during the deposition of the oxide material of the dielectric dummy layer 230, the hybrid layer 209 may be partially oxidized. Oxidation may be due to the hybrid layer 209 being exposed to an oxygen-rich environment. Therefore, the germanium-containing mixed layer 209 can be transformed into a mixture including germanium-doped silicon (Si). m Ge n ) and silicon germanium oxide (Si 1-xy Ge x O y The mixture is a compound of the mixture. In some embodiments, oxidation may occur in the shallow surface portion of the mixed layer 209, which transforms into a silicon-germanium oxide film, while the inner portion of the mixed layer 209 remains germanium-doped silicon and is substantially oxygen-free. Hereafter, the partially oxidized mixed layer 209 is referred to as mixed layer 2090.

[0030] refer to Figure 13 This includes a partial cross-sectional view of two adjacent source / drain regions 212SD. A dielectric dummy layer 230 extends to the isolation member 214, the sidewalls of the gate spacer layer 226, and the top surface of the gate spacer layer 226. Due to the ALD process, the thickness of the dielectric dummy layer 230 at the bottom of the source / drain trench 228 can be substantially the same as the thickness of the dielectric dummy layer 230 on the sidewalls of the gate spacer layer 226.

[0031] refer to Figure 1 and Figure 14-15 Method 100 includes a frame 122 in which an internal spacer recess 232 is formed. (See reference) Figure 14The dielectric dummy layer 230 is selectively and partially recessed to form an internal spacer recess 232. The internal spacer recess 232 may have a concave profile curved away from the source / drain trench 228. In embodiments, the selective recessing of the dielectric dummy layer 230 may be performed using a selective wet etching process or a selective dry etching process. Exemplary selective wet etching processes may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Examples of selective dry etching processes include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof. Figure 15 As shown, the dielectric dummy layer 230 is removed from the source / drain region 212SD, exposing the fin-shaped base 212B.

[0032] refer to Figure 1 and Figure 16 Method 100 includes a frame 124 in which an inner spacer layer 234 is deposited over an inner spacer recess 232. The composition of the inner spacer layer 234 differs from that of the dielectric dummy layer 230 to ensure that each of them can be selectively etched without substantially damaging the other. In some embodiments, the inner spacer layer 234 may comprise silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon nitride (SiN), silicon carbonitride (SiOC), or silicon oxynitride (SiON). In some embodiments, the inner spacer layer 234 may be deposited using CVD or ALD.

[0033] refer to Figure 1 and Figure 17 Method 100 includes block 126, wherein an inner spacer layer 234 is etched to form an inner spacer component 236 over an inner spacer recess 232. In some embodiments, the etching at block 124 may include using a dry etching process, such as a reactive ion etching (RIE) process using plasma. Exemplary dry etching processes may include using boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or combinations thereof. In the illustrated embodiment, the inner spacer component 236 extends laterally to a position directly below the dummy gate stack 220. Alternatively, the inner spacer component 236 may remain substantially below the gate spacer layer 226 without extending to a position directly below the dummy gate stack 220. It is noteworthy that the formation of the inner spacer component 236 (including the fabrication steps at blocks 122-126) may be optional. In other words, in some embodiments, the formation of the internal spacer component 236 may be omitted, and the internal spacer component 236 may not exist in the final structure.

[0034] refer to Figure 1 and Figure 18-19 Method 100 includes block 128, wherein a separation layer 238 is deposited at the bottom of source / drain trench 228. In some embodiments, the separation layer 238 is a buffer epitaxial layer epitaxially grown from the top surface of fin base 212B. As an example, the epitaxial growth of the buffer epitaxial layer 238 can be performed by VPE, ultra-high vacuum CVD (UHV-CVD), MBE, and / or other suitable epitaxial growth processes. In some embodiments, the buffer epitaxial layer 238 comprises the same material as the substrate 202, such as silicon. In some alternative embodiments, the buffer epitaxial layer 238 comprises a semiconductor material different from silicon, such as SiGe, SiSn, or other suitable semiconductor materials. In some embodiments, the buffer epitaxial layer 238 is dopant-free, for example, no intentional doping is performed during epitaxial growth. By comparison, in one example, the substrate 202 is lightly doped and has a higher doping concentration than the buffer epitaxial layer 238. The separation layer 238 provides a high-resistivity path from the S / D region to the semiconductor substrate, thereby suppressing leakage current in the semiconductor substrate. It is worth noting that the formation of the separation layer 238 (including the manufacturing step at frame 128) may be optional. That is, in some embodiments, the formation of the separation layer 238 may be omitted, and the separation layer 238 may not be present in the final structure.

[0035] refer to Figure 1 and Figure 20-21Method 100 includes block 130, wherein a bottom isolation layer 240 is formed above a separation layer 238 (or on a substrate 202 if the formation of separation layer 238 is omitted). Since the bottom isolation layer 240 may intersect with source / drain components and the oxygen content may oxidize the source / drain components, the bottom isolation layer 240 may be formed of an oxygen-free dielectric material (e.g., nitrogen). In the example process, a chlorinated silicon nitride layer is deposited above a source / drain trench 228 (including above the top surface of the buffer epitaxial layer 238). The chlorinated silicon nitride layer may be deposited using ammonia (NH3) and a chlorinated silicon precursor (e.g., silicon tetrachloride (SiCl4), dichlorosilane (Si2H4Cl2), dichlorosilane (SiH2Cl2), or hexachlorosilane (Si2Cl6)). The chlorinated silicon nitride layer may be deposited using plasma-enhanced atomic layer deposition (PEALD) or thermal ALD deposition. A directional plasma treatment process is then performed to remove chlorine from the bottom of the chlorinated silicon nitride layer. In some embodiments, the directed plasma treatment may include the use of argon (Ar) plasma, nitrogen (N2) plasma, and / or hydrogen (H2) plasma. Following the directed plasma treatment, a dry etching process using a fluorinated etchant (e.g., trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), or sulfur hexafluoride (SF6)) may be performed. Because the dry etching process etches the chlorinated silicon nitride along the sidewalls faster than etching the relatively chlorine-free silicon nitride layer at the bottom of the source / drain trench 228, a bottom isolation layer 240 can be formed over the buffer epitaxial layer 238, such as... Figure 20 and 21 As shown. It is worth noting that the formation of the bottom isolation layer 240 (including the manufacturing step at frame 130) may be optional. That is, in some embodiments, the formation of the bottom isolation layer 240 may be omitted, and the bottom isolation layer 240 may not be present in the final structure.

[0036] refer to Figure 1 and Figure 22-23 Method 100 includes block 132, wherein a source / drain component 244 is formed over the source / drain region 212SD. Although not explicitly shown, method 100 may include a cleaning process to clean the surface of the semiconductor device 200 prior to the formation of any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include removing oxides using deionized (DI) water, a mixture of ammonium hydroxide and hydrogen peroxide, DI water, a mixture of hydrochloric acid and hydrogen peroxide, a mixture of sulfuric acid peroxide, or hydrofluoric acid. Dry cleaning processes may include helium (He) and hydrogen (H2) treatment.

[0037] refer to Figure 22The source / drain component 244 can be n-type or p-type. When the source / drain component 244 is n-type, it may include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. When the source / drain component 244 is p-type, it may include silicon germanium (SiGe) and a p-type dopant, such as boron (B), boron difluoride (BF2), or a combination thereof. Although not explicitly shown in the figures, in some embodiments, the source / drain component 244 may include multiple layers. For example, the source / drain component 244 may include a lightly doped epitaxial component above the bottom isolation layer 240 and a heavily doped epitaxial component above the lightly doped epitaxial component. The lightly doped epitaxial component has a smaller dopant concentration and impurity concentration to reduce crystal defects. The heavily doped epitaxial component occupies most of the volume to reduce contact resistance. The source / drain components 244 can be formed using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the source / drain components 244 can be achieved through in-situ doping.

[0038] refer to Figure 23 It includes a partial cross-sectional view of two adjacent source / drain regions 212SD. Figure 23 In some embodiments shown, the n-type source / drain component 244N may be adjacent to the p-type source / drain component 244P. The n-type source / drain component 244N may include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The p-type source / drain component 244P may include silicon germanium (SiGe) and a p-type dopant, such as boron (B). Both the n-type source / drain component 244N and the p-type source / drain component 244P may be in direct contact with the top surface of the bottom isolation layer 240. For ease of illustration and description, the n-type source / drain component 244N and the p-type source / drain component 244P may be collectively referred to as source / drain component 244, such as... Figure 22 As shown.

[0039] refer to Figure 1 and Figure 24-25 Method 100 includes block 134, wherein a contact etch stop layer (CESL) 246, an interlayer dielectric layer (ILD) 248, and a capping layer 249 are deposited in the source / drain region 212SD. Figure 24As shown, CESL 246 is deposited over source / drain components 244. CESL 246 may comprise silicon nitride or aluminum nitride. In some embodiments, CESL 246 may be deposited using CVD or ALD. An ILD layer 248 is then deposited over CESL 246. In some embodiments, ILD layer 248 comprises silicon oxide formed of tetraethyl silicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. ILD layer 248 may be deposited using CVD, flowable CVD (FCVD), spin coating, or suitable deposition techniques. After depositing ILD layer 248, semiconductor device 200 may be planarized using a planarization process to remove the gate top hard mask layer 222 and expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process.

[0040] refer to Figure 25 To protect the ILD layer 248 from damage during the removal step of the dielectric dummy layer 230, the ILD layer 248 is selectively recessed to form a top recess, and a capping layer 249 is formed over the top recess. The capping layer 249 is formed of a different material than the dielectric dummy layer 230. When the dielectric dummy layer 230 comprises silicon oxide, the capping layer 249 is not formed of silicon oxide, thereby ensuring etch selectivity. In some embodiments, the capping layer 249 may comprise silicon nitride, silicon carbonitride, silicon carbide, or silicon carbonitride. In one embodiment, the capping layer 249 may comprise silicon nitride. Another planarization is performed to remove excess capping layer 249 and expose the dummy gate stack 220. After planarization, the top surfaces of the capping layer 249, CESL 246, gate spacer layer 226, and dummy gate stack 220 are coplanar.

[0041] refer to Figure 1 and Figure 26-27 Method 100 includes block 136, wherein dummy gate stack 220 is selectively removed. Figure 27 This is a cross-sectional view of the channel region 212C, along... Figure 26 The BB line in the middle. The exposure of the dummy gate stack 220 at the end of the operation at block 134 allows for its removal. Removal of the dummy gate stack 220 may include one or more etching processes selectively applied to the material of the dummy gate stack 220. For example, removal of the dummy gate stack 220 may be performed using selective wet etching, selective dry etching, or a combination thereof. Removal of the dummy gate stack 220 forms a gate trench that exposes the stack of channel member 2080 and dielectric dummy layer 230.

[0042] refer to Figure 1 and Figures 28-29 Method 100 includes block 138, wherein a dielectric dummy layer 230 is selectively removed from channel region 212C. After removal of the dummy gate stack 220, the dielectric dummy layer 230 in channel region 212C is exposed and subsequently removed in a separate etching process. For example, a selective wet etching process or a selective dry etching process can be performed to remove the dielectric dummy layer 230. An exemplary selective wet etching process may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Examples of selective dry etching processes include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof. After selective removal of the dielectric dummy layer 230, a mixed layer 2090 in channel region 212C is exposed. In some embodiments, removing the dielectric dummy layer 230 also removes the oxide surface portion of the mixed layer 2090, because the etch contrast between the oxide surface portion of the mixed layer 2090 and the dielectric dummy layer 230 is limited, both of which consist of oxide. The interior portion of the mixed layer 2090 is exposed, which is primarily semiconductor material (germanium-doped silicon) other than oxide.

[0043] refer to Figure 1 and Figures 30-31 Method 100 includes block 140, in which a trimming process is performed to remove the hybrid layer 2090 from the channel region 212C. The trimming process can use any suitable etching process, such as dry etching, wet etching, and / or RIE. In one example, the trimming process is a wet etching process using an etchant composed of NH4OH, H2O2, and H2O. The NH4OH:H2O2 ratio in the etchant can range from about 5:100 to about 20:100. In some embodiments, the trimming process can be performed at room temperature or slightly above, such as from about 25°C to about 60°C, for a duration of about 20 seconds to about 100 seconds.

[0044] In addition to removing the hybrid layer 2090 from channel region 212C, the trimming process also slightly removes the surface portion of the exposed floating channel member 2080 within channel region 212C. This is due to the limited etch contrast between the hybrid layer 2090 and the channel member 2080, as silicon is the primary component of both. The removal of the surface portions of the hybrid layer 2090 and the channel member 2080 results in a bend (also known as a concave or concave surface) on the top and bottom surfaces of the channel member 2080. Reference Figure 30The thickness of the channel member 2080 (denoted as Tc), measured at the center of the corresponding channel region 212C, is less than the thickness (denoted as Te) measured at the end of the channel member 2080. Furthermore, in some embodiments, the inner spacer member 236 may also undergo etching losses during trimming, thereby thinning in the X direction. For example, the inner spacer member 236 may become thinner than the gate spacer layer 226 measured in the X direction. In some embodiments, the outer wall of the inner spacer member 236 facing the gate trench may bend from towards the gate trench due to etching losses (e.g., Figure 30 (As shown) bends towards the epitaxial source / drain component 244. In some alternative embodiments, the material of the inner spacer component 236 may exhibit high etch selectivity and remain substantially intact during the removal of the mixed layer 2090, such that the inner spacer component 236 may have the same thickness as the gate spacer layer 226 measured in the X direction, or become thicker due to the sidewall bending of the inner spacer component 236 facing the gate trench (e.g. Figure 30 (As shown). It is worth noting that the trimming process leaves the ends of the channel member 2080 and the hybrid layer 2090 largely unetched, as these ends are protected by the gate spacer layer 226. In other words, after the trimming process, the ends of the hybrid layer 2090, which is vertically stacked between the inner spacer member 236 and the channel member 2080, and between the bottom inner spacer member 236 and the substrate 202, remain intact.

[0045] Figure 31A dashed rectangle is retained to represent the outline of the combination of the hybrid layer 2090 directly beneath the gate spacer layer 226 and the remaining end of the channel member 2080. The dashed rectangle also facilitates a visual comparison of the trimmed dimensions of the central portion of the channel member 2080. The dimensions of the central portion of the channel member 2080 are reduced in both the horizontal and vertical directions of the YZ plane. In the vertical direction, compared to the dashed rectangle, the thickness (Tc) of the channel member 2080 is reduced by approximately 4% to approximately 30%, for example, by approximately 0.2 nm to approximately 1.2 nm in some embodiments, and the width (Wc) of the channel member 2080 is reduced by approximately 2% to approximately 8%, for example, by approximately 0.5 nm to approximately 1.5 nm in some embodiments. The reduction measured in the horizontal direction (in nanometers) can be greater than the reduction in the vertical direction, possibly because the etching rate of the crystal surfaces exposed on the sidewalls of the channel member 2080 (e.g., the (110) surface) is higher than the etching rate of the different crystal surfaces exposed on the top and bottom surfaces of the channel member 2080 (e.g., the (100) surface). Furthermore, due to more direct exposure to the etchant, the topmost channel member 2080 can experience greater etching loss than the channel members below it. Therefore, the width (Wc) and thickness (Tc) of the topmost channel member 2080 can be smaller than the width and thickness of the channel members below it. The bottommost channel member 2080 can have the largest width (Wc) and thickness (Tc), and the dimensions of the intermediate channel members gradually transition between the dimensions of the topmost and bottommost channel members. Additionally, the corners of the channel member 2080 can be rounded due to the trimming process. The topmost channel member 2080 can have more rounded corners than the corners below it, while the bottommost channel member 2080 can have the least rounded corners, closest to right angles. The corners of the middle channel members 2080 gradually transition between the corners of the topmost and bottommost channel members.

[0046] Refer again Figure 30 Regarding the topmost channel member 2080, the remaining end of the hybrid layer 2090 lies below its bottom surface, not on its top surface. The remaining end of the hybrid layer 2090 also directly intersects with the sidewalls of the source / drain member 244 and the buffer epitaxial layer 238. The hybrid layer 2090 comprises germanium-doped silicon (Si). m Ge n ) and silicon germanium oxide (Si 1-xy Ge x O y) mixture, such as an internally germanium-doped silicon and a silicon germanium oxide surface layer. In some embodiments, n ranges from about 0.02% to about 5%, n is less than m (n < m), x ranges from about 0.01% to about 3%, y ranges from about 1% to about 30%, and x is less than y (x < y). In the illustrated embodiment, the length of the remaining end portion of the mixed layer 2090 measured along the X direction is less than the thickness of the internal spacer member 236 measured along the X direction. In some embodiments, the thickness of the mixed layer 2090 measured along the Z direction may range between about 0.1 nm and about 0.6 nm. In some embodiments, the bottommost mixed layer 209 is thick enough to physically contact the buffer epitaxial layer 238 or the bottom isolation layer 240. In some embodiments, the bottommost mixed layer 209 is thick enough to physically contact both the buffer epitaxial layer 238 and the bottom isolation layer 240.

[0047] Reference Figure 1 and Figures 32-33 , method 100 includes block 142, wherein after releasing the channel member 2080, a gate structure 250 is formed to wrap around each channel member 2080 in a surround fashion. The gate structure 250 is also referred to as a metal gate structure 250 due to its metal-containing layer. An isolation member 214 is disposed beside the channel member 2080. The gate structure 250 is disposed above the channel member 2080. The gate structure 250 includes an interface layer, a gate dielectric layer above the interface layer, and at least one metal layer above the gate dielectric layer. The interface layer interfaces with the channel member 2080. The gate dielectric layer and the isolation member 214 are mixed at the interface between the gate dielectric layer and the isolation member.

[0048] In the illustrated embodiment, the gate structure 250 includes: an interface layer 250a, which intersects with the channel member 2080 and the substrate 202 in the channel region 212C; a high-k dielectric layer 250b above the interface layer 250a; and a gate electrode layer 250c above the high-k dielectric layer 250b. The interface layer 250a and the high-k dielectric layer 250b can be collectively referred to as the gate dielectric layer. The interface layer 250a may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer 250a can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer 250b may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer may comprise other high-k dielectrics, such as titanium oxide (TiO2), zirconium hafnium oxide (HfZrO), tantalum oxide (Ta2O5), silicon hafnium oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), lanthanum hafnium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), combinations thereof, or other suitable materials. The high-k dielectric layer 250b may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The interface layer 250a may directly interface with the remainder of the hybrid layer 2090. Depending on the thickness of the hybrid layer 2090 and the interface layer 250a, the high-k dielectric layer 250b can also directly intersect with the remaining portion of the hybrid layer 2090.

[0049] The gate electrode layer 250c of the gate structure 250 may include a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a substrate, a wetting layer, an adhesion layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode layer 250c may include titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode layer 250c may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a generally flat top surface of the gate structure. The gate structure 250 includes a portion between channel members 2080 in the channel region 212C.

[0050] refer to Figure 33 The transistors formed on the two channel regions 212C shown can have opposite conductivity types, such as an n-type transistor and a p-type transistor. Therefore, the gate structure 250 can include a p-type gate structure portion and an n-type gate structure portion. The p-type gate structure portion includes a p-type work function metal layer disposed near the channel member 2080. The n-type gate structure portion includes an n-type work function metal layer disposed near the channel member 2080. Figure 33 The embodiment shown applies a trimming process at frame 140 in both the n-type and p-type device regions, ensuring that no mixing layer 2090 remains in the two channel regions 212C shown. Alternatively, the trimming process at frame 140 can be applied to one of the regions, for example... Figure 34 As shown. In Figure 34 In the original design, the trimming process at frame 140 is applied to the channel region 212C on the left, which can be an n-type device region, while the hybrid layer 2090 remains in the location of another channel region 212C on the right, which can be a p-type device region with the opposite conductivity type to the left. Alternatively, the trimming process at frame 140 is applied to the channel region 212C on the left, which can be a p-type device region, while the hybrid layer 2090 remains in the location of another channel region 212C on the right, which can be an n-type device region with the opposite conductivity type to the left. Because the trimming process is skipped, the channel member 2080 in the right channel region 212C is also wider and thicker than the channel member 2080 in the left channel region 212C.

[0051] refer to Figure 1 and Figure 35Method 100 includes block 144, wherein a source / drain contact plug 252 and an optional silicide component 254 are formed in a source / drain region 212SD. In an exemplary process, a contact hole is first formed by etching a capping layer 249, an ILD layer 248, and a CESL 246. The etching process can be a self-aligned process, such that the vertical sidewalls of the CESL 246 are used as etch stop layers to remove the capping layer 249 and the ILD layer 248. Optionally, the upper portion of the source / drain component 244 can be etched to have a concave shape as the bottom of the contact hole. In the illustrated embodiment, the source / drain component 244 is recessed below the bottom surface of the topmost channel member 2080. The silicide component 254 is formed at the bottom of the contact hole. The silicide component 254 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. Subsequently, source / drain contact plugs 252 are formed on the silicide component 254. Each source / drain contact plug 252 may include a conductive barrier layer and a bulk metal layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The bulk metal layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. The silicide component 254 and the source / drain contact plug 252 may be collectively referred to as the source / drain contact.

[0052] While not intended to be limiting, embodiments of this disclosure offer one or more of the following advantages. For example, embodiments of this disclosure replace the germanium-containing sacrificial layer with an oxide-containing dielectric dummy layer, and perform an additional trimming process after selectively removing the dielectric dummy layer to release the channel components to further remove germanium residues in the channel region. A metal gate structure is then formed to surround each channel component. This process reduces germanium atoms as impurities in the channel region and improves the performance uniformity of the GAA transistor. Furthermore, embodiments of this disclosure can be readily integrated into existing semiconductor manufacturing processes.

[0053] In one exemplary aspect, this disclosure relates to a method. The method includes: forming a stack over a substrate, the stack including a plurality of channel layers interleaved by a plurality of sacrificial layers; patterning the stack to form a fin structure; forming isolation members on the sidewalls of the fin structure; forming a dummy gate stack over a channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; after depositing the gate spacer layer, recessing the source / drain regions of the fin structure to form source / drain trenches; removing the sacrificial layers in the channel regions to release the channel layers as channel members; depositing a dielectric dummy layer to fill the space between the channel members; forming source / drain members in the source / drain regions; after forming the source / drain members, removing the dummy gate stack; removing the dielectric dummy layer to release the channel members; after removing the dielectric dummy layer, trimming the channel members to reduce the thickness of the channel members in the channel regions; and forming a gate structure to surround each channel member. In some embodiments, the trimming of the channel members also reduces the width of the channel members in the channel regions. In some embodiments, the reduction in the width of the channel member is greater than the reduction in the thickness of the channel member. In some embodiments, trimming of the channel member removes a germanium-containing surface portion from the channel member. In some embodiments, the germanium concentration in the germanium-containing surface portion is in the range of about 0.02% to about 5%. In some embodiments, the germanium-containing surface portion is formed during the formation of the isolation member. In some embodiments, the germanium-containing surface portion is formed during the formation of the source / drain member. In some embodiments, after trimming the channel member, the end of the germanium-containing surface portion of the channel member remains below the gate spacer layer. In some embodiments, the method further includes laterally recessing a dielectric dummy layer to form an inner spacer recess, depositing an inner spacer layer over the inner spacer recess, and etching back the inner spacer layer to form an inner spacer member in the inner spacer recess. Trimming of the channel member also reduces the thickness of the inner spacer member. In some embodiments, trimming of the channel member forms concave profiles on the top and bottom surfaces of the channel member. In some embodiments, the top surface of the isolation member has a concave profile.

[0054] In another exemplary aspect, this disclosure relates to a method. The method includes forming a fin structure over a substrate, the fin structure comprising a plurality of silicon layers interleaved with a plurality of silicon-germanium layers. A plurality of mixed layers comprising germanium-doped silicon are formed between two adjacent silicon layers and the silicon-germanium layers. The method further includes: forming a dummy gate stack over a channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; after depositing the gate spacer layer, recessing source / drain regions of the fin structure to form source / drain trenches; selectively removing the silicon-germanium layers in the channel regions to expose the mixed layers; depositing an oxide layer in the space between the silicon layers; forming source / drain components in the source / drain trenches; removing the dummy gate stack; selectively removing the oxide layer; removing the mixed layers from the channel regions; and forming a gate structure to surround each silicon layer. In some embodiments, the germanium concentration in the mixed layers is less than the germanium concentration in the silicon-germanium layers. In some embodiments, the deposition of the oxide layer oxidizes the mixed layer. In some embodiments, selectively removing the oxide layer also removes oxidized portions of the mixed layer. In some embodiments, removing the hybrid layer reduces the thickness and width of the silicon layer in a cross-section perpendicular to the length of the silicon layer. In some embodiments, removing the hybrid layer forms concave profiles of the top and bottom surfaces of the silicon layer in a cross-section along the length of the silicon layer. In some embodiments, removing the hybrid layer includes a wet etching process.

[0055] In another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes a plurality of nanostructures suspended above a substrate, a gate structure surrounding each nanostructure, a gate spacer layer disposed on the sidewalls of the gate structure, source / drain components adjacent to the nanostructures, an internal spacer component disposed between the gate structure and the source / drain component, and a germanium-containing hybrid layer vertically stacked between the internal spacer component and the nanostructures. In some embodiments, the germanium-containing hybrid layer includes an internal portion of silicon-germanium and an external portion of silicon-germanium oxide. In some embodiments, the top and bottom surfaces of the nanostructures have concave profiles.

[0056] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: A stack is formed over a substrate, the stack comprising multiple channel layers interleaved with multiple sacrificial layers; The stacked components are patterned to form a fin-like structure; An isolation component is formed on the sidewall of the fin-like structure; A dummy gate stack is formed above the channel region of the fin structure; A gate spacer layer is deposited over the dummy gate stack; After depositing the gate spacer layer, the source / drain regions of the fin structure are recessed to form source / drain trenches; Remove the sacrificial layer in the trench region to release the trench layer as a trench component; Deposit a dielectric pseudo-layer to fill the space between the channel components; Source / drain components are formed in the source / drain region; After forming the source / drain components, the dummy gate stack is removed; Remove the dielectric dummy layer to release the channel component; After removing the dielectric dummy layer, the channel member is trimmed to reduce the thickness of the channel member in the channel region; and A gate structure is formed to surround each of the channel components.

2. The method for forming a semiconductor device according to claim 1, wherein, The modification of the channel component also reduces the width of the channel component in the channel region.

3. The method for forming a semiconductor device according to claim 2, wherein, The reduction in the width of the channel component is greater than the reduction in the thickness of the channel component.

4. The method for forming a semiconductor device according to claim 1, wherein, The trimming of the channel component removes the germanium-containing surface portion from the channel component.

5. The method for forming a semiconductor device according to claim 4, wherein, The germanium-containing surface portion is formed during the formation of the insulating component.

6. The method for forming a semiconductor device according to claim 4, wherein, The germanium-containing surface portion is formed during the formation of the source / drain components.

7. The method for forming a semiconductor device according to claim 1, wherein, After the channel member is trimmed, the end of the germanium-containing surface portion of the channel member remains beneath the gate spacer layer.

8. The method for forming a semiconductor device according to claim 1, further comprising: The dielectric dummy layer is laterally recessed to form an internal spacer groove; An internal spacer layer is deposited above the internal spacer groove; as well as The internal spacer layer is etched back to form an internal spacer component in the internal spacer groove. The modification of the channel component also reduces the thickness of the internal spacer component.

9. A method for forming a semiconductor device, comprising: A fin-like structure is formed above a substrate, the fin-like structure comprising multiple silicon layers interlaced with multiple silicon-germanium layers, wherein multiple mixed layers containing germanium-doped silicon are formed between two adjacent silicon layers and the silicon-germanium layers; A dummy gate stack is formed above the channel region of the fin structure; A gate spacer layer is deposited over the dummy gate stack; After depositing the gate spacer layer, the source / drain regions of the fin structure are recessed to form source / drain trenches; Selectively remove the silicon-germanium layer in the channel region to expose the hybrid layer; An oxide layer is deposited in the space between the silicon layers; Source / drain components are formed in the source / drain trench; Remove the dummy gate stack; The oxide layer is selectively removed; Remove the mixing layer from the channel region; and A gate structure is formed to surround each of the silicon layers.

10. A semiconductor structure comprising: Multiple nanostructures are suspended above the substrate; A gate structure that surrounds each of the nanostructures; A gate spacer layer is disposed on the sidewall of the gate structure; Source / drain components are adjacent to the nanostructure; An internal spacer component is placed between the gate structure and the source / drain component; as well as A germanium-containing hybrid layer is vertically stacked between the internal spacer component and the nanostructure.

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