Nitride power device with gate voltage management function

Abstract

The invention relates to the technical field of semiconductor power devices, in particular to a nitride power device with a grid voltage management function, which comprises a grid voltage manager and a main power transistor. According to the invention, on a semiconductor, the grid voltage manager can adjust the voltage applied to the grid electrode of the main power transistor by an external driving signal so as to avoid overvoltage breakdown of the grid electrode of the main power transistor, so that the high threshold voltage and large grid voltage working range can be realized.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor power devices, and in particular to a nitride power device with gate voltage management function. Background Technology

[0002] Nitride semiconductor power devices are a core component of power electronics technology. To reduce power losses, nitride power devices have become an effective way to improve and enhance power efficiency. High electron mobility transistors (HEMTs) constructed from nitride wide-bandgap materials (such as AlGaN, GaN, InAlN, AlN, InGaN, etc.) are gradually being deployed in power electronics applications as an emerging power semiconductor device technology. However, in some commercially available nitride HEMT power transistors (such as silicon-based p-GaN / AlGaN / GaNHEMTs), their relatively low threshold voltage and gate breakdown voltage pose serious reliability problems in high-temperature, high-irradiation, high-voltage, and high-power power electronics applications.

[0003] Researchers have found that traditional nitride HEMT power transistors (such as p-GaN gate HEMTs) have a threshold voltage of less than 3V, typically around 1.5V, a gate breakdown voltage of less than 10V, and a rated operating voltage usually below 7V. If operating in harsh environments (such as high voltage, high power, high temperature, and high radiation), traditional nitride HEMT power transistors are prone to gate failure or false turn-on, leading to catastrophic consequences for power systems and load devices. In a half-bridge power transistor topology, the high voltage-to-time ratio (dV / dt) generated during the switching process of the upper half-bridge power transistor causes the Miller capacitance of the lower half-bridge power transistor to charge and discharge rapidly, generating a high current. This high current causes a voltage drop through the gate drive resistor of the lower transistor, ultimately leading to false turn-on of the lower half-bridge power transistor; this phenomenon is called the Miller effect. Typically, transistors are required to have a high threshold voltage or a negative bias to overcome the Miller effect.

[0004] On the other hand, to reduce the cost of nitride power chips, nitride materials are typically epitaxially grown on silicon substrates. However, silicon, as a non-insulating substrate, has a potential that fluctuates depending on the potentials of the two power ports of the bidirectional switch. This causes silicon-based nitride bidirectional switches to operate inefficiently, requiring power transistors with ultra-high gate breakdown voltage to regulate the substrate potential of the silicon-based nitride bidirectional switch. The gate breakdown voltage of these power transistors should be greater than or equal to the rated operating voltage of the silicon-based nitride bidirectional switch. Existing p-GaN gate HEMTs cannot meet these requirements. Summary of the Invention

[0005] To improve the gate threshold voltage and breakdown voltage, this application provides a nitride power device with gate voltage management function.

[0006] This application provides a nitride power device with gate voltage management function, which adopts the following technical solution:

[0007] A nitride power device with gate voltage management functionality includes a gate voltage manager and a main power transistor. The gate voltage manager includes a withstand region for sharing excess voltage from the input voltage to prevent gate overvoltage breakdown of the main power transistor. The withstand region employs a semiconductor device with withstand voltage capability.

[0008] In one embodiment: based on different semiconductor devices, the voltage-resistant region has two ports, a voltage-resistant region anode and a voltage-resistant region cathode, or has three ports, a voltage-resistant region gate, a voltage-resistant region source and a voltage-resistant region drain;

[0009] When it has two ports, the gate voltage manager has an input port and an output port. The cathode of the withstand voltage region is electrically connected to the input port, and the anode of the withstand voltage region is electrically connected to the output port. The output port is electrically connected to the gate of the main power transistor.

[0010] When it has three ports, the gate voltage manager has three ports: an input port, an output port, and a clamping port. The drain of the withstand voltage region is electrically connected to the input port, the gate of the withstand voltage region is electrically connected to the clamping port, and the source of the withstand voltage region is electrically connected to the output port. The output port is electrically connected to the gate of the main power transistor, and the clamping port is electrically connected to the source or substrate of the main power transistor.

[0011] In one embodiment: when having two ports, the withstand region is a depletion-type transistor with a gate-source short circuit, or a series structure of the source of a depletion-type transistor with a gate-source short circuit and a resistor, or a capacitor, or a withstand diode, or a enhancement-type transistor with a gate-source short circuit.

[0012] When there are three ports, the withstand voltage region is either a depletion-type transistor or an enhancement-type transistor.

[0013] In one embodiment: the main power transistor is a unidirectional voltage enhancement type power transistor, a common-source bidirectional voltage enhancement type power transistor, a single-gate bidirectional voltage enhancement type power transistor, or a common-drift region bidirectional voltage enhancement type power transistor.

[0014] In one embodiment: the main power transistor has a secondary gate that can conduct Miller current to the input port to suppress the Miller effect, and the secondary gate is electrically connected to the input port; when the main power transistor is a unidirectional voltage enhancement type power transistor, the number of secondary gates is one; when the main power transistor is a common-source bidirectional voltage enhancement type power transistor, a single-gate bidirectional voltage enhancement type power transistor, or a common-drift region bidirectional voltage enhancement type power transistor, the number of secondary gates is two.

[0015] In one embodiment: the secondary gate is located in the drift region of the main power transistor and is close to, covers or partially overlaps the gate of the main power transistor; the distance between the secondary gate and the gate of the main power transistor is between 20 nanometers and 3 micrometers and is isolated by a dielectric.

[0016] In one embodiment: the gate voltage manager further includes a discharge region for rapidly releasing the gate charge of the main power transistor to achieve rapid turn-off of the main power transistor, and / or a clamping region for clamping the positive and reverse voltages between the gate and source of the main power transistor to avoid gate breakdown of the main power transistor due to voltage oscillation or overvoltage drive, wherein the negative terminal of the clamping region is electrically connected to the output port and the positive terminal of the clamping region is electrically connected to the clamping port, and / or the anode of the discharge region is electrically connected to the output port and the cathode of the discharge region is electrically connected to the input port.

[0017] In one embodiment: when the breakdown voltage region is an enhancement-mode transistor, the gate voltage manager includes two discharge regions and at least one clamping region. The second discharge region is used to quickly release the gate charge of the enhancement-mode transistor to achieve rapid turn-off of the enhancement-mode transistor. The second clamping region is used to clamp the voltage between the gate of the breakdown voltage region and the clamping port to regulate the potential of the source of the breakdown voltage region. The cathode of the discharge region of the second discharge region is electrically connected to the input port. The anode of the discharge region of the second discharge region is electrically connected to the gate of the breakdown voltage region.

[0018] If a second clamping region exists, the positive terminal of the second clamping region is electrically connected to the clamping port; the negative terminal of the second clamping region is electrically connected to the gate of the withstand voltage region; the potential of the source of the withstand voltage region is the difference between the positive clamping voltage of the second clamping region and the threshold voltage of the enhancement-mode transistor.

[0019] In one embodiment: the discharge region is a discharge diode or a gate-source short-circuited enhancement transistor;

[0020] The clamping region can be a clamping resistor, or an A structure formed by a clamping diode, or a B structure formed by two diodes connected back-to-back in series, or a C structure formed by two diodes connected face-to-face in series, or a structure in parallel with an A, B, or C structure consisting of m sequentially connected diodes and n sequentially connected diodes in reverse parallel, or a structure in parallel with an A, B, or C structure consisting of m sequentially connected enhancement-mode transistors with shorted gate-sources and n sequentially connected enhancement-mode transistors with shorted gate-sources, or a structure in parallel with an A, B, or C structure consisting of m sequentially connected diodes and n sequentially connected enhancement-mode transistors with shorted gate-sources, or a structure in parallel with an A, B, or C structure. The structure consists of: a B or C structure connected in parallel, or a reverse parallel structure consisting of m sequentially series-connected enhancement-mode transistors with shorted gate-source and n sequentially series-connected diodes, or a structure consisting of m sequentially series-connected diodes and n sequentially series-connected diodes in reverse parallel, or a structure consisting of m sequentially series-connected enhancement-mode transistors with shorted gate-source and n sequentially series-connected enhancement-mode transistors in reverse parallel, or a structure consisting of m sequentially series-connected enhancement-mode transistors with shorted gate-source and n sequentially series-connected enhancement-mode transistors in reverse parallel, or a structure consisting of m sequentially series-connected enhancement-mode transistors with shorted gate-source and n sequentially series-connected enhancement-mode transistors in reverse parallel.

[0021] In one embodiment: the gate voltage manager includes a boost region with unidirectional conduction characteristics. When the boost region is present, the discharge region and the clamping region must exist in the gate voltage manager; the boost region anode is electrically connected to the input port, and the boost region cathode is electrically connected to the withstand voltage region drain or withstand voltage region cathode of the withstand voltage region.

[0022] The condition for turning on the main power transistor is that the input voltage at the input port reaches the sum of the turn-on voltage of the boost region and the threshold voltage of the main power transistor;

[0023] Furthermore, the ratio of the leakage current from the discharge cathode to the discharge anode of the discharge region to the leakage current from the clamping negative electrode to the clamping positive electrode of the clamping region is less than or equal to the ratio of the difference between the threshold voltage of the main power transistor and the turn-on voltage of the discharge region to the turn-on voltage of the boost region.

[0024] In one embodiment, the boost region is q diodes connected in series in sequence, or q enhancement transistors connected in series with their gate and source shorted.

[0025] In summary, this application has the following beneficial effects:

[0026] 1. Achieving higher gate breakdown voltage and threshold voltage for nitride power transistors. This invention implements the gate voltage manager and the main power transistor. The gate voltage manager can adjust the gate voltage applied to the main power transistor by the drive signal. Therefore, the nitride power device with gate voltage management function can tolerate a larger range of drive signal voltages, increasing the gate drive operating window. Specifically, the boost region adjusts the turn-on voltage of the nitride power device by adjusting the number q of sequentially connected diodes; the gate withstand voltage region adjusts the gate withstand voltage of the nitride power device by adjusting the breakdown voltage of the depletion-mode power transistor; and the clamping region clamps the gate potential of the main power transistor to prevent overvoltage.

[0027] 2. Suppressing gate voltage ringing and Miller effect. The nitride power device with gate voltage management function disclosed in this invention has unidirectional conduction characteristics in its boost and discharge regions, which can block the association between the internal parasitic capacitance and external parasitic inductance of the main power transistor, thereby suppressing LC resonance. The secondary gate of the main power transistor can direct the Miller current induced by the Miller capacitance to the drive input port, reducing the influence of the Miller effect on the gate of the main power transistor.

[0028] 3. It has the advantages of simple process and low cost. The fabrication process of the components involved in each region of the nitride power device with gate voltage management function disclosed in this invention is compatible with commercial fabrication processes, without the need to develop additional fabrication processes. Therefore, the nitride power device with gate voltage management function can be monolithically integrated on a semiconductor substrate. Attached Figure Description

[0029] Figure 1a -L illustrates a schematic diagram of 12 optional gate compression managers 1 of the present invention.

[0030] Figure 2 The diagram illustrates two optional boost regions 2 of the present invention, and shows examples where q=1 and q=2.

[0031] Figure 3a -b illustrates a schematic diagram of the seven optional pressure-resistant zones 3 of the present invention.

[0032] Figure 4 A schematic diagram of two optional discharge regions 4 of the present invention is shown.

[0033] Figure 5a -d illustrates a schematic diagram of 19 optional clamping regions 5 of the present invention, and illustrates 4 examples.

[0034] Figure 6a -b illustrates a schematic diagram of the eight optional main power transistors 6 of the present invention.

[0035] Figure 7A schematic diagram is shown of a gate voltage manager 109 driving a unidirectional voltage-enhanced power transistor 601.

[0036] Figure 8 A schematic diagram is shown of a gate voltage manager 110 driving a unidirectional voltage-enhanced power transistor 601.

[0037] Figure 9 A schematic diagram is shown of a gate voltage manager 101 driving a unidirectional voltage-enhanced power transistor 601.

[0038] Figure 10 A schematic diagram is shown of a gate voltage manager 101 driving a unidirectional voltage-enhanced power transistor 605 with a subgate.

[0039] Figure 11 A schematic diagram is shown of a gate voltage manager 101 driving a unidirectional voltage-enhanced power transistor 606 with a subgate.

[0040] Figure 12 A schematic diagram is shown of a gate voltage manager 101 driving a unidirectional voltage-enhanced power transistor 607 with a subgate.

[0041] Figure 13a -g illustrates the basic semiconductor devices and components related to the p-GaN gate HEMT platform of this invention.

[0042] Figure 14a The diagram illustrates the operating state of Sub-Example 1.1 of the present invention under high gate voltage stress.

[0043] Figure 14b The diagram illustrates the operating state of Sub-Example 1.2 of the present invention under high gate pulse voltage stress.

[0044] Figure 14c The diagram illustrates the operating state of Sub-Example 1.3 of the present invention under high gate voltage stress.

[0045] Figure 15a The diagram illustrates the operating state of Example 2 of the present invention under low gate voltage stress.

[0046] Figure 15b The diagram illustrates the operating state under high gate voltage stress in Example 2 of the present invention.

[0047] Figure 15c The diagram illustrates the operating state under gate rising edge voltage stress in Example 2 of the present invention.

[0048] Figure 15d The diagram illustrates the operating state of Example 2 of the present invention under gate falling edge voltage stress.

[0049] Figure 15eThe gate pulse waveform under gate voltage stress in Example 2 of the present invention is illustrated.

[0050] Figure 16 The diagram illustrates the operating state of the drain electrode in Example 3 of this invention when dV / dt stress occurs.

[0051] Explanation of reference numerals in the attached figures:

[0052] 1. Gate voltage manager; 2. Boost region; 3. Breakdown region; 4. Discharge region; 5. Clamping region; 6. Main power transistor; 11. Input port; 12. Output port; 13. Clamping port; 201. q diodes connected in series; 202. q enhancement-mode transistors connected in series with gate-source short circuit; 21. Anode of the boost region; 22. Cathode of the boost region; 301. A depletion-mode transistor; 302. A depletion-mode transistor source connected in series with a resistor; 303. A depletion-mode transistor with gate-source short circuit; 304. A depletion-mode transistor source connected in series with a resistor; 305. A capacitor; 306. A breakdown diode; 307. An enhancement-mode transistor with gate-source short circuit. 31. Gate of the withstand voltage region; 32. Source of the withstand voltage region; 33. Drain of the withstand voltage region; 34. Anode of the withstand voltage region; 35. Cathode of the withstand voltage region; 401. A discharge diode; 402. An enhancement-mode transistor with a short-circuited gate and source; 41. Anode of the discharge region; 42. Cathode of the discharge region; 500. A clamping resistor; 501. A clamping diode (forming structure A); 502. Structure B formed by two diodes connected back-to-back in series; 503. Structure C formed by two diodes connected face-to-face in series; 504. A structure of m sequentially connected series diodes and n sequentially connected series diodes in reverse parallel and in parallel with structure A; 505. A structure of m sequentially connected series diodes and n sequentially connected series diodes in reverse parallel and in parallel with structure B. Structures: 506. A structure consisting of m sequentially connected series diodes and n sequentially connected series diodes in reverse parallel with a C structure; 507. A structure consisting of m sequentially connected series enhancement-mode transistors with shorted gate-sources and n sequentially connected series enhancement-mode transistors with shorted gate-sources in reverse parallel with an A structure; 508. A structure consisting of m sequentially connected series enhancement-mode transistors with shorted gate-sources and n sequentially connected series enhancement-mode transistors with shorted gate-sources in reverse parallel with a B structure; 509. A structure consisting of m sequentially connected series enhancement-mode transistors with shorted gate-sources and n sequentially connected series enhancement-mode transistors with shorted gate-sources in reverse parallel with a C structure; 510. A structure consisting of m sequentially connected series diodes and n sequentially connected series enhancement-mode transistors with shorted gate-sources in reverse parallel with a C structure. Structure A in parallel; 511. A structure of m sequentially connected series diodes and n sequentially connected series gate-source short-circuited enhancement-mode transistors in reverse parallel with structure B in parallel; 512. A structure of m sequentially connected series diodes and n sequentially connected series gate-source short-circuited enhancement-mode transistors in reverse parallel with structure C in parallel; 513. A structure of m sequentially connected series gate-source short-circuited enhancement-mode transistors and n sequentially connected series diodes in reverse parallel with structure A in parallel; 514. A structure of m sequentially connected series gate-source short-circuited enhancement-mode transistors and n sequentially connected series diodes in reverse parallel with structure B in parallel; 515. A structure of m sequentially connected series gate-source short-circuited enhancement-mode transistors and n sequentially connected series diodes in reverse parallel with structure C in parallel;516. A reverse parallel structure of m sequentially connected series diodes and n sequentially connected series diodes; 517. A reverse parallel structure of m sequentially connected series enhancement-mode transistors with shorted gate-source and n sequentially connected series enhancement-mode transistors with shorted gate-source; 518. A reverse parallel structure of m sequentially connected series diodes and n sequentially connected series enhancement-mode transistors with shorted gate-source; 519. A reverse parallel structure of m sequentially connected series enhancement-mode transistors with shorted gate-source and n sequentially connected series diodes; 51. Clamping region positive electrode; 52. Clamping Negative terminal of the bit region; 601, unidirectional voltage enhancement mode power transistor; 6011, unidirectional gate; 6012, unidirectional source; 6013, unidirectional drain; 602, common-source bidirectional voltage enhancement mode power transistor; 6021, common-source gate; 6024, common-source source; 6022, common-source first drain; 6023, common-source second drain; 603, single-gate bidirectional voltage enhancement mode power transistor; 6031, single-gate gate; 6032, single-gate first drain; 6033, single-gate second drain; 60 34. Single-gate substrate; 604. Common-drift bidirectional voltage-enhanced power transistor; 6041. Common-drift first gate; 6042. Common-drift second gate; 6043. Common-drift first source; 6044. Common-drift second source; 8. Secondary gate; 81. Unidirectional secondary gate; 82. Common-source first gate; 83. Common-source second gate; 84. Single-gate first gate; 85. Single-gate second gate; 86. Common-drift first gate; 87. Common-drift second gate 605. Unidirectional voltage enhancement-mode power transistor with a secondary gate; 606. Common-source bidirectional voltage enhancement-mode power transistor with a secondary gate; 607. Single-gate bidirectional voltage enhancement-mode power transistor with a secondary gate; 608. Common-drift-region bidirectional voltage enhancement-mode power transistor with a secondary gate; 71. Substrate; 72. Buffer layer; 73. Channel layer; 74. Barrier layer; 75. p-GaN gate; 76. Contact; 77. Isolation region; 78. Metal; 79. Dielectric; 91. Drift region. Detailed Implementation

[0053] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0054] In the following description, numerous specific details are set forth for explanatory purposes in order to provide a thorough understanding of the inventive concept. As part of this specification, some of the accompanying drawings of this disclosure are block diagrams illustrating structures and devices to avoid complicating the disclosed principles. For clarity, not all features of the actual embodiment need to be described. Furthermore, the language used in this disclosure has been primarily chosen for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention in order to apply to the necessary claims to determine such inventive subject matter. Additionally, the specialized terminology used in this disclosure is for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention in order to apply to the necessary claims to determine such inventive subject matter. References to “an embodiment” or “an embodiment” in this disclosure mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment, and multiple references to “an embodiment” or “an embodiment” should not be construed as necessarily referring to the same embodiment.

[0055] Unless explicitly defined, the terms “a,” “an,” and “the” are not intended to refer to a singular entity, but rather to include a general category whose specific examples can be used for illustration. Therefore, the use of the terms “a” or “an” can mean any number of at least one, including “a,” “one or more,” “at least one,” and “one or more.” The term “or” means any of the options and any combination of the options, including all options unless explicitly indicated that the options are mutually exclusive. The phrase “at least one of” when combined with a list of items refers to a single item in the list or any combination of items in the list. The phrase does not require all items listed unless explicitly defined as such.

[0056] The components involved in the nitride power device with gate voltage management function disclosed in this invention include resistors, capacitors, transistors and diodes, which are preferably monolithically integrated on a nitride substrate or monolithically integrated on a heteroepitaxial nitride substrate; optionally, the components involved are independent components and formed on a printed circuit board.

[0057] The nitride power device with gate voltage management function in this application includes a basic functional unit and a sub-functional unit. The basic functional unit is a gate voltage manager 1 and a main power transistor 6. The sub-functional unit of the gate voltage manager 1 includes a boost region 2, a withstand voltage region 3, a discharge region 4, and a clamping region 5.

[0058] refer to Figure 1a -j, the sub-functional units can be combined into 12 gate compression managers based on constraints.

[0059] refer to Figure 2-12Since each sub-functional unit has multiple equivalently replaceable semiconductor devices and components, this invention cannot freely combine all semiconductor devices and components and list them one by one. Those skilled in the art can make equivalent substitutions based on the technical features of this invention.

[0060] refer to Figure 13a -g, This application demonstrates the feasibility of implementing the present invention based on a p-GaN gate HEMT integration platform. The p-GaN gate HEMT integration platform includes a substrate 71, a buffer layer 72, a channel layer 73, a barrier layer 74, a p-GaN gate 75, a contact 76, an isolation region 77, a metal 78, and a dielectric 79.

[0061] refer to Figure 13a -g lists the cross-sectional structures of basic devices involved in this invention, such as diodes, transistors, resistors, and capacitors. Based on the above components, those skilled in the art can construct all the functional units involved in this invention. In addition, this application lists the cross-sectional structures of special devices or components, such as the secondary gate 8 and various bidirectional transistors, to facilitate those skilled in the art's understanding of the special components involved in this application. Given that the secondary gate 8 and the main power transistor 6 have various positional relationships, including overlapping, non-overlapping, etc., those skilled in the art should understand the implications by referring to... Figure 13a The cross-sectional structure shown by -g is only an optional option.

[0062] In the accompanying drawings of this application, light-colored dashed boxes are used to represent basic functional units; dark-colored dashed boxes are used to represent sub-functional units; hollow circles are used to represent ports of functional units; and the semiconductor components or parts involved are represented based on industry-standard symbols (compliant with IEC standards).

[0063] This invention discloses the technical features and functions of functional units related to nitride power devices with gate voltage management capabilities, as explained below:

[0064] Nitride power devices with gate voltage management:

[0065] (1) Technical features:

[0066] Nitride power devices with gate voltage management functionality include basic functional units: gate voltage manager 1 and main power transistor 6.

[0067] (2) Unit function:

[0068] Nitride power devices with gate voltage management can regulate the gate drive voltage through the gate voltage manager 1, preventing gate overvoltage breakdown of the main power transistor 6 under high gate drive voltage. This also suppresses the Miller effect and parasitic oscillations, improving the gate withstand voltage and threshold voltage of the power device. Therefore, nitride power devices with gate voltage management are suitable for demanding power electronic applications such as high voltage, high power, high temperature, and high radiation, and can be used for substrate potential modulation in nitride bidirectional switches.

[0069] Regarding Gate Voltage Manager 1:

[0070] (1) Technical features:

[0071] refer to Figure 1a -j, Gate Voltage Manager 1 is a basic functional unit of a nitride power device with gate voltage management function, including sub-functional units: boost region 2, withstand voltage region 3, discharge region 4, and clamping region 5. Among them, withstand voltage region 3 is a mandatory sub-functional unit, while boost region 2, discharge region 4, and clamping region 5 are optional units.

[0072] Depending on the composition of the sub-functional units and the different semiconductor devices and components constituting each sub-functional unit, the number of ports of the gate voltage manager 1 can be two or three. See Appendix for details. Figure 1a -j, where two ports are: input port 11 and output port 12; and three ports are: input port 11, output port 12, and clamp port 13.

[0073] (2) Unit function:

[0074] The gate voltage manager 1 is used to regulate the input voltage (Vin) applied by the driver chip to the gate of the main power transistor 6 through the input port 11 and to manage the charging and discharging of the gate of the main power transistor 6.

[0075] Regarding boost zone 2:

[0076] (1) Technical features:

[0077] refer to Figure 2 The boost region 2 is an optional sub-functional unit of the gate voltage manager 1. It can be either a selectable q sequentially connected diodes 201 or a selectable q sequentially connected gate-source short-circuited enhancement transistors 202. It includes two ports: a boost region anode 21 and a boost region cathode 22. The boost region anode 21 is electrically connected to the input port 11, and the boost region cathode 22 is electrically connected to the withstand region drain 33 or withstand region cathode 35 of the withstand region 3, where q = 0, 1, 2...;

[0078] The magnitude of the turn-on voltage (Von_add) of boost region 2 is determined by q; if the turn-on voltage of a diode is Von_d, then the turn-on voltage Von_add of boost region 2 formed by q sequentially connected diodes 201 is (q×Von_d); if the threshold voltage of an enhancement-mode transistor is Vth_t, then the turn-on voltage Von_add of boost region 2 formed by q sequentially connected enhancement-mode transistors 202 with short-circuited gate and source is (q×Vth_t).

[0079] (2) Unit function:

[0080] The boost region 2 has unidirectional conduction characteristics; the boost region 2 of the gate voltage manager 1 is an optional component;

[0081] If boost region 2 exists in gate voltage manager 1 (q≠0), then discharge region 4 and clamping region 5 must also exist in gate voltage manager 1; the condition for turning on main power transistor 6 is: the input voltage (Vin) at input port 11 reaches the sum of the turn-on voltage (Von_add) of boost region 2 and the threshold voltage (Vth_m) of main power transistor 6.

[0082] That is, Vin = Von_add + Vth_m;

[0083] If boost region 2 does not exist in gate voltage manager 1 (q = 0), then the presence of discharge region 4 and clamping region 5 in gate voltage manager 1 is optional. The condition for turning on main power transistor 6 is: the input voltage (Vin) at input port 11 reaches the threshold voltage (Vth_m) of main power transistor 6.

[0084] That is, Vin = Vth_m.

[0085] Regarding pressure-resistant zone 3:

[0086] (1) Technical features:

[0087] refer to Figure 3a -b, the withstand voltage region 3 is a mandatory sub-functional unit of the gate voltage manager 1. It can be either a depletion transistor 301 or an enhancement transistor 302, and includes three ports: withstand voltage region gate 31, withstand voltage region source 32 and withstand voltage region drain 33.

[0088] Optionally, the voltage-resistant region 3 is a depletion-type transistor 303 with a gate-source short circuit, or a series structure 304 of a depletion-type transistor source with a gate-source short circuit and a resistor, or a capacitor 305, or a voltage-resistant diode 306, or an enhancement-type transistor 307 with a gate-source short circuit, which includes two ports: a voltage-resistant region anode 34 and a voltage-resistant region cathode 35.

[0089] The input port 11 is electrically connected to the drain 33 of the withstand voltage region or to the cathode 35 of the withstand voltage region; the output port 12 is electrically connected to the source 32 of the withstand voltage region or to the anode 34 of the withstand voltage region; and the clamping port 13 is electrically connected to the gate 31 of the withstand voltage region. When a boost region 2 is present, the boost region 2 is electrically connected between the input port 11 and the drain 33 or the cathode 35 of the withstand voltage region.

[0090] (2) Unit function:

[0091] The transistors, capacitors, and diodes used in the voltage withstand region 3 have voltage withstand capability. The voltage withstand capability of the voltage withstand region 3 depends on the length of the drift region 91 of the semiconductor device or the thickness of the capacitor dielectric. The length of the drift region 91 and the thickness of the capacitor dielectric should be set according to the actual application requirements.

[0092] The withstand voltage region 3 can absorb excess voltage from the input voltage (Vin) at input port 11 to prevent the gate of the main power transistor 6 from breaking down due to overvoltage. The excess voltage is the input voltage (Vin) minus the gate operating voltage (Vg_m_o) of the main power transistor 6 and minus the turn-on voltage (Von_add) of boost region 2. If boost region 2 exists in gate voltage manager 1 (q≠0), then:

[0093] Excess voltage = Vin - Vg_m_o - Von_add;

[0094] If boost region 2 does not exist in gate voltage manager 1 (q=0), then:

[0095] Excess voltage = Vin - Vg_m_o;

[0096] The gate operating voltage (Vg_m_o) of the main power transistor 6 is the gate voltage that enables the main power transistor 6 to be fully turned on.

[0097] Regarding discharge region 4:

[0098] (1) Technical features:

[0099] refer to Figure 4 The discharge region 4 is an optional sub-functional unit of the gate voltage manager 1. It can be an optional discharge diode 401 or an optional gate-source short-circuited enhancement transistor 402. It includes two ports: discharge region anode 41 and discharge region cathode 42. The discharge region anode 41 is electrically connected to the output port 12 and the discharge region cathode 42 is electrically connected to the input port 11.

[0100] Among them, the discharge zone 4 should have the same withstand voltage capability as the withstand voltage zone 3.

[0101] See appendix Figure 1k-L, if the withstand voltage region 3 is an enhancement transistor 302, the gate voltage manager 1 needs to set two discharge regions 4; the discharge region cathode 42 of the second discharge region 4 is electrically connected to the input port 11; the discharge region anode 41 of the second discharge region 4 is electrically connected to the withstand voltage region gate 31.

[0102] (2) Unit function:

[0103] During the turn-off process of the main power transistor 6, the discharge region 4 is used to quickly release the gate charge of the main power transistor 6 to achieve fast turn-off of the main power transistor 6. When there are two discharge regions 4, the second discharge region 4 is used to quickly release the gate charge of the enhancement-mode transistor 302 to achieve fast turn-off of the enhancement-mode transistor 302.

[0104] Regarding clamping zone 5:

[0105] (1) Technical features:

[0106] refer to Figure 5a -d, Clamping region 5 is an optional sub-functional unit of the gate voltage manager 1. It can be: a clamping resistor 500; an A structure 501 formed by a clamping diode; a B structure 502 formed by two diodes connected back-to-back in series; a C structure 503 formed by two diodes connected face-to-face in series; a structure 504, 505, or 506 consisting of m sequentially connected diodes and n sequentially connected diodes in reverse parallel, connected in parallel with either A, B, or C structures respectively; a structure 507, 508, or 509 consisting of m sequentially connected gate-source short-circuited enhancement-mode transistors and n sequentially connected gate-source short-circuited enhancement-mode transistors in reverse parallel, connected in parallel with either A, B, or C structures respectively; or a structure 5 consisting of m sequentially connected diodes and n sequentially connected gate-source short-circuited enhancement-mode transistors in reverse parallel, connected in parallel with either A, B, or C structures respectively. 10 or 511 or 512, or optional m sequentially series-connected gate-source short-circuited enhancement-mode transistors and n sequentially series-connected diodes in reverse parallel configuration, and structure A or B or C respectively connected in parallel; 513 or 514 or 515, or optional m sequentially series-connected diodes and n sequentially series-connected diodes in reverse parallel configuration; 516, or optional m sequentially series-connected gate-source short-circuited enhancement-mode transistors and n sequentially series-connected gate-source short-circuited enhancement-mode transistors in reverse parallel configuration; 517, or optional m sequentially series-connected diodes and n sequentially series-connected gate-source short-circuited enhancement-mode transistors in reverse parallel configuration; 518, or optional m sequentially series-connected gate-source short-circuited enhancement-mode transistors and n sequentially series-connected diodes in reverse parallel configuration; 519, which includes two ports: clamping region positive terminal 51 and clamping region negative terminal 52 (m = x = 0, 1, 2 ...; n = y = 0, 1, 2 ...).

[0107] If the withstand voltage region 3 uses a depletion-type transistor 301, the absolute value of the threshold voltage Vth_301 of the depletion-type transistor 301 should be controlled to be the same as the gate operating voltage (Vg_m_o) of the main power transistor 6 (i.e., |Vth_301|=Vg_m_o). Then the clamping region 5 should use an optional clamping resistor 500, or an optional clamping diode forming an A structure 501, or an optional back-to-back series-connected diode forming a B structure 502, or an optional face-to-face series-connected diode forming a C structure 503.

[0108] If the withstand voltage region 3 cannot meet the above conditions, and the withstand voltage region 3 adopts an optional depletion-type transistor 303 with gate-source short circuit, or an optional depletion-type transistor source with gate-source short circuit and a resistor in series structure 304, or an optional capacitor 305, or an optional withstand voltage diode 306, or an optional enhancement-type transistor 307 with gate-source short circuit. To prevent gate overvoltage breakdown of the main power transistor 6, the clamping region 5 should adopt one of the following configurations: 504, 505, or 506, consisting of m sequentially connected diodes and n sequentially connected diodes in reverse parallel configuration, connected in parallel with either structure A, B, or C; 507, 508, or 509, consisting of m sequentially connected gate-source short-circuited enhancement-mode transistors and n sequentially connected gate-source short-circuited enhancement-mode transistors in reverse parallel configuration, connected in parallel with either structure A, B, or C; 510, 511, or 512, consisting of m sequentially connected diodes and n sequentially connected gate-source short-circuited enhancement-mode transistors in reverse parallel configuration, connected in parallel with either structure A, B, or C; or 506, consisting of m sequentially connected diodes and n sequentially connected gate-source short-circuited enhancement-mode transistors in reverse parallel configuration, connected in parallel with either structure A, B, or C; or 507, 508, or 509, consisting of m sequentially connected diodes and n sequentially connected gate-source short-circuited enhancement-mode transistors in reverse parallel configuration, connected in parallel with either structure A, B, or C; or 508, 509, consisting of m sequentially connected diodes and n sequentially connected gate-source short-circuited enhancement-mode transistors in reverse parallel configuration, connected in parallel with either structure A, B, or C. Structures 513, 514, or 515 of an enhancement-mode transistor with a gate-source short circuit in sequence and n sequentially connected in series in reverse parallel with structures A, B, or C respectively; or optional structures 516 of m sequentially connected in series and n sequentially connected in reverse parallel; or optional structures 517 of m sequentially connected in series and n sequentially connected in series with a gate-source short circuit in sequence; or optional structures 518 of m sequentially connected in series and n sequentially connected in series with a gate-source short circuit in sequence; or optional structures 519 of m sequentially connected in series and n sequentially connected in reverse parallel with enhancement-mode transistors with a gate-source short circuit in sequence and n sequentially connected in series.

[0109] At this time, the source-gate reverse clamping voltage (Vpin_sg) of the main power transistor 6 is determined by m; the gate-source forward clamping voltage (Vpin_gs) of the main power transistor 6 is determined by n.

[0110] When the gate voltage manager 1 includes a clamping region 5, regardless of whether the withstand voltage region 3 has two or three ports, the gate voltage manager 1 always has a clamping port 13. The clamping region has a negative terminal 52 and a positive terminal 51; the negative terminal 52 is electrically connected to the output port 12, and the positive terminal 51 is electrically connected to the clamping port 13.

[0111] See appendix Figure 1k -L, if the withstand voltage region 3 is an enhancement transistor 302, the gate voltage manager 1 shall have at least one clamping region 5; if there is a second clamping region 5, the positive terminal 51 of the second clamping region 5 shall be electrically connected to the clamping port 13; the negative terminal 52 of the second clamping region 5 shall be electrically connected to the gate 31 of the withstand voltage region.

[0112] (2) Unit function:

[0113] The clamping region 5 can clamp the forward and reverse voltages between the gate and source of the main power transistor 6, preventing gate breakdown of the main power transistor 6 due to voltage oscillations or overvoltage drive. When implementing this invention, m and n should be reasonably set according to the forward and reverse withstand voltage capabilities of the main power transistor 6 gate. Furthermore, when two clamping regions 5 exist, the second clamping region 5 is used to clamp the voltage between the gate 31 of the withstand voltage region and the clamping port 13 to regulate the potential of the source 32 of the withstand voltage region; the potential of the source 32 of the withstand voltage region is the difference between the forward clamping voltage of the second clamping region 5 and the threshold voltage of the enhancement-mode transistor 302.

[0114] Regarding main power transistor 6:

[0115] (1) Technical features:

[0116] Referring to Figure 6-12, the main power transistor 6 is a functional unit of a nitride power device with gate voltage management function. It is an optional unidirectional voltage-enhanced power transistor 601, which includes three electrodes: unidirectional gate 6011, unidirectional source 6012 and unidirectional drain 6013.

[0117] The main power transistor 6 driven by the gate voltage manager 1 is a unidirectional voltage-enhanced power transistor 601. The electrical interconnection layout involves the following: the output port 12 of the gate voltage manager 1 is electrically connected to the unidirectional gate 6011 of the unidirectional voltage-enhanced power transistor 601. When the gate voltage manager 1 has a clamping port 13, the clamping port 13 is electrically connected to the unidirectional source 6012 of the unidirectional voltage-enhanced power transistor 601.

[0118] Optionally, the main power transistor 6 is a common-source bidirectional voltage-enhanced power transistor 602, which includes four electrodes: a common-source gate 6021, a common-source source 6024, a common-source first drain 6022, and a common-source second drain 6023.

[0119] The main power transistor 6 driven by the gate voltage manager 1 is a common-source bidirectional voltage enhancement-mode power transistor 602. The electrical interconnection layout involves the following: the output port 12 of the gate voltage manager 1 is electrically connected to the common-source gate 6021 of the common-source bidirectional voltage enhancement-mode power transistor 602. When the gate voltage manager 1 has a clamping port 13, the clamping port 13 is electrically connected to the common-source source 6024 of the common-source bidirectional voltage enhancement-mode power transistor 602.

[0120] Optionally, the main power transistor 6 is a single-gate bidirectional voltage-enhanced power transistor 603, which includes four electrodes: a single-gate gate 6031, a single-gate first drain 6032, a single-gate second drain 6033, and a single-gate substrate 6034.

[0121] The main power transistor 6 driven by the gate voltage manager 1 is a single-gate bidirectional voltage enhancement-mode power transistor 603. The electrical interconnection layout involves the following: the output port 12 of the gate voltage manager 1 is electrically connected to the single-gate gate 6031 of the single-gate bidirectional voltage enhancement-mode power transistor 603. When the gate voltage manager 1 has a clamping port 13, the clamping port 13 is electrically connected to the single-gate substrate 6034 of the single-gate bidirectional voltage enhancement-mode power transistor 603.

[0122] Optionally, the main power transistor 6 is a common-drift bidirectional voltage-enhanced power transistor 604, which includes four electrodes: a first gate 6041, a second gate 6042, a first source 6043, and a second source 6044.

[0123] The main power transistor 6 driven by the gate voltage manager 1 is a common-drift bidirectional voltage-enhanced power transistor 604. The electrical interconnection layout involves two independent gate voltage managers 1.

[0124] The output port 12 of the first gate voltage manager 1 is electrically connected to the first gate 6041 of the common drift region of the common drift region bidirectional voltage-enhanced power transistor 604; when the first gate voltage manager 1 has a clamping port 13, the clamping port 13 is electrically connected to the first source 6043 of the common drift region of the common drift region bidirectional voltage-enhanced power transistor 604.

[0125] The output port 12 of the second gate voltage manager 1 is electrically connected to the second gate 6042 of the common drift region of the common drift region bidirectional voltage-enhanced power transistor 604; when the second gate voltage manager 1 has a clamping port 13, the clamping port 13 is electrically connected to the second source 6044 of the common drift region of the common drift region bidirectional voltage-enhanced power transistor 604.

[0126] (2) Unit function:

[0127] For different power electronic topology applications, the main power transistor 6 is available in unidirectional and bidirectional voltage-tolerant transistors. Both unidirectional and bidirectional voltage-tolerant transistors can be configured with a gate voltage manager 1 to improve gate reliability.

[0128] This invention discloses the technical features and functions of components related to nitride power devices with gate voltage management capabilities, as explained below:

[0129] Regarding the secondary gate 8:

[0130] (1) Technical features:

[0131] refer to Figure 6b and Figure 10-12 The main power transistor 6 may optionally have a secondary gate 8. The secondary gate 8 can conduct Miller current to the input port 11 to suppress the Miller effect.

[0132] The secondary gate 8 is located in the drift region 91 of the main power transistor 6 and is close to, covers, or partially overlaps with the gate of the main power transistor 6, as shown in the attached figure. Figure 13d -g, The drift region 91 of the main power transistor 6 is essentially the region between the drain and gate of the main power transistor 6, and it is used to withstand the high drain voltage of the main power transistor 6. The distance (Lgo) from the secondary gate 8 to the gate of the main power transistor 6 is between 20 nanometers and 3 micrometers and is isolated by dielectric 79. The secondary gate 8 is electrically connected to the input port 11 of the gate voltage manager 1.

[0133] If the main power transistor 6 is a unidirectional voltage-enhanced power transistor 605 with a secondary gate, it includes a secondary gate 8 defined as a unidirectional secondary gate 81, which is located between and close to the unidirectional gate 6011 and the unidirectional drain 6013, and is electrically connected to the input port 11 of the gate voltage manager 1.

[0134] If the main power transistor 6 is a common-source bidirectional voltage-enhanced power transistor 606 with secondary gates, it includes two secondary gates 8 defined as a common-source first gate 82 and a common-source second gate 83. The common-source first gate 82 is located between the common-source gate 6021 and the common-source first drain 6022 and is close to the common-source gate 6021. The common-source second gate 83 is located between the common-source gate 6021 and the common-source second drain 6023 and is close to the common-source gate 6021; the common-source first gate 82 and the common-source second gate 83 are electrically connected to the input port 11 of the gate voltage manager 1.

[0135] If the main power transistor 6 is a single-gate bidirectional voltage-enhanced power transistor 607 with a secondary gate, it includes two secondary gates 8, defined as a single-gate first gate 84 and a single-gate second gate 85. The single-gate first gate 84 is located between the single-gate gate 6031 and the single-gate first drain 6032 and is close to the single-gate gate 6031; the single-gate second gate 85 is located between the single-gate gate 6031 and the single-gate second drain 6033 and is close to the single-gate gate 6031.

[0136] The first gate 84 and the second gate 85 of the single gate are electrically connected to the input port 11 of the gate voltage manager 1. Optionally, the first gate 84 and the second gate 85 of the single gate can also cover the single gate 6031 and be short-circuited to each other.

[0137] If the main power transistor 6 is a common-drift bidirectional voltage-enhanced power transistor 608 with secondary gates, it includes two secondary gates 8, defined as a first common-drift gate 86 and a second common-drift gate 87. The first common-drift gate 86 is located between and close to the first common-drift gate 6041 and the second common-drift gate 6042; the second common-drift gate 87 is located between and close to the second common-drift gate 6042 and the first common-drift gate 6041.

[0138] The first gate 86 of the common drift region is electrically connected to the input port 11 of the first gate voltage manager 1; the second gate 87 of the common drift region is electrically connected to the input port 11 of the second gate voltage manager 1.

[0139] The secondary gate 8 mainly adopts a metal / insulator / semiconductor (MIS) structure gate. The MIS structure gate is divided into planar MIS gate and grooved MIS gate. Its threshold voltage (Vth_o) should be less than the threshold voltage (Vth_m) of the main power transistor 6 to avoid affecting the switching performance of the main power transistor 6.

[0140] The maximum operating voltage (Vsg_o) of the secondary gate 8 should be greater than or equal to the input voltage (Vin) of the input port 11 to avoid breakdown of the secondary gate 8. The maximum operating voltage (Vsg_o) is mainly determined by the thickness and material of the insulating layer of the MIS structure, and its thickness (To) is usually 5 nanometers to 50 nanometers; the length (Lo) of the secondary gate 8 is between 100 nanometers and 5 micrometers.

[0141] If the secondary gate 8 is present on the high-voltage main power transistor 6, the high-voltage main power transistor 6 typically requires a field plate formed by metal 78 to modulate the electric field in order to improve its breakdown voltage capability. For the unidirectional breakdown voltage enhancement power transistor 605 with a secondary gate, the common-source bidirectional breakdown voltage enhancement power transistor 606 with a secondary gate, and the common-drift region bidirectional breakdown voltage enhancement power transistor 608 with a secondary gate, the field plate should be electrically connected to the source of the main power transistor 6; for the single-gate bidirectional breakdown voltage enhancement power transistor 607 with a secondary gate, the field plate should be electrically connected to the single-gate substrate 6034 of the main power transistor 6.

[0142] (2) Component functions:

[0143] The secondary gate 8 can guide the current generated by the Miller capacitance through the input port 11 to the driver chip, so as to avoid the Miller effect conducting current through the gate of the main power transistor 6, effectively suppressing the mis-turn-on of the main power transistor 6 and the gate voltage oscillation caused by the Miller effect.

[0144] For high-voltage, high-power half-bridge topology applications, the secondary gate 8 should be present in the main power transistor 6 to suppress the Miller effect.

[0145] For bidirectional switching substrate potential modulation applications, the secondary gate 8 should not be present in the main power transistor 6 to prevent the maximum operating voltage (Vsg_o) of the secondary gate 8 from limiting the gate breakdown voltage capability of the nitride power device of this invention. For bidirectional switching substrate potential modulation applications, this invention only needs to have a high gate breakdown voltage capability; other capabilities (such as increasing the threshold voltage, suppressing LC parasitic oscillations, and suppressing the Miller effect) should be appropriately configured to maintain the advantages of circuit simplicity and efficiency.

[0146] Figure 1 illustrates 12 types of gate voltage manager 1. This application cannot freely arrange and combine the gate voltage manager 1 and the main power transistor 6 to create all possible electrical interconnect layouts. (Reference) Figure 7-12 This application illustrates the basic electrical layout features of the present invention based on gate voltage manager 109 and gate voltage manager 110 with unidirectional voltage-enhanced power transistor 601, based on gate voltage manager 101 with unidirectional voltage-enhanced power transistor 601 and unidirectional voltage-enhanced power transistor 605 with a secondary gate, and based on gate voltage manager 101 with common-source bidirectional voltage-enhanced power transistor 606 with a secondary gate and single-gate bidirectional voltage-enhanced power transistor 607 with a secondary gate.

[0147] This application also discloses several representative embodiments of nitride power devices with gate voltage management functions to illustrate the advantages of the present invention in improving gate breakdown voltage, improving threshold voltage, suppressing LC parasitic oscillations, and suppressing the Miller effect, including:

[0148] Case 1: High gate voltage withstand capability nitride power device with gate voltage management function

[0149] Referring to Figure 1, 12 types of gate voltage managers 1 are listed, all of which include a voltage withstand region 3. This invention achieves high gate withstand voltage capability based on the voltage withstand region 3 bearing the excess voltage of the gate of the main power transistor 6. Therefore, this invention can employ any of the 12 types of gate voltage managers 1 to improve gate withstand voltage. Since the voltage withstand region 3 includes 7 types of semiconductors or components, for ease of understanding and to avoid redundancy, the following sub-examples are provided:

[0150] Sub-case 1.1:

[0151] refer to Figure 14a This case uses a depletion-type transistor 301, a gate voltage manager 105, and a unidirectional voltage-enhanced power transistor 601.

[0152] Assuming an input voltage (Vin) of 100V at input port 11, the threshold voltage (Vth_301) of depletion-type transistor 301 is -6V. The threshold voltage of depletion-type transistor 301 is determined by factors such as gate dielectric thickness, barrier layer, and metal work function. Since the gate 31 of the breakdown region is connected to the unidirectional source 6012, the potential of the gate 31 of the breakdown region is equal to the potential of the unidirectional source 6012, which is 0V. When the potential of the unidirectional gate 6011 just exceeds 6V, the voltage difference between the gate 31 and the source 32 of the breakdown region is just less than the threshold voltage of depletion-type transistor 301, which is -6V. Therefore, the channel of depletion-type transistor 301 is turned off, and the voltage difference between the drain 33 and the source 32 of the breakdown region of depletion-type transistor 301 is an excessive voltage of 94V. Based on the above mechanism, the highest gate drive voltage that this invention can tolerate is determined by the withstand voltage capability of the breakdown region 3.

[0153] Sub-case 1.2:

[0154] refer to Figure 14b This case employs a capacitor 305, a gate voltage manager 108, a structure 517 consisting of m sequentially connected enhancement-mode transistors with shorted gate-source circuits and n sequentially connected enhancement-mode transistors with shorted gate-source circuits in reverse parallel configuration, and a unidirectional voltage-rated enhancement-mode power transistor 601. Since the voltage-rated region 3 in this case is the capacitor 305, this case is suitable for voltage pulse gate drive.

[0155] Note: If the gate drive type of the unidirectional voltage-enhanced power transistor 601 is voltage-driven, according to sub-case 1.1, the depletion-type transistor 301 in the voltage-depletion region 3 can control the gate operating voltage (Vg_m_o) of the unidirectional voltage-enhanced power transistor 601 by setting the depletion-type transistor threshold voltage or the gate clamping voltage of an enhancement transistor 302. However, other semiconductor devices or components (i.e., a depletion-type transistor source with a gate-source short circuit connected in series with a resistor 304, a capacitor 305, a voltage-depletion diode 306, and an enhancement transistor 307 with a gate-source short circuit) do not have the electrical characteristics of a depletion-type transistor. In such cases, a gate voltage manager 1 (e.g., 101, 102, 103, 106, 107, or 108) with a clamping region 5 should be used to prevent gate overvoltage breakdown of the unidirectional voltage-enhanced power transistor 601.

[0156] refer to Figure 14b Assuming a voltage pulse from 0V to 100V is applied to input port 11, capacitor 305 will charge during this process (i.e., a forward charging current is generated from the negative terminal 52 of the clamping region to the positive terminal 51 of the clamping region, and the clamping region 5 is in the forward ON state). If the threshold voltage of the enhancement-mode transistor in the clamping region 5 is 2V; the number of reverse transistors m is 2; and the number of forward transistors n is 3, then the reverse clamping voltage (Vpin_sg) of the clamping region 5 is 4V and the forward clamping voltage (Vpin_gs) is 6V. Therefore, during the charging process of capacitor 305, the potential of the unidirectional gate 6011 is clamped at 6V by the clamping region 5 (i.e., Vg_m_o = 6V), and the remaining 94V excess voltage is applied across capacitor 305.

[0157] Sub-case 1.3:

[0158] refer to Figure 14c This case uses an enhancement-mode transistor 302, a gate voltage manager 112, m sequentially connected series gate-source short-circuited enhancement-mode transistors and n sequentially connected series gate-source short-circuited enhancement-mode transistors in reverse parallel structure 517, two discharge diodes 401, and a unidirectional voltage-resistant enhancement-mode power transistor 601.

[0159] Assuming the input voltage (Vin) at input port 11 is 100V, the threshold voltage (Vth_302) of enhancement-mode transistor 302 is 2V, m is 2, and n is 4, then the forward clamping voltage is 8V and the reverse clamping voltage is 4V. Since the gate 31 of the withstand region is connected to the negative terminal 52 of the clamping region, the potential of the gate 31 of the withstand region is equal to the forward clamping voltage (8V). The potential of the unidirectional gate 6011 is the difference between the forward clamping voltage and the threshold voltage of the enhancement-mode transistor 302 (6V). At this time, the channel of the enhancement-mode transistor 302 is turned off, and the voltage difference between the drain 33 of the withstand region and the source 32 of the withstand region of the enhancement-mode transistor 302 is an excessive voltage of 94V.

[0160] Case 2: Nitride power devices with gate voltage management function that have high threshold voltage and suppress parasitic oscillations

[0161] This case study uses boost region 2 to increase the threshold voltage. Therefore, gate voltage managers 101 and 106, both with boost region 2, are suitable for this case study.

[0162] This case study employs a gate voltage manager 101, q sequentially connected gate-source short-circuited enhancement-type transistors 202, a depletion-type transistor 301, a discharge diode 401, an A-structure 501 formed by clamping diodes, and a unidirectional voltage-resistant enhancement-type power transistor 601.

[0163] If the threshold voltage of the enhancement-type transistor in boost region 2 is 2V; if the number of transistors q is 1; then the turn-on voltage (Von_add) of boost region 2 is 2V. If the threshold voltage of depletion-type transistor 301 is -6V, then according to Case 1.1, the gate operating voltage (Vg_m_o) of unidirectional voltage-depleted enhancement-type power transistor 601 is 6V. Note: The leakage current Ia of discharge diode 401 and the leakage current Ib of structure A 501 formed by clamping diode should satisfy claim 10, and Ia and Ib can be adjusted by adjusting the device width of structure A 501 formed by discharge diode 401 and clamping diode.

[0164] State 1 (Off): Reference Figure 15a Assuming the input voltage (Vin) at input port 11 is lower than Von_add (if Vin is 1V), according to the condition for turning on the main power transistor 6 after setting boost region 2, since boost region 2 cannot be turned on (OFF), Vin is entirely applied to boost region 2. At this time, the gate-source potential difference of depletion-type transistor 301 is 0V, and depletion-type transistor 301 is in the ON state; the potential of unidirectional gate 6011 is lower than its threshold voltage (Vth_m), and unidirectional voltage-enhanced power transistor 601 is in the OFF state.

[0165] State 2 (Open State): Reference Figure 15bAssuming the input voltage (Vin) at input port 11 is higher than the sum of Von_add and Vth_m (if Vth_m is 2V; if Vin is 10V), boost region 2 is ON, and the voltage drop across boost region 2 is 2V. Since Vin's voltage after sharing 2V through boost region 2 is 8V, which is greater than the absolute value of the threshold voltage of depletion-type transistor 301, according to Case 1.1, depletion-type transistor 301 is OFF. At this time, the potential of unidirectional gate 6011 is 6V, which is higher than its threshold voltage (Vth_m), so unidirectional voltage-enhanced power transistor 601 is ON, and the drain-source voltage difference of depletion-type transistor 301 is 2V.

[0166] State 3 (rising edge): Reference Figure 15c During the turn-on process of the unidirectional voltage-enhancing power transistor 601, if the input voltage (Vin) rises from 0V to 100V, the boost region 2 transitions from the off state to the on state; the depletion-type transistor 301 transitions from the on state to the off state; and the unidirectional voltage-enhancing power transistor 601 transitions from the off state to the on state. Because the channel resistance of the depletion-type transistor 301 increases instantaneously during the transition from the on state to the off state, the resistance of the drive input path increases instantaneously. (Reference) Figure 11 (e., switching frequency 100kHz) The unidirectional voltage-enhanced power transistor 601 of this invention exhibits no gate voltage overshoot after the rising edge and the gate voltage stabilizes at 6V. However, conventional enhancement-mode power transistors using a 6V drive voltage experience a rising edge voltage overshoot of approximately 0.15V.

[0167] State 4 (falling edge): Reference Figure 15d During the turn-off process of the unidirectional voltage-enhanced power transistor 601, if the input voltage (Vin) drops from 100V to 0V, the boost region 2 transitions from the on state to the off state; the depletion-mode transistor 301 transitions from the off state to the on state; and the unidirectional voltage-enhanced power transistor 601 transitions from the on state to the off state. At this time, the gate-source capacitance of the unidirectional voltage-enhanced power transistor 601 discharges through the discharge diode 401 and charges the external parasitic inductor connected in series at the input port 11. Since the energy stored in the external parasitic inductor cannot overcome the potential barrier of the boost region 2, the gate-source capacitance of the unidirectional voltage-enhanced power transistor 601 cannot be repeatedly charged and discharged. (Reference) Figure 15e (Switching frequency is 100kHz) The unidirectional voltage-enhanced power transistor 601 of this invention exhibits no gate voltage oscillation and its gate voltage is stable at -0.3V (due to the clamping effect of the A structure 501 formed by the clamping diode). In contrast, conventional enhancement-mode power transistors using a 6V drive voltage have a falling edge voltage oscillation amplitude of approximately 0.4V.

[0168] Case 3: Nitride power devices with gate voltage management to suppress the Miller effect

[0169] Optional components (secondary gate 8) in the main power transistor 6 are used to suppress the Miller effect; therefore, refer to Figure 6b The main power transistor 6 with a secondary gate 8 (i.e., 605, 606, 607, or 608) is suitable for this case. A basic electrical layout configuration for driving the main power transistor 6 with a secondary gate 8 is provided below. Figure 10-12 .

[0170] refer to Figure 16 This case employs a gate voltage manager 101, q sequentially connected gate-source short-circuited enhancement-type transistors 202, a depletion-type transistor 301, a discharge diode 401, an A-structure 501 formed by clamping diodes, and a unidirectional voltage-degradable enhancement-type power transistor 605 with a secondary gate.

[0171] If the input voltage (Vin) at input port 11 is 0V, according to Case 2, the unidirectional voltage-enhancing power transistor 605 with a secondary gate is in the off state. If a positive voltage transient pulse (+dV / dt) is applied to the unidirectional drain 6013, a positive Miller current is generated from the secondary gate 81 to input port 11. The positive Miller current creates a voltage drop across the drive resistor, which applies a positive voltage to input port 11. Thanks to the barrier (whose height is determined by q) generated in boost region 2 on the drive path, the positive voltage induced by the positive Miller current is blocked, preventing the unidirectional voltage-enhancing power transistor 605 with a secondary gate from being falsely turned on. If a negative voltage transient pulse (-dV / dt) is applied to the unidirectional drain 6013, a reverse Miller current is generated from the secondary gate 81 to input port 11. The reverse Miller current creates a voltage drop across the drive resistor, which applies a negative voltage to input port 11. The negative voltage at input port 11 causes the A-structure 501 formed by the discharge diode 401 and the clamping diode to conduct. If the turn-on voltage of the discharge diode 401 is 0.3V, the reverse Miller current causes the gate potential of the unidirectional voltage-enhancing power transistor 605 with a secondary gate to be clamped at -0.3V by the discharge diode 401, avoiding excessive negative gate voltage stress. In summary, the unidirectional voltage-enhancing power transistor 605 with a secondary gate benefits from its secondary gate 81, which can suppress gate misconduction and high negative gate voltage stress caused by the Miller effect.

[0172] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A nitride power device with gate voltage management function, characterized in that: It includes a gate voltage manager (1) and a main power transistor (6). The gate voltage manager (1) includes a withstand voltage region (3) for sharing the excess voltage of the input voltage to avoid overvoltage breakdown of the gate of the main power transistor (6). The withstand voltage region (3) is made of a semiconductor device with withstand voltage capability.

2. The nitride power device with gate voltage management function according to claim 1, characterized in that: Based on different semiconductor devices, the voltage-resistant region (3) has two ports: a voltage-resistant region anode (34) and a voltage-resistant region cathode (35), or it has three ports: a voltage-resistant region gate (31), a voltage-resistant region source (32), and a voltage-resistant region drain (33). When it has two ports, the gate voltage manager (1) has two ports: an input port (11) and an output port (12). The cathode (35) of the withstand voltage region is electrically connected to the input port (11), and the anode (34) of the withstand voltage region is electrically connected to the output port (12). The output port (12) is electrically connected to the gate of the main power transistor (6). When it has three ports, the gate voltage manager (1) has three ports: an input port (11), an output port (12), and a clamping port (13). The drain (33) of the withstand voltage region is electrically connected to the input port (11), the gate (31) of the withstand voltage region is electrically connected to the clamping port (13), and the source (32) of the withstand voltage region is electrically connected to the output port (12). The output port (12) is electrically connected to the gate of the main power transistor (6), and the clamping port (13) is electrically connected to the source or substrate (71) of the main power transistor (6).

3. The nitride power device with gate voltage management function according to claim 2, characterized in that: When it has two ports, the withstand voltage region (3) is a depletion-type transistor (303) with gate-source short circuit, or a series structure (304) of the source of a depletion-type transistor with gate-source short circuit and a resistor, or a capacitor (305), or a withstand voltage diode (306), or an enhancement-type transistor (307) with gate-source short circuit. When there are three ports, the withstand voltage region (3) is a depletion transistor (301) or an enhancement transistor (302).

4. The nitride power device with gate voltage management function according to claim 1, characterized in that: The main power transistor (6) is a unidirectional voltage-enhanced power transistor (601), a common-source bidirectional voltage-enhanced power transistor (602), a single-gate bidirectional voltage-enhanced power transistor, or a common-drift region bidirectional voltage-enhanced power transistor (604).

5. The nitride power device with gate voltage management function according to claim 4, characterized in that: The main power transistor (6) is provided with a secondary gate (8) that can conduct Miller current to the input port (11) to suppress the Miller effect. The secondary gate (8) is electrically connected to the input port (11). When the main power transistor (6) is a unidirectional voltage-enhanced power transistor (601), the number of secondary gates (8) is one. When the main power transistor (6) is a common-source bidirectional voltage-enhanced power transistor (602), a single-gate bidirectional voltage-enhanced power transistor, or a common-drift bidirectional voltage-enhanced power transistor (604), the number of secondary gates (8) is two.

6. The nitride power device with gate voltage management function according to claim 5, characterized in that: The secondary gate (8) is located in the drift region (91) of the main power transistor (6) and is close to, covers or partially overlaps the gate of the main power transistor (6); the distance between the secondary gate (8) and the gate of the main power transistor (6) is between 20 nanometers and 3 micrometers and is isolated by a dielectric (79).

7. The nitride power device with gate voltage management function according to any one of claims 1 to 6, characterized in that: The gate voltage manager (1) further includes a discharge region (4) for rapidly releasing the gate charge of the main power transistor (6) to achieve rapid turn-off of the main power transistor (6), and / or a clamping region (5) for clamping the positive and reverse voltages between the gate and source of the main power transistor (6) to avoid gate breakdown of the main power transistor (6) due to voltage oscillation or overvoltage drive. The clamping region negative terminal (52) of the clamping region (5) is electrically connected to the output port (12), and the clamping region positive terminal (51) is electrically connected to the clamping port (13). The discharge region anode (41) of the discharge region (4) is electrically connected to the output port (12), and the discharge region cathode (42) is electrically connected to the input port (11).

8. The nitride power device with gate voltage management function according to claim 7, characterized in that: When the withstand voltage region (3) is an enhancement-mode transistor (302), the gate voltage manager (1) includes two discharge regions (4) and at least one clamping region (5). The second discharge region (4) is used to quickly release the gate charge of the enhancement-mode transistor (302) to achieve rapid turn-off of the enhancement-mode transistor (302). The second clamping region (5) is used to clamp the voltage between the gate (31) of the withstand voltage region and the clamping port (13) to regulate the potential of the source (32) of the withstand voltage region. The cathode (42) of the discharge region of the second discharge region (4) is electrically connected to the input port (11). The anode (41) of the discharge region of the second discharge region (4) is electrically connected to the gate (31) of the withstand voltage region. If a second clamping region (5) exists, the positive terminal (51) of the second clamping region (5) is electrically connected to the clamping port (13); the negative terminal (52) of the second clamping region (5) is electrically connected to the gate (31) of the withstand voltage region; the potential of the source (32) of the withstand voltage region is the difference between the positive clamping voltage of the second clamping region (5) and the threshold voltage of the enhancement transistor (302).

9. The nitride power device with gate voltage management function according to claim 8, characterized in that: The discharge region (4) is a discharge diode (401) or a gate-source short-circuited enhancement transistor (402); The clamping region (5) is a clamping resistor (500), or an A structure formed by a clamping diode, or a B structure formed by two diodes connected back-to-back, or a C structure formed by two diodes connected face-to-face, or a structure (504, 505, 506) of m sequentially connected diodes and n sequentially connected diodes in reverse parallel (516) connected in parallel with A or B or C structure respectively, or a structure (507, 508, 509) of m sequentially connected gate-source short-circuited enhancement transistors and n sequentially connected gate-source short-circuited enhancement transistors in reverse parallel (517) connected in parallel with A or B or C structure respectively, or a structure (518) of m sequentially connected diodes and n sequentially connected gate-source short-circuited enhancement transistors in reverse parallel (518) connected in parallel with A or B The following structures are available: (510, 511, 512) or (519) a structure consisting of m sequentially connected enhancement transistors with shorted gate-sources and n sequentially connected diodes in reverse parallel; (513, 514, 515) a structure consisting of m sequentially connected diodes with shorted gate-sources and n sequentially connected diodes in reverse parallel; (516) a structure consisting of m sequentially connected enhancement transistors with shorted gate-sources and n sequentially connected enhancement transistors in reverse parallel; (517) a structure consisting of m sequentially connected diodes and n sequentially connected enhancement transistors with shorted gate-sources and n sequentially connected enhancement transistors in reverse parallel; (518) a structure consisting of m sequentially connected enhancement transistors with shorted gate-sources and n sequentially connected enhancement transistors in reverse parallel; and (519) a structure consisting of m sequentially connected enhancement transistors with shorted gate-sources and n sequentially connected diodes in reverse parallel.

10. The nitride power device with gate voltage management function according to claim 7, characterized in that: The gate voltage manager (1) includes a boost region (2) with unidirectional conduction characteristics. When the boost region (2) is present, the discharge region (4) and the clamping region (5) must be present in the gate voltage manager (1). The boost region anode (21) of the boost region (2) is electrically connected to the input port (11), and the boost region cathode (22) is electrically connected to the withstand region drain (33) or withstand region cathode (35) of the withstand region (3). The condition for turning on the main power transistor (6) is that the input voltage of the input port (11) reaches the sum of the turn-on voltage of the boost region (2) and the threshold voltage of the main power transistor (6); Furthermore, the ratio of the leakage current from the discharge cathode (42) to the discharge anode (41) of the discharge region (4) to the leakage current from the clamping negative electrode (52) to the clamping positive electrode (51) of the clamping region (5) is less than or equal to the ratio of the difference between the threshold voltage of the main power transistor (6) and the turn-on voltage of the discharge region (4) to the turn-on voltage of the boost region (2).

11. The nitride power device with gate voltage management function according to claim 9, characterized in that: The boost region (2) consists of q diodes (201) connected in series or q enhancement transistors (202) connected in series with their gate and source shorted.

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