High electron mobility transistor device
By employing an isolation layer structure made of different materials and protecting magnesium ions, the problems of large capacitance and easy capture of magnesium ions in existing high electron mobility transistor devices are solved, achieving electric field dispersion and threshold voltage improvement, thereby improving the switching performance and stability of the device.
Patent Information
- Application Number
- CN202511098898.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-06
- Publication Date
- 2025-11-11
AI Technical Summary
In existing high electron mobility transistor devices, the use of the same material for the first and second isolation layers makes it impossible to effectively modulate the concentration of two-dimensional electron gas in the channel layer. Furthermore, the large capacitance between the gate and source leads to easy wear and tear on the switch. At the same time, magnesium ions in the p-type doped gallium nitride layer are easily captured and disappear, resulting in a lower threshold voltage.
The first and second isolation layers are formed using different materials and are simultaneously in contact with the gate structure. This modulates the concentration of two-dimensional electron gas in the channel layer, reduces the capacitance between the gate and the source, and coats the second isolation layer with a p-type doped gallium nitride layer before forming the second isolation layer to protect magnesium ions from being captured.
It effectively disperses the drain electric field, reduces the capacitance between the gate and the source, improves switching losses, increases the threshold voltage, and enhances the stability and performance of the transistor device.
Smart Images
Figure CN120936068A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a high electron mobility transistor (HEMT) device, and more particularly to a high electron mobility transistor device with multiple isolation layers formed of different materials. Background Technology
[0002] Please refer to the following: Figure 1 A cross-sectional schematic diagram of a high electron mobility transistor device in the prior art. (See attached diagram.) Figure 1 As shown, the current enhancement-mode gallium nitride (GaN) high electron mobility transistor device 100 mainly includes a first isolation layer 130 and a second isolation layer 140 using silicon nitride (SiN) as the material. The first isolation layer 130 is adjacent to the gate structure 160 and covers the overall barrier layer 120, thereby preventing the modulation of the concentration of two-dimensional electron gas (2DEG) in the channel layer 110, which makes it impossible to effectively disperse the electric field of the drain 150. In addition, because the source 170 extends partially above the gate structure 160, the capacitance (Cgs) between the gate structure 160 and the source 170 is relatively large, making the switching of the prior art electron mobility transistor device 100 prone to wear and tear, and requiring improvement. Summary of the Invention
[0003] One object of the present invention is to provide a high electron mobility transistor device in which the first isolation layer and the second isolation layer are formed of different materials and the first isolation layer and the second isolation layer simultaneously contact the gate structure to modulate the concentration of two-dimensional electron gas (2DEG) in the channel layer.
[0004] Another object of the present invention is to provide a high electron mobility transistor device in which the first isolation layer and the second isolation layer are formed of different materials and the first isolation layer and the second isolation layer simultaneously contact the gate structure, thereby reducing the capacitance (Cgs) between the gate and the source and improving the switching loss of the high electron mobility transistor device.
[0005] Another object of the present invention is to provide a high electron mobility transistor device in which, during the growth of the second isolation layer, the first isolation layer can protect magnesium ions (Mg+) in the p-type doped gallium nitride layer from being captured and disappeared by hydrogen gas (H2), thereby increasing the threshold voltage (Vth) of the high electron mobility transistor device.
[0006] To achieve the above objectives, the high electron mobility transistor device of the present invention includes a channel layer, a barrier layer, a gate structure, a first isolation layer, a second isolation layer, a drain, and a regenerated layer. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer and includes a p-type doped gallium nitride (pGaN) layer and a gate metal. The p-type doped gallium nitride layer is disposed on the barrier layer, and the gate metal is disposed on the p-type doped gallium nitride layer, wherein the gate metal has a gate contact top surface. The first isolation layer covers the gate structure and is disposed on the barrier layer, wherein the gate contact top surface is exposed to the first isolation layer. The second isolation layer covers the first isolation layer and is partially disposed on the barrier layer, wherein the second isolation layer covers the gate contact top surface. The regenerated layer is disposed between the drain and the barrier layer, wherein the first isolation layer, the second isolation layer, and the regenerated layer are formed of different materials, and the dielectric constant of the material used to form the first isolation layer is less than the dielectric constant of the material used to form the second isolation layer.
[0007] According to one embodiment of the present invention, the first isolation layer includes a first contact portion, wherein the first contact portion is located on the barrier layer, and the channel layer below the first contact portion has a first 2DEG concentration; the second isolation layer includes a second contact portion, wherein the second contact portion is disposed on the barrier layer, and the channel layer below the second contact portion has a second 2DEG concentration, wherein the second 2DEG concentration is greater than the first 2DEG concentration.
[0008] According to one embodiment of the present invention, the first isolation layer is a silicon dioxide (SiO2) layer, and the second isolation layer is a silicon nitride (SiN) layer.
[0009] According to one embodiment of the present invention, the high electron mobility transistor device further includes a third isolation layer disposed on the second isolation layer and covering a portion of the regenerated layer, and a drain electrode disposed on the regenerated layer.
[0010] According to one embodiment of the present invention, the third isolation layer includes a third contact portion covering the second isolation layer and the regeneration layer, wherein the channel layer below the overlap of the third contact portion and the regeneration layer has a third 2DEG concentration, the second isolation layer includes a second contact portion disposed on the barrier layer, the channel layer below the second contact portion has a second 2DEG concentration, and the third 2DEG concentration is greater than the second 2DEG concentration.
[0011] According to one embodiment of the present invention, the regenerated layer includes at least one combination layer consisting of an aluminum-containing layer and an aluminum-free layer, wherein the aluminum-free layer is located on the aluminum-containing layer, wherein the aluminum-containing layer is an aluminum nitride (AlN) layer, and the aluminum-free layer is a gallium nitride (GaN) layer.
[0012] By utilizing the characteristic that the first and second isolation layers of the high electron mobility transistor device of the present invention are formed of different materials and that the first and second isolation layers simultaneously contact the gate structure, the carrier concentration (two-dimensional electron gas (2DEG) concentration) in the channel layer can be modulated, allowing the carrier concentration to gradually increase from the gate towards the drain, thereby effectively dispersing the drain electric field. Furthermore, the aforementioned characteristics can simultaneously reduce the capacitance (Cgs) between the gate and source and the capacitance (Cgd) between the gate and drain, thereby improving the switching losses of the high electron mobility transistor device. In addition, before forming the second isolation layer, the p-type doped gallium nitride layer of the high electron mobility transistor device of the present invention is first covered by the first isolation layer. Therefore, during the growth of the second isolation layer, the first isolation layer can protect the magnesium ions (Mg+) in the p-type doped gallium nitride layer from being captured and eliminated by the hydrogen gas (H2) added during the growth of the second isolation layer, thereby increasing the threshold voltage (Vth) of the high electron mobility transistor device. Attached Figure Description
[0013] Figure 1 This is a cross-sectional schematic diagram of a high electron mobility transistor device in the prior art.
[0014] Figure 2 This is a cross-sectional schematic diagram of a first embodiment of the high electron mobility transistor device of the present invention.
[0015] Figure 3 This is a cross-sectional schematic diagram of a second embodiment of the high electron mobility transistor device of the present invention.
[0016] Among them, the attached reference numerals
[0017] High electron mobility transistor devices 1, 1a, 100-channel layers 10, 110
[0018] Barrier layers 20, 120; Gate structures 30, 160
[0019] p-type doped gallium nitride (pGaN) layers 31, 161; gate metal 32, 162
[0020] Gate contact top surface 321 First isolation layer 40, 130
[0021] First contact part 41; Second isolation layers 50, 140
[0022] Second contact 51 Drain electrodes 60, 150
[0023] Regenerated layers 70, 70a; Source electrodes 90, 170
[0024] Aluminum-containing layers 71, 71a; Aluminum-free layers 72, 72a
[0025] Third isolation layer 80 Third contact part 81
[0026] First 2DEG concentration (2DEG1) Second 2DEG concentration (2DEG2)
[0027] Third 2DEG concentration (2DEG3) Source extension 91 Detailed Implementation
[0028] To better understand the technical content of this invention, preferred embodiments are described below. Please refer to the following. Figure 2 A cross-sectional schematic diagram of a first embodiment of the high electron mobility transistor device of the present invention.
[0029] like Figure 2 As shown, in the first embodiment, the high electron mobility transistor device 1 of the present invention includes a channel layer 10, a barrier layer 20, a gate structure 30, a first isolation layer 40, a second isolation layer 50, a drain 60, a regrowth layer 70, a third isolation layer 80, and a source 90. In actual implementation, the channel layer 10 is formed on a buffer layer (not shown), and the buffer layer is formed on a silicon substrate (not shown). The barrier layer 20 is disposed on the channel layer 10, and the gate structure 30 is disposed on the barrier layer 20. The gate structure 30 includes a p-type doped gallium nitride (pGaN) layer 31 and a gate metal 32. The gate metal 32 is disposed on the p-type doped gallium nitride layer 31, and the p-type doped gallium nitride layer 31 is disposed on the barrier layer 20, wherein the gate metal 32 has a gate contact top surface 321.
[0030] In this embodiment, the first isolation layer 40 is a silicon dioxide (SiO2) layer. The first isolation layer 40 is disposed on the barrier layer 20 and covers the gate structure 30, wherein the top surface 321 of the gate contact is exposed to the first isolation layer 40. In other words, as Figure 2 As shown, the p-type doped gallium nitride layer 31 on the barrier layer 20 is covered on both sides by the first isolation layer 40, and the gate metal 32 on the p-type doped gallium nitride layer 31 is also covered on both sides by the first isolation layer 40, with only the top surface of the gate metal 32 ( Figure 2 The gate contact top surface 321 is not covered by the first isolation layer 40.
[0031] In this embodiment, the second isolation layer 50 is a silicon nitride (SiN) layer. The second isolation layer 50 covers the first isolation layer 40, and a portion of the second isolation layer 50 is disposed on the barrier layer 20. The second isolation layer 50 also covers the gate contact top surface 321, thereby allowing the first isolation layer 40 and the second isolation layer 50 to simultaneously contact the gate structure 30. The regenerated layer 70 is disposed between the drain 60, the source 90, and the barrier layer 20. In another embodiment, the regenerated layer 70 is formed between the gate structure 30 and the drain 60, and between the barrier layer 20 and the third isolation layer 80. Furthermore, the drain 60 is directly formed on the barrier layer 20.
[0032] The regenerated layer 70 in this embodiment includes an aluminum-containing layer 71 and an aluminum-free layer 72. The aluminum-containing layer 71 is an aluminum nitride (AlN) layer or an aluminum gallium nitride (AlGaN) layer, and the aluminum-free layer 72 is a gallium nitride (GaN) layer. The thickness of the aluminum-free layer 72 is greater than the thickness of the aluminum-containing layer 71. According to an embodiment of the present invention, the thickness of the aluminum-containing layer 71 can be 1 nm to 2 nm, and the thickness of the aluminum-free layer 72 can be 4 nm to 8 nm. The third isolation layer 80 in this embodiment is a silicon nitride (SiN) layer. The third isolation layer 80 is disposed on the second isolation layer 50 and covers a portion of the regenerated layer 70. The drain electrode 60 is disposed on the regenerated layer 70.
[0033] Because the first isolation layer 40 is a silicon dioxide layer, and the second isolation layer 50 and the third isolation layer 80 are both silicon nitride (SiN) layers, the dielectric constant of the first isolation layer 40 is smaller than that of the second isolation layer 50 and the third isolation layer 80. This results in a higher 2DEG concentration in the channel layer 10 below the second isolation layer 50 compared to the channel layer 10 below the first isolation layer 40. Simultaneously, because the regenerated layer 70 contains aluminum, the 2DEG concentration in the channel layer 10 below the overlap between the third isolation layer 80 and the regenerated layer 70 is higher than the 2DEG concentration in the channel layer below the second isolation layer 50.
[0034] Specifically, such as Figure 2As shown, the first isolation layer 40 includes a first contact portion 41, which is disposed on the barrier layer 20. The first contact portion 41 is adjacent to the p-type doped gallium nitride layer 31 of the gate structure 30 and directly contacts the barrier layer 20. The channel layer 10 below the first contact portion 41 has a first 2DEG concentration (2DEG1). The second isolation layer 50 includes a second contact portion 51, which is adjacent to the first contact portion 41 and disposed on the barrier layer 20. The channel layer 10 below the second contact portion 51 has a second 2DEG concentration (2DEG2). The third isolation layer 80 includes a third contact portion 81, which covers a portion of the second isolation layer 50 and a portion of the regenerated layer 70. In this embodiment, the third contact portion 81 covers the second contact portion 51. The channel layer 10 below the overlap between the third contact portion 81 and the regenerated layer 70 has a third 2DEG concentration (2DEG3), wherein the second 2DEG concentration (2DEG2) is greater than the first 2DEG concentration (2DEG1), and the third 2DEG concentration (2DEG3) is greater than the second 2DEG concentration (2DEG2). This causes the concentration of 2DEG in the channel layer 10 to show a trend from low concentration to high concentration from the gate structure 30 to the drain 60, thereby modulating the concentration of 2DEG in the lower channel layer 10 located between the gate structure 30 and the drain 60. This effectively disperses the electric field of the drain 60 and reduces the conduction current, thereby improving the stability of the high electron mobility transistor device 1 of the present invention.
[0035] Furthermore, because the first isolation layer 40 is a silicon dioxide (SiO2) layer, due to the material properties of silicon dioxide (SiO2), the first isolation layer 40 located between the source extension 91 and the gate structure 30 can effectively reduce the capacitance (Cgs) between the gate structure 30 and the source 90. Similarly, the first isolation layer 40 is located between the drain 60 and the gate structure 30, thereby reducing the capacitance (Cgd) between the drain 60 and improving the switching losses of the high electron mobility transistor device 1 of the present invention. Moreover, before the formation of the second isolation layer 50, the p-type doped gallium nitride layer 31 of the high electron mobility transistor device 1 of the present invention is first covered by the first isolation layer 40. Thus, during the growth of the second isolation layer 50, the silicon dioxide (SiO2) first isolation layer 40 can protect the magnesium ions (Mg+) in the p-type doped gallium nitride layer 31 from being captured and disappeared by the hydrogen gas (H2) added during the growth of the second isolation layer 50, thereby increasing the threshold voltage (Vth) of the high electron mobility transistor device 1.
[0036] It should be noted that the materials used to form the first isolation layer 40, the second isolation layer 50, the regenerated layer 70, and the third isolation layer 80 of the present invention are not limited to the foregoing embodiments. As long as the first isolation layer 40, the second isolation layer 50, and the regenerated layer 70 are formed of different materials, and the dielectric constant of the material used to form the first isolation layer 40 is less than the dielectric constant of the material used to form the second isolation layer 50, and the dielectric constant of the material used to form the first isolation layer 40 is less than the dielectric constant of the material used to form the third isolation layer 80, the present invention is applicable.
[0037] Please refer to Figure 3 A cross-sectional schematic diagram of a second embodiment of the high electron mobility transistor device of the present invention.
[0038] like Figure 3 As shown, the difference between the high electron mobility transistor device 1a of the second embodiment and the high electron mobility transistor device 1a of the first embodiment lies in the regeneration layer 70a. The remaining structure of the high electron mobility transistor device 1a of the second embodiment is the same as that of the first embodiment, so the relevant details will not be repeated. The regeneration layer 70a of the second embodiment includes two aluminum-containing layers 71 and 71a, and two aluminum-free layers 72 and 72a, wherein the aluminum-free layer 72 is located between the aluminum-containing layers 71 and 71a, and the aluminum-containing layer 71a is located between the aluminum-free layers 72 and 72a. In this embodiment, the aluminum-containing layers 71 and 71a are aluminum nitride (AlN) layers, and the aluminum-free layers 72 and 72a are gallium nitride (GaN) layers. The thickness of the aluminum-free layers 72 and 72a is greater than the thickness of the aluminum-containing layers 71 and 71a. According to a specific embodiment of the present invention, the thickness of the aluminum-containing layers 71 and 71a is 1 nm, and the thickness of the aluminum-free layers 72 and 72a is 2 nm to 4 nm. It should be noted that the number of aluminum-containing layers 71 and 71a and the number of aluminum-free layers 72 and 72a can be varied, as long as the arrangement of the aluminum composition of the regenerated layer 70a is high aluminum content, low aluminum content (or aluminum-free), and high aluminum content (please refer to...). Figure 3 (Example shown).
[0039] It should be noted that the above embodiments are merely examples for illustrative purposes, and the scope of the claims claimed in this invention should be determined by the scope of the claims, and not limited to the above embodiments.
Claims
1. A high electron mobility transistor device, characterized in that, include: One channel layer; A barrier layer is disposed on the channel layer; A gate structure is disposed on the barrier layer. The gate structure includes a p-type doped gallium nitride layer and a gate metal. The p-type doped gallium nitride layer is disposed on the barrier layer, and the gate metal is disposed on the p-type doped gallium nitride layer. The gate metal has a gate contact top surface. A first isolation layer covers the gate structure and is disposed on the barrier layer, wherein the top surface of the gate contact is exposed to the first isolation layer; A second isolation layer covers the first isolation layer and a portion of the second isolation layer is disposed on the barrier layer, wherein the second isolation layer covers the top surface of the gate contact; One leak pole; as well as A regenerated layer is disposed between the drain and the barrier layer, wherein the first isolation layer, the second isolation layer and the regenerated layer are formed of different materials, and the dielectric constant of the material used to form the first isolation layer is less than the dielectric constant of the material used to form the second isolation layer.
2. The high electron mobility transistor device as claimed in claim 1, characterized in that, The first isolation layer includes a first contact portion located on the barrier layer, and the channel layer below the first contact portion has a first 2DEG concentration. The second isolation layer includes a second contact portion located on the barrier layer, and the channel layer below the second contact portion has a second 2DEG concentration, wherein the second 2DEG concentration is greater than the first 2DEG concentration.
3. The high electron mobility transistor device as claimed in claim 1, characterized in that, It also includes a third isolation layer, which is disposed on the second isolation layer and covers a portion of the regenerated layer, and the drain electrode is disposed on the regenerated layer.
4. The high electron mobility transistor device as claimed in claim 3, characterized in that, The dielectric constant of the material used to form the first isolation layer is less than that of the material used to form the third isolation layer.
5. The high electron mobility transistor device as claimed in claim 3, characterized in that, The third isolation layer includes a third contact portion that covers the second isolation layer and the regenerated layer. The channel layer below the overlap of the third contact portion and the regenerated layer has a third 2DEG concentration. The second isolation layer includes a second contact portion disposed on the barrier layer. The channel layer below the second contact portion has a second 2DEG concentration. The third 2DEG concentration is greater than the second 2DEG concentration.
6. The high electron mobility transistor device as claimed in claim 3, characterized in that, The third isolation layer is a silicon nitride (SiN) layer.
7. The high electron mobility transistor device as claimed in claim 1, characterized in that, The first isolation layer is a silicon dioxide (SiO2) layer, and the second isolation layer is a silicon nitride (SiN) layer.
8. The high electron mobility transistor device as claimed in claim 1, characterized in that, The regenerated layer includes an aluminum-containing layer and an aluminum-free layer, wherein the aluminum-free layer is located on the aluminum-containing layer.
9. The high electron mobility transistor device as claimed in claim 8, characterized in that, The aluminum-containing layer is an aluminum nitride (AlN) layer, and the aluminum-free layer is a gallium nitride (GaN) layer.
10. The high electron mobility transistor device as claimed in claim 8, characterized in that, The thickness of the aluminum-free layer is greater than the thickness of the aluminum-containing layer.