Semiconductor element and manufacturing method thereof
By changing the configuration of the gate contact landing region to partially overlap with the channel doped region of the transistor, the problem of gate-induced drain leakage current was solved, enabling the miniaturization of semiconductor devices and reduction of power consumption while maintaining high pixel density.
Patent Information
- Application Number
- CN202410808818.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-07
- Filing Date
- 2024-06-21
- Publication Date
- 2025-11-11
AI Technical Summary
In existing field-effect transistor devices, the leakage problem caused by gate-induced drain leakage current is difficult to solve effectively, especially in high-density displays, which increases power consumption and reduces pixel density and yield.
By changing the configuration of the gate contact landing region to at least partially overlap with the channel doped region of the transistor, the source and drain contact landing regions partially overlap with the gate contact landing region in the arrangement direction, while keeping the width of the channel doped region and the gate width unchanged.
Without increasing leakage current or affecting the alignment accuracy of the gate contact structure, the miniaturization of semiconductor devices was achieved, reducing power consumption while maintaining high pixel density.
Smart Images
Figure CN120936069A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a transistor device and a method for manufacturing the same. Background Technology
[0002] Field-effect transistors (FETs) in semiconductor integrated circuits generate high leakage currents when the source and drain are in the off state (Ioff). Especially under high drain-gate bias, the band-to-band tunneling effect between the drain and gate insulators can lead to gate-induced drain leakage (GIDL), resulting in rapid leakage of the charge information stored in the FET.
[0003] Taking the field-effect transistors (FETs) in the pixel cells of an active-matrix organic light-emitting diode (AMOLED) display as an example, when a gate-induced drain current occurs in the FET, the information must be restored within a very short refresh time; otherwise, the information already input to the pixel cell will be lost. However, with the gradual increase in display pixel density (pixel-per-inch, PPI), not only does the difficulty of controlling and operating the display increase, but the overall leakage current of the active matrix also leads to a sharp increase in the display's power consumption.
[0004] While the industry currently employs offset gate technology, moving the gate closer to the source end to reduce gate-induced drain current in field-effect transistors (FETs) by increasing the gate-drain distance or reducing the gate width, several issues arise. Increasing the gate-drain distance increases pixel cell width, reducing pixel density; conversely, reducing the gate width to be substantially smaller than the channel length may affect gate contact alignment, thus lowering pixel cell fabrication yield. Therefore, effectively miniaturizing semiconductor devices without compromising yield has become a crucial challenge in the semiconductor technology field.
[0005] Therefore, there is a need to provide an advanced semiconductor device and its manufacturing method to solve the problems faced by the existing technology. Summary of the Invention
[0006] An embodiment of the present invention discloses a semiconductor device, comprising: a substrate, a gate structure, a source region, a drain region, a gate contact structure, a source contact structure, and a drain contact structure. The gate structure, source region, and drain region are all located within the substrate. The gate contact structure rests on the gate resting region above the gate structure and is electrically in contact with the gate structure. The source contact structure rests on the source resting region above the source and is electrically in contact with the source. The drain contact structure rests on the drain resting region above the drain and is electrically in contact with the drain. At least one of the source resting region and the drain resting region at least partially overlaps with the gate resting region in the arrangement direction of the source and drain regions.
[0007] Another embodiment of the present invention discloses a method for fabricating a semiconductor device, comprising the following steps: First, providing a substrate. Next, forming a gate structure on the substrate. Then, forming a source region and a drain region in the substrate. Forming a gate contact structure, which rests on a gate resting region above the gate structure and is electrically in contact with the gate structure. Forming a source contact structure, which rests on a source resting region above the source and is electrically in contact with the source. Forming a drain contact structure, which rests on a drain resting region above the drain and is electrically in contact with the drain. At least one of the source resting region and the drain resting region overlaps at least partially with the gate resting region in the arrangement direction of the source and drain regions.
[0008] According to the above embodiments, the present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a transistor, a gate contact landing region, a source contact landing region, and a drain contact landing region, all three of which at least partially overlap with a channel doped region of the transistor. By changing the configuration of the gate contact landing region to at least partially overlap with the channel doped region of the transistor, the gate contact landing region can at least partially overlap with at least one of the source and drain contact landing regions along the source and drain arrangement direction of the transistor.
[0009] Since the width of the doped region of the device channel is not changed and the width of the gate is not shortened, the length of the transistor gate can be reduced without increasing device leakage current or affecting the alignment accuracy of the gate contact structure, which helps to miniaturize the overall size of the semiconductor device. Attached Figure Description
[0010] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings:
[0011] Figures 1A to 1D As an embodiment of the present invention, a cross-sectional schematic diagram of a series of fabrication processes for a semiconductor device is shown.
[0012] Figure 2 for Figure 1D The illustrated top view of the semiconductor device structure; and
[0013] Figure 3 This is a top view of the structure of a traditional semiconductor device.
[0014] Symbol Explanation
[0015] 100: Semiconductor components
[0016] 101: Semiconductor substrate
[0017] 101C: Channel Doped Region
[0018] 101S: Surface
[0019] 102: Spacer wall
[0020] 103: Gate Structure
[0021] 103D: Gate dielectric layer
[0022] 103E: Gate electrode layer
[0023] 103L: Gate landing region
[0024] 104: Lightly doped drain region
[0025] 105: Source Region
[0026] 105L: Source Pole Landing Zone
[0027] 106G: Metal silicide layer
[0028] 106S: Metal silicide layer
[0029] 106D: Metal silicide layer
[0030] 107: Interlayer dielectric layer
[0031] 108G: Gate contact structure
[0032] 108S: Source contact structure
[0033] 108D: Drain contact structure
[0034] 115: Drain region
[0035] 115L: Drain landing area
[0036] 110: Shallow trench isolation structure
[0037] 110T: Groove
[0038] 300: Semiconductor Components
[0039] 301C: Channel Doped Region
[0040] 303: Gate structure
[0041] 303L: Gate landing region
[0042] 305: Source Region
[0043] 308G: Gate contact structure
[0044] 315: Drain region
[0045] A1: Component Area
[0046] B: Length
[0047] CT: Width
[0048] R: Direction
[0049] H1: Distance
[0050] H2: Distance
[0051] H3: Width dimension
[0052] K: Width
[0053] Pg: Spacing
[0054] Psd: Spacing
[0055] W: Width
[0056] T1: Transistor unit
[0057] T3: Transistor Unit Detailed Implementation
[0058] This invention provides a semiconductor device and a method for manufacturing the same, which helps to miniaturize the size of semiconductor devices without increasing leakage current or affecting the alignment accuracy of the gate contact structure. To make the above embodiments and other objects, features, and advantages of this invention more apparent, several embodiments are described below in conjunction with the accompanying drawings.
[0059] However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the claims of the present invention. Those skilled in the art will be able to make equivalent modifications and variations based on the description in the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.
[0060] Please refer to Figures 1A to 1D , Figures 1A to 1DThis is a schematic cross-sectional view illustrating a series of fabrication process structures for a semiconductor element 100 according to an embodiment of the present invention. In some embodiments of the present invention, the method for fabricating the semiconductor element 100 includes the following steps: First, a semiconductor substrate 101 is provided. In some embodiments of the present invention, the semiconductor substrate 101 may be a silicon-containing substrate, such as a silicon wafer, silicon-on-insulator (SOI), or other semiconductor substrates. In some embodiments of the present invention, the semiconductor substrate 101 may also be composed of, for example, germanium (Ge), or compound semiconductor materials, such as gallium arsenide (GaAs). In this embodiment, the substrate 101 may be a silicon wafer.
[0061] Next, a shallow trench isolation structure 110 is formed in the semiconductor substrate 101 to define a device region A1 in the semiconductor substrate 101. In this embodiment, the formation of the shallow trench isolation structure 110 includes the following steps: First, a trench 110T is formed on the surface 101S of the semiconductor substrate 101 by a photoresist etching process, extending into the semiconductor substrate 101, and defining a device region A1 on the surface 101S of the semiconductor substrate 101. Then, a dielectric material is deposited on the surface 101S of the semiconductor substrate 101 by a deposition process, filling the trench 110T, and the dielectric material on the surface 101S of the semiconductor substrate 101 is removed by an etch-back or planarization process (e.g., chemical-mechanical planarization, CMP), leaving a portion of the dielectric material remaining in the trench 110T as the shallow trench isolation structure 110 (e.g., ...). Figure 1A shown).
[0062] Next, an ion implantation process is performed on the device region A1 on the surface 101S of the semiconductor substrate 101 to form a channel doped region 101C in the semiconductor substrate 101 of the device region A1. Then, a gate dielectric layer 103D is formed on the surface 101S of the semiconductor substrate 101 of the device region A1. In some embodiments of the present invention, the gate dielectric layer 103D may be a silicon oxide layer (but not limited thereto) or other suitable dielectric material layer. Using the gate dielectric layer 103D as a mask, another ion implantation process is performed on the device region A1 to form a lightly doped drain (LDD) 104 (e.g., ...) in the substrate 101 of the device region A1. Figure 1B shown).
[0063] Subsequently, a stacked gate electrode layer 103E is formed above the gate dielectric layer 103D, and spacers 102 made of silicon oxide and / or silicon nitride are formed on the sidewalls of the gate dielectric layer 103D and the gate electrode layer 103E to form a gate structure 103. The gate structure 103 is located above the channel doped region 101C, and the area of the gate structure 103 is substantially the same as the area of the channel doped region 101C. The width of the spacers 102 is substantially between 0.01 micrometers (μm) and 0.1 micrometers.
[0064] Using the gate structure 103 as a mask, a second ion implantation process is performed on the device region A1 on the surface 101S of the semiconductor substrate 101 to form a source region 105 and a drain region 115 in the semiconductor substrate 101 of the device region A1, adjacent to the gate structure 103 and electrically contacting the lightly doped drain region 104. In this embodiment, the channel doped region 101C, the gate structure 103, the lightly doped drain region 104, the source region 105, and the drain region 115 together constitute a metal-oxide-semiconductor field-effect transistor (MOSFET) unit T1. Figure 1C As shown, the source region 105 and the drain region 115 are adjacent to the two sides of the channel doped region 101C, and the channel doped region 101C (measured from the edge of the source region 105 to the edge of the drain region 115) has a width W greater than 0.5 micrometers (μm).
[0065] Subsequently, metal silicide layers 106G, 106S, and 106D are formed on the surfaces of the gate electrode layer 103E, source region 105, and drain region 115, respectively, using a metal silicide growth process. An inter-layer dielectric (ILD) 107 is then deposited on the metal-oxide-semiconductor field-effect transistor device T1. A gate contact structure 108G, a source contact structure 108S, and a drain contact structure 108D are then formed in the inter-layer dielectric layer 107, forming... Figure 1D The semiconductor element 100 is shown.
[0066] For example, in some embodiments of the present invention, the gate contact structure 108G, the source contact structure 108S, and the drain contact structure 108D can be metal plugs formed in the interlayer dielectric layer 107 using a metal damascene fabrication process. The gate contact structure 108G rests above the gate structure 103 and is electrically in contact with the gate electrode layer 103E (metal silicide layer 106G), and their contact interface together defines a gate resting region 103L. The source contact structure 108S rests above the source region 105 and is electrically in contact with the source region 105 (metal silicide layer 106S), and their contact interface together defines a source resting region 105L. The drain contact structure 108D rests above the drain region 115 and is electrically in contact with the drain region 115 (metal silicide layer 106D), and their contact interface together defines a drain resting region 115L.
[0067] In some embodiments of the present invention, the distance H1 between the source landing region 105L and the gate landing region 103L and the distance H2 between the drain landing region 115L and the gate landing region 103L may be equal or different. For example, in this embodiment, the distances between the source landing region 105L and the drain landing region 115L and the gate landing region 103L are both equal, substantially greater than or equal to 0.1 micrometers (H1=H2≥0.1 micrometers).
[0068] The area of the gate landing region 103L is substantially smaller than or equal to the area of the gate structure 103; the area of the source landing region 105L is substantially smaller than or equal to the area of the source region 105; and the area of the drain landing region 115L is substantially smaller than or equal to the area of the drain region 115. In this embodiment, the area of the gate structure 103 can be 0.3 square micrometers (μm). 2 The area size of the source region 105 and the drain region 115 can be 0.72 square micrometers, respectively.
[0069] Since the length and width H3 of the gate landing region 103L are smaller than the channel length L of the channel doped region 101C (essentially between 0.5 micrometers and 10 micrometers, preferably 1 micrometer), overlapping the gate landing region 103L with the gate structure 103 (channel doped region 101C) does not change the channel length L, nor does it shorten the width W of the gate 103 (e.g., 0.3 micrometers). Therefore, it does not increase the leakage current of the transistor cell T1, nor does it affect the alignment accuracy between the gate contact structure 108G and the gate structure 103.
[0070] Please refer to Figure 2 , Figure 2 It is based on Figure 1D A top view of the structure of the semiconductor device 100 is shown. Figure 2In this embodiment, the semiconductor element 100 includes four adjacent metal-oxide-semiconductor field-effect transistor (MOSFET) units T1, which can form an array of MOSFET units T1. In each MOSFET unit T1, the gate landing region 103L at least partially overlaps with the channel doped region 101C; the gate landing region 103L and the source landing region 105L at least partially overlap in the arrangement direction R of the source region 105 and the drain region 115; and the gate landing region 103L and the drain landing region 115L also at least partially overlap in the direction R.
[0071] The length dimension of each semiconductor element 100 in the vertical direction R can include the sum of the width W of the channel doped region 101C, the redundant length B protruding from both sides of the channel doped region 101C (essentially between 0.03 μm and 0.16 μm), and the spacing Pg between adjacent gate structures 103 (essentially between 0.06 μm and 0.21 μm) (W + 2B + 2Pg). The length dimension of the transistor unit T1 in the parallel direction R can be the sum of the length L of the channel doped region 101C, the width S of the source region 105, the width D of the drain region 115, and the spacing Psd between adjacent source and drain regions 105 (essentially between 0.12 and 0.21 μm) (L + S + D + Psd).
[0072] Compared to the interlayer interconnect structure of a traditional semiconductor device 300 (please refer to...) Figure 3 , Figure 3 This is a top view illustrating the structure of a conventional semiconductor device 300. Since the gate contact structure 308G of the transistor unit T3 of the conventional semiconductor device 300 is disposed outside the channel doped region 301C (electrically in contact with the gate landing region 303L of the gate structure 303), the length dimension of the gate structure 303 in the vertical direction R of the transistor unit T3 must include, in addition to the width W of the channel doped region 301C, the redundant length B protruding from both sides of the channel doped region 301C, and the spacing Pg between two adjacent gate structures 303, the width K of the gate structure 303 extending outward to accommodate the gate landing region 303L, and the width of the overlap between the gate structure 303 and the gate landing region 303L (i.e., the width CT of the gate landing region 303L).
[0073] Assuming that the widths of the channel doped regions 101C and 301C in transistor units T1 and T3 are equal (both W); the spacing between adjacent gate structures 103 and 303 is equal (both Pg); and the redundant lengths of the gate structure 103 protruding from both sides of the channel doped regions 103C and 301C are equal (both B), then the length of transistor unit T3 in the parallel direction R must be expanded to W + 2B + Pg + CT + K. The lengths of metal-oxide-semiconductor field-effect transistor units T3 and T1 in the vertical direction R include the sum of the length L of the channel doped region 301C, the width S of the source region 305, the width D of the drain region 315, and the spacing Psd between adjacent source and drain regions 305 (L + S + D + Psd).
[0074] The area size (W+2B+Pg+CT+K)×(L+S+D+Psd) of the metal-oxide-semiconductor field-effect transistor unit T3 is still much larger than the area size (W+2B+Pg)×(L+S+D+Psd) of the transistor unit T1. Therefore, the semiconductor device 100 can significantly reduce the area size of the metal-oxide-semiconductor field-effect transistor unit T1 by changing the configuration of the gate contact landing region 103L, thereby miniaturizing the area size of the semiconductor device 100.
[0075] It is also worth noting that, although Figure 1D The semiconductor element 100 shown in the figure contains only one metal-oxide-semiconductor field-effect transistor unit T1, but Figure 1D The invention is for illustrative purposes only, and the structure of the semiconductor element 100 is not limited thereto. In other embodiments of the invention, the semiconductor element 100 includes a plurality of transistor units (not shown) that are the same as or different from the metal-oxide-semiconductor field-effect transistor unit T1.
[0076] According to the above embodiments, the present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a transistor, a gate contact landing region, a source contact landing region, and a drain contact landing region, all three of which at least partially overlap with a channel doped region of the transistor. By changing the configuration of the gate contact landing region to at least partially overlap with the channel doped region of the transistor, the gate contact landing region can at least partially overlap with at least one of the source and drain contact landing regions along the source and drain arrangement direction of the transistor.
[0077] Since the width of the doped region of the device channel is not changed and the width of the gate is not shortened, the length of the transistor gate can be reduced without increasing device leakage current or affecting the alignment accuracy of the gate contact structure, which helps to miniaturize the overall size of the semiconductor device.
[0078] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A semiconductor element, comprising: Substrate; The gate structure is located on the substrate; The source region is located within the substrate. The drain region is located within the substrate. A gate contact structure, which rests on the gate landing area above the gate structure and is in electrical contact with the gate structure; A source contact structure, which rests on the source landing region above the source and is in electrical contact with the source; and A drain contact structure is placed in the drain landing area above the drain and makes electrical contact with the drain. In this configuration, at least one of the source landing region and the drain landing region overlaps at least partially with the gate landing region in the arrangement direction of the source region and the drain region.
2. The semiconductor device of claim 1, wherein the substrate includes a channel doped region, the gate structure is located above the channel doped region, and the source region and the drain region are respectively adjacent to both sides of the channel doped region.
3. The semiconductor device of claim 1, wherein the gate landing region has an area smaller than that of the channel doped region, and the gate landing region at least partially overlaps with the channel doped region.
4. The semiconductor device of claim 1, wherein the channel doped region has a width greater than 0.5 micrometers (μm).
5. The semiconductor device of claim 1, wherein the gate structure includes a gate electrode having a width substantially greater than 0.3 micrometers.
6. The semiconductor device of claim 1, wherein one of the source landing region and the drain region has a distance substantially greater than 0.1 micrometers from the gate landing region.
7. The semiconductor device of claim 1, further comprising a dielectric layer covering the gate structure, the source region, and the drain region; each of the gate landing region, the drain landing region, and the drain landing region passing through an opening in the dielectric layer for exposing a portion of the gate structure, a portion of the source region, and a portion of the drain region to the outside.
8. A method for manufacturing a semiconductor device, comprising: Provide base materials; A gate structure is formed on the substrate; Source and drain regions are formed in the substrate; A gate contact structure is formed, and a gate landing area is placed on the gate structure and makes electrical contact with the gate structure. A source contact structure is formed, which is deposited in the source landing region above the source region and makes electrical contact with the source; and A drain contact structure is formed, which falls on the drain landing area above the drain region and makes electrical contact with the drain. in, At least one of the source landing region and the drain landing region overlaps at least partially with the gate landing region in the arrangement direction of the source region and the drain region.
9. The method for fabricating a semiconductor device as claimed in claim 8 further includes forming a channel doped region in the substrate, such that the gate structure is located above the channel doped region; and such that the source region and the drain region are respectively adjacent to both sides of the channel doped region.
10. The method for fabricating a semiconductor device as claimed in claim 8, wherein the formation of the gate contact structure, the source contact structure, and the drain contact structure comprises: A dielectric layer is formed, covering the gate structure, the source region, and the drain region; as well as The dielectric layer is etched to form a first opening that exposes a portion of the gate structure to the outside, thereby defining the gate landing area; A second opening is formed to expose a portion of the source region to the outside, thereby defining the source landing region; And a third opening is formed to expose a portion of the drain region to the outside, thereby defining the drain landing region.