Method for contacting each gate of spin qubit gate array

Abstract

An array of gate structures (3, 4) suitable for the production of spin qubit quantum dot devices is synthesized on a flat surface (1). The gate structure includes alternately arranged first and second types of structures. Electrical connections to the gate structures of the first and second types are generated in a sequence of separate processing steps. The connection to the first gate type comprises the formation of a first conductive line (17) routed substantially parallel to the flat surface and connected to the gate structure of the first type by a first via connection (18). A conformal dielectric layer (25) is formed on the first conductive line (17), i.e. On a top surface and sidewalls of the first conductive line, prior to generating a similar connection to the second type of gate structure. The conformal layer (25) is configured such that it forms protective spacers on the sidewalls of the first conductive lines (17) during processing of the second conductive lines (39), avoiding short circuits between the conductive lines.

Description

Technical Field

[0001] The present invention relates to semiconductor spin qubit quantum dot devices comprising an array of gate structures, and more particularly to a method for generating conductive contacts with said gate structures. Background Technology

[0002] In recent years, quantum dot devices on semiconductor materials have been extensively explored as one of the main approaches to realizing feasible quantum computing chips. Various architectures have been explored, all sharing the common feature of closely spaced gates configured such that quantum dots are confined beneath one or more of these gates. The gates can be, for example, metal gates formed on a thin layer of silicon oxide on a silicon substrate. Through the close spacing of the gates and by applying appropriate voltages to the gates, it is possible to generate quantum dots—small, isolated islands of electrons or holes—below each gate and manipulate qubits associated with those quantum dots. A qubit can be defined, for example, by the spin state of an individual electron of the quantum dot. Magnetic resonance is used to control the spin state, and readout devices (e.g., single-electron transistors) can be integrated near one or more quantum dots. Quantum dot devices operate at temperatures in the Kelvin or sub-Kelvin range (i.e., about 1 K or lower) to achieve sufficient qubit coherence time and qubit-based computation.

[0003] Contacting gates via conductive structures is challenging due to the small space between adjacent gates in a device. Conventional damascene methods used to fabricate conductive vias and lines are susceptible to overlay errors of the same order of magnitude as the gate pitch, leading to unacceptable misalignment errors and the risk of short circuits. Summary of the Invention

[0004] This invention relates to methods and apparatus as disclosed in the appended claims. Throughout the specification, the term "conductive" means "electrically conductive." An array of gate structures is fabricated on a flat surface, the array being adapted for fabricating spin qubit quantum dot devices. The gate structures comprise alternating arrangements of first and second types of structures, such as injection gates and barrier gates. According to the invention, electrical connections to the first and second types of gate structures are generated in a separate sequence of processing steps. The connection to the first gate type includes the formation of a first conductor, which is substantially parallel to the wiring on the flat surface and is connected to the first type of gate structure via a first path connection. Prior to fabricating a similar connection to the second type of gate structure, a conformal dielectric layer is formed on the first conductor, i.e., on the top surface and sidewalls of the first conductor. The conformal layer is configured, for example, in terms of its material and thickness, such that it forms protective spacers on the sidewalls of the first conductor during the fabrication of the second conductor, thereby preventing short circuits between the conductors.

[0005] This invention particularly relates to a method for generating electrical connections to a plurality of adjacent gate structures in a spin qubit gate array, the method comprising the following steps:

[0006] - On the surface of a planar substrate, the gate structure is generated by forming a hard mask layer on the gate layer, patterning the hard mask layer, and transferring the patterned hard mask layer to the gate layer, thereby obtaining adjacent gate structures, each gate structure having a hard mask portion, wherein the gate structure comprises first and second types of structures alternately arranged in the longitudinal direction.

[0007] - Generate a first path connection to a first type of gate structure and mutually parallel first wires respectively connected to the first path connection, the first wires being substantially parallel to the wiring on the planar substrate surface.

[0008] Subsequently, a conformal dielectric layer is formed on the sidewalls and top surface of the first conductor, which has sidewalls and a top surface. The term "conformal layer" is defined as a layer that conforms to the morphology of the surface on which it is deposited. Implicitly, this means that the thickness of the layer is suitable for this purpose, i.e., the layer is thin compared to the dimensions defining the features of the topology.

[0009] Subsequently, a second via connection to the second type of gate structure and mutually parallel second wires connected to the second via connection are generated, the second wires being substantially parallel to the planar substrate surface wiring.

[0010] The conformal layer forms spacers on the sidewalls of the first conductor, and the spacers remain on the sidewalls during the formation of the second conductor, so that the conformal layer can isolate the first conductor from the second conductor, regardless of possible alignment errors between the first and second types of gate structures of one party and the corresponding first and second conductors of the other party.

[0011] According to one embodiment:

[0012] - The first path connection and the first wire are generated through the following steps:

[0013] The gate structure and hard mask portion are embedded in the first dielectric layer.

[0014] Planarize the first dielectric layer.

[0015] A first trench is formed in the first dielectric layer, the first trench overlapping with each gate structure of the first type, such that at least a portion of the hard mask portion of each gate structure of the first type is exposed at the bottom of the first trench.

[0016] At least a portion of the material exposed at the bottom of the first trench of the corresponding hard mask portion is removed, thereby creating a first passage opening that exposes the first type of gate structure.

[0017] The first path opening and the first trench are filled with a conductive material to obtain the first path connection.

[0018] The conductive material and the first dielectric layer are planarized to obtain a first wire embedded in the planarized first dielectric layer.

[0019] - Subsequently, the first dielectric layer is recessed until the first conductor is located at the top of the recessed surface of the first dielectric layer, the first conductor having sidewalls and a top surface.

[0020] - A conformal dielectric layer is formed on the recessed surface of the first conductor, as well as on the sidewalls and top surface.

[0021] - Subsequently, a second via connection to the second type of gate structure and mutually parallel second wires connected to the second via connection are generated, the second wires being substantially parallel to the planar substrate surface wiring, wherein the second via connection and the second wires are generated through the following steps:

[0022] The first conductor, including the conformal layer, is embedded in the second dielectric layer.

[0023] Planarize the second dielectric layer.

[0024] By using an etching formulation that selectively removes material from the second dielectric layer relative to the conformal layer, a second trench is formed in the second dielectric layer, and the second trench overlaps with a second type of gate structure.

[0025] Material of the conformal layer is removed from the bottom of the second trench while retaining the conformal layer on the sidewalls of the first conductor, thereby forming a deepened second trench, wherein at least a portion of the hard mask portion of the second type of gate structure is exposed at the bottom of the deepened second trench. At least a portion of the material of the corresponding hard mask portion exposed at the bottom of the deepened second trench is removed, thereby creating a second via opening exposing the second type of gate structure.

[0026] The second pathway connection is achieved by filling the second pathway opening and the deepened second trench with a conductive material.

[0027] The conductive material and the second dielectric layer are planarized to obtain a second wire embedded in the planarized second dielectric layer.

[0028] According to one embodiment, the gate layer is a single-layer gate material, such that the mask portion is formed directly on a corresponding gate structure uniformly formed from the gate material.

[0029] According to one embodiment, the gate layer includes a bottom layer formed of a first gate material and a top layer formed directly on the bottom layer of a second gate material, such that a mask portion is formed directly on a corresponding gate structure formed by stacking a bottom gate portion of the first gate material and a top gate portion of the second gate material on top of the first gate portion, and:

[0030] - The formation of the first passage opening includes removing at least a portion of the top gate portion of the first type of gate structure relative to the bottom gate portion.

[0031] - The formation of the second passage opening includes removing at least a portion of the hard mask portion on the second type of gate structure without removing the top gate portion of the second type of gate structure.

[0032] According to one embodiment, the lateral dimension of the gate structure and the spacing between adjacent gate structures are between 5 and 50 nm, and the thickness of the conformal layer is between 1 and 5 nm.

[0033] According to one embodiment, the material of the hard mask portion is silicon nitride, and the conformal layer includes at least a top layer formed of silicon carbonate.

[0034] According to one embodiment, the second gate material is a metal.

[0035] This invention also relates to a spin qubit quantum dot device, comprising:

[0036] - An array of alternating first and second type gate structures arranged longitudinally on a flat surface.

[0037] - A first path connection to a gate structure of the first type, the first path connection being connected to a corresponding first wire substantially parallel to the wiring on the flat surface.

[0038] - A second via connection to a second type of gate structure, the second via connection being connected to respective second conductors extending substantially parallel to the flat surface.

[0039] The first and second conductors are embedded in a dielectric material layer, the layer including spacers on the sidewalls of the first conductor.

[0040] According to an embodiment of the device, the lateral dimension of the gate structure and the spacing between adjacent gate structures are between 5 and 50 nm, and the thickness of the spacer is between 1 and 5 nm. Attached Figure Description

[0041] Figures 1 to 18 Key steps in a method according to an embodiment of the present invention are shown, illustrating the effects of misalignment and ways to mitigate them.

[0042] Figures 19 to 29 The theoretical case where misalignment does not occur is shown.

[0043] Figures 30 to 37 An embodiment including a gate structure formed of two different materials is shown. Detailed Implementation

[0044] Figure 1 This is a schematic diagram of an array of structures suitable for producing quantum dot devices. The array is formed on surface 1 of a substrate, details of which are not shown, but according to known practice, such as a silicon substrate including a silicon oxide layer on its surface, the array structure is formed directly on the silicon oxide layer, with the aim of generating quantum dots at the interface between silicon and silicon oxide. The array includes a larger structure 2 at the outer ends, which can, for example, serve as source and drain electrodes in the final device, and alternating rows of first and second type gate structures 3 and 4. These latter gate structures function in the final device to enable read and write operations on the quantum dots and to separate the quantum dots from each other. These corresponding gate structures are known to be referred to as implant gates and barrier gates, and this terminology will be used in this detailed description. Thus, in the presented example, the first type of gate structure is the implant gate 3, and the second type of gate structure is the barrier gate 4. However, within the broader scope of the appended claims, the meaning of "first and second gate structures" may be reversed, or the first and second types may refer to other gate types besides barrier gates and implant gates.

[0045] Figure 1 The exemplary configuration shown includes two injection gates 3 separated by a barrier gate 4 between the two injection gates, and another barrier gate 4 separating the injection gates 3 from the laterally placed source and drain electrodes 2. This is merely an example of a configuration to which the invention can be applied, and the number of gate structures can be greater than shown.

[0046] Apart from Figure 1 In addition to those shown, the final quantum dot device may also include additional gate structures or electrodes, such as confinement structures formed of the same material as the gate structures and placed near the gate array. This additional structure is not shown in the figures; the focus is on the actual array itself. The materials for gates 3 and 4, as well as source and drain structures 2, can be any suitable conductive material, such as copper or ruthenium. The invention is not limited to the specific dimensions of the various structures, but rather finds its primary use in relation to very small gate features. For example, relative to… Figure 1From the perspective of the included axis system, the width of the implanted gate 3 in the X direction can be on the order of 10-15 nm, the width of the barrier gate 4 is slightly smaller, for example, 5-10 nm, and the spacing between adjacent gates is on the order of 5-10 nm. In the orthogonal Y direction, the dimensions may be slightly larger, so that the gate has a rectangular shape as shown in the figure. However, as is known in the art, other gate shapes are also possible (square, circular, etc.).

[0047] from Figure 1 As can be seen, the injection and barrier gates 3 and 4, as well as the source and drain electrodes 2, are each covered by corresponding hard mask portions 3', 4', and 2', which can be formed of silicon nitride (Si3N4, hereinafter abbreviated as "SiN"). After forming the gate structures 3 and 4 and the electrodes 2 by photolithography and etching, the hard mask portions are retained. This includes depositing a hard mask layer on the gate material layer, patterning the hard mask layer, and transferring the patterned hard mask to the gate layer by etching. The methods for patterning the hard mask and transferring the patterned hard mask features to the gate layer at the aforementioned small feature size are known in themselves, and the present invention can be applied in conjunction with any such known methods. In other words, the present invention can be applied to materials obtained by any method known in the art, such as... Figure 1 The configuration shown. The thickness of gates 3, 4, electrode 2, and hard mask portions 2', 3', 4' can be on the order of a few nanometers, for example, between 10 and 50 nm.

[0048] refer to Figure 2 as well as Figure 3 The cross-sectional view along line AA shown shows that the array is first covered by a dielectric material layer 5, which is then planarized to a flat horizontal plane extending above and at a distance "h" from the top of the hard mask portions 2', 3', and 4', where the distance h is, for example, between 10 and 50 nm. Alternatively, layer 5 is planarized downwards to the hard mask portions 2'-4', which serve as planarization stop surfaces, and another dielectric layer of the same material and thickness h is deposited on the planarized surface. The material of layer 5 and the material of the additional deposited layer of thickness h (if applicable) can be any dielectric material suitable for interlayer dielectric (ILD) materials in back-to-end (BEOL) processing, such as silicon oxide. Therefore, layer 5 shown in the figures is an embodiment of the "first dielectric layer" mentioned in the following method steps set forth in the appended claims:

[0049] A gate structure (3, 4) and a hard mask portion (3', 4') are embedded in the first dielectric layer (5).

[0050] 4'),

[0051] Planarize the first dielectric layer (5),

[0052] Based on the above description, it is clear that the "first dielectric layer" can be a uniform layer formed by a single deposition and then planarized, as well as a layer comprising a first layer planarized to the level of the hard mask portions 3', 4' and a second planarized layer formed thereon. Furthermore, the step of planarizing this layer results in the planarized surface being spaced apart from the upper surface of the hard mask portions 3', 4' by a distance "h".

[0053] The planarization steps mentioned in this specification may include a grinding step for thinning the layer, as well as more refined planarization techniques applied according to known parameters and formulations, such as chemical mechanical polishing (CMP).

[0054] refer to Figure 4 This illustrates the deposition and patterning of a hard mask layer 10 on a planarized ILD surface 6 using standard photolithography and etching techniques. The hard mask 10 can be formed of SiN or any other suitable material. The pattern includes two trenches 11, which are positioned above the implanted gate 3 as shown in the cross-sectional views taken by two orthogonal planes AA and BB along the X and Y directions, respectively. Figure 5a and 5b As shown. The width of trench 11 in the X direction is slightly smaller than the width of implanted gate 3. The latter is preferred, but trench 11 may have the same width as implanted gate 3 or even a slightly larger width, as long as the method steps described below can be implemented.

[0055] In the Y direction, the trench has a closed end face 12 aligned with the side 13 of the implanted gate 3. In the X direction, the trench is aligned with the implanted gate. However, it can be seen that the alignment of the trench width relative to the implanted gate in the X direction is not perfect, and a misalignment of a few nanometers occurs. This misalignment is a result of overlay errors during the photolithography step used to generate the patterned hard mask 10. This overlay error may be unavoidable, and therefore, misalignment between 0 and approximately 5 nm must be considered. In other words, the center line of the trench 11 can be perfectly aligned with the center line of the implanted gate 3, or, when misalignment is present, the center lines can be offset relative to each other. The present invention is configured to correctly contact the implanted and barrier gates 3, 4, as shown, even when a significant measurable misalignment occurs. The following paragraphs will describe how this is done.

[0056] refer to Figure 6 And 7, the trench pattern of the hard mask 10 is transferred to the ILD layer 5 by anisotropic etching, that is, trenches 14 are formed in the ILD layer 5. The hard mask portion 3' is partially exposed at the bottom of these trenches 14. After the hard mask 10 is stripped, the material of the hard mask portion 3' is anisotropically removed, thereby creating a via opening 15 above the implanted gate 3, as again along the... Figure 7a and7b The cross-sectional view is shown by planes oriented in the X and Y directions respectively.

[0057] like Figure 8 As shown, the trenches 14 and via openings 15 are then filled with a conductive material 16, preferably a metal. As is known in the art, a seed layer and / or a barrier layer (not shown) may be deposited before metal deposition. Figure 9a and 9b As shown, metal 16 is planarized to form metal lines 17 that are substantially parallel to the wiring on the substrate surface 1 and connected to the injection gate 3 via via 18.

[0058] refer to Figure 10 Then, the material is etched back relative to the conductor 17 to create a recess in the ILD material of layer 5 until the conductor extends upward from the recessed surface 19. The recessed etch-back process stops at the upper surface of the hard mask portions 2', 3', and 4'.

[0059] Then, as Figure 11 As shown, a conformal dielectric layer 25 is deposited. The term "conformal" as used herein is defined as a layer that conforms to the morphology of the surface on which it is deposited. Implicitly, this means that the thickness of the layer is suitable for this purpose, i.e., the layer is thin compared to the dimensions defining the features of the topology, in this case, the width and height of the conductor 17. Therefore, the conformal layer forms pads on the sidewalls and top surface of the conductor 17 and on the recessed ILD surface 19. In the case of the aforementioned gate dimensions, the thickness of the conformal layer 25 is, for example, between 1 and 5 nanometers. The material of the conformal layer 25 is selected according to its function, as described below, and may be, for example, silicon oxide (hereinafter referred to as SiCO) or silicon oxynitride (hereinafter referred to as SiOCN). The conformal layer 25 may also comprise multiple sublayers. For example, layer 25 may be a stack of SiN layers with SiCO layers thereon, or a stack of SiON (silicon oxynitride) layers with SiOCN layers thereon. The deposition of these types of layers 25 can be accomplished using known techniques, such as those applied to fabrication processes that require similar conformal layer deposition on nanoscale features, such as self-aligned dual or multiple patterning methods.

[0060] Following the deposition of conformal layer 25, another ILD material 26 is deposited, and as... Figure 12 Planarize the material as shown, and then as... Figure 13As shown, another patterned hard mask 27 is formed on the planarized surface. This pattern again includes a trench shape 28, which is now aligned with the barrier gate 4. As shown, the width of the trench 28 can be slightly larger than the width of the corresponding barrier gate 4, but the trench 28 can have the same or smaller width as the barrier gate 4. Again, as indicated by the fact that the centerline of the trench 28 is offset by a few nanometers relative to the centerline of the barrier gate 4, a certain degree of misalignment occurs in the X direction.

[0061] refer to Figure 14 The hard mask 27 is then transferred to the underlying ILD layer 26, specifically by anisotropic etching at each trench location to form trenches 29 in the ILD material. Due to misalignment, the trenches 28 in the hard mask 27 partially overlap with the conformal layer 25 formed on the sidewalls of the conductor 17. The etching process for removing the ILD material is selective relative to the conformal layer 25, such that the latter is essentially not removed by the etching process.

[0062] In the case of misaligned conductive lines 17, this selectivity has the effect of self-alignment of the conformal layer 25 formed on the sidewalls of the misaligned lines 17: on the right-hand side of the trenches 29 formed in the ILD layer 26, these trenches 29 are effectively aligned with the conformal layer, rather than with the trenches 28 defined in the hard mask 27. This self-alignment function will ensure that no short circuits occur between adjacent conductors in the final device, as further described herein.

[0063] Even if the material of the conformal layer 25 is not removed during the etching of the ILD material 26, the material of the conformal layer 25 needs to be removed at the bottom of the trench 29, while still retaining the conformal layer 25 on the sidewalls of the conductor 17. Therefore, the removal of the conformal layer 25 from the bottom of the trench 29 is accomplished by a specific etching formulation configured to remove material only from the horizontal surfaces and not from the vertical surfaces. These types of plasma etching formulations are well known in the art and are used in the aforementioned dual or multiple patterning processes for generating side spacers. The application of this etching formulation leads to… Figure 15 As shown: a trench 29' is formed on the corresponding barrier gate 4, and a hard mask portion 4' is exposed at the bottom of the trench 29'. The trench 29' is deepened relative to the trench 29, and is therefore referred to as a "deepened trench" in the appended claims.

[0064] The hard mask portion 4' is then removed by selective etching relative to the material of the conformal layer 25. When the hard mask portion 4' is formed of SiN, this means that the material of the conformal layer 25 can be, for example, SiCO, or the conformal layer can be a stack of SiN and SiCO.

[0065] The removal of the hard mask portion 4' results in the formation of the passage opening 35, such as Figure 16a and 16b As shown. Then, the through-hole opening 35 and the groove 29' are filled with metal 36. Figure 17 ),like Figure 18 As shown, the surface is planarized to create via connections 38 and wires 39 connected to the barrier gate 4. Planarization also removes the conformal layer 25 on top of the first wire 17, resulting in a planarized dielectric surface in which the wires are embedded, including the first wire 17 contacting the injection gate 3 and the second wire 39 contacting the barrier gate 4. These lines are isolated from each other by the ILD material of layer 5 and the material of the conformal layer 25.

[0066] As can be clearly seen from the preceding description, without the presence of conformal layer 25, in Figure 18 There will be a high risk of short circuits between adjacent conductors at locations A and B. In other words, conformal layer 25 ensures that conductors 17 and 39 are isolated from each other at these locations, even though the corresponding trench-shaped hard masks 10 and 27 are misaligned. This explains the function of conformal layer 25. To achieve this result, the material of conformal layer 25 needs to be selected such that the ILD material of layers 5 and 26, as well as the material of hard mask portions 3' and 4', can be selectively removed relative to that material.

[0067] Figures 19 to 29 The same sequence is shown, but now trench masks 10 and 27 are perfectly aligned with the widths of the injection gate 3 and the barrier gate 4, respectively. Figure 29 As can be seen in the image, at this point, any pair of adjacent conductors 17 and 39 are isolated from each other by the materials of ILD material 26 and conformal layer 25. This also occurs if there is a very small degree of misalignment. In other words, when the misalignment error is zero or small, the self-alignment function of conformal layer 25 is not effectively applied. However, once the misalignment exceeds a given value, this self-alignment function begins to take effect, such as... Figure 1-18 As shown, this avoids the eventual short circuit between adjacent lines.

[0068] The quantum dot device produced according to the present invention includes first and second type gate structures 3, 4, having first and second path connections 18, 38 and first and second wires 17, 39 connected to the respective first and second type gate structures. The first and second wires are embedded in the dielectric layer 26' (e.g., ...). Figure 18 and 29The device can be identified by the fact shown in the diagram, where the layer includes spacers on the sidewall of the first conductor 17. The spacers are the portion of the conformal layer 25 retained on the sidewall of the first conductor 17. In the finished device, the spacers are defined as a dielectric material layer distinct from the remaining portion of the dielectric layer 26' embedded in the first and second conductors. The "remaining portion" is... Figure 12 and 25 The material of layer 26 applied in the steps shown.

[0069] Figures 30 to 37 Another embodiment is shown. For example... Figure 30 As shown, the initial structure now comprises two metal sections: the injection gate 3 includes a bottom 3a and a top 3b, while the barrier gate 4 includes a bottom 4a and a top 4b. The bottom and top are formed of different metals, such as W and Ru. In a specific order, as... Figure 31 As shown, the first trench 14 is formed above the barrier gate 3, but these first trenches can alternatively be formed above the injection gate, as in the previous embodiments. As stated above, theoretically the trenches are perfectly aligned with the barrier gate 3, but a certain degree of misalignment is possible.

[0070] like Figure 32 As shown, the hard mask portion 4' and the top gate portion 4b of the barrier gate are removed at the bottom of the trench 14 to create a via opening 15 facing the remaining bottom barrier gate portion 4a. Figure 33 As shown, this is followed by metal filling and recessing of the ILD material, resulting in the first conductor 17 being located on top of the recessed ILD surface 19 and connected to the barrier gate via via connection 18. Figure 34 As shown, a conformal layer 25 was deposited, followed by ( Figure 35 Another ILD layer is formed above the implanted gate 3, and a trench 29' is formed therein, and aligned with it as shown, keeping in mind that a certain degree of misalignment is possible. (Reference) Figure 36 At the bottom of trench 29', the hard mask portion 3' is anisotropically removed, and a second metal fill is used to generate wires 39 and via connections 38 to the top 3b of the injected gate. The bimetallic gate structure enables the generation of a height difference between the two types of gate contacts, which is beneficial in increasing the distance between adjacent gate contacts. This is advantageous because it reduces the likelihood of electrical short circuits occurring between gate contacts.

[0071] Although the invention has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration are intended to be illustrative or exemplary, and not restrictive. By studying the drawings, this disclosure, and the appended claims, those skilled in the art can understand and practice other variations of the disclosed embodiments in the practice of the claimed invention. In the claims, the word "a" does not exclude other elements or steps, and the indefinite article "a" or "a" does not exclude a plural. The mere fact that certain measures are stated in mutually different dependent claims does not imply that combinations of these measures cannot be advantageously used. Any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A method for generating electrical connections to a plurality of adjacent gate structures (3, 4) of a spin qubit gate array, the method comprising the steps of: - On the surface of a planar substrate (1), the gate structure is generated by forming a hard mask layer on the gate layer, patterning the hard mask layer, and transferring the patterned hard mask layer onto the gate layer, thereby obtaining the adjacent gate structures (3, 4), each gate structure having a hard mask portion (3', 4'), wherein the gate structure comprises alternating structures of first and second types in the longitudinal direction. - Generate a first path connection (18) connected to a first type of gate structure (3) and mutually parallel first wires (17) respectively connected to the first path connection, the first wires being substantially parallel to the wiring on the flat substrate surface (1). - Subsequently, a conformal dielectric layer (25) is formed on the sidewalls and top surface of the first conductor (17). The first conductor (17) has sidewalls and a top surface. - Subsequently, a second path connection (38) is generated connecting to the second type of gate structure (4, 3), and mutually parallel second wires (39) are respectively connected to the second path connection, the second wires (39) being substantially parallel to the wiring on the flat substrate surface (1). The conformal layer (25) forms a spacer on the sidewall of the first conductor (17), and the spacer is retained on the sidewall during the formation of the second conductor (39).

2. The method according to claim 1, characterized in that: - The first path connection (18) and the first wire (17) are generated through the following steps: The gate structures (3, 4) and hard mask portions (3', 4') are embedded in the first dielectric layer (5). Planarize the first dielectric layer (5), A first trench (14) is formed in the first dielectric layer, the first trench overlapping the first type of gate structure (3, 4) respectively, such that at least a portion of the hard mask portion (3', 4') on the first type of gate structure is exposed at the bottom of the first trench (14). At least a portion of the material of the corresponding hard mask portions (3', 4') exposed at the bottom of the first trench is removed to create a first via opening (15) exposing the gate structure (3, 4) of the first type. The first passage opening (15) and the first trench (14) are filled with a conductive material (16) to obtain the first passage connection (18). The conductive material (16) and the first dielectric layer (5) are planarized to obtain the first wire (17) embedded in the planarized first dielectric layer (5). - Subsequently, the first dielectric layer (5) is recessed until the first conductor (17) is located on top of the recessed surface (19) of the first dielectric layer (5), the first conductor (17) having sidewalls and a top surface. - The conformal dielectric layer (25) is formed on the recessed surface (19) and on the sidewalls and top surface of the first conductor (17). - Subsequently, a second path connection (38) is generated to connect to the gate structure (4, 3) of the second type, and second parallel wires (39) are generated to connect to the second path connection respectively, the second wires (39) being substantially parallel to the wiring on the flat substrate surface (1), wherein the second path connection and the second wires are generated by the following steps: The first conductor (17), including the conformal layer (25), is embedded in the second dielectric layer (26). Planarize the second dielectric layer (26), By using an etching formulation that is selective for the material of the conformal layer (25) to remove the material of the second dielectric layer (26), a second trench (29) is formed in the second dielectric layer, the second trench being respectively connected to the second type of gate structure (4, 3) Overlap, Remove the material of the conformal layer (25) from the bottom of the second trench (29). Meanwhile, the conformal layer on the sidewall of the first conductor (17) is retained, thereby forming a deepened second trench (29'), wherein at least a portion of the hard mask portion (4', 3') on the second type of gate structure is exposed at the bottom of the deepened second trench (29'). At least a portion of the material of the corresponding hard mask portions (4', 3') exposed at the bottom of the deepened second trench is removed to create a second via opening (35) that exposes the gate structure (4, 3) of the second type. The second passage opening (35) and the deepened second trench (29') are filled with a conductive material (36) to obtain the second passage connection (38). The conductive material and the second dielectric layer (26) are planarized to obtain a second conductor (39) embedded in the planarized second dielectric layer (26).

3. The method according to claim 1 or 2, characterized in that, The gate layer is a single-layer gate material, such that the mask portions (3', 4') are directly formed on the corresponding gate structures (3, 4) uniformly formed by the gate material.

4. The method according to claim 1 or 2, characterized in that, The gate layer includes a bottom layer formed of a first gate material and a top layer formed of a second gate material directly on the bottom layer, such that the mask portions (3', 4') are formed directly on the respective gate structures, the respective gate structures being formed by a stack of a bottom gate portion (3a, 4a) of the first gate material and a top gate portion (3b, 4b) of the second gate material on top of the first gate portion, and wherein: - The formation of the first passage opening (15) includes removing at least a portion of the top gate portion (3b, 4b) of the first type of gate structure relative to the bottom gate portion (3a, 4a). - The formation of the second passage opening (35) includes removing at least a portion of the hard mask portion (4', 3') on the second type of gate structure without removing the top gate portion (4b, 3b) of the second type of gate structure.

5. The method according to any one of the preceding claims, characterized in that, The lateral dimensions of the gate structures (3, 4) and the spacing between adjacent gate structures are between 5 and 50 nm, and the thickness of the conformal layer (25) is between 1 and 5 nm.

6. The method according to any one of the preceding claims, characterized in that, The material of the hard mask portions (3', 4') is silicon nitride, and the conformal layer (25) therein includes at least a top layer formed of silicon carbonate.

7. The method according to any one of claims 4 to 6, characterized in that, The second gate material is a metal.

8. A spin qubit quantum dot device, comprising: - An array of alternating gate structures (3, 4) of the first and second types arranged longitudinally on a flat plane (1), -A first path connection (18) to a first type of gate structure (3), the first path connection being connected to a corresponding first wire (17) that is substantially parallel to the wiring of the flat surface (1), - A second via connection (38) to the second type of gate structure (4), the second via connection being connected to a corresponding second conductor (39) that is substantially parallel to the wiring of the flat surface (1), The first and second conductors (17, 39) are embedded in a dielectric material layer (26'), the layer including spacers on the sidewalls of the first conductor (17).

9. The device according to claim 8, characterized in that, The lateral dimensions of the gate structures (3, 4) and the spacing between adjacent gate structures are between 5 and 50 nm, and the thickness of the spacer is between 1 and 5 nm.

Images