Semiconductor structure preparation method and semiconductor structure
By removing the target defects on the surface of the silicon carbide substrate and epitaxially growing a single-crystal silicon layer, combined with annealing, the SiC channel interface defect problem was solved, the channel mobility of semiconductor devices was improved, and the high-performance requirements were met.
Patent Information
- Application Number
- CN202511135073.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-13
- Publication Date
- 2025-11-11
AI Technical Summary
In the existing technology, silicon-based power electronic devices cannot meet the high-performance requirements of semiconductor devices due to the limitations of material properties. In particular, SiC channels have a large number of interface defects, which leads to a decrease in channel mobility.
By removing potential hazards such as C-Si bonds, carbon vacancies, carbonates, carbides, and weak carbon bonds on the surface of the silicon carbide substrate, a single-crystal silicon layer is epitaxially grown using a chemical vapor deposition process under preset reaction source and temperature and pressure. The gate oxide layer is then annealed in an inert gas atmosphere to reduce interface defects and improve channel mobility.
It effectively reduces interface defects between the silicon carbide substrate and the gate oxide layer, avoids the reduction of carrier number and Coulomb scattering effect, and improves the channel mobility of semiconductor devices.
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Figure CN120936082A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) generally come in two types: depletion-mode and enhancement-mode. Enhancement-mode MOSFETs can be further divided into NPN and PNP types. NPN type is usually called N-channel, and PNP type is also called P-channel. MOSFETs are voltage-controlled devices; they control the drain current (ID) through the gate-source voltage (VGS). Because they utilize majority carriers for conduction, they have good temperature stability.
[0003] However, due to the limitations of its material properties, silicon-based power electronic devices can no longer meet the high-performance requirements of semiconductor devices in today's power electronics field. How to further improve the electrical performance parameters of MOSFETs is one of the research goals that researchers are constantly pursuing. Summary of the Invention
[0004] Based on this, the present disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, which can at least effectively reduce interface defects between the silicon carbide substrate and the gate oxide layer, improve the channel mobility of the gate of the semiconductor device, and thus improve the electrical performance parameters of the semiconductor device.
[0005] According to various embodiments of this disclosure, one aspect provides a method for fabricating a semiconductor structure, comprising:
[0006] A silicon carbide substrate is provided, and the target potential defects on the surface of the silicon carbide substrate are removed to obtain a target Si surface with a roughness within the target range;
[0007] A single-crystal silicon layer of a predetermined thickness is epitaxially grown on the target Si surface using a depressurized chemical vapor deposition process with a predetermined reaction source, a first predetermined temperature, and a first predetermined pressure.
[0008] An oxidation process is used under an oxygen atmosphere, a second preset temperature, and a second preset pressure to oxidize a single-crystal silicon layer to obtain a gate oxide layer of a preset thickness.
[0009] The gate oxide layer is annealed in a preset inert gas atmosphere and at a third preset temperature; the first preset temperature is lower than the second preset temperature, the second preset temperature is lower than the third preset temperature; and the second preset pressure is greater than the first preset pressure.
[0010] The semiconductor structure fabrication method in the above embodiments removes target defects such as C-Si bonds, carbon vacancies, carbonates, carbides, and carbon (C) planes containing weak carbon bonds from the surface of the silicon carbide substrate. This reduces the surface roughness of the silicon carbide substrate to within a target range, resulting in a target Si surface with a roughness within the target range. Then, a reduced-pressure chemical vapor deposition process is used under a preset reaction source, a first preset temperature, and a first preset pressure to epitaxially grow a single-crystal silicon layer of a preset thickness on the target Si surface with a neat and uniform lattice arrangement. The thickness of the single-crystal silicon layer can be consistent with the thickness of the gate oxide layer. Finally, an oxidation process is used under an oxygen atmosphere, a second preset temperature, and a second preset pressure to oxidize the single-crystal silicon layer and minimize its roughness. To prevent silicon carbide from being oxidized, a dense and uniform gate oxide layer of a predetermined thickness is obtained, effectively avoiding the generation of carbon defects. The gate oxide layer is annealed in a predetermined inert gas atmosphere and at a third predetermined temperature, avoiding the use of oxide gas. The first predetermined temperature is lower than the second predetermined temperature, which is lower than the third predetermined temperature. The second predetermined pressure is greater than the first predetermined pressure to prevent silicon carbide from being oxidized by oxide gas at high temperatures, further reducing interface defects between the silicon carbide substrate and the gate oxide layer. This prevents electrons generated in the inversion layer of the semiconductor device from being captured by high-density interface traps, thereby avoiding a significant reduction in the number of charge carriers at the channel, avoiding the aggravation of the Coulomb scattering effect on the channel surface, and improving the channel mobility of the semiconductor device.
[0011] In some embodiments, the target defects include C-Si bonds, carbon vacancies, carbonates, carbides, weak carbon bonds, or combinations thereof; the target gas source includes SiH2Cl2 and H2; removing the target defects from the surface of the silicon carbide substrate includes:
[0012] Plasma generated from a target gas source including SiH2Cl2 and H2 is used to remove target hazards on the surface of a silicon carbide substrate.
[0013] Based on the preset time for plasma etching of silicon carbide substrate surface under target temperature and target pressure, a target Si surface with roughness within the target range is obtained.
[0014] The semiconductor structure fabrication method in the above embodiments utilizes SiH2Cl2 plasma, which has many advantages in chemical reactions, such as fast reaction speed, high selectivity, and low energy consumption. By using SiH2Cl2 plasma to react with carbon atoms in the target defects on the silicon carbide substrate, other compounds are generated to remove target defects such as C-Si bonds, carbon vacancies, carbonates, carbides, and weak carbon bonds on the surface of the silicon carbide substrate. This reduces the surface roughness of the silicon carbide substrate to the target range, so as to facilitate the subsequent epitaxial growth of a single-crystal silicon layer with the target lattice on the target Si surface.
[0015] In some embodiments, the target temperature is 400℃-500℃; the target pressure is 3kPa-20kPa; the preset time is 30 seconds-60 seconds; and the target range of Ra value used to characterize the roughness of the target Si surface is 0.2nm-0.3nm, so as to facilitate the subsequent epitaxial growth of a single-crystal silicon layer with the target lattice on the target Si surface, thereby obtaining a dense and uniform gate oxide layer of a preset thickness based on the single-crystal silicon layer, effectively reducing the interface defects generated between the silicon carbide substrate and the gate oxide layer.
[0016] In some embodiments, the preset reaction source includes: SiH2Cl2 and H2; the first preset temperature is 500℃-650℃; the first preset pressure is 5Torr-15Torr; and the preset thickness is 2nm-10nm.
[0017] In some embodiments, the supply flow rate of the reaction source gas is 1000 sccm-3000 sccm.
[0018] In some embodiments, the second preset temperature is 700°C-850°C; the second preset pressure is 300 Torr-500 Torr. Since the initial oxidation temperature of silicon is 700°C and the initial oxidation temperature of silicon carbide is 900°C, the temperature during the oxidation of the single-crystal silicon layer is set to 700°C-850°C to prevent silicon carbide from being oxidized and damaged.
[0019] In some embodiments, the O2 flow rate for forming the oxygen atmosphere is 20,000 sccm-50,000 sccm, which oxidizes the single-crystal silicon layer into a dense gate oxide layer, reduces the time of the gate oxide layer formation process steps, and lowers the preparation cost.
[0020] In some embodiments, the third preset temperature is 900°C to 1200°C to prevent impurities from spreading and to repair shallow defects.
[0021] In some embodiments, the preset inert gas includes N2, Ar, He, or a combination thereof, and oxide gases are avoided to prevent silicon carbide from being oxidized by oxide gases at high temperatures.
[0022] In some embodiments, the oxygen atmosphere includes oxygen, ozone, oxygen ions, or a combination thereof.
[0023] According to various embodiments of this disclosure, another aspect provides a semiconductor device, comprising: a semiconductor structure fabricated using the semiconductor structure fabrication method described in any of the foregoing embodiments. This reduces interface defects between the silicon carbide substrate and the gate oxide layer, preventing electrons generated in the inversion layer of the semiconductor device from being trapped by high-density interface traps, thereby avoiding a significant reduction in the number of charge carriers at the channel, preventing the exacerbation of Coulomb scattering at the channel surface, and improving the channel mobility of the semiconductor device. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic flowchart of a semiconductor structure fabrication method provided in one embodiment of the present disclosure;
[0026] Figure 2 This is a schematic cross-sectional view of the semiconductor structure obtained after providing a silicon carbide substrate in a semiconductor structure fabrication method provided in one embodiment of the present disclosure.
[0027] Figure 3 This is a schematic diagram illustrating the principle of removing potential hazards from the surface of a silicon carbide substrate in a semiconductor structure fabrication method provided in one embodiment of the present disclosure.
[0028] Figure 4 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a target Si surface in a semiconductor structure fabrication method provided in one embodiment of the present disclosure.
[0029] Figure 5 This is a schematic diagram showing the surface roughness of a silicon carbide substrate obtained by conventional methods and measured by atomic force microscopy.
[0030] Figure 6 This is a schematic diagram showing the surface roughness of a target Si surface obtained in a semiconductor structure fabrication method provided in one embodiment of the present disclosure, measured by an atomic force microscope.
[0031] Figure 7 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a single-crystal silicon layer in a semiconductor structure fabrication method provided in one embodiment of the present disclosure.
[0032] Figure 8 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a gate oxide layer in a semiconductor structure fabrication method provided in one embodiment of the present disclosure.
[0033] Figure 9 In one embodiment of this disclosure, the voltage V between the drain and source is... DS At 5V, the drain current I DS With gate voltage V GS A schematic diagram of the change curve;
[0034] Figure 10In one embodiment of this disclosure, the voltage V between the gate and the source is... GS At a voltage of 30V, the on-state current I of the device is obtained. ON Decrease ΔI ON With V GS A schematic diagram showing the curve change over the application time (in hours).
[0035] Explanation of reference numerals in the attached figures:
[0036] 10. Silicon carbide substrate; 20. Target Si surface; 30. Single crystal silicon layer; 40. Gate oxide layer. Detailed Implementation
[0037] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.
[0043] The source and drain of an N-channel MOSFET are connected to an N-type semiconductor, while the source and drain of a P-channel MOSFET are connected to a P-type semiconductor. The output current of a MOSFET is controlled by the input voltage (or electric field), and the input current can be considered to be minimal or non-existent. This results in a very high input impedance, which is why it is called a field-effect transistor (FET).
[0044] However, due to the limitations of its material properties, silicon-based power electronic devices can no longer meet the high-performance requirements of semiconductor devices in today's power electronics field. Based on this, wide-bandgap semiconductor materials, represented by silicon carbide (SiC), have emerged. Compared to silicon (Si) devices, SiC devices have lower on-resistance, faster switching speed, higher breakdown voltage, and lower thermal conductivity. These superior characteristics give SiC devices significant advantages in high frequency and high power density.
[0045] However, the SiC channel of MOSFETs using SiC substrates has many interface defects, which severely restricts the improvement of SiC device mobility. Especially in NMOS, due to the large number of defects at the interface between silicon carbide and gate oxide, such as excessive interface roughness, electrons generated in the inversion layer are captured by high-density interface traps, which leads to a significant reduction in the number of charge carriers at the channel. This intensifies the Coulomb scattering effect on the channel surface, resulting in a further decrease in channel mobility.
[0046] Therefore, this application aims to provide a semiconductor structure fabrication method and semiconductor structure, which can at least effectively reduce interface defects between silicon carbide substrate and gate oxide layer, and improve the channel mobility of gate in semiconductor devices.
[0047] Please refer to Figure 1 In some embodiments, a method for fabricating a semiconductor structure is provided, comprising:
[0048] Step S11: Provide a silicon carbide substrate, remove the target defects on the surface of the silicon carbide substrate, and obtain a target Si surface with a roughness within the target range;
[0049] Step S12: Using a pre-set reaction source, a first pre-set temperature and a first pre-set pressure, a reduced pressure chemical vapor deposition process is used to epitaxially grow a single-crystal silicon layer of a pre-set thickness on the target Si surface.
[0050] Step S13: Using an oxidation process under an oxygen atmosphere, a second preset temperature, and a second preset pressure, the single-crystal silicon layer is oxidized to obtain a gate oxide layer of a preset thickness;
[0051] Step S14: Anneal the gate oxide layer in a preset inert gas atmosphere and at a third preset temperature; the first preset temperature is lower than the second preset temperature, the second preset temperature is lower than the third preset temperature; the second preset pressure is greater than the first preset pressure.
[0052] For example, please continue to refer to Figure 1By removing target defects such as C-Si bonds, carbon vacancies, carbonates, carbides, and weak carbon bonds from the surface of a silicon carbide substrate, the surface roughness of the silicon carbide substrate after defect removal is reduced to within the target range, resulting in a target Si surface with a roughness within the target range. Then, using a reduced-pressure chemical vapor deposition process under a preset reaction source, a first preset temperature, and a first preset pressure, a single-crystal silicon layer of a preset thickness is epitaxially grown on the target Si surface with a neat and uniform lattice arrangement. The thickness of the single-crystal silicon layer can be consistent with the thickness of the gate oxide layer. Finally, an oxidation process is used under an oxygen atmosphere, a second preset temperature, and a second preset pressure to oxidize the single-crystal silicon layer while minimizing the oxidation of silicon carbide, resulting in a dense and thick silicon carbide surface. A gate oxide layer of uniform, predetermined thickness is formed, effectively preventing the formation of carbon defects. The gate oxide layer is annealed under a predetermined inert gas atmosphere and a third predetermined temperature, effectively reducing the use of oxide gas. The first predetermined temperature is lower than the second predetermined temperature, and the second predetermined temperature is lower than the third predetermined temperature. The second predetermined pressure is greater than the first predetermined pressure to prevent silicon carbide from being oxidized by oxide gas at high temperatures, further reducing interface defects between the silicon carbide substrate and the gate oxide layer. This prevents electrons generated in the inversion layer of the semiconductor device from being captured by high-density interface traps, thereby avoiding a significant reduction in the number of charge carriers at the channel, avoiding the aggravation of Coulomb scattering effect on the channel surface, and improving the channel mobility of the semiconductor device.
[0053] Please refer to Figure 2 In some embodiments, the provided silicon carbide (SiC) substrate can be a single-layer structure or a multi-layer structure. Target defects on the surface of the silicon carbide substrate can be removed by plasma generated based on a target gas source, resulting in a target Si surface with a roughness within the target range. Target defects include C-Si bonds, carbon vacancies, carbonates, carbides, weak carbon bonds, or combinations thereof.
[0054] Please refer to Figure 3 In some embodiments, the target gas source includes SiH2Cl2 and H2; step S11, removing the target hazard from the surface of the silicon carbide substrate, includes:
[0055] Step S111: Use plasma generated by a target gas source including SiH2Cl2 and H2 to remove target hazards on the surface of the silicon carbide substrate;
[0056] Step S112: Based on the target temperature and target pressure, plasma etching of the silicon carbide substrate surface for a preset time is performed to obtain a target Si surface with a roughness within the target range.
[0057] For example, please continue to refer to Figure 3In step S111, taking advantage of the advantages of SiH2Cl2 plasma in chemical reactions, such as fast reaction speed, strong selectivity and low energy consumption, SiH2Cl2 plasma reacts with carbon atoms in the target defects on the silicon carbide substrate to generate other compounds, thereby removing target defects such as C-Si bonds, carbon vacancies, carbonates, carbides and weak carbon bonds on the surface of the silicon carbide substrate. This reduces the surface roughness of the silicon carbide substrate to the target range, so as to facilitate the subsequent epitaxial growth of a single crystal silicon layer with the target lattice on the target Si surface.
[0058] For example, the carbon-rich layer on the surface of a silicon carbide substrate is prone to forming weak carbon bonds (CC bonds). CC bonds are much weaker than Si-C bonds, potentially creating structural weaknesses and reducing the stability of the silicon carbide substrate during high-temperature processes (such as oxidation and annealing) and chemical treatments (such as cleaning and etching). This can lead to surface roughening, the introduction of defects, or changes in surface states. During epitaxial growth, weakly bonded regions may become heterogeneous nucleation sites, leading to polymorphic co-occurrence (e.g., 3C-SiC nucleation on a 4H-SiC substrate) or stacking faults (SF), resulting in a decline in epitaxial layer quality (polymorphism, stacking faults, defect propagation, poor adhesion). For example, please refer to [reference needed]. Figures 3-6 In step S112, the surface of the silicon carbide substrate is etched for a preset time, such as 30 seconds to 60 seconds, based on the plasma at a target temperature of 400℃-500℃ and a target pressure of 3kPa-20kPa, to obtain a target Si surface with a roughness within the target range. Figure 5 Example Figure 2 The surface roughness of the silicon carbide substrate 10, where surface target defects have not been removed, can be measured using atomic force microscopy (AFM). Figure 2 The surface roughness of the silicon carbide substrate 10, which has not had potential surface defects removed, is obtained. Figure 5 The surface roughness diagram shown is as follows. Figure 5 The root mean square (RMS) value of Ra, used to characterize the surface roughness of the target Si, is 0.44 nm. Through the process step S11 of removing the target defects from the surface of the silicon carbide substrate, a silicon carbide substrate 10 with the surface target defects removed is obtained. Figure 4 As shown, the surface of the silicon carbide substrate 10 has a target Si surface 20, which is measured using an atomic force microscope (AFM). Figure 4 The target Si surface 20 is obtained. Figure 6 The surface roughness diagram shown is as follows. Figure 6 The RMS value of Ra, used to characterize the surface roughness Ra of the target Si surface 20, is 0.25 nm. This is compared to... Figure 5 , Figure 6It can be clearly seen that after removing the target hidden dangers such as C-Si bonds, carbon vacancies, carbonates, carbides, and weak carbon bonds on the surface of the silicon carbide substrate in step S111 of this application, the roughness of the surface of the silicon carbide substrate is reduced to the target range.
[0059] For example, the RMS value used to characterize the surface roughness Ra of the target Si surface can be in the range of 0.2 nm to 0.3 nm. For instance, the RMS value of the surface roughness Ra of the target Si surface can be 0.2 nm, 0.25 nm, or 0.3 nm, etc.
[0060] For example, in step S112, the target temperature can be 400℃, 420℃, 450℃, 470℃ or 500℃, etc.; the target pressure can be 3kPa, 6kPa, 10kPa, 15kPa, 18kPa or 20kPa, etc.; the preset time for etching the silicon carbide substrate surface can be 30 seconds, 35 seconds, 40 seconds, 45 seconds, 50 seconds, 55 seconds or 60 seconds, etc.
[0061] Please refer to Figure 7 In some embodiments, step S12 uses a reaction source including SiH2Cl2 and H2, and at a first preset temperature of 500℃-650℃ and a first preset pressure of 5Torr-15Torr, a single crystal silicon layer with a target lattice is epitaxially grown on a target Si surface with a roughness within the target range. This facilitates the epitaxial growth of a dense and uniform gate oxide layer of a preset thickness based on the target silicon lattice, effectively reducing interface defects between the silicon carbide substrate and the gate oxide layer.
[0062] For example, in step S12, the first preset temperature can be 500℃, 550℃, 600℃, or 650℃, etc. The first preset pressure can be 5 Torr, 8 Torr, 10 Torr, 12 Torr, or 15 Torr, etc. The preset thickness of the gate oxide layer can be 2nm, 4nm, 6nm, 8nm, or 10nm, etc.
[0063] In some embodiments, in step S12, the supply flow rate of the reaction source gas is 1000 sccm-3000 sccm, for example, the supply flow rate of the reaction source gas is 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm, or 3000 sccm, etc. By setting the supply flow rate of the reaction source gas to 1000 sccm-3000 sccm, it is possible to avoid the growth time of the single crystal silicon layer being too long, resulting in an excessively thick single crystal silicon layer, and also to avoid the growth time of the single crystal silicon layer being too short, resulting in an insufficient single crystal silicon layer thickness.
[0064] Please refer to Figure 8In some embodiments, in step S13, an oxidation process is used under an oxygen atmosphere, a second preset temperature of 700°C-850°C, and a second preset pressure of 300 Torr-500 Torr to oxidize the single-crystal silicon layer 30, resulting in a gate oxide layer 40 of a preset thickness. The thickness of the gate oxide layer 40 can be substantially the same as the thickness of the single-crystal silicon layer 30. Since the starting temperature for silicon oxidation is 700°C and the starting temperature for silicon carbide oxidation is 900°C, the temperature during the oxidation of the single-crystal silicon layer is set to 700°C-850°C to prevent silicon carbide from being oxidized and damaged.
[0065] For example, in step S13, the second preset temperature can be 700℃, 750℃, 800℃ or 850℃, etc.; the second preset pressure can be 300 Torr, 350 Torr, 400 Torr, 450 Torr or 500 Torr, etc.
[0066] For example, in step S13, the O2 flow rate for forming the oxygen atmosphere is 20,000 sccm-50,000 sccm. For instance, the O2 flow rate for forming the oxygen atmosphere can be 20,000 sccm, 25,000 sccm, 30,000 sccm, 35,000 sccm, 40,000 sccm, 45,000 sccm, or 50,000 sccm, etc. By setting the O2 flow rate for forming the oxygen atmosphere to 20,000 sccm-50,000 sccm, the single-crystal silicon layer is oxidized into a dense gate oxide layer, reducing the time required for the gate oxide layer formation process and lowering the fabrication cost.
[0067] In some embodiments, in step S14, the gate oxide layer 40 is annealed in a preset inert gas atmosphere including at least one of N2, Ar, or He, and at a third preset temperature of 900°C to 1200°C to ensure the formation of a high-quality gate oxide layer 40; the first preset temperature is lower than the second preset temperature and the third preset temperature; the second preset pressure is greater than the first preset pressure. This prevents impurity diffusion and repairs shallow defects. Annealing can promote atomic rearrangement and repair lattice defects through a high-temperature environment, thereby improving device performance. In addition, annealing can densify porous films, which can reduce gate leakage current.
[0068] In some embodiments, the oxygen atmosphere includes oxygen, ozone, oxygen ions, or combinations thereof to improve the quality of the prepared gate oxide layer.
[0069] It should be noted that the inert gas in the embodiments of this application includes rare gases, nitrogen, and other chemically stable gases.
[0070] For example, in step S14, the third preset temperature can be 900℃, 1000℃, or 1200℃, etc.
[0071] For example, in step S14, the preset inert gas includes N2, and oxide gases are avoided to prevent silicon carbide from being oxidized by oxide gases at high temperatures.
[0072] According to various embodiments of this disclosure, another aspect provides a semiconductor device, comprising: a semiconductor structure fabricated using the semiconductor structure fabrication method of any of the foregoing embodiments. This reduces interface defects between the silicon carbide substrate and the gate oxide layer, preventing electrons generated in the inversion layer of the semiconductor device from being trapped by high-density interface traps, thereby avoiding a significant reduction in the number of charge carriers at the channel, preventing the exacerbation of Coulomb scattering effects at the channel surface, and improving the channel mobility of the semiconductor device.
[0073] As a typical representative of wide bandgap semiconductors, silicon carbide has a breakdown field strength that is 10 times that of silicon. For chips with the same voltage resistance, its thickness can be 1 / 10 that of silicon chips. Therefore, using silicon carbide to form the gate channel can effectively reduce the chip thickness and reduce the difficulty of the process.
[0074] Please refer to Figure 9 In some embodiments, after the semiconductor structure is fabricated using the semiconductor structure fabrication method described in any of the foregoing embodiments, a gate conductive layer is formed on the surface of the gate oxide layer facing away from the silicon carbide substrate. The gate oxide layer and the gate conductive layer are used together to form the gate. Then, an ion implantation process is performed into the silicon carbide substrate based on the gate to obtain a first doped region, a gate, and a second doped region arranged sequentially along a first direction parallel to the surface of the silicon carbide substrate. A channel is formed in the substrate located between the first doped region and the second doped region and directly below the gate. Figure 9 As shown, in this application (the embodiment of this application), the ratio of the width (W) to the length (L) of the channel in the metal-oxide-semiconductor field-effect transistor provided can be 50 / 10, and the voltage V between the drain and source is... DS At 5V, the width or length of the channel can be measured in micrometers (μm), and the drain current I... DS With gate voltage V GS A schematic diagram of the change curve.
[0075] In some other embodiments, after forming the silicon carbide substrate, a gate oxide layer is formed directly on the surface of the silicon carbide substrate, and then the gate oxide layer is directly subjected to high-temperature annealing. The ratio of the width (W) to the length (L) of the channel in the formed MOS device can be 50 / 10, and the gate oxide layer thickness T OX The wavelength is 120nm, and the voltage V between the drain and source is... DS At 5V, the width or length of the channel can be measured in micrometers (μm), and the drain current I... DS With gate voltage VGS A schematic diagram of the change curve, such as... Figure 9 As shown in the BSL curve; the voltage V between the gate and source. GS At a voltage of 30V, the obtained device on-state current I ON The decrease △I ON With V GS A schematic diagram showing the curve change over the application time (in hours).
[0076] Analysis revealed that the gate channel mobility is reduced due to the high roughness of the carbon (C) surface of the gate oxide layer in the MOS device, the high interface state density, and the interface defects that may occur between the silicon carbide substrate surface and the gate oxide layer. Figure 9 In this context, under the same electrical excitation conditions and device design parameters, for example, the ratio of channel width (W) to length (L) can be 50 / 10, and the voltage V between the drain and source can also be... DS At 5V, the width or length of the channel can be measured in micrometers (μm). The electrical performance parameters shown in the curve in this case are significantly better than those shown in the BSL curve.
[0077] Please refer to Figure 10 In some embodiments, the semiconductor device fabricated using the semiconductor structure fabrication method described in any of the foregoing embodiments has a voltage V between the gate and the source. GS At a voltage of 30V, the on-state current I of the device is obtained. ON The decrease △I ON With V GS A schematic diagram of the curve change over the application time (in hours), as shown below. Figure 10 The curve corresponding to "SiC surface treatment plus single crystal silicon oxide gate" is shown in the figure.
[0078] Please refer to Figure 10 In some embodiments, after directly growing a single-crystal silicon layer on the surface of a SiC substrate, the single-crystal silicon layer is oxidized into a gate oxide layer. The resulting semiconductor device has a voltage V between the gate and the source. GS At a voltage of 30V, the on-state current I of the device is obtained. ON Decrease ΔI ON With V GS A schematic diagram of the curve change over the application time (in hours), as shown below. Figure 10 The curve corresponding to "monocrystalline silicon oxide gate" is shown in the figure.
[0079] Please continue to refer to this. Figure 10 By comparing the three schematic diagrams, it can be found that the semiconductor device fabricated using the semiconductor structure fabrication method described in any of the aforementioned embodiments has a voltage V between the gate and source.GS At a voltage of 30V, the device's on-state current I is obtained. ON Decrease ΔI ON With V GS The variation in application time (in hours) is significantly smaller than that of the time-to-time variation. Figure 10 The other two are also mentioned. Therefore, under the same testing conditions, the electrical performance parameters of the semiconductor device fabricated using the semiconductor structure fabrication method described in any of the foregoing embodiments are significantly better than those of the other two. Figure 10 The diagram illustrates the electrical performance parameters of two other semiconductor devices. Therefore, the embodiments of this application, compared to the prior art, include at least the following unexpected technical effects:
[0080] By employing plasma generated based on a target gas source, potential defects such as C-Si bonds, carbon vacancies, carbonates, carbides, and weak carbon bonds on the surface of a silicon carbide substrate can be removed. This reduces the surface roughness of the silicon carbide substrate to within the target range, resulting in a target Si surface with a roughness within the target range. Then, a reduced-pressure chemical vapor deposition process is used at a preset reaction source, a first preset temperature, and a first preset pressure to epitaxially grow a single-crystal silicon layer of a preset thickness on the uniformly arranged target Si surface. The thickness of the single-crystal silicon layer can be consistent with the thickness of the gate oxide layer. Finally, an oxidation process is used in an oxygen atmosphere at a second preset temperature and a second preset pressure to oxidize the single-crystal silicon layer while minimizing carbon deposits. Silicon carbide is oxidized to obtain a dense and uniform gate oxide layer of a predetermined thickness, effectively avoiding the generation of carbon defects. The gate oxide layer is annealed under a predetermined inert gas atmosphere and a third predetermined temperature, avoiding the use of oxide gas. The first predetermined temperature is lower than the second predetermined temperature, which is lower than the third predetermined temperature. The second predetermined pressure is greater than the first predetermined pressure to prevent silicon carbide from being oxidized by oxide gas at high temperatures, further reducing interface defects between the silicon carbide substrate and the gate oxide layer. This prevents electrons generated in the inversion layer of the semiconductor device from being captured by high-density interface traps, thereby avoiding a significant reduction in the number of charge carriers at the channel, avoiding the aggravation of the Coulomb scattering effect on the channel surface, and improving the channel mobility of the semiconductor device.
[0081] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0082] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0083] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0085] The above embodiments merely illustrate several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A silicon carbide substrate is provided, and the target defects on the surface of the silicon carbide substrate are removed to obtain a target Si surface with a roughness within the target range; A single-crystal silicon layer of a predetermined thickness is epitaxially grown on the target Si surface using a depressurized chemical vapor deposition process with a predetermined reaction source, a first predetermined temperature, and a first predetermined pressure. The single-crystal silicon layer is oxidized using an oxidation process under an oxygen atmosphere, a second preset temperature, and a second preset pressure to obtain a gate oxide layer of a preset thickness. The gate oxide layer is annealed under a preset inert gas atmosphere and a third preset temperature. The first preset temperature is lower than the second preset temperature, and the second preset temperature is lower than the third preset temperature; the second preset pressure is greater than the first preset pressure.
2. The semiconductor structure fabrication method according to claim 1, characterized in that, The target hazards include C-Si bonds, carbon vacancies, carbonates, carbides, weak carbon bonds, or combinations thereof; Removing the target potential hazard from the surface of the silicon carbide substrate includes: Plasma generated from a target gas source including SiH2Cl2 and H2 is used to remove target hazards from the surface of the silicon carbide substrate. The plasma etching of the silicon carbide substrate surface at the target temperature and target pressure is performed for a preset time to obtain a target Si surface with a roughness within the target range.
3. The semiconductor structure fabrication method according to claim 2, characterized in that, The target temperature is 400℃-500℃; the target pressure is 3kPa-20kPa; the preset time is 30 seconds-60 seconds. The target range for the Ra value used to characterize the surface roughness of the target Si surface is 0.2 nm to 0.3 nm.
4. The method for fabricating a semiconductor structure according to any one of claims 1-3, characterized in that, The preset reaction source includes: SiH2Cl2 and H2; the first preset temperature is 500℃-650℃; the first preset pressure is 5Torr-15Torr; and the preset thickness is 2nm-10nm.
5. The semiconductor structure fabrication method according to claim 4, characterized in that, The supply flow rate of the reaction source gas is 1000 sccm-3000 sccm.
6. The method for fabricating a semiconductor structure according to any one of claims 1-3, characterized in that, The second preset temperature is 700℃-850℃; the second preset pressure is 300Torr-500Torr.
7. The semiconductor structure fabrication method according to claim 6, characterized in that, The O2 flow rate for forming the oxygen atmosphere is 20,000 sccm-50,000 sccm.
8. The method for fabricating a semiconductor structure according to any one of claims 1-3, characterized in that, The third preset temperature is 900℃ to 1200℃.
9. The method for fabricating a semiconductor structure according to any one of claims 1-3, characterized in that, The preset inert gas includes N2, Ar, He, or a combination thereof; and / or The oxygen atmosphere includes oxygen, ozone, oxygen ions, or combinations thereof.
10. A semiconductor device, characterized in that, include: A semiconductor structure prepared by the semiconductor structure preparation method according to any one of claims 1-9.