A cascode GaN device and a method of fabricating the same

Abstract

The application relates to the field of semiconductors and discloses a common-source common-gate GaN device and a preparation method thereof. The common-source common-gate GaN device comprises a lead frame base island, a MOS chip and a GaN chip. The lead frame base island is provided with a first conductive area serving as a source of the GaN device. The source of the MOS chip is arranged on the back surface, and the gate and the drain are arranged on the front surface. The source on the back surface of the MOS chip is electrically connected with the first conductive area. The GaN chip is stacked on the MOS chip. The source, the gate and the drain of the GaN chip are arranged on the front surface, and the back surface of the GaN chip is also provided with the source. The source on the back surface of the GaN chip is electrically connected with the drain on the front surface of the MOS chip. Alternatively, the front surface of the MOS chip is also provided with the source, the front surface of the GaN chip is provided with the drain, the back surface is provided with the source and the gate, and the source and the gate on the back surface of the GaN chip are electrically connected with the drain and the source on the front surface of the MOS chip in correspondence. The application can reduce the size of the GaN device and lower the cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a common-source common-gate GaN device and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) is a third-generation wide-bandgap semiconductor material, and its semiconductor device characteristics are superior to Si-based semiconductor devices in high-temperature, high-pressure, high-frequency and other application scenarios. The structure of GaN FET device currently mainly has depletion mode (D-mode) and enhancement mode (E-mode).

[0003] The common-source common-gate structure GaN device (Cascode GaN) is cascaded by a high-voltage depletion mode GaN power device and a low-voltage enhancement mode Si MOSFET (metal oxide semiconductor field effect transistor). From its structure, it can be known that when the device is not applied with a gate voltage and the drain-source voltage is greater than zero, it works in a forward blocking mode; when the gate voltage is greater than the threshold voltage of the Si MOSFET, the device is forward conducting; once the Si MOSFET is reverse conducting, the device will work in a reverse conducting mode.

[0004] At present, the traditional depletion mode GaN chip usually has a large area and is a single-sided electrode structure, all electrodes are located on the front surface, and the back surface is an insulating structure, which does not have a double-sided conduction capability, and cannot be stacked on other chips to connect the chip to the circuit in a direct contact manner, so the Cascode structure mainly forms a series connection between the MOS chip 4 and the GaN chip 5 through the substrate 3 (as shown in Figure 1 The substrate 3 (substrate chip) as shown in Figure 1 is used as a medium, and a wire bonding process is needed to complete the interconnection between the chips by using multiple leads 6, and the product preparation process is relatively complex, with many steps and high cost.

[0005] Another Cascode structure GaN device, as disclosed in the Chinese patent application with publication number CN111430335B, is to stack the MOS chip on the surface of the GaN chip to form a series connection. However, this structure requires that the size of the GaN chip be large enough, and the electrode area on the surface of the GaN chip also be large enough to meet the bearing of the MOS chip, which is not conducive to product cost control and device miniaturization.

[0006] The disclosure of the above background art is only used to assist in understanding the inventive concept and technical solutions of the present application, and it does not necessarily belong to the prior art of the present patent application, nor does it necessarily give technical teaching; in the absence of explicit evidence that the above content has been disclosed before the filing date of the present patent application, the above background art should not be used to evaluate the novelty and inventiveness of the present application. SUMMARY

[0007] The purpose of the present application is to provide a common-source common-gate GaN device and a preparation method thereof, which can realize the reduction of the volume of the Cascode GaN device, the simplification of the production process of the Cascode GaN device, the reduction of the product cost and the improvement of the electrical performance.

[0008] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows:

[0009] A common-source common-gate GaN device comprises a lead frame base island, a MOS chip and a GaN chip.

[0010] The lead frame base island is provided with a first conductive area configured as the source of the GaN device.

[0011] The source of the MOS chip is arranged on the back surface thereof, and the gate and the drain of the MOS chip are arranged on the front surface thereof; the MOS chip is arranged on the first conductive area, and the source on the back surface thereof is electrically connected with the first conductive area.

[0012] The GaN chip is stacked on the MOS chip, and the GaN chip is electrically connected with the MOS chip in the following manner:

[0013] The source, the gate and the drain of the GaN chip are arranged on the front surface thereof, and the back surface of the GaN chip is provided with a second conductive area electrically connected with the source on the front surface of the GaN chip; the second conductive area on the back surface of the GaN chip is electrically connected with the drain on the front surface of the MOS chip.

[0014] Alternatively,

[0015] The front surface of the MOS chip is also provided with the source thereof, the drain of the GaN chip is arranged on the front surface thereof, the source and the gate of the GaN chip are arranged on the back surface thereof, the source on the back surface of the GaN chip is electrically connected with the drain on the front surface of the MOS chip, and the gate on the back surface of the GaN chip is electrically connected with the source on the front surface of the MOS chip.

[0016] Further, in any of the above technical solutions or the combination of the above technical solutions, the source, the gate and the drain of the GaN chip are arranged on the front surface thereof, the back surface of the GaN chip is provided with a second conductive area, the second conductive area on the back surface of the GaN chip is electrically connected with the source on the front surface of the GaN chip through a via hole, and a conductive layer is arranged on the inner wall of the via hole.

[0017] The second conductive area on the back surface of the GaN chip is connected and electrically connected with the drain of the MOS chip through conductive adhesive.

[0018] Further, any one of the above technical solutions or a combination of the above technical solutions, the GaN chip further comprises an insulating substrate, the through hole is arranged on the insulating substrate, and the source of the GaN chip and the second conductive area are electrically connected in a synchronous growth mode of a metal layer on a front surface of the insulating substrate, an inner wall of the through hole, and a back surface of the insulating substrate.

[0019] Further, any one of the above technical solutions or a combination of the above technical solutions, the source on the back surface of the MOS chip is welded or electrically connected through conductive glue to the first conductive area on the lead frame base island.

[0020] The gate of the MOS chip is electrically connected to the gate of the GaN device through a bonding wire.

[0021] The drain of the GaN chip is electrically connected to the drain of the GaN device through a bonding wire.

[0022] The gate of the GaN chip is electrically connected to the first conductive area through a bonding wire.

[0023] Further, any one of the above technical solutions or a combination of the above technical solutions, the area of the drain of the MOS chip is greater than the area of the GaN chip; and / or,

[0024] The back surface of the GaN chip is fully covered with a metal layer, and the metal layer is configured as the second conductive area.

[0025] Further, any one of the above technical solutions or a combination of the above technical solutions, the front surface of the MOS chip is also provided with the source thereof, the source of the GaN chip is arranged above the drain of the MOS chip, and the gate of the GaN chip is arranged above the source of the MOS chip.

[0026] The source of the GaN chip and the drain of the MOS chip, and the gate of the GaN chip and the source of the MOS chip are synchronously welded and connected through eutectic welding.

[0027] Further, any one of the above technical solutions or a combination of the above technical solutions, the source on the back surface of the MOS chip is welded or electrically connected through conductive glue to the first conductive area on the lead frame base island.

[0028] The gate of the MOS chip is electrically connected to the gate of the GaN device through a bonding wire.

[0029] The drain of the GaN chip is electrically connected to the drain of the GaN device through a bonding wire.

[0030] Further, in any of the above technical solutions or a combination of the above technical solutions, the source of the GaN chip is adjacent to the gate of the GaN chip, and the source of the MOS chip is adjacent to the drain of the MOS chip.

[0031] Further, in any of the above technical solutions or a combination of the above technical solutions, the minimum distance between the source and the gate of the GaN chip is not less than 100 μm.

[0032] Further, in any of the above technical solutions or a combination of the above technical solutions, the lead frame base island is configured as an independent base island, and the lead frame base island is arranged separately from the gate and the drain of the GaN device.

[0033] Further, in any of the above technical solutions or a combination of the above technical solutions, the lead frame base island, the MOS chip, and the GaN chip are encapsulated by EMC resin.

[0034] According to another aspect of the present application, a preparation method of a common-source and common-gate GaN device is provided, comprising the following steps:

[0035] The MOS chip and the GaN chip are designed, the source of the MOS chip is arranged on the back surface of the MOS chip, the gate and the drain of the MOS chip are arranged on the front surface of the MOS chip, the source, the gate, and the drain of the GaN chip are arranged on the front surface of the GaN chip, and the back surface of the GaN chip is also provided with the source of the GaN chip;

[0036] The lead frame base island and the gate and the drain of the GaN device are designed separately, and the front surface of the lead frame base island is provided with the source of the GaN device;

[0037] The MOS chip is arranged on the lead frame base island, and the source on the back surface of the MOS chip is electrically connected to the source of the GaN device on the front surface of the lead frame base island by conductive glue or welding;

[0038] The GaN chip is arranged on the MOS chip, and the source on the back surface of the GaN chip is electrically connected to the drain on the front surface of the MOS chip by conductive glue;

[0039] Other electrodes are electrically connected by bonding wires to obtain a GaN device semi-finished product, comprising: the gate of the MOS chip is electrically connected to the gate of the GaN device by a bonding wire, the drain of the GaN chip is electrically connected to the drain of the GaN device by a bonding wire, and the gate of the GaN chip is electrically connected to the source of the GaN device on the front surface of the lead frame base island by a bonding wire;

[0040] The GaN device semi-finished product is packaged by an EMC resin through a mold injection forming process.

[0041] According to another aspect of the present application, a preparation method of a common-source common-gate GaN device is provided, comprising the following steps:

[0042] The MOS chip and the GaN chip are designed, the MOS chip is provided with a source on its front surface and back surface, the gate and the drain of the MOS chip are arranged on the front surface of the MOS chip, the drain of the GaN chip is arranged on the front surface of the GaN chip, and the source and the gate of the GaN chip are arranged on the back surface of the GaN chip;

[0043] The gate and the drain of the GaN device are designed separately from the lead frame base island, and the source of the GaN device is arranged on the front surface of the lead frame base island;

[0044] The MOS chip is arranged on the lead frame base island, and the source on the back surface of the MOS chip is electrically connected to the source of the GaN device on the front surface of the lead frame base island through conductive glue or welding;

[0045] The GaN chip is arranged on the MOS chip, the source of the GaN chip is arranged above the drain of the MOS chip, and the gate of the GaN chip is arranged above the source of the MOS chip, and the source of the GaN chip and the drain of the MOS chip and the gate of the GaN chip and the source of the MOS chip are synchronously welded through eutectic welding;

[0046] Other electrodes are electrically connected through bonding wires to obtain a GaN device semi-finished product, comprising: electrically connecting the gate of the MOS chip to the gate of the GaN device through a bonding wire, and electrically connecting the drain of the GaN chip to the drain of the GaN device through a bonding wire;

[0047] The GaN device semi-finished product is packaged through a molding process using EMC resin.

[0048] The technical scheme provided by the present application has the following beneficial effects:

[0049] a. The first common-source common-gate GaN device provided by the present application combines the LV MOS backplane source setting technology and the technology of connecting the source on the front surface of the GaN chip to the back surface thereof, adopts the GaN chip stacked on the MOS chip, electrically connects the source on the back surface of the MOS chip to the first conductive area on the front surface of the lead frame base island, realizes that only the drain and the gate of the GaN chip and the gate of the MOS chip need three bonding wires, saves one substrate, realizes the reduction of the size of the Cascode GaN device, simplifies the production process of the Cascode GaN device, reduces the product cost, and improves the electrical performance thereof;

[0050] b. The second common-source common-gate GaN device provided by the application is provided with a source on the front surface and the back surface of the MOS chip, is provided with a gate and a source on the back surface of the GaN chip and is provided with only a drain on the front surface of the GaN chip, the GaN chip is stacked on the MOS chip, and the eutectic welding process is adopted to realize the corresponding interconnection of the gate of the GaN chip and the source of the MOS chip and the source of the GaN chip and the drain of the MOS, finally only two electrodes of the drain of the GaN chip and the gate of the MOS need to be electrically connected with the drain and the gate of the GaN device through the bonding wires, the number of the wires is further reduced, and one substrate is also saved, the volume of the Cascode GaN device is reduced, the production process of the Cascode GaN device is simplified, the product cost is reduced, and the GaN device with better electrical performance can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0052] Figure 1 The structure schematic diagram of the common-source common-gate GaN device in the prior art is shown in the figure.

[0053] Figure 2 The structure schematic diagram of the first MOS chip provided by an exemplary embodiment of the present application is shown in the figure.

[0054] Figure 3 The perspective schematic diagram of the first GaN chip provided by an exemplary embodiment of the present application is shown in the figure.

[0055] Figure 4 The perspective schematic diagram of the three-dimensional structure of the first GaN chip provided by an exemplary embodiment of the present application is shown in the figure.

[0056] Figure 5 The structure schematic diagram of the first GaN device provided by an exemplary embodiment of the present application is shown in the figure.

[0057] Figure 6 The structure schematic diagram of the second MOS chip provided by an exemplary embodiment of the present application is shown in the figure.

[0058] Figure 7 The side view schematic diagram of the second GaN chip provided by an exemplary embodiment of the present application is shown in the figure.

[0059] Figure 8A second top view schematic diagram of a GaN chip according to an exemplary embodiment of the present application;

[0060] Figure 9 A second structure schematic diagram of a GaN device according to an exemplary embodiment of the present application;

[0061] Figure 10 A first cross-sectional schematic diagram of a GaN chip according to an exemplary embodiment of the present application.

[0062] Wherein, the reference signs include: 1 - lead frame base island, 11 - first conductive region, 2 - conductive glue, 3 - substrate, 4 - MOS chip, 5 - GaN chip, 51 - second conductive region, 52 - through hole, 6 - lead, 61 - first bonding lead, 62 - second bonding lead, 63 - third bonding lead, 64 - fourth bonding lead, 65 - fifth bonding lead, 71 - gate of GaN device, 72 - drain of GaN device, S - source, D - drain, G - gate. DETAILED DESCRIPTION

[0063] In order to make the personnel in the art better understand the present application scheme, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0064] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, device, product or apparatus including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or apparatuses.

[0065] Based on the deficiencies of the prior art, the present application aims to first establish GaN on LV MOS (Low Voltage Metal-Oxide-Semiconductor Field-Effect Transistor) by GaN Die, MOS Die, lead frame base island, high-precision patch, thermal ultrasonic bonding, molding, etc. The Cascode structure GaN power device electrical characteristics are completed to realize the reduction of the volume of the Cascode GaN device, the simplification of the production process of the Cascode GaN device, the reduction of the product cost and the improvement of the electrical performance.

[0066] In one embodiment of the present application, a cascode GaN device is provided, as shown in the accompanying drawings, which comprises a lead frame base island 1, a MOS chip 4 and a GaN chip 5. Figures 2 to 5 As shown in the accompanying drawings, the source of the MOS chip 4 is arranged on the back surface thereof, and the gate and the drain of the MOS chip 4 are arranged on the front surface thereof.

[0067] As shown in the accompanying drawings, the source, the gate and the drain of the GaN chip 5 are arranged on the front surface thereof, and the back surface of the GaN chip 5 is provided with a second conductive area 51 which is electrically connected with the source on the front surface of the GaN chip 5. Figure 2 As shown in the accompanying drawings, the source, the gate and the drain of the GaN chip 5 are arranged on the front surface thereof, and the back surface of the GaN chip 5 is provided with a second conductive area 51 which is electrically connected with the source on the front surface of the GaN chip 5.

[0068] Figure 3 As shown in the accompanying drawings, the source, the gate and the drain of the GaN chip 5 are arranged on the front surface thereof, and the back surface of the GaN chip 5 is provided with a second conductive area 51 which is electrically connected with the source on the front surface of the GaN chip 5. Figure 4 As shown in the accompanying drawings, the source, the gate and the drain of the GaN chip 5 are arranged on the front surface thereof, and the back surface of the GaN chip 5 is provided with a second conductive area 51 which is electrically connected with the source on the front surface of the GaN chip 5.

[0069] Figure 5 As shown in the accompanying drawings, the source, the gate and the drain of the GaN chip 5 are arranged on the front surface thereof, and the back surface of the GaN chip 5 is provided with a second conductive area 51 which is electrically connected with the source on the front surface of the GaN chip 5.

[0070] The MOS chip 4 is arranged on the lead frame base island 1, and the back surface of the MOS chip 4 is connected with the first conductive area 11 and the source on the back surface thereof is electrically connected with the first conductive area 11. Specifically, the source on the back surface of the MOS chip 4 is welded or electrically connected with the first conductive area 11 on the lead frame base island 1 through conductive glue.

[0071] The GaN chip 5 is stacked on the MOS chip 4, and the second conductive area 51 on the back surface of the GaN chip 5 is electrically connected with the drain on the front surface of the MOS chip 4.

[0072] ​​Preferably, the GaN chip 5 provided in the embodiment is provided with a sapphire as an insulating substrate, the through hole 52 is arranged on the insulating substrate, and an integrated metal layer is synchronously grown on the front surface of the insulating substrate, the inner wall of the through hole 52 and the back surface of the insulating substrate, so that the source of the GaN chip 5 is arranged on the front surface and the back surface, as shown in Figure 10

[0073] The second conductive area 51 on the back surface of the GaN chip 5 is connected and electrically connected to the drain of the MOS chip 4 through conductive glue. Preferably, the area of the drain of the MOS chip 4 is larger than the area of the GaN chip 5, that is, the GaN chip 5 is arranged in the drain area on the front surface of the MOS chip 4. More preferably, the back surface of the GaN chip 5 is fully covered with a metal layer, and the metal layer is configured as the second conductive area 51. In this way, reliable connection of the source of the GaN chip 5 and the drain of the MOS chip 4 can be achieved.

[0074] In the embodiment, the gate of the MOS chip 4 and the gate of the GaN device are electrically connected through a bonding wire; the drain of the GaN chip 5 and the drain of the GaN device are electrically connected through a bonding wire; and the gate of the GaN chip 5 and the first conductive area 11 are electrically connected through a bonding wire.

[0075] The lead frame base island 1, the MOS chip 4 and the GaN chip 5 are encapsulated and formed by EMC resin. Figures 1 to 10 In the figure, S represents the source of the device / chip, D represents the drain of the device / chip, and G represents the gate of the device / chip.

[0076] The cascode GaN device provided in the embodiment combines the LV MOS backplane S electrode technology and the GaN-S electrode through hole technology to connect the S end to the backplane, adopts high-voltage GaN stacked on the LV MOS for packaging, and the lower surface of the LV MOS is the S electrode, that is, the MOS S does not need to be wired. The upper surface is the D and G electrodes, wherein the D electrode adopts a large area, the high-voltage GaN is attached to the D area of the LV MOS, and the GaN adopts a through hole to connect the S electrode to the backplane, so that the connection of the GaN S and the MOS D is realized through the patch. Finally, the electrodes that need to be wired are only the GaN D, the GaN G and the MOS G corresponding to the three bonding wires, and one substrate is saved, so that the volume of the cascode GaN device is reduced, the production process of the cascode GaN device is simplified, the product cost is reduced, and the electrical performance is improved.

[0077] The preparation method of the cascode GaN device provided in the embodiment includes the following steps.

[0078] ​The MOS chip is designed to have the source arranged on the back surface, and the gate and the drain arranged on the front surface; the GaN chip is designed to have the source, the gate and the drain arranged on the front surface, and the back surface also arranged with the source, and the sources on the front and back surfaces are electrically connected through a through hole with a metal layer on the inner wall.

[0079] The gate and the drain of the GaN device are arranged on the lead frame base island, and the source of the GaN device is arranged on the front surface of the lead frame base island. The gate and the drain of the GaN device are not directly connected, but are connected through the WB process, the source of the GaN device is arranged as the first conductive area on the front surface of the lead frame base island, and the pin end electric function pin1 / 2 / 3 corresponds to G gate / D drain / S source, or pin1 / 2 / 3 corresponds to G gate / S source / D drain, that is, Figure 5 The positions of the gate 71 of the GaN device and the drain 72 of the GaN device in the above formula can be interchanged.

[0080] The MOS chip and the conductive glue 2 are pasted on the lead frame base island through high-precision die bonding equipment, the source of the LVMOS is directly welded on the first conductive area of the lead frame base island to form the source of the GaN device, replacing the traditional wire bonding, almost eliminating the parasitic parameters generated by interconnection, reducing the key parameter Ron (on-resistance), increasing the current performance of the product, and improving the electrical performance of the product.

[0081] The back surface substrate of the GaN chip and the conductive glue are pasted on the front surface D electrode area of the LV MOS through high-precision die bonding equipment to realize the welding interconnection of the S electrode of the GaN chip and the D electrode of the LV MOS. Similarly, the source of the GaN chip and the drain on the front surface of the LVMOS are interconnected by welding, replacing the traditional wire bonding, almost eliminating the parasitic parameters generated by interconnection, reducing the key parameter Ron, and saving the substrate chip.

[0082] After the lead frame base island, the MOS chip and the GaN chip are sequentially connected and the adhesive chip die is cured, the WB product is cleaned with Plasma.

[0083] The cleaned WB product is bonded with a lead to obtain a GaN device semi-finished product, including: the gate of the GaN chip is electrically connected with the source of the GaN device on the front surface of the lead frame base island through the first bonding lead 61, the gate of the MOS chip is electrically connected with the gate of the GaN device through the second bonding lead 62, and the drain of the GaN chip is electrically connected with the drain of the GaN device through the third bonding lead 63.

[0084] The GaN device semi-finished products (dies, wires, lead frame base islands, etc.) are encapsulated with EMC resin through molding process to obtain the encapsulated product, thereby realizing the electrical and heat dissipation functions of the device.

[0085] The packaged product undergoes electroplating and cutting to remove excess parts such as the lead frame base island and pin fixing ribs, thus separating individual GaN devices. Finally, the individual GaN devices are subjected to electrical performance testing to eliminate defective products, obtaining GaN power devices that meet both electrical performance and appearance standards.

[0086] In another embodiment of the present invention, a common-source, common-gate GaN device is provided, such as... Figures 6 to 9 As shown, it includes a lead frame base island 1, a MOS chip 4, and a GaN chip 5.

[0087] like Figure 5 As shown, the lead frame base island 1 and the gate 71 and drain 72 of the GaN device are separately disposed. A first conductive region 11 is disposed on the upper surface, i.e. the front surface, of the lead frame base island 1. The first conductive region 11 is configured as the source of the GaN device.

[0088] like Figure 8 As shown, the MOS chip 4 has its source electrode on both its front and back sides, and its gate and drain electrodes are located on its front side. In this invention, the front and back sides are opposite to each other. In the accompanying drawings, the front side is the visible surface of the device / chip, and the back side is the invisible surface of the device / chip.

[0089] like Figure 6 and Figure 7 As shown, in this embodiment, the drain of the GaN chip 5 is disposed on its front side, and the source and gate of the GaN chip 5 are disposed on its back side.

[0090] The MOS chip 4 is disposed on the lead frame base island 1. The back side of the MOS chip 4 is attached to the first conductive region 11, and the source electrode on its back side is electrically connected to the first conductive region 11. Specifically, the source electrode on the back side of the MOS chip 4 is electrically connected to the first conductive region 11 on the lead frame base island 1 by soldering or by means of conductive adhesive.

[0091] The GaN chip 5 is stacked on the MOS chip 4, and the source of the GaN chip 5 is arranged above the drain of the MOS chip 4, and the gate of the GaN chip 5 is arranged above the source of the MOS chip 4; the source of the GaN chip 5 and the drain of the MOS chip 4, and the gate of the GaN chip 5 and the source of the MOS chip 4 are connected by synchronous soldering of eutectic welding. Preferably, the minimum distance between the source and the gate of the GaN chip is not less than 100 μm, which can ensure the insulation between different electrodes.

[0092] The gate of the MOS chip 4 is electrically connected with the gate of the GaN device through a bonding wire, and the drain of the GaN chip 5 is electrically connected with the drain of the GaN device through a bonding wire. Preferably, the source of the GaN chip 5 is arranged adjacent to the gate thereof, and the source of the MOS chip 4 is arranged adjacent to the drain thereof, and the gate of the MOS chip on the front surface is arranged on the side away from the drain, so that the bonding wire is less likely to intersect.

[0093] The lead frame base island 1, the MOS chip 4 and the GaN chip 5 are molded by EMC resin.

[0094] The common-source common-gate GaN device provided in the embodiment combines the LV MOS backplane and the S electrode technology (double S electrode) on the front surface, the GaN back surface is provided with a local G electrode, and the front surface is not provided with a G electrode, and the MOS chip and the GaN chip are eutectic welded, so that the G electrode of the GaN and the S electrode of the MOS, the S electrode of the GaN and the D electrode of the MOS are respectively interconnected, and finally only two groups of GaN D and MOS G are wired. Compared with the above embodiment, the wiring is further reduced, and one substrate (substrate chip) is also saved, the volume of the Cascode GaN device is reduced, the production process of the Cascode GaN device is simplified, the product cost is reduced, and a GaN device with better electrical performance can be obtained.

[0095] The common-source common-gate GaN device provided in the embodiment has a preparation method including the following steps.

[0096] The MOS chip and the GaN chip are designed, the MOS chip is provided with its source on its front surface and back surface, the gate and the drain of the MOS chip are provided on its front surface, the drain of the GaN chip is provided on its front surface, and its source and gate are provided on its back surface. Preferably, the back surface of the MOS chip is entirely covered with a metal layer and serves as its source, a partial area of the front surface of the MOS chip is provided with its source, and the source is provided adjacent to the drain on the front surface. A partial area of the back surface of the GaN chip is provided with its gate, another partial area of the back surface of the GaN chip is provided with its source, the back surface of the GaN chip is not provided with its drain, a partial area of the front surface of the GaN chip is provided with its drain, or the front surface of the GaN chip is entirely covered with its drain.

[0097] The gate and the drain of the GaN device are designed separately from the lead frame base island, and the front surface of the lead frame base island is provided with the source of the GaN device. The gate and the drain of the GaN device are not directly connected, but are connected by the WB process, the source of the GaN device is provided as the first conductive area on the front surface of the lead frame base island, and the pin end electrical function pin1 / 2 / 3 of the GaN device corresponds to G gate / D drain / S source, or pin1 / 2 / 3 corresponds to G gate / S source / D drain, that is, Figure 5 The positions of the gate 71 of the GaN device and the drain 72 of the GaN device in the above formula can be interchanged.

[0098] The MOS chip is pasted to the lead frame base island by high-precision die bonding equipment, the source of the LVMOS of the application is directly welded to the first conductive area of the lead frame base island to form the source of the GaN device, replacing the traditional wire bonding, almost eliminating the parasitic parameters generated by interconnection, reducing the key parameter Ron (on-resistance) of the product, increasing the current performance of the product, and improving the electrical performance of the product.

[0099] The GaN chip is pasted on the MOS chip by high-precision die bonding equipment, and the source of the GaN chip is provided above the drain of the MOS chip, and the gate of the GaN chip is provided above the source of the MOS chip. The source of the GaN chip and the drain of the MOS chip, and the gate of the GaN chip and the source of the MOS chip are synchronously welded by eutectic welding. The GaN G electrode and the MOS S electrode are interconnected and welded by using the eutectic welding technology to replace the traditional wire bonding, the GaN S electrode and the MOS D electrode are interconnected and welded to replace the traditional wire bonding, which can reduce the Ron parameter of the product and improve the electrical performance of the product.

[0100] After the glue for bonding / welding the die of the lead frame base island, the MOS chip and the GaN chip is cured, the WB product is cleaned by Plasma.

[0101] The bonded lead of the cleaned WB product is obtained to obtain a GaN device semi-finished product, including: the gate of the MOS chip is electrically connected with the gate of the GaN device through the fourth bonding lead 64, and the drain of the GaN chip is electrically connected with the drain of the GaN device through the fifth bonding lead 65.

[0102] The GaN device semi-finished product (Die and Wire and lead frame base island, etc.) is packaged by using the EMC resin through a molding process to obtain a packaged product, and the electrical and heat dissipation functions of the device are realized.

[0103] The packaged product is electroplated and cut, and the excess part such as the lead frame base island and the pin end fixing rib is cut off, and a single GaN device is separated. Finally, the single GaN device is electrically tested to remove defective products, and a GaN power device with qualified electrical performance and appearance is obtained.

[0104] It should be noted that the above-mentioned common-source common-gate GaN device preparation method embodiments and the corresponding common-source common-gate GaN device embodiments belong to the same inventive concept, and the entire contents of the common-source common-gate GaN device embodiments are incorporated by reference into the corresponding common-source common-gate GaN device preparation embodiments.

[0105] It should be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0106] The above is only a specific embodiment of the present application, and it should be noted that for ordinary skilled persons in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should be regarded as the protection scope of the present application.

Claims

1. A cascode GaN device, characterized in that, It includes a lead frame base island (1), a MOS chip (4), and a GaN chip (5). A first conductive region (11) is provided on the lead frame base island (1), and the first conductive region (11) is configured as the source of the GaN device; The source of the MOS chip (4) is disposed on its back side, and the gate and drain of the MOS chip (4) are disposed on its front side; the MOS chip (4) is disposed in the first conductive region (11), and the source on its back side is electrically connected to the first conductive region (11); The GaN chip (5) is stacked on the MOS chip (4), and the GaN chip (5) is electrically connected to the MOS chip (4) in the following manner: The source, gate and drain of the GaN chip (5) are disposed on its front side, and a second conductive region (51) is disposed on the back side of the GaN chip (5). The second conductive region (51) is electrically connected to the source on the front side of the GaN chip (5), and the second conductive region (51) on the back side of the GaN chip (5) is electrically connected to the drain on the front side of the MOS chip (4). or, The MOS chip (4) also has its source on the front side, the drain of the GaN chip (5) is located on its front side, and the source and gate of the GaN chip (5) are located on its back side. The source on the back side of the GaN chip (5) is electrically connected to the drain on the front side of the MOS chip (4), and the gate on the back side of the GaN chip (5) is electrically connected to the source on the front side of the MOS chip (4).

2. The cascode GaN device according to claim 1, characterized in that, The source, gate and drain of the GaN chip (5) are disposed on its front side, and a second conductive region (51) is disposed on the back side of the GaN chip (5). The second conductive region (51) is electrically connected to the source of the GaN chip (5) on the front side through a through hole (52). A conductive layer is disposed on the inner wall of the through hole (52). The second conductive area (51) on the back of the GaN chip (5) is bonded and electrically connected to the drain of the MOS chip (4) by conductive adhesive.

3. The cascode GaN device according to claim 2, characterized in that, The GaN chip (5) also includes an insulating substrate, on which the through hole (52) is provided. Metal layers are grown simultaneously on the front side of the insulating substrate, the inner wall of the through hole (52) and the back side of the insulating substrate to form the source electrode and the second conductive region (51) of the GaN chip (5) that are electrically connected.

4. The cascode GaN device according to claim 2, characterized in that, The source electrode on the back of the MOS chip (4) is electrically connected to the first conductive region (11) on the lead frame base island (1) by welding or by conductive adhesive. The gate of the MOS chip (4) is electrically connected to the gate of the GaN device through bonding leads; The drain of the GaN chip (5) is electrically connected to the drain of the GaN device through bonding leads; The gate of the GaN chip (5) is electrically connected to the first conductive region (11) via a bonding wire.

5. The cascode GaN device according to claim 1, characterized in that, The drain area of ​​the MOS chip (4) is larger than the area of ​​the GaN chip (5); and / or, The back of the GaN chip (5) is fully covered by a metal layer, which is configured as the second conductive region (51).

6. The cascode GaN device according to claim 1, characterized in that, The MOS chip (4) also has its source on the front side, the source of the GaN chip (5) is disposed above the drain of the MOS chip (4), and the gate of the GaN chip (5) is disposed above the source of the MOS chip (4). The source of the GaN chip (5) and the drain of the MOS chip (4), as well as the gate of the GaN chip (5) and the source of the MOS chip (4), are synchronously welded together by eutectic bonding.

7. The cascode GaN device according to claim 6, characterized in that, The source of the MOS chip (4) on the back side is electrically connected to the first conductive region (11) on the lead frame base island (1) by welding or by conductive adhesive; the gate of the MOS chip (4) is electrically connected to the gate of the GaN device by bonding wire; the drain of the GaN chip (5) is electrically connected to the drain of the GaN device by bonding wire.

8. The cascode GaN device according to claim 6, characterized in that, The source and gate of the GaN chip (5) are arranged adjacent to each other, the source and drain of the MOS chip (4) are arranged adjacent to each other, and the gate on the front side of the MOS chip (4) is arranged on the side away from its drain.

9. The cascode GaN device according to claim 1, characterized in that, The leadframe base island (1) is configured as an independent base island, and the leadframe base island (1) is separated from the gate and drain of the GaN device; and / or, The lead frame base island (1), MOS chip (4) and GaN chip (5) are encapsulated in EMC resin.

10. A method for fabricating a cascode GaN device, characterized in that, Includes the following steps: Design and fabricate MOS chips and GaN chips. The source of the MOS chip is located on its back side, and the gate and drain of the MOS chip are located on its front side. The source, gate and drain of the GaN chip are located on its front side, and the source of the GaN chip is also located on its back side. The design separates the leadframe base island and the gate and drain of the GaN device, with the source of the GaN device located on the front side of the leadframe base island. The MOS chip is placed on the lead frame base island, and the source on the back of the MOS chip is electrically connected to the source of the GaN device on the front of the lead frame base island by conductive adhesive or by soldering. The GaN chip is disposed on the MOS chip, and the source on the back of the GaN chip is electrically connected to the drain on the front of the MOS chip through conductive adhesive. GaN device semi-finished product is obtained by electrically connecting other electrodes through bonding wires, including: electrically connecting the gate of the MOS chip to the gate of the GaN device through bonding wires, electrically connecting the drain of the GaN chip to the drain of the GaN device through bonding wires, and electrically connecting the gate of the GaN chip to the source of the GaN device on the front side of the lead frame base island through bonding wires. GaN device semi-finished products are encapsulated using EMC resin through injection molding.

11. A method for fabricating a cascode GaN device, characterized in that, Includes the following steps: Design and fabricate MOS chips and GaN chips. The source of the MOS chip is located on both the front and back sides. The gate and drain of the MOS chip are located on the front side. The drain of the GaN chip is located on the front side and the source and gate are located on the back side. The design separates the leadframe base island and the gate and drain of the GaN device, with the source of the GaN device located on the front side of the leadframe base island. The MOS chip is placed on the lead frame base island, and the source on the back of the MOS chip is electrically connected to the source of the GaN device on the front of the lead frame base island by conductive adhesive or by soldering. The GaN chip is disposed on the MOS chip, with the source of the GaN chip disposed above the drain of the MOS chip and the gate of the GaN chip disposed above the source of the MOS chip. The source of the GaN chip and the drain of the MOS chip, as well as the gate of the GaN chip and the source of the MOS chip, are simultaneously welded using eutectic bonding. To obtain a GaN device semi-finished product by electrically connecting other electrodes through bonding wires, the method includes: electrically connecting the gate of the MOS chip to the gate of the GaN device through bonding wires, and electrically connecting the drain of the GaN chip to the drain of the GaN device through bonding wires. GaN device semi-finished products are encapsulated using EMC resin through injection molding.

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