A semiconductor structure and a method of fabricating the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, and comprises the following steps: providing a substrate comprising a first device area and a second device area; forming a gate stack material layer and a protection material layer which are sequentially stacked on the upper surface of the substrate, the thickness of the protection material layer above the first device area is less than the thickness of the protection material layer above the second device area; based on etching of the gate stack material layer and the protection material layer, a plurality of first gate units and a plurality of second gate units which are arranged at intervals are respectively formed above the first device area and the second device area, wherein the protection material layer after etching forms a protection layer; a groove is formed in the substrate between two adjacent second gate units, and the protection layer on the top of the second gate units is synchronously etched and thinned when the groove is formed; and an epitaxial layer is formed in the groove to form an epitaxial structure. The semiconductor structure and the preparation method thereof avoid exposure of the gate layer above the second device area, improve the gate height difference, and improve the device yield.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] In the development of 28nm process devices, the performance optimization of PMOS (P-channel Metal-Oxide-Semiconductor) devices is one of the key directions. According to the physical characteristics of PMOS devices, the greater the compressive stress that PMOS devices bear, the more significant the driving current improvement effect, and the enhancement of driving current is directly related to the optimization of device electrical performance.

[0003] To achieve this goal, the industry generally uses germanium silicon epitaxy (EPI) technology to effectively increase the compressive stress of PMOS devices and thus improve the electrical performance of the devices. However, in order to ensure that germanium silicon epitaxy only precisely acts on the PMOS region, it is necessary to clearly distinguish PMOS from NMOS (N-channel Metal-Oxide-Semiconductor), so the PMOS region will be etched additionally.

[0004] However, additional etching will cause the oxide layer and nitride layer on the top of the gate structure in the PMOS device to be etched for protection of the gate, which on the one hand leads to a height difference between the gate structures of NMOS devices and PMOS devices, especially the shoulder height problem, causing device characteristics to be mismatched, ultimately affecting the switching speed and power consumption of the device, and on the other hand, in subsequent processes, the exposed gate structure can also cause metal ions in the metal electrode to enter the gate layer, which not only affects the performance of the device, but also interferes with the normal process. SUMMARY

[0005] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof aiming at the problem that the existing technology causes the PMOS to have an epitaxial layer, which exposes the gate layer in the PMOS and causes a height difference between the gate structures of PMOS and NMOS, affecting the switching speed of the device and the process.

[0006] To achieve the above-mentioned purpose, on the one hand, the present application provides a preparation method of a semiconductor structure, comprising the following steps:

[0007] providing a substrate, the substrate comprising a first device region and a second device region;

[0008] forming a gate stack material layer and a protection material layer stacked in sequence on the upper surface of the substrate, the thickness of the protection material layer above the first device region being less than the thickness of the protection material layer above the second device region;

[0009] Based on etching of the gate stack material layer and the protective material layer, a plurality of first gate units arranged at intervals are formed above the first device region, and a plurality of second gate units arranged at intervals are formed above the second device region, wherein the protective material layer after etching forms a protective layer;

[0010] A trench is formed in the substrate between two adjacent second gate units, and at the same time of forming the trench, the protective layer on the top of the second gate unit is etched and thinned synchronously;

[0011] An epitaxial layer is formed in the trench to form an epitaxial structure.

[0012] In one embodiment, the thickness of the protective material layer above the first device region and the thickness of the protective material layer above the second device region have a preset difference, and the etching thickness of the top of the second gate unit in the process of forming the trench is equal to the preset difference.

[0013] In one embodiment, forming the protective material layer comprises the following steps:

[0014] The protective material layer with a preset thickness is formed on the upper surface of the gate stack material layer;

[0015] The protective material layer above the second device region is thinned.

[0016] In one embodiment, forming the first gate unit and the second gate unit comprises the following steps:

[0017] The gate stack material layer and the protective material layer above the first device region and the second device region are etched respectively to obtain a gate stack and the protective layer;

[0018] A side wall structure is formed on the exposed surface of the gate stack and the protective layer above the first device region and the second device region after etching, and the gate stack, the protective layer and the side wall structure above the first device region constitute the first gate unit, and the gate stack, the protective layer and the side wall structure above the second device region constitute the second gate unit.

[0019] In one embodiment, etching the protective layer on the top of the second gate unit also comprises etching part of the side wall structure on the top of the second gate unit.

[0020] In one embodiment, forming the trench comprises the following steps:

[0021] dry-etching the substrate between adjacent second gate units from the substrate surface opening to form a pre-trench;

[0022] wet-etching the pre-trench to obtain the trench.

[0023] In one embodiment, the protective layer on top of the second gate unit is synchronously etched and thinned when the pre-trench is formed.

[0024] The present application also provides a semiconductor structure, comprising:

[0025] a substrate comprising a first device region and a second device region;

[0026] a first gate unit and a second gate unit, the first gate unit and the second gate unit are respectively located above the first device region and the second device region, and the first gate unit and the second gate unit each comprise a gate stack and a protective layer, the top of the first gate unit and the top of the second gate unit are flush;

[0027] an epitaxial structure comprising a trench in the substrate between two adjacent second gate units and an epitaxial layer filling the trench.

[0028] In one embodiment, the first gate unit and the second gate unit each further comprise a side wall structure, the side wall structure comprises a blocking layer, an insulating layer and an isolation layer which are sequentially stacked.

[0029] In one embodiment, the isolation layer in the first gate unit covers the insulating layer sidewall and the protective layer upper surface, the isolation layer in the second gate unit covers the insulating layer sidewall, and the top of the isolation layer in the first gate unit and the top of the protective layer in the second gate unit are flush.

[0030] The semiconductor structure and the preparation method thereof have the following beneficial effects: when the first gate unit and the second gate unit are formed above the first device area and the second device area respectively based on etching of the gate stack material layer and the protective material layer, the thickness of the protective material layer above the first device area is less than the thickness of the protective material layer above the second device area, so that in the process of etching and thinning the second gate unit top synchronously to form the epitaxial structure in the substrate of the second device area, the problem that the protective layer of the second gate unit top is exposed after being etched, thereby affecting the device performance and the process progress, is avoided, the product yield is effectively improved, and the smooth progress of the subsequent process is ensured; in addition, in some embodiments, the thickness of the protective material layer above the first device area and the thickness of the protective material layer above the second device area have a preset difference, and the etching thickness of the second gate unit top in the process of forming the trench is equal to the preset difference, so that after the second gate unit top is synchronously etched and thinned, the first gate unit top and the second gate unit top can be kept flush, and the problem that the transistor characteristics are not matched due to the inconsistent height of the first gate unit and the second gate unit, thereby affecting the overall performance of the device, is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0032] Figure 1 The flowchart of the preparation method of the semiconductor structure provided in an embodiment;

[0033] Figure 2 The cross-sectional structure schematic diagram of the preparation method of the semiconductor structure provided in an embodiment after the protective material layer is formed on the upper surface of the gate stack material layer;

[0034] Figure 3 The cross-sectional structure schematic diagram of the preparation method of the semiconductor structure provided in an embodiment after the first shielding layer is formed;

[0035] Figure 4 The cross-sectional structure schematic diagram of the preparation method of the semiconductor structure provided in an embodiment after the protective material layer above the first device area is thinned;

[0036] Figure 5 The cross-sectional structure schematic diagram of the preparation method of the semiconductor structure provided in an embodiment after the first shielding layer is removed;

[0037] Figure 6A cross-sectional structure schematic diagram after forming a barrier layer and an insulating layer in a preparation method of a semiconductor structure provided in an embodiment;

[0038] Figure 7 A cross-sectional structure schematic diagram after forming a first gate unit and a second gate unit in a preparation method of a semiconductor structure provided in an embodiment;

[0039] Figure 8 A cross-sectional structure schematic diagram after forming a second shielding layer in a preparation method of a semiconductor structure provided in an embodiment;

[0040] Figure 9 A cross-sectional structure schematic diagram after forming a pre-trench in a preparation method of a semiconductor structure provided in an embodiment;

[0041] Figure 10 A cross-sectional structure schematic diagram after forming an epitaxial layer in a preparation method of a semiconductor structure provided in an embodiment.

[0042] Explanation of reference signs:

[0043] 1-substrate, 11-first device region, 12-second device region, 2-gate stack material layer, 21-gate dielectric material layer, 22-gate material layer, 23-buffer material layer, 3-protective material layer, 31-first shielding layer, 4-first gate unit, 41-second shielding layer, 5-second gate unit, 6-epitaxial structure, 61-trench, 611-pre-trench, 62-epitaxial layer, 7-gate stack, 71-gate dielectric layer, 72-gate layer, 73-buffer layer, 8-protective layer, 9-side wall structure, 91-barrier layer, 92-insulating layer, 93-isolation layer. DETAILED DESCRIPTION

[0044] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present application is more thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0046] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0047] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0048] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0049] Embodiments of the application are described herein with reference to the drawings, which show ideal embodiments (and intermediate structures) of the application. Variations in the shapes of the regions shown are expected due to, for example, manufacturing techniques and / or tolerances, and therefore embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an implanted region that is shown as a rectangle typically has rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Thus, the regions shown in the drawings are schematic in nature and their shapes are not intended to represent the actual shape of a region of a device and are not intended to limit the scope of the application.

[0050] Referring now to the drawings, wherein like reference numerals refer to similar or identical elements throughout the several views, and initially to FIG. 1, there is shown a semiconductor structure 100 according to an embodiment of the present application. Figures 1 to 10 The present application provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0051] S1: providing a substrate 1, the substrate comprising a first device region 11 and a second device region 12;

[0052] S2: forming a gate stack material layer 2 and a protection material layer 3 successively on the surface of the substrate 1, the thickness of the protection material layer 3 above the first device region 11 is less than the thickness of the protection material layer 3 above the second device region 12;

[0053] S3: based on the gate stack material layer 2 and the protection material layer 3, forming a plurality of first gate units 4 arranged at intervals above the first device region 11 and a plurality of second gate units 5 arranged at intervals above the second device region 12, respectively, wherein the protection material layer 3 after etching forms a protection layer 8;

[0054] S4: forming a trench 61 in the substrate 1 between two adjacent second gate units 5, and at the same time of forming the trench 61, the top of the second gate units is synchronously etched and thinned;

[0055] S5: forming an epitaxial layer 62 in the trench 61 to form an epitaxial structure 6.

[0056] The preparation method of the semiconductor structure avoids the problem that, when the first gate unit 4 and the second gate unit 5 are formed above the first device region 11 and the second device region 12 respectively based on etching of the protection material layer 3 and the gate stack material layer 2, the gate material layer 22 in the second gate unit 5 is exposed after the protection material layer 3 on the top of the second gate unit 5 is etched, thereby affecting the device performance and the process progress, effectively improves the product yield, and provides a guarantee for the smooth progress of the subsequent process.

[0057] Step S1 is performed to provide a substrate 1, which includes a first device region 11 and a second device region 12.

[0058] The material of the substrate 1 includes silicon, but can also include one or more other semiconductor materials, such as germanium, a silicon-germanium alloy, a compound semiconductor (for example, gallium nitride, gallium arsenide, etc.) or an alloy thereof, an oxide semiconductor (for example, zinc oxide, gallium oxide, etc.) or a combination thereof. In the present embodiment, the substrate 1 includes a plurality of device regions for forming NMOS devices or PMOS devices, and in the present embodiment, the first device region 11 is an NMOS device region for forming an NMOS device, and the second device region 12 is a PMOS device region for forming a PMOS device.

[0059] Referring to Figures 2 to 5 Step S2 is performed to form, on the upper surface of the substrate 1, a gate stack material layer 2 and a protection material layer 3 stacked in sequence, the thickness of the protection material layer 3 above the first device region 11 being less than the thickness of the protection material layer 3 above the second device region 12.

[0060] The gate stack material layer 2 is used to form a base material layer of the gate structure above the first device region 11 and the second device region 12, and the gate stack material layer 2 comprises a gate dielectric material layer 21, a gate material layer 22 and a buffer material layer 23 which are sequentially stacked. The material of the gate dielectric material layer 21 comprises silicon dioxide or other suitable material; the material of the gate material layer 22 comprises polysilicon or other suitable material; and the material of the buffer material layer 23 comprises silicon nitride or other suitable material. The method for forming the gate dielectric material layer 21 comprises chemical vapor deposition, physical vapor deposition or other suitable method; the method for forming the gate material layer 22 comprises chemical vapor deposition, physical vapor deposition or other suitable method; and the method for forming the buffer material layer 23 comprises chemical vapor deposition, physical vapor deposition or other suitable method. The thickness of the gate dielectric material layer 21, the gate material layer 22 and the buffer material layer 23 can be selected according to actual conditions without limitation in the case of meeting the performance of the semiconductor structure.

[0061] In some embodiments, the step S2 further comprises steps S21-S22, and the forming of the protective material layer 3 comprises the following steps:

[0062] S21: forming the protective material layer 3 with a preset thickness on the upper surface of the gate stack material layer 2. The material of the protective material layer 3 comprises silicon oxynitride, silicon oxide or other suitable material. The method for forming the protective material layer 3 comprises chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable method. The preset thickness can be selected according to actual conditions without limitation in the case of meeting the performance of the semiconductor structure. The protective material layer 3 is used to prevent the gate stack material layer from being chemically corroded or physically damaged.

[0063] S22: thinning the protective material layer 3 above the second device region 12. The thinning of the protective material layer 3 above the second device region 12 comprises the following steps: forming a first shielding layer 31 on the upper surface of the protective material layer 3 above the first device region 11, thinning the protective material layer 3 above the second device region 12 based on the first shielding layer 31, and removing the first shielding layer 31. The first shielding layer 31 is used to protect the protective material layer 3 above the first device region 11, and the first shielding layer 31 comprises photoresist or other suitable shielding material. The thickness of the first shielding layer 31 can be selected according to actual conditions without limitation in the case of meeting the performance of the semiconductor structure. The method for thinning the protective material layer 3 above the second device region 12 comprises dry etching, wet etching, chemical mechanical polishing or other suitable method.

[0064] In addition, the thickness of the protective material layer 3 above the first device region 11 and the thickness of the protective material layer 3 above the second device region 12 have a preset difference. In some embodiments, to ensure that the top of the first gate unit 4 and the second gate unit 5 formed subsequently are flush, the thickness of the thinned part of the protective material layer 3 above the second device region 12 during the formation of the protective material layer 3 is the same as the preset difference. The preset difference is in the range of 8nm-15nm, and the value of the preset difference is 10nm, for example. The preset difference can be obtained by calculating the height difference between the second device region 12 and the gate structure of the first device region 11 after the epitaxial structure 6 is formed in the second device region 12 in the prior art.

[0065] Referring to Figures 6 to 7 , step S3 is performed to form a plurality of first gate units 4 arranged at intervals above the first device region 11 and a plurality of second gate units 5 arranged at intervals above the second device region 12 based on the gate stack material layer 2 and the protective material layer 3. The etched protective material layer 3 forms a protective layer 8.

[0066] In some embodiments, step S3 further includes steps S31-S32, and the formation of the first gate unit 4 and the second gate unit 5 includes the following steps:

[0067] S31: The gate stack material layer 2 and the protective material layer 3 above the first device region 11 and the second device region 12 are etched to obtain a gate stack layer 7 and a protective layer 8. The etching method of the gate stack material layer 2 and the protective material layer 3 includes dry etching, wet etching or other suitable methods. The etched gate stack layer 7 includes a gate dielectric layer 71, a gate layer 72 and a buffer layer 73 which are sequentially stacked. The gate dielectric layer 71 is used as an insulating material between the gate layer 72 and the substrate 1 to prevent the current from flowing directly from the gate layer 72 to the substrate, thereby ensuring that the gate voltage can effectively control the formation of the channel. The gate layer 72 is a key part of controlling the formation of the channel and the flow of current, and the transistor is turned on and off by changing the gate voltage. The buffer layer 73 can be used as a stress buffer layer to reduce the degradation of device performance caused by stress in the gate structure. In addition, the buffer layer 73 can be used as an etching stop layer during the process to prevent over-etching during the subsequent etching of the second gate unit 5 when forming the epitaxial structure 6, thereby affecting the device yield. In some embodiments, the height difference between the top of the protective layer 8 above the first device region 11 and the top of the protective layer 8 above the second device region 12 after etching is equal to the preset difference.

[0068] S32: Forming a side wall structure 9 on the exposed surface of the etched gate stack 7 and the protection layer 8, the gate stack 7, the protection layer 8 and the side wall structure 9 above the first device region 11 form the first gate unit 4, and the gate stack 7, the protection layer 8 and the side wall structure 9 above the second device region 12 form the second gate unit 5.

[0069] The side wall structure 9 is used to provide physical support for the gate structure, prevent current flow from the gate to the source and drain regions, and reduce parasitic capacitance. The side wall structure 9 includes a blocking layer 91, an insulating layer 92 and an isolation layer 93 stacked in sequence, the blocking layer 91 covers the sidewall of the gate stack 7 and the protection layer 8, the insulating layer 92 covers the sidewall of the blocking layer 91, and the isolation layer 93 covers the sidewall of the insulating layer 92 and the upper surface of the protection layer 8. The blocking layer 91 helps to protect the gate from chemical corrosion in subsequent process steps, the insulating layer 92 provides additional insulation performance as an intermediate layer, while also helping to reduce parasitic capacitance between the gate and the source / drain regions, and the isolation layer 93 is designed to provide mechanical protection and further chemical stability, ensuring that the side wall structure 9 remains intact in subsequent process steps. The material of the blocking layer 91 includes silicon nitride or other suitable materials; the material of the insulating layer 92 includes silicon dioxide or other suitable materials; and the material of the isolation layer 93 includes silicon nitride or other suitable materials. The method of forming the blocking layer 91 includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method of forming the insulating layer 92 includes chemical vapor deposition, physical vapor deposition or other suitable methods; and the method of forming the isolation layer 93 includes chemical vapor deposition, physical vapor deposition or other suitable methods. The thickness of the blocking layer 91, the insulating layer 92 and the isolation layer 93 can be selected according to actual conditions, which is not limited herein, provided that the performance of the semiconductor structure is met. The side wall structure 9 can also include other stack structures, and is not limited to the stack structure composed of the blocking layer 91, the insulating layer 92 and the isolation layer 93 in the embodiment.

[0070] Please refer to Figures 8 to 10 , steps S4-S5 are performed to form a trench 61 in the substrate 1 between two adjacent second gate units 5, and the top of the second gate unit is etched synchronously while the trench 61 is formed; and an epitaxial layer 62 is formed in the trench 61 to form an epitaxial structure 6.

[0071] In some embodiments, step S4 further includes steps S41-S42, and forming the trench 61 includes the following steps:

[0072] S41: from the substrate 1 surface opening, dry etching the substrate 1 between the adjacent second gate units 5 to form a pre-groove 611; wherein the bottom of the pre-groove 611 is spaced apart from the bottom of the substrate 1; the pre-groove 611 is obtained by dry etching, which can quickly achieve the required depth of the pre-groove 611; in the case of meeting the performance of the semiconductor structure, the spacing distance between the bottom of the pre-groove 611 and the bottom of the substrate 1 can be selected according to the actual situation, which is not limited here.

[0073] In the process of forming the pre-groove 611, a second shielding layer 41 is formed above the first device area 11 to cover the first gate unit 4, and based on the second shielding layer 41, the substrate 1 between the second gate units 5 is etched to form a groove 61 in the substrate 1, and the second shielding layer 41 is removed. The second shielding layer 41 is used to protect the first gate unit 4 from being affected in the subsequent process. The second shielding layer 41 includes photoresist or other suitable shielding material; in the case of meeting the performance of the semiconductor structure, the thickness of the second shielding layer 41 can be selected according to the actual situation, which is not limited here.

[0074] In addition, in the process of forming the pre-groove 611, the protective layer 8 on the top of the second gate unit 5 is etched and thinned synchronously, and the etching and thinning of the protective layer 8 on the top of the second gate unit 5 also includes etching the partial side wall structure 9 on the top of the second gate unit 5, that is, the etching and thinning of the protective layer 8 on the top of the second gate unit 5 also includes etching the isolation layer 93 on the top of the second gate unit 5. Therefore, based on the second gate unit 5 formed by the protective material layer 3 with a large thickness, in the etching process, the problem that the gate layer 72 in the second gate unit 5 is exposed after the top of the second gate unit 5 is etched, thereby affecting the device performance and the process progress, is avoided, which effectively improves the product yield and provides a guarantee for the smooth progress of the subsequent process.

[0075] In some embodiments, the thickness of the protective material layer 3 above the first device area 11 and the thickness of the protective material layer 3 above the second device area 12 have a preset difference, and in the process of forming the groove 61, the etching thickness of the top of the second gate unit 5 is equal to the preset difference, that is, the etching thickness of the isolation layer 93 and the protective layer 8 on the top of the second gate unit 5 is equal to the preset difference. Therefore, after the top of the second gate unit 5 is etched and thinned synchronously, the top of the first gate unit 4 and the top of the second gate unit 5 remain flush, avoiding the inconsistent height of the first gate unit 4 and the second gate unit 5 leading to the mismatch of the transistor characteristics and thereby affecting the overall performance of the device.

[0076] S42: wet etching the pre-trench 611 to obtain the trench 61. The pre-trench 611 is etched by wet etching, which is isotropic etching, and thus the shape of the sigma trench can be more regular. For example, the shape of the sigma trench is hexagonal.

[0077] Specifically, the method for forming the epitaxial layer 62 includes chemical vapor deposition, physical vapor deposition or other suitable methods. The material of the epitaxial layer 62 includes germanium-silicon or other suitable materials. The epitaxial structure 6 is used to increase the compressive stress of the device above the second device region 12, so as to meet the requirement of the semiconductor structure for the driving current of the device above the second device region 12, thereby improving the overall response speed of the device.

[0078] It should be understood that, although Figure 1 The steps in the flowchart of the method are shown in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 1 At least part of the steps in the method can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0079] Please continue to refer to Figure 10 The present application also provides a semiconductor structure, which is prepared by the above-mentioned method for preparing a semiconductor structure, and includes a substrate 1, a first gate unit 4, a second gate unit 5 and an epitaxial structure 6. The substrate 1 includes a first device region 11 and a second device region 12. The first gate unit 4 and the second gate unit 5 are located above the first device region 11 and the second device region 12, respectively. The first gate unit 4 and the second gate unit 5 each include a gate electrode layer 7 and a protection layer 8. The top of the first gate unit 4 is flush with the top of the second gate unit 5. The epitaxial structure 6 includes a trench 61 in the substrate 1 between two adjacent second gate units 5 and an epitaxial layer 62 filling the trench 61.

[0080] In some embodiments, the first gate unit 4 and the second gate unit 5 each further include a side wall structure 9, which includes a blocking layer 91, an insulating layer 92 and an isolation layer 93 stacked in sequence.

[0081] Specifically, the side wall structure of the first gate unit 4 and the second gate unit 5 are both covered by the barrier layer 91 on the side wall of the gate stack 7 and the protection layer 8, and the insulating layer 92 covers the side wall of the barrier layer 91, but the isolation layer 93 in the first gate unit 4 covers the side wall of the insulating layer 92 and the upper surface of the protection layer 8, and the isolation layer 93 in the second gate unit 5 covers the side wall of the insulating layer 92, and the top of the isolation layer 93 in the first gate unit 4 is flush with the top of the protection layer 8 in the second gate unit 5.

[0082] By keeping the top of the first gate unit 4 flush with the top of the second gate unit 5 in the semiconductor structure formed by the preparation method of the semiconductor structure described above, the problem that the inconsistent height of the first gate unit 4 and the second gate unit 5 leads to the mismatch of the transistor characteristics and further affects the overall performance of the device is avoided.

[0083] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0084] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0085] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a first device region and a second device region; A gate stack material layer and a protective material layer are formed sequentially on the upper surface of the substrate, wherein the thickness of the protective material layer above the first device region is less than the thickness of the protective material layer above the second device region; Based on the etching of the gate stack material layer and the protective material layer, a plurality of spaced first gate cells are formed above the first device region and a plurality of spaced second gate cells are formed above the second device region, wherein the etched protective material layer forms a protective layer; A trench is formed in the substrate between two adjacent second gate cells, and at the same time the trench is formed, the protective layer on top of the second gate cell is simultaneously etched and thinned. An epitaxial layer is formed within the trench to form an epitaxial structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, There is a preset difference between the thickness of the protective material layer above the first device region and the thickness of the protective material layer above the second device region, and during the formation of the trench, the etching thickness at the top of the second gate cell is equal to the preset difference.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming the protective material layer includes the following steps: A protective material layer of a predetermined thickness is formed on the upper surface of the gate stack material layer; The protective material layer located above the second device region is thinned.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of the first gate cell and the second gate cell includes the following steps: The gate stack material layer and the protective material layer above the first device region and the second device region are etched respectively to obtain the gate stack and the protective layer; Sidewall structures are formed on the exposed surfaces of the gate stack and the protective layer above the etched first device region and second device region, respectively. The gate stack, the protective layer and the sidewall structure above the first device region constitute the first gate cell, and the gate stack, the protective layer and the sidewall structure above the second device region constitute the second gate cell.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The etching process for thinning the protective layer at the top of the second gate cell also includes etching a portion of the sidewall structure at the top of the second gate cell.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming the trench includes the following steps: Dry etching is performed on the substrate between adjacent second gate cells through an opening on the substrate surface to form a pre-trench; The pre-groove is wet-etched to obtain the groove.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, During the formation of the pre-trench, the protective layer on top of the second gate cell is simultaneously etched and thinned.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing a semiconductor structure as described in any one of claims 1 to 7, comprising: The substrate includes a first device region and a second device region; The first gate cell and the second gate cell are located above the first device region and the second device region, respectively. Both the first gate cell and the second gate cell include a gate stack and a protective layer. The top of the first gate cell and the top of the second gate cell are flush. The epitaxial structure includes a trench located in the substrate between two adjacent second gate cells and an epitaxial layer filling the trench.

9. The semiconductor structure according to claim 8, characterized in that, Both the first gate unit and the second gate unit further include a sidewall structure, which includes a barrier layer, an insulating layer and an isolation layer stacked sequentially.

10. The semiconductor structure according to claim 9, characterized in that, The isolation layer in the first gate unit covers the sidewall of the insulating layer and the upper surface of the protective layer, and the isolation layer in the second gate unit covers the sidewall of the insulating layer. The top of the isolation layer in the first gate unit is flush with the top of the protective layer in the second gate unit.

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