Semiconductor structure and manufacturing method thereof

Abstract

Semiconductor structures and methods of manufacture are provided. In some embodiments, the disclosed semiconductor structure includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first thickness of the upper semiconductor layer in the first region is greater than a second thickness of the upper semiconductor layer in the second region.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to semiconductor devices and methods of manufacturing thereof. Background Technology

[0002] Silicon-on-insulator (SOI) wafers are a cutting-edge semiconductor substrate that offers many advantages over traditional bulk silicon substrates, making them a preferred choice for advanced semiconductor manufacturing processes. SOI technology involves integrating a thin layer of single-crystal silicon on top of an insulating layer typically made of silicon dioxide (SiO2), which itself sits atop a bulk silicon substrate. This sandwich structure provides several key benefits, such as reduced power consumption, improved performance, enhanced radiation hardness, and reduced latch-up effect.

[0003] SOI wafers are fabricated using various techniques, such as oxygen ion implantation, bonding and etch-back, and smart-cut processes. These methods allow for precise control over the thickness of the silicon layer and the quality of the buried oxide, enabling customization to meet specific performance requirements. SOI technology represents a significant advancement in semiconductor manufacturing, providing unparalleled performance, reliability, and versatility for a wide range of applications across industries. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor structure including: a lower semiconductor layer; an upper semiconductor layer; and an insulating layer between the lower semiconductor layer and the upper semiconductor layer, wherein a first thickness of the upper semiconductor layer in a first region is greater than a second thickness of the upper semiconductor layer in a second region.

[0005] In some embodiments, the lower semiconductor layer and the upper semiconductor layer comprise silicon; and the insulating layer comprises silicon oxide.

[0006] In some embodiments, the insulating layer extends in a first region and a second region; and the lower semiconductor layer is separated from the upper semiconductor layer, which includes silicon, by the insulating layer.

[0007] In some embodiments, the first upper surface of the upper semiconductor layer in the first region is higher than the second upper surface of the upper semiconductor layer in the second region.

[0008] In some embodiments, the insulating layer extends in the second region but not in the first region; and the lower semiconductor layer contacts the upper semiconductor layer, which includes silicon, in the first region.

[0009] In some embodiments, the upper semiconductor layer has a flush upper surface.

[0010] In some embodiments, the thickness of the insulating layer is in the range of 10 nm to 30 nm.

[0011] In some embodiments, the semiconductor structure further includes: a first set of transistors having a first operating voltage and formed in the upper semiconductor layer in the first region; and a second set of transistors having a second operating voltage lower than the first operating voltage and formed in the upper semiconductor layer in the second region.

[0012] In some embodiments, the first material of the upper semiconductor layer is different from the second material of the lower semiconductor layer.

[0013] In some embodiments, the first material of the upper semiconductor layer is the same as the second material of the lower semiconductor layer.

[0014] Another aspect of this disclosure provides a semiconductor structure including: a lower semiconductor layer; an upper semiconductor layer; and an insulating layer between the lower semiconductor layer and the upper semiconductor layer, wherein a first thickness of the insulating layer in a first region is greater than a second thickness of the insulating layer in a second region.

[0015] In some embodiments, the lower semiconductor layer and the upper semiconductor layer comprise silicon; and the insulating layer comprises silicon oxide.

[0016] In some embodiments, the upper insulating layer has a flush upper surface; and the first lower surface of the insulating layer in the first region is lower than the second lower surface of the insulating layer in the second region.

[0017] In some embodiments, the upper semiconductor layer has a flush upper surface; and the first upper surface of the lower semiconductor layer in the first region is lower than the second upper surface of the lower semiconductor layer in the second region.

[0018] In some embodiments, the semiconductor structure further includes: a first set of transistors having a first operating voltage and formed in the upper semiconductor layer in the first region; and a second set of transistors having a second operating voltage lower than the first operating voltage and formed in the upper semiconductor layer in the second region.

[0019] Another aspect of this disclosure provides a method for forming a semiconductor structure, comprising: removing a portion of a first semiconductor layer in a second region such that a first upper surface of the first semiconductor layer in the first region is higher than a second upper surface of the first semiconductor layer in the second region; forming an insulating layer on the second semiconductor layer; bonding the first semiconductor layer to the insulating layer; and thinning the first semiconductor layer such that a first thickness of the first semiconductor layer in the first region is greater than a second thickness of the first semiconductor layer in the second region.

[0020] In some embodiments, the semiconductor structure further includes: bonding the first semiconductor layer to the insulating layer by: bonding the flush lower surface of the first semiconductor layer to the flush upper surface of the insulating layer.

[0021] Another aspect of this disclosure provides a method for forming a semiconductor structure, comprising: removing a portion of a second semiconductor layer in a first region such that a first upper surface of the second semiconductor layer in the first region is lower than a second upper surface of the second semiconductor layer in a second region; forming an insulating layer on the second semiconductor layer, wherein a first thickness of the insulating layer in the first region is greater than a second thickness of the insulating layer in the second region; bonding a first semiconductor layer to the insulating layer; and thinning the first semiconductor layer.

[0022] In some embodiments, forming the insulating layer includes: forming the insulating layer to cover a first upper surface and a second upper surface of the second semiconductor layer, wherein the first upper surface of the insulating layer in the first region is lower than the second upper surface of the insulating layer in the second region; and polishing the insulating layer to form a flush upper surface of the insulating layer.

[0023] In some embodiments, forming the insulating layer includes: forming the insulating layer to cover a first upper surface and a second upper surface of the second semiconductor layer, wherein the first upper surface of the insulating layer in the first region is lower than the second upper surface of the insulating layer in the second region; removing a portion of the insulating layer in the second region to expose a portion of the second semiconductor layer in the second region; and oxidizing the exposed portion of the second semiconductor layer in the second region to allow the portion of the insulating layer in the second region to regrow, such that the insulating layer has a flush upper surface.

[0024] In some embodiments, forming the insulating layer on the second semiconductor layer includes: oxidizing the upper surface of the second semiconductor layer to form the insulating layer;

[0025] Another aspect of this disclosure provides a method for forming a semiconductor structure, comprising: forming a mask layer on a second semiconductor layer; removing a portion of the mask layer in a first region to expose a first portion of the second semiconductor layer in the first region; removing a portion of the first portion of the second semiconductor layer in the first region such that a first upper surface of the second semiconductor layer in the first region is lower than a second upper surface of the second semiconductor layer in a second region covered by the mask layer; oxidizing the first portion of the second semiconductor layer in the first region to form a first portion of an insulating layer in the first region; removing the mask layer in the second region to expose a second portion of the second semiconductor layer in the second region; oxidizing the second portion of the second semiconductor layer in the second region to form a second portion of the insulating layer in the second region, wherein a first thickness of the first portion of the insulating layer in the first region is greater than a second thickness of the second portion of the insulating layer in the second region; bonding a first semiconductor layer to the insulating layer; and thinning the first semiconductor layer.

[0026] Another aspect of this disclosure provides a method for forming a semiconductor structure, comprising: forming an insulating layer on a second semiconductor layer; removing a portion of the insulating layer to expose the second semiconductor layer in a first region; growing a semiconductor material of the second semiconductor layer in the first region such that a first upper surface of the second semiconductor layer in the first region is flush with the upper surface of the insulating layer; bonding a first semiconductor layer to the upper surface of the insulating layer and the first upper surface of the second semiconductor layer; and thinning the first semiconductor layer. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0028] Figure 1 A schematic diagram of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0029] Figure 2 A flowchart of a manufacturing method for forming a semiconductor structure according to some embodiments of the present disclosure is shown.

[0030] Figures 3A-3D Various embodiments according to this disclosure are shown in Figure 2 A schematic side cross-sectional view of a portion of the semiconductor structure at certain manufacturing stages of the method shown.

[0031] Figure 4 A schematic diagram of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0032] Figure 5 A flowchart of a manufacturing method for forming a semiconductor structure according to some embodiments of the present disclosure is shown.

[0033] Figures 6A-6D Various embodiments according to this disclosure are shown in Figure 5 A schematic side cross-sectional view of a portion of the semiconductor structure at certain manufacturing stages of the method shown.

[0034] Figure 7 A flowchart of a manufacturing method for forming a semiconductor structure according to some embodiments of the present disclosure is shown.

[0035] Figures 8A-8D Various embodiments according to this disclosure are shown in Figure 7 A schematic side cross-sectional view of a portion of the semiconductor structure at certain manufacturing stages of the method shown.

[0036] Figure 9 A schematic diagram of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0037] Figure 10 A flowchart of a manufacturing method for forming a semiconductor structure according to some embodiments of the present disclosure is shown.

[0038] Figure 11A-11D Various embodiments according to this disclosure are shown in Figure 10 A schematic side cross-sectional view of a portion of the semiconductor structure at certain manufacturing stages of the method shown.

[0039] The contents of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0040] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with each other in ways not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0041] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "described" can also be understood to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0042] It should be readily understood that the meanings of “on,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer, and “above” or “above” means not only “on” or “above” but also includes “on” or “above” without an intermediate feature or layer (i.e., directly on).

[0043] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element(s) as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0044] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0045] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0046] As described above, SOI wafers offer advantages such as low power consumption, improved performance, enhanced radiation hardness, and reduced latch-up effects. First, SOI wafers provide lower power consumption compared to their bulk silicon counterparts due to reduced parasitic capacitance and leakage current. This is particularly advantageous for power efficiency-critical applications, such as mobile devices and battery-operated systems. Second, by minimizing parasitic capacitance and reducing the effects of substrate coupling, SOI wafers enable faster switching speeds, improved signal integrity, and enhanced overall performance of integrated circuits. This is crucial for high-speed digital applications, RF circuits, and mixed-signal designs. Third, the insulating layers in SOI wafers provide inherent isolation between devices, offering improved radiation hardness compared to bulk silicon substrates. This makes SOI technology suitable for aerospace, automotive, and other harsh environment applications where reliability is critical. Fourth, by eliminating the parasitic thyristor structures present in traditional CMOS designs, SOI wafers help mitigate latch-up effects (a common problem in bulk silicon devices). This enhances the robustness and reliability of SOI-based circuits, especially in high-voltage and mixed-signal applications.

[0047] SOI wafers can be fabricated using various industry-standard techniques, such as oxygen ion implantation, bonding and etch-back, and smart dicing processes. These methods enable precise control over the thickness of the top silicon layer (i.e., the top device layer) and the quality of the buried oxide, allowing for customization to meet specific performance requirements. It should be noted that existing fabrication processes result in a top device layer of fixed thickness. To enhance device performance, there is a collaborative effort in the industry to reduce the thickness of the top silicon layer, thereby transitioning from partially depleted devices to fully depleted devices.

[0048] However, in some CMOS designs, the gate oxide thickness of high-voltage (HV) transistors / devices is significantly greater than that of low-voltage (LV) transistors / devices. Forming the HV gate oxide layer consumes a considerable amount of silicon layer thickness, resulting in an excessively thin top device layer in the HV region. This severely impacts the performance of HV region devices. Conversely, thickening the top device layer to address this issue degrades the performance of LV region devices. In other words, due to variations in the gate oxide layer thickness, the thickness of the top silicon film differs for different operating voltage regions, making it impossible to simultaneously optimize the performance of both HV and LV devices. Therefore, the industry urgently needs novel SOI wafer solutions capable of addressing the problem of excessively thin device layers in the HV region.

[0049] To address one or more of the aforementioned problems, this disclosure proposes an innovative SOI structure having a top silicon layer, insulating layer, and / or bulk substrate of customized thickness in both the HV and LV regions. Various designs of this disclosure can address the issue of excessively thin device layers in the HV region while optimizing device performance in the LV region, potentially replacing conventional SOI structures. Specifically, this disclosure relates to various designs that effectively address the problem of insufficient device layer thickness in the HV region and ensure robust performance and reliability of HV devices, thereby alleviating concerns associated with excessively thin layers. Simultaneously, various designs of this disclosure also contribute to improved device performance in the LV region because it optimizes capacitance, reduces leakage current, and improves overall device efficiency. By implementing the novel SOI structure disclosed herein, manufacturers can achieve balanced performance in both the HV and LV regions, overcoming the limitations of conventional SOI designs. The disclosed innovative SOI structure unlocks new possibilities in semiconductor manufacturing to provide enhanced device performance, reliability, and versatility in a variety of applications, such as in dynamic random access memory (DRAM) manufacturing processes and / or 3D NAND memory manufacturing processes.

[0050] Figure 1 A schematic diagram of a semiconductor structure 100 according to some embodiments of the present disclosure is shown. For example... Figure 1 As shown, the semiconductor structure 100 may be a silicon-on-insulator (SOI) wafer, comprising a lower semiconductor layer 130 (also referred to herein as "second semiconductor layer 130"), an upper semiconductor layer 150 (also referred to herein as "first semiconductor layer 150"), and an insulating layer 140 between the lower semiconductor layer 130 and the upper semiconductor layer 150. The semiconductor structure 100 may include one or more first regions 110 and one or more second regions 120. A first thickness of the upper semiconductor layer 150 in the first region 110 is greater than a second thickness of the upper semiconductor layer 150 in the second region 120.

[0051] In some embodiments, the lower semiconductor layer 130 may be a bulk substrate providing foundation support for the insulating layer 140 and the upper semiconductor layer 150. The lower semiconductor layer 130 serves as the foundation for constructing semiconductor devices and circuits, providing mechanical support and electrical connections. The lower semiconductor layer 130 may include any suitable semiconductor material. In some embodiments, silicon is the most common material for bulk substrates in SOI wafers. In some other embodiments, depending on specific requirements or applications, the lower semiconductor layer 130 may include other materials. For example, sapphire substrates offer excellent thermal insulation and electrical insulation properties, making them suitable for high-power and high-frequency applications. Sapphire substrates are also highly transparent in the visible and near-infrared spectra, making them suitable for optoelectronic devices. As another example, silicon-germanium (SiGe) substrates combine the properties of both silicon and germanium, providing enhanced performance in terms of mobility, strain engineering, and device integration. SiGe substrates can be used for high-speed and RF applications. As yet another example, silicon carbide (SiC) substrates exhibit excellent thermal conductivity, high-temperature stability, and tolerance to harsh environments, making them ideal for power electronic devices, high-temperature sensors, and RF devices. As another example, gallium arsenide (GaAs) substrates, due to their high electron mobility and direct bandgap, can be used in optoelectronic and high-frequency devices to achieve efficient light emission and detection as well as high-speed electronic performance.

[0052] In some embodiments, the insulating layer 140 of the SOI wafer may comprise any suitable dielectric material having electrical isolation, thermal stability, compatibility, and dielectric strength. For example, the insulating layer 140 may typically comprise silicon dioxide (SiO2), commonly referred to as an oxide. The insulating layer 140 serves as a key component in the SOI structure, providing electrical isolation between the lower semiconductor layer 130 (i.e., the bulk substrate) and the upper semiconductor layer 150 (also referred to as the active layer). In some embodiments, the thickness of the insulating layer 140 may range from 10 nm to 30 nm. It should be noted that silicon dioxide is chosen as the insulating material for several reasons. First, silicon dioxide is an excellent electrical insulator, thus preventing charge carriers from being transferred through it. This property ensures minimal electrical interaction between the lower semiconductor layer 130 and the upper semiconductor layer 150, thereby reducing parasitic capacitance and leakage current. Second, silicon dioxide exhibits high thermal stability, enabling it to withstand the high temperatures experienced during semiconductor manufacturing processes such as oxidation, deposition, and annealing. Third, silicon dioxide is compatible with standard semiconductor processing techniques, making it well-suited for integration into existing manufacturing processes. It can be easily deposited, patterned, and etched using techniques such as chemical vapor deposition (CVD) and photolithography. Fourth, silicon dioxide has high dielectric strength, meaning it can withstand high electric field strengths without breakdown. This property ensures the reliability and integrity of the insulating layer under a variety of operating conditions. Therefore, the insulating layer 140 in the SOI wafer plays a crucial role in providing electrical isolation and ensuring the performance, reliability, and manufacturability of the semiconductor devices fabricated on the substrate.

[0053] In some embodiments, the upper semiconductor layer 150 is an active layer in an SOI wafer. In some embodiments, the upper semiconductor layer 150 may be a thin layer of single-crystal silicon located above the insulating layer 140 and separated from the lower semiconductor layer 130. In some embodiments, the upper semiconductor layer 150 serves as the main region for fabricating semiconductor devices such as transistors and diodes. In some embodiments, the upper semiconductor layer 150 comprises high-quality single-crystal silicon material, which provides excellent electrical properties, including high carrier mobility, low defect density, and uniformity, thereby ensuring optimal device performance and reliability. In some embodiments, various suitable semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), etc., are fabricated directly on the upper semiconductor layer 150 using standard semiconductor processing techniques. These devices can utilize the properties of the single-crystal silicon active layer to achieve the desired electrical functions.

[0054] In some other embodiments, the upper semiconductor layer 150 may include any other suitable semiconductor material that can be used as an active layer in a semiconductor device. For example, the upper semiconductor layer 150 may include III-V compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), etc., which are widely used in high-frequency and optoelectronic devices. These III-V compound semiconductor materials can provide high electron mobility and bandgap properties suitable for applications such as RF amplifiers, lasers, and photodetectors. As another example, the upper semiconductor layer 150 may include II-VI compound semiconductors, such as zinc oxide (ZnO), cadmium sulfide (CdS), etc., which are used in a variety of electronic and optoelectronic devices due to their unique electrical and optical properties. These II-VI compound semiconductor materials can be used to form sensors, light-emitting diodes (LEDs), and solar cells. As yet another example, the upper semiconductor layer 150 may include organic semiconductors, such as polymers, small molecules, etc., which are used in flexible electronics, organic light-emitting diodes (OLEDs), and organic photovoltaic devices (OPVs). These organic semiconductor materials can provide advantages such as low-cost manufacturing, flexibility, and large-area coverage. As another example, the upper semiconductor layer 150 may include perovskite semiconductor materials, such as methylammonium lead iodide (MAPbI3), which can be used in solar cells, LEDs and photodetectors due to their excellent photoelectric properties and low-cost manufacturing processes.

[0055] In some implementations, various semiconductor devices requiring a wide range of voltages can be formed on the same SOI wafer. For example, memory devices such as 3D NAND flash memory devices, 3D ferroelectric memory devices, and 3D DRAM devices can include multiple voltage sources, each configured to provide a corresponding voltage level to a corresponding HV or LV semiconductor device located in a different region of the SOI wafer. This corresponding level is, for example, a low voltage (LV) level (e.g., below about 10V) or a high voltage (HV) level (e.g., above about 10V). Therefore, semiconductor structure 100 can include one or more first regions 110 serving as HV circuit regions and one or more second regions 120 serving as LV circuit regions. In a particular example, when the SOI wafer is used to form peripheral circuitry for a NAND memory device, one or more first regions 110 (i.e., HV circuit regions) can include one or more word line driver circuits, bit line driver circuits, etc., while one or more second regions 120 (i.e., LV circuit regions) can include one or more page buffer circuits, logic circuits, input / output (I / O) circuits, etc. That is, a first set of transistors (not shown) having a first operating voltage can be formed in the upper semiconductor layer 150 in the first region 110, and a second set of transistors (not shown) having a second operating voltage lower than the first operating voltage can be formed in the upper semiconductor layer 150 in the second region 120.

[0056] In some implementations, the upper semiconductor layer 150 (i.e., the active layer) can be customized to meet the requirements of a specific application by adjusting parameters such as doping concentration, crystal orientation, and strain engineering. This customization allows for optimization of device performance, power efficiency, and integration density. In some implementations, the thickness of the upper semiconductor layer 150 (i.e., the active layer) can be precisely controlled during the wafer fabrication process, typically in the range of several nanometers to several micrometers. This controlled thickness allows for customization of device characteristics and performance. Specifically, such as... Figure 1 As shown, the first thickness of the upper semiconductor layer 150 in the first region 110 (i.e., the HV region) is greater than the second thickness of the upper semiconductor layer 150 in the second region 120 (i.e., the LV region). That is, the first upper surface of the upper semiconductor layer 150 in the first region 110 is higher than the second upper surface of the upper semiconductor layer 150 in the second region 120. In some embodiments, the thickness difference between the upper semiconductor layer 150 in the HV region and the upper semiconductor layer 150 in the LV region can be formed by a photolithographic etching process of the upper semiconductor layer 150 before bonding it to the insulating layer 140 and by a smart dicing process of the upper semiconductor layer 150 before bonding it to the insulating layer 140.

[0057] Compared to conventional SOI wafers, the disclosed semiconductor structure 100 significantly thickens the upper semiconductor layer 150 (i.e., the active layer) in the HV region, effectively addressing the issue of thin device layers in the HV region. This enhancement ensures robust performance and reliability of the HV device by providing sufficient thickness. Furthermore, the disclosed semiconductor structure 100 ensures that the upper semiconductor layer 150 (i.e., the active layer) in the LV region remains relatively thin, thereby enhancing the performance of the LV device. This optimization allows for improved capacitance, reduced leakage current, and enhanced overall efficiency of the LV device, while maintaining compatibility with low-voltage operation. By implementing this enhancement, the disclosed semiconductor structure 100 achieves balanced performance in both the HV and LV regions, overcoming the limitations of conventional processes. This innovation promises to advance semiconductor manufacturing, providing improved device performance, reliability, and versatility in a variety of applications. It should be noted that, although... Figure 1 Only two types of regions corresponding to two voltage levels (i.e., HV and LV) are shown, but in the spirit of this disclosure, three or more types of regions corresponding to multiple voltage levels (e.g., HHV, HV, LV, and LLV, etc.) can be applied.

[0058] refer to Figure 2 The present disclosure shows a flowchart of a manufacturing method 200 for forming a semiconductor structure 100 according to some embodiments thereof. Figures 3A-3D Various embodiments according to this disclosure are shown in Figure 2 The diagram shows a schematic side cross-sectional view of a portion of the semiconductor structure at certain manufacturing stages of method 200. It should be understood that the operations shown in method 200 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 2 The different execution orders shown.

[0059] like Figure 2 As shown, method 200 may begin with operation 210, wherein a portion of the first semiconductor layer in the second region may be removed such that the first upper surface of the first semiconductor layer in the first region is higher than the second upper surface of the first semiconductor layer in the second region. Figure 3A A schematic side cross-sectional view of the first semiconductor layer is shown after operation 210 of method 200.

[0060] like Figure 3AAs shown, the first semiconductor layer 150 may be a semiconductor substrate, which may include silicon (e.g., single-crystal silicon, c-Si) or any other suitable semiconductor material described above that can be used as an active layer in a semiconductor device. In this embodiment, a portion of the first semiconductor layer 150 in the second region 120 may be removed such that the first upper surface of the first semiconductor layer 150 in the first region 110 is higher than the second upper surface of the first semiconductor layer 150 in the second region 120.

[0061] In some embodiments, a portion of the first semiconductor layer 150 in the second region 120 can be removed by a patterning process (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.) to create a thickness difference between the first semiconductor layer 150 in the first region 110 and the second region 120. In some specific embodiments, a photolithography-etching process can be performed, including substrate preparation, photoresist application, exposure, development, etching, resist stripping, and post-processing, to precisely pattern the first semiconductor layer 150.

[0062] Return to reference Figure 2 Method 200 can proceed to operation 220, in which an insulating layer can be formed on the second semiconductor layer. Figure 3B A schematic side cross-sectional view of the insulating layer and the second semiconductor layer is shown after operation 220 of method 200.

[0063] like Figure 3B As shown, the insulating layer 140 can be formed on the second semiconductor layer 130 and can extend in both the first region 110 and the second region 120. In some embodiments, the fabrication process for forming the insulating layer 140 on the second semiconductor layer 130 may include a substrate fabrication process for preparing the semiconductor layer 130. This process begins with the fabrication of a high-quality silicon wafer (referred to as a bulk substrate). The substrate is thoroughly cleaned to remove any contaminants and ensure a clean surface for subsequent processing steps. In some embodiments, the insulating layer 140 can be deposited on the second semiconductor layer 130 by performing a series of thin film deposition processes (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.).

[0064] In some other embodiments, the insulating layer 140 can be formed on the second semiconductor layer 130 using a thermal oxidation process. For example, the silicon substrate is exposed to high temperatures in the presence of oxygen or water vapor. During oxidation, oxygen atoms diffuse into the silicon substrate and react with silicon atoms to form a silicon dioxide (SiO2) layer on the surface. This process can be performed in a high-temperature furnace or using rapid thermal processing (RTP) technology. Furthermore, forming the insulating layer 140 may also include oxide thickness control processes. In some embodiments, the thickness of the silicon dioxide layer can be precisely controlled by adjusting parameters (e.g., temperature, time, oxygen concentration) during the oxidation process, allowing the thickness of the insulating layer 140 to be customized to meet specific design requirements. Finally, forming the insulating layer 140 may also include planarization processes, such as chemical mechanical polishing (CMP), to achieve a flat and smooth surface topography.

[0065] Return to reference Figure 2 Method 200 can proceed to operation 230, in which the first semiconductor layer can be bonded to the insulating layer. Figure 3C A schematic side cross-sectional view of the bonded semiconductor structure is shown after operation 230 of method 200.

[0066] like Figure 3C As shown, the flush lower surface of the first semiconductor layer 150 can be bonded to the flush upper surface of the insulating layer 140. In some embodiments, bonding the first semiconductor layer 150 to the insulating layer 140 may include a series of fabrication processes, including surface preparation, surface activation, alignment and contact, bonding, annealing, and post-bonding treatment. In surface preparation, both the first semiconductor layer 150 (i.e., the active layer) and the insulating layer 140 are prepared by cleaning and ensuring that the surfaces of both are free of contaminants, thereby promoting strong adhesion during bonding. Surface activation processes can then be employed to enhance the bonding between the first semiconductor layer 150 (i.e., the active layer) and the insulating layer 140. For example, plasma treatment or chemical functionalization can be used to modify surface chemistry and promote bonding. Next, the first semiconductor layer 150 (i.e., the active layer) and the insulating layer 140 can be brought into close contact with each other while ensuring proper alignment of their respective surfaces to ensure uniformity and integrity throughout the wafer.

[0067] It should be noted that various bonding methods can be used to bond the first semiconductor layer 150 (i.e., the active layer) to the insulating layer 140, including direct bonding, anodic bonding, and wafer bonding with an intermediate layer. In direct bonding, the two surfaces of the first semiconductor layer 150 (i.e., the active layer) and the insulating layer 140 are brought into contact under controlled conditions (such as temperature and pressure) to promote molecular adhesion. The bonded interface forms a strong and permanent bond without the need for additional bonding agents. In anodic bonding, when the first semiconductor layer 150 (i.e., the active layer) and the insulating layer 140 are in contact, an electric field can be applied to the first semiconductor layer 150 (i.e., the active layer) and the insulating layer 140, thereby generating a strong bond by inducing ion migration and electrostatic attraction at the interface. In some embodiments, an intermediate layer (not shown) can be introduced between the first semiconductor layer 150 (i.e., the active layer) and the insulating layer 140 to promote bonding. The intermediate layer can be a thin oxide or nitride layer that enhances bonding and promotes adhesion.

[0068] It should also be noted that the bonding process is typically carried out under controlled conditions (including temperature, pressure, and duration) optimized to achieve strong and reliable bonding while minimizing defects and stresses in the bonded structure. After bonding, as... Figure 3C The bond structures shown can undergo annealing or other post-bonding treatments to further improve bond strength, remove defects, and reduce stress in the bond structure. Additionally, various inspection and testing techniques (such as microscopy, bond strength measurement, and defect analysis) can be employed to ensure the quality and integrity of the bond structure before proceeding to subsequent processing steps.

[0069] Return to reference Figure 2 Method 200 can proceed to operation 240, in which the first semiconductor layer can be thinned such that the first thickness of the first semiconductor layer in the first region is greater than the second thickness of the first semiconductor layer in the second region. Figure 3D A schematic side cross-sectional view of the bonded semiconductor structure is shown after operation 240 of method 200.

[0070] In such Figure 3D In some embodiments shown, after the first semiconductor layer 150 (i.e., the active layer) is bonded to the insulating layer 140, the first semiconductor layer 150 (i.e., the active layer) can be thinned to achieve the desired thickness of the first semiconductor layer 150 in the first region 110 and the second region 120. In some embodiments, the first semiconductor layer 150 can be thinned by performing a mechanical polishing process followed by an optional chemical mechanical polishing (CMP) process.

[0071] In some embodiments, the bonding structure may undergo a mechanical polishing process to remove excess portions of the first semiconductor layer 150 (i.e., the active layer), thereby thinning the active layer. In some embodiments, any suitable precision polishing apparatus for controlled removal of silicon material can be used to perform the mechanical polishing process to reduce the thickness of the first semiconductor layer 150 (i.e., the active layer) in the first region 110 and the second region 120 to predetermined target thicknesses, respectively. In some embodiments, the mechanical polishing process may be performed incrementally, wherein frequent measurements are taken to monitor the thickness of the first semiconductor layer 150 (i.e., the active layer) in the first region 110 and the second region 120 and to ensure uniform thinning across the entire wafer.

[0072] In some embodiments, after a mechanical polishing process, the bonded structure may undergo a CMP process to further thin and smooth the first semiconductor layer 150 (i.e., the active layer). It should be noted that the CMP process may include the simultaneous application of a chemical etchant and a mechanical polishing agent to remove material from the wafer surface. For example, during the CMP process, a slurry containing abrasive particles and a chemical etchant may be applied to the surface of the first semiconductor layer 150 (i.e., the active layer), and one or more polishing pads may be pressed against certain areas of the first semiconductor layer 150 (i.e., the active layer) to produce a chemical and mechanical polishing effect. The combination of chemical reaction and mechanical polishing agent helps to achieve precise control over the thinning process and ensures a smooth, uniform surface finish. The CMP process may continue until the first semiconductor layer 150 (i.e., the active layer) reaches the desired final thickness in the first region 110 and the second region 120, as determined by metrological measurements and quality control criteria.

[0073] It should be noted that throughout the thinning process, metrological techniques such as optical interferometry, elliptic polarization, or atomic force microscopy (AFM) can be used to monitor the thickness of the first semiconductor layer 150 (i.e., the active layer) in the first region 110 and the second region 120. Furthermore, quality control measures can be implemented to ensure that the thinning process meets specified requirements for thickness uniformity, surface roughness, and defect density. Any deviation from the target thickness or quality standards of the first semiconductor layer 150 (i.e., the active layer) in the first region 110 and the second region 120 can be addressed by adjusting the thinning parameters or process conditions. Once the first semiconductor layer 150 (i.e., the active layer) reaches the required thickness in the first region 110 and the second region 120, the bonded structure can undergo final cleaning to remove any residues or contaminants from the thinning process.

[0074] Figure 4 A schematic diagram of a semiconductor structure 400 according to some embodiments of the present disclosure is shown. For example... Figure 4As shown, the semiconductor structure 400 may be a silicon-on-insulator (SOI) wafer, comprising a lower semiconductor layer 430 (also referred to herein as "second semiconductor layer 430"), an upper semiconductor layer 450 (also referred to herein as "first semiconductor layer 450"), and an insulating layer 440 between the lower semiconductor layer 430 and the upper semiconductor layer 450. The semiconductor structure 400 may include one or more first regions 110 and one or more second regions 120. The first thickness of the insulating layer 440 in the first region 110 is greater than the second thickness of the insulating layer 440 in the second region 120.

[0075] It should be noted that, with such Figure 1 Compared to the semiconductor structure 100 shown, the same properties of the lower semiconductor layer 430, insulating layer 440, and upper semiconductor layer 450 in semiconductor structure 400 can be found in the descriptions of the lower semiconductor layer 130, insulating layer 140, and upper semiconductor layer 150 above, and will not be repeated here. The following describes only the different parts of the lower semiconductor layer 430, insulating layer 440, and upper semiconductor layer 450 in semiconductor structure 400.

[0076] like Figure 4 As shown, the lower semiconductor layer 430 may have a non-flush upper surface. In some embodiments, the first upper surface of the lower semiconductor layer 430 in the first region 110 (i.e., the HV circuit region) may be lower than the second upper surface of the lower semiconductor layer 430 in the second region 120 (i.e., the LV circuit region). That is, the first thickness of the lower semiconductor layer 430 in the first region 110 (i.e., the HV region) is less than the second thickness of the lower semiconductor layer 430 in the second region 120 (i.e., the LV region). Furthermore, the insulating layer 440 may have a non-flush lower surface. In some embodiments, the first lower surface of the insulating layer 440 in the first region 110 (i.e., the HV circuit region) may be lower than the second lower surface of the insulating layer 440 in the second region 120 (i.e., the LV circuit region). That is, the first thickness of the insulating layer 440 in the first region 110 (i.e., the HV region) is greater than the second thickness of the insulating layer 440 in the second region 120 (i.e., the LV region). The upper surface of the insulating layer 440 is a flush surface, and the first semiconductor layer 450 above the insulating layer 440 has a uniform thickness and flush upper and lower surfaces.

[0077] Compared to conventional SOI wafers, the disclosed semiconductor structure 400 significantly thickens the insulating layer 440 in the HV region, effectively addressing leakage issues in the HV region. Furthermore, the disclosed semiconductor structure 400 enhances device performance by employing multiple photolithography steps to create varying back gate oxide thicknesses in different voltage regions such as HV, LV, and LLV. This optimization allows for improved capacitance, reduced leakage current, and enhanced overall efficiency of LV devices while maintaining compatibility with low-voltage operation. By implementing these improvements to the disclosed semiconductor structure 400, it can achieve optimized back gate oxide thicknesses tailored to different voltage requirements, thereby achieving a balance of performance in both the HV and LV regions, overcoming limitations of conventional processes, and obtaining enhanced device performance, reduced leakage issues, and improved reliability across various voltage regions. It should be noted that although… Figure 4 Only two types of regions corresponding to two voltage levels (i.e., HV and LV) are shown, but in the spirit of this disclosure, three or more types of regions corresponding to multiple voltage levels (e.g., HHV, HV, LV, and LLV, etc.) can be applied.

[0078] refer to Figure 5 The diagram shows a flowchart of a manufacturing method 500 for forming a semiconductor structure 400 according to some embodiments of the present disclosure. Figures 6A-6D Various embodiments according to this disclosure are shown in Figure 5 The diagram shows a schematic side cross-sectional view of a portion of the semiconductor structure at certain manufacturing stages of method 500. It should be understood that the operations shown in method 500 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 5 The different execution sequences are shown. It should be noted that some detailed manufacturing processes can be referenced in the above combination. Figure 2 The description of method 200 will not be repeated in this document, and only the different parts will be described below.

[0079] like Figure 5 As shown, method 500 may begin with operation 510, wherein a portion of the second semiconductor layer in the first region may be removed such that the first upper surface of the second semiconductor layer in the first region is lower than the second upper surface of the second semiconductor layer in the second region. Figure 6A A schematic side cross-sectional view of the first semiconductor layer is shown after operation 510 of method 500.

[0080] like Figure 6AAs shown, a portion of the second semiconductor layer 430 in the first region 110 can be removed, such that the first upper surface of the second semiconductor layer 430 in the first region 110 is lower than the second upper surface of the second semiconductor layer 430 in the second region 120. In some embodiments, a portion of the second semiconductor layer 430 in the first region 110 can be removed by a patterning process (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.) to create a thickness difference between the second semiconductor layer 430 in the first region 110 and the second region 120. In some specific embodiments, a photolithography-etching process can be performed, including substrate preparation, photoresist application, exposure, development, etching, resist stripping, and post-processing, to precisely pattern the second semiconductor layer 430.

[0081] Return to reference Figure 5 Method 500 can proceed to operation 520, wherein an insulating layer can be formed on the second semiconductor layer, wherein the first thickness of the insulating layer in the first region is greater than the second thickness of the insulating layer in the second region. Figure 6B and Figure 6C Schematic side cross-sectional views of the insulating layer and the second semiconductor layer are shown respectively at a specific stage of operation 520 of method 500.

[0082] like Figure 6B As shown, the insulating layer 440 can be formed on the second semiconductor layer 430 and can extend in both the first region 110 and the second region 120. In some embodiments, the insulating layer 440 can be deposited on the second semiconductor layer 430 by performing any suitable thin film deposition process (e.g., CVD, PECVD, PVD, ALD, etc.). In some other embodiments, the insulating layer 440 can be formed by performing a thermal oxidation process on the upper surface of the second semiconductor layer 430. Because the second semiconductor layer 430 has a non-flush upper surface, the formed insulating layer 440 also has a non-flush upper surface. Figure 6C As shown, in some embodiments, a CMP process can be performed on the insulating layer 440 to form a flush upper surface of the insulating layer 440. Therefore, the first thickness of the insulating layer 440 in the first region 110 can be greater than the second thickness of the insulating layer 440 in the second region 120. In some other embodiments not shown in the figures, portions of the insulating layer 440 in the second region 120 can be removed using a photolithographic wet etching process, and a subsequent oxidation process can be performed to reform the insulating layer 440 with a flush upper surface.

[0083] Return to reference Figure 5 Method 500 can proceed to operation 530, in which the first semiconductor layer can be bonded to the insulating layer and the first semiconductor layer can be thinned. Figure 6DA schematic side cross-sectional view of the bonded semiconductor structure is shown after operation 530 of method 500.

[0084] like Figure 6D As shown, the first semiconductor layer 450 (i.e., the active layer) can be bonded to the insulating layer 440 using any of the suitable bonding methods described above. After bonding the first semiconductor layer 450 (i.e., the active layer) to the insulating layer 440, the first semiconductor layer 450 (i.e., the active layer) can be thinned to achieve the desired thickness. In some embodiments, the first semiconductor layer 450 can be thinned by performing a CMP process.

[0085] refer to Figure 7 The diagram shows a flowchart of another manufacturing method 700 for forming a semiconductor structure 400 according to some embodiments of the present disclosure. Figures 8A-8D Various embodiments according to this disclosure are shown in Figure 7 The diagram shows a schematic side cross-sectional view of a portion of the semiconductor structure at certain manufacturing stages of method 700. It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with… Figure 7 The different execution sequences are shown. It should be noted that some detailed manufacturing processes can be referenced in the above combination. Figure 2 The description of method 200 will not be repeated in this document, and only the different parts will be described below.

[0086] like Figure 7 As shown, method 700 can begin at operation 710, wherein a mask layer can be formed on the second semiconductor layer. Figure 8A A schematic side cross-sectional view of a mask layer 490 formed on the second semiconductor layer 430 after operation 710 of method 700 is shown. In some embodiments, the mask layer 490 may be a hard mask layer, such as a SiN layer.

[0087] refer to Figure 7 and Figure 8B Method 700 can proceed to operation 720, wherein a portion of the mask layer 490 in the first region 110 can be removed to expose a first portion of the second semiconductor layer 430 in the first region 110, a portion of the second semiconductor layer 430 in the first region 110 can be removed such that a first upper surface of the second semiconductor layer 430 in the first region 110 is lower than a second upper surface of the second semiconductor layer 430 in the second region 120 covered by the remaining portion of the mask layer 490, and the first upper surface of the second semiconductor layer 430 in the first region 110 can be oxidized to form a first portion of the insulating layer 440 in the first region 110.

[0088] refer to Figure 7 and Figure 8C Method 700 can proceed to operation 730, wherein the mask layer 490 in the second region 120 can be removed to expose the second upper surface of the second semiconductor layer 430 in the second region 120, and then the second upper surface of the second semiconductor layer 430 in the second region 120 can be oxidized to form a second portion of the insulating layer 440 in the second region 120. The first thickness of the insulating layer 440 in the first region 110 is greater than the second thickness of the insulating layer 440 in the second region 120.

[0089] refer to Figure 7 and Figure 8D Method 700 can proceed to operation 740, in which the first semiconductor layer 450 can be bonded to the insulating layer 440, and the first semiconductor layer 450 can be thinned. Figure 8D A schematic side cross-sectional view of the bonded semiconductor structure is shown after operation 740 of method 700.

[0090] Figure 9 A schematic diagram of a semiconductor structure 900 according to some embodiments of the present disclosure is shown. For example... Figure 9 As shown, the semiconductor structure 900 can be a silicon-on-insulator (SOI) wafer, comprising a lower semiconductor layer 930 (also referred to herein as "second semiconductor layer 930") and an upper semiconductor layer 950 (also referred to herein as "first semiconductor layer 950"). The lower semiconductor layer 930 and the upper semiconductor layer 950 can be in direct contact with each other in a first region 110 (i.e., the HV region). An insulating layer 940 can be located between the lower semiconductor layer 930 and the upper semiconductor layer 950 in a second region 120 (i.e., the LV region).

[0091] refer to Figure 10 The present disclosure shows a flowchart of a manufacturing method 1000 for forming a semiconductor structure 900 according to some embodiments thereof. Figure 11A-11D Various embodiments according to this disclosure are shown in Figure 10 The diagram shows a schematic side cross-sectional view of a portion of the semiconductor structure at certain manufacturing stages of method 1000. It should be understood that the operations shown in method 1000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with… Figure 10 The different execution sequences are shown. It should be noted that some detailed manufacturing processes can be referenced in the above combination. Figure 2 The description of method 200 will not be repeated in this document, and only the different parts will be described below.

[0092] like Figure 10 and Figure 11A As shown, method 1000 may begin with operation 1010, wherein an insulating layer 940 may be formed on the second semiconductor layer 930, and the insulating layer 940 may extend in both the first region 110 and the second region 120. In some embodiments, the insulating layer 940 may be deposited on the second semiconductor layer 930 by performing any suitable thin film deposition process (e.g., CVD, PECVD, PVD, ALD, etc.). In some other embodiments, the insulating layer 940 may be formed by performing a thermal oxidation process on the upper surface of the second semiconductor layer 930.

[0093] refer to Figure 10 and Figure 11B Method 1000 can proceed to operation 1020, wherein a portion of the insulating layer 940 in the first region 110 can be removed to expose the second semiconductor layer 930 in the first region 110. In some embodiments, the portion of the insulating layer 940 in the first region 110 can be removed by a patterning process (e.g., photolithography, dry etching, wet etching, cleaning, etc.). In some specific embodiments, a photolithography etching process (including substrate preparation, photoresist application, exposure, development, etching, resist stripping, and post-processing) can be performed to precisely pattern the insulating layer 940. It should be noted that in some embodiments, a portion of the second semiconductor layer 930 can also be removed during the process of removing a portion of the insulating layer 940 in the first region 110, such that the first upper surface of the second semiconductor layer 930 in the first region 110 is lower than the second upper surface of the second semiconductor layer 930 in the second region 120.

[0094] refer to Figure 10 and Figure 11C Method 1000 can proceed to operation 1030, in which a semiconductor material of a second semiconductor layer 930 can be grown in the first region 110 such that the first upper surface of the second semiconductor layer 930 in the first region 110 is flush with the upper surface of the insulating layer 940. In some embodiments, an epitaxial growth process and a subsequent CMP process can be performed in operation 1030.

[0095] refer to Figure 10 and Figure 11D Method 1000 can proceed to operation 1040, in which the first semiconductor layer 950 can be bonded to the insulating layer 940 and the second semiconductor layer 930, and the first semiconductor layer 950 can be thinned. For example... Figure 11DAs shown, the first semiconductor layer 950 (i.e., the active layer) can be bonded to the insulating layer 940 and the second semiconductor layer 930 using any of the suitable bonding methods described above. After bonding, the first semiconductor layer 950 (i.e., the active layer) can be thinned to achieve the desired thickness. In some embodiments, the first semiconductor layer 950 can be thinned by performing a CMP process.

[0096] The foregoing description of a particular implementation can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance given herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementations.

[0097] The scope and extent of this disclosure should not be limited by any of the above-described embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor structure, comprising: Lower semiconductor layer; Upper semiconductor layer; as well as An insulating layer is provided between the lower semiconductor layer and the upper semiconductor layer. The first thickness of the upper semiconductor layer in the first region is greater than the second thickness of the upper semiconductor layer in the second region.

2. The semiconductor structure according to claim 1, wherein: The lower semiconductor layer and the upper semiconductor layer comprise silicon; and The insulating layer comprises silicon oxide.

3. The semiconductor structure according to claim 1, wherein: The insulating layer extends in the first region and the second region; and The lower semiconductor layer is separated from the upper semiconductor layer, which includes silicon, by the insulating layer.

4. The semiconductor structure according to claim 3, wherein: The first upper surface of the upper semiconductor layer in the first region is higher than the second upper surface of the upper semiconductor layer in the second region.

5. The semiconductor structure according to claim 1, wherein: The insulating layer extends in the second region but not in the first region; and The lower semiconductor layer is in contact with the upper semiconductor layer, which includes silicon, in the first region.

6. The semiconductor structure according to claim 5, wherein: The upper semiconductor layer has a flush upper surface.

7. The semiconductor structure according to claim 1, wherein: The thickness of the insulating layer is in the range of 10 nm to 30 nm.

8. The semiconductor structure according to claim 1, further comprising: A first set of transistors, having a first operating voltage and formed in the upper semiconductor layer in the first region; as well as The second group of transistors has a second operating voltage lower than the first operating voltage and is formed in the upper semiconductor layer in the second region.

9. The semiconductor structure according to claim 1, wherein, The first material of the upper semiconductor layer is different from the second material of the lower semiconductor layer.

10. The semiconductor structure according to claim 1, wherein, The first material of the upper semiconductor layer is the same as the second material of the lower semiconductor layer.

11. A semiconductor structure, comprising: Lower semiconductor layer; Upper semiconductor layer; as well as An insulating layer is provided between the lower semiconductor layer and the upper semiconductor layer. The first thickness of the insulating layer in the first region is greater than the second thickness of the insulating layer in the second region.

12. The semiconductor structure according to claim 11, wherein: The lower semiconductor layer and the upper semiconductor layer comprise silicon; and The insulating layer comprises silicon oxide.

13. The semiconductor structure according to claim 11, wherein: The insulating layer has a flush upper surface; and The first lower surface of the insulating layer in the first region is lower than the second lower surface of the insulating layer in the second region.

14. The semiconductor structure according to claim 11, wherein: The upper semiconductor layer has a flush upper surface; and The first upper surface of the lower semiconductor layer in the first region is lower than the second upper surface of the lower semiconductor layer in the second region.

15. The semiconductor structure according to claim 11, further comprising: A first set of transistors, having a first operating voltage and formed in the upper semiconductor layer in the first region; as well as The second group of transistors has a second operating voltage lower than the first operating voltage and is formed in the upper semiconductor layer in the second region.

16. The semiconductor structure according to claim 11, wherein, The first material of the upper semiconductor layer is different from the second material of the lower semiconductor layer.

17. The semiconductor structure according to claim 11, wherein, The first material of the upper semiconductor layer is the same as the second material of the lower semiconductor layer.

18. A method for forming a semiconductor structure, comprising: Remove a portion of the first semiconductor layer in the second region, such that the first upper surface of the first semiconductor layer in the first region is higher than the second upper surface of the first semiconductor layer in the second region; An insulating layer is formed on the second semiconductor layer; The first semiconductor layer is bonded to the insulating layer; as well as The first semiconductor layer is thinned such that the first thickness of the first semiconductor layer in the first region is greater than the second thickness of the first semiconductor layer in the second region.

19. The method according to claim 18, wherein, Bonding the first semiconductor layer to the insulating layer includes: The flush lower surface of the first semiconductor layer is bonded to the flush upper surface of the insulating layer.

20. The method according to claim 18, wherein, Forming the insulating layer on the second semiconductor layer includes: The upper surface of the second semiconductor layer is oxidized to form the insulating layer.

21. A method for forming a semiconductor structure, comprising: Remove a portion of the second semiconductor layer in the first region, such that the first upper surface of the second semiconductor layer in the first region is lower than the second upper surface of the second semiconductor layer in the second region; An insulating layer is formed on the second semiconductor layer, wherein the first thickness of the insulating layer in the first region is greater than the second thickness of the insulating layer in the second region; Bonding the first semiconductor layer to the insulating layer; and Thin the first semiconductor layer.

22. The method according to claim 21, wherein, Forming the insulating layer includes: The insulating layer is formed to cover the first upper surface and the second upper surface of the second semiconductor layer, wherein the first upper surface of the insulating layer in the first region is lower than the second upper surface of the insulating layer in the second region; and Polish the insulating layer to form a flush upper surface of the insulating layer.

23. The method according to claim 21, wherein, Forming the insulating layer includes: An insulating layer is formed to cover the first upper surface and the second upper surface of the second semiconductor layer, wherein the first upper surface of the insulating layer in the first region is lower than the second upper surface of the insulating layer in the second region; Remove a portion of the insulating layer in the second region to expose a portion of the second semiconductor layer in the second region; and The exposed portion of the second semiconductor layer in the second region is oxidized to allow the portion of the insulating layer in the second region to regrow, such that the insulating layer has a flush upper surface.

24. A method for forming a semiconductor structure, comprising: A mask layer is formed on the second semiconductor layer; Remove a portion of the mask layer in the first region to expose a first portion of the second semiconductor layer in the first region; Remove a portion of the first portion of the second semiconductor layer in the first region, such that the first upper surface of the second semiconductor layer in the first region is lower than the second upper surface of the second semiconductor layer covered by the mask layer in the second region; Oxidize the first portion of the second semiconductor layer in the first region to form the first portion of the insulating layer in the first region; Remove the mask layer in the second region to expose a second portion of the second semiconductor layer in the second region; Oxidize the second portion of the second semiconductor layer in the second region to form the second portion of the insulating layer in the second region, wherein the first thickness of the first portion of the insulating layer in the first region is greater than the second thickness of the second portion of the insulating layer in the second region; Bonding the first semiconductor layer to the insulating layer; and Thin the first semiconductor layer.

25. A method for forming a semiconductor structure, comprising: An insulating layer is formed on the second semiconductor layer; Remove a portion of the insulating layer to expose the second semiconductor layer in the first region; Semiconductor material is grown in the second semiconductor layer in the first region such that the first upper surface of the second semiconductor layer in the first region is flush with the upper surface of the insulating layer. The first semiconductor layer is bonded to the upper surface of the insulating layer and the first upper surface of the second semiconductor layer; as well as Thin the first semiconductor layer.

Images