Radio frequency device and preparation method thereof
By inverting and bonding the substrate structure during the fabrication of RF devices and thinning it from the back side of the bottom silicon layer, and using the intermediate insulating layer as a stop layer, the problem of large parasitic capacitance of SOI substrates is solved, and the RF performance of RF switching devices is improved.
Patent Information
- Application Number
- CN202510969391.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-11-11
AI Technical Summary
The large parasitic capacitance of SOI substrates affects the RF performance of RF switching devices.
A method for fabricating a radio frequency device is provided, which involves inverting a first substrate structure and bonding it to a second substrate structure, thinning and removing it from the back side of the bottom silicon layer, and using an intermediate insulating layer as a stop layer to significantly reduce parasitic capacitance and eliminate the coupling effect of substrate capacitance.
It significantly reduces parasitic capacitance, decreases signal leakage, improves the uniformity of breakdown voltage and power handling capability of RF switches, and enhances RF performance.
Smart Images
Figure CN120936098A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a radio frequency device and its fabrication method. Background Technology
[0002] As an important front-end module of mobile terminals such as mobile phones and Wi-Fi, radio frequency (RF) switching devices are usually composed of multi-stage structures connected in series to improve voltage withstand capability. The important performance parameters for evaluating RF switching devices are: breakdown voltage (RFBV) and harmonics.
[0003] SOI substrates (silicon-on-insulator substrates) have become the mainstream substrate choice for RF switching devices due to their core advantages such as the insulation and isolation of the buried oxide layer (intermediate insulating layer) and process compatibility. SOI substrates consist of a bottom silicon layer, an intermediate insulating layer, and a top silicon layer. However, because SOI substrates include a bottom silicon layer, there are substrate parasitic capacitances, which affect the RF performance of RF switching devices. Summary of the Invention
[0004] This application provides a radio frequency device and its fabrication method, which can solve the problem that the large parasitic capacitance of the SOI substrate of the radio frequency switch device affects the radio frequency performance of the radio frequency switch device.
[0005] On one hand, embodiments of this application provide a method for fabricating a radio frequency device, including:
[0006] A first substrate structure is provided, the first substrate structure comprising: a bottom silicon, an intermediate insulating layer on the bottom silicon and a top silicon on the intermediate insulating layer, wherein a plurality of gate structures, a first dielectric layer and a plurality of mutually independent metal interconnect structures are formed on the surface of the top silicon, the first dielectric layer covers the gate structures, the metal interconnect structures are located in the first dielectric layer, a plurality of source regions and a plurality of drain regions are formed in the top silicon, one source region and one drain region are respectively located in the top silicon on both sides of a gate structure, at least one segment of the metal interconnect structure is connected to the source region, and at least another segment of the metal interconnect structure is connected to the drain region;
[0007] Provide a second substrate structure;
[0008] The semiconductor structure containing the first substrate structure is inverted, and the inverted semiconductor structure is bonded to the second substrate structure;
[0009] From the back side of the underlying silicon, a portion of the thickness of the underlying silicon is reduced;
[0010] Remove the remaining thickness of the underlying silicon and stop on the back side of the intermediate insulating layer.
[0011] Optionally, in the method for fabricating the radio frequency device, the second substrate structure includes: a silicon substrate and a second dielectric layer located on the silicon substrate.
[0012] Optionally, in the method for fabricating the radio frequency device, a portion of the thickness of the underlying silicon is thinned from the back side of the underlying silicon using a chemical mechanical polishing process.
[0013] Optionally, in the fabrication method of the radio frequency device, a portion of the thickness of the underlying silicon is thinned from the back side of the underlying silicon using a dry etching process.
[0014] Optionally, in the fabrication method of the radio frequency device, the inverted semiconductor structure is bonded to the second substrate structure using a van der Waals bonding process.
[0015] Optionally, in the fabrication method of the radio frequency device, the thickness of the underlying silicon is greater than 0 μm and less than or equal to 1000 μm.
[0016] Optionally, in the fabrication method of the radio frequency device, each of the gate structures includes: a gate oxide layer, a polysilicon gate, and a sidewall structure, wherein the gate oxide layer is located on the top silicon layer, the polysilicon gate covers the gate oxide layer, and the sidewall structure is located on both sides of the polysilicon gate.
[0017] On the other hand, embodiments of this application also provide a radio frequency device, including:
[0018] A first substrate structure includes: an intermediate insulating layer and a top silicon layer located on the intermediate insulating layer. A plurality of gate structures, a first dielectric layer, and a plurality of independent metal interconnect structures are formed on the surface of the top silicon layer. The first dielectric layer covers the gate structures. The metal interconnect structures are located in the first dielectric layer. A plurality of source regions and a plurality of drain regions are formed in the top silicon layer. A source region and a drain region are located on both sides of the top silicon layer of a gate structure. At least one segment of the metal interconnect structure is connected to the source region, and at least another segment of the metal interconnect structure is connected to the drain region.
[0019] The second substrate structure is formed by inverting and bonding the semiconductor structure containing the first substrate structure onto the second substrate structure.
[0020] The technical solution of this application has at least the following advantages:
[0021] The method for fabricating an RF device provided in this application includes a second substrate structure. The semiconductor structure containing the first substrate structure is inverted and bonded to the second substrate structure. Then, the underlying silicon is thinned and removed from the back side of the bottom silicon layer, stopping at the back side of the intermediate insulating layer. This application utilizes the second substrate structure as a new substrate for the RF device and the intermediate insulating layer in the first substrate structure as a removal stop layer to thin and remove the bottom silicon. This significantly reduces the parasitic capacitance of the first substrate structure, effectively eliminates the negative effects of substrate parasitic capacitance, eliminates the coupling effect of substrate capacitance, reduces signal leakage, improves the overall breakdown voltage uniformity of the RF switch, and improves power handling capability, thereby improving the RF performance of the RF switching device. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0023] Figure 1 This is a flowchart of a method for fabricating a radio frequency device according to an embodiment of the present invention;
[0024] Figures 2-6 This is a schematic diagram of the semiconductor structure in each process step of fabricating the radio frequency device according to an embodiment of the present invention;
[0025] The reference numerals in the attached figures are explained as follows:
[0026] 10- Bottom silicon, 20- Intermediate insulating layer, 30- Top silicon, 31- Shallow trench isolation structure, 32- First source region, 33- First drain region, 34- Second source region, 35- Second drain region, 41- First gate oxide layer, 42- First polysilicon gate, 43- First sidewall structure, 51- Second gate oxide layer, 52- Second polysilicon gate, 53- Second sidewall structure, 60- Barrier layer, 70- First dielectric layer, 81- First metal interconnect structure, 82- Second metal interconnect structure, 83- Third metal interconnect structure, 84- Fourth metal interconnect structure, 91- Silicon substrate, 92- Second dielectric layer. Detailed Implementation
[0027] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0028] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0029] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0030] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0031] This application provides a method for fabricating a radio frequency device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a radio frequency (RF) device according to an embodiment of the present invention. The method for fabricating the RF device includes:
[0032] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the formation of the first to fourth metal interconnect structures according to an embodiment of this application. A first substrate structure is provided, which includes: a bottom silicon 10, an intermediate insulating layer 20 on the bottom silicon 10, and a top silicon 30 on the intermediate insulating layer 20. Multiple gate structures, a first dielectric layer, and multiple independent metal interconnect structures are formed on the surface of the top silicon 30. The first dielectric layer 70 covers the gate structures. The metal interconnect structures are located in the first dielectric layer 70. Multiple source regions and multiple drain regions are formed in the top silicon 30. One source region and one drain region are located on both sides of the top silicon 30 of a gate structure. At least one segment of the metal interconnect structure is connected to the source region, and at least another segment of the metal interconnect structure is connected to the drain region.
[0033] Preferably, the thickness of the underlying silicon 10 is greater than 0 μm and less than or equal to 1000 μm.
[0034] Preferably, the first dielectric layer 70 is made of silicon dioxide.
[0035] This embodiment takes the formation of two gate structures on the surface of the top silicon 30 as an example, namely the first gate structure and the second gate structure.
[0036] Specifically, the first gate structure includes: a first gate oxide layer 41, a first polysilicon gate 42, and a first sidewall structure 43. The first gate oxide layer 41 is located on the top silicon layer 30, the first polysilicon gate 42 covers the first gate oxide layer 41, and the first sidewall structure 43 is located on both sides of the first polysilicon gate 42. The second gate structure includes: a second gate oxide layer 51, a second polysilicon gate 52, and a second sidewall structure 53. The second gate oxide layer 51 is located on the top silicon layer 30, the second polysilicon gate 52 covers the second gate oxide layer 51, and the second sidewall structure 53 is located on both sides of the second polysilicon gate 52.
[0037] Furthermore, a barrier layer 60 is also covered on the first gate structure, the second gate structure, and part of the surface of the top silicon 30.
[0038] The top silicon 30 also has a plurality of shallow trench isolation structures 11, which are used to isolate different first gate structures and second gate structures.
[0039] Furthermore, the first source region 32 and the first drain region 33 are located in the top layer silicon 30 on both sides of the first polysilicon gate 42, and the second source region 34 and the second drain region 35 are located in the top layer silicon 30 on both sides of the second polysilicon gate 52.
[0040] In this embodiment, the first metal interconnect structure 81, the second metal interconnect structure 82, the third metal interconnect structure 83, and the fourth metal interconnect structure 84 are located in the first dielectric layer 70. The first metal interconnect structure 81 is connected to the first source region 32, the second metal interconnect structure 82 is connected to the first drain region 33, the third metal interconnect structure 83 is connected to the second source region 34, and the fourth metal interconnect structure 84 is connected to the second drain region 35.
[0041] It is worth noting that the semiconductor structure on the first substrate structure is merely an example in this application, and this application does not impose any specific limitations on the semiconductor structure on the first substrate structure. It can be any conventional film structure of radio frequency devices.
[0042] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3This is a schematic diagram of the second base structure according to an embodiment of the present application, providing a second base structure.
[0043] Preferably, the second substrate structure includes a silicon substrate 91 and a second dielectric layer 92 located on the silicon substrate 91.
[0044] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of a semiconductor structure after bonding a first substrate structure and a second substrate structure according to an embodiment of this application. The semiconductor structure containing the first substrate structure is inverted, and the inverted semiconductor structure is bonded to the second substrate structure. Specifically, the first dielectric layer 70 in the inverted semiconductor structure is bonded to the second dielectric layer 92.
[0045] Preferably, the material of the second dielectric layer 92 is silicon dioxide.
[0046] Preferably, the inverted semiconductor structure is bonded to the second substrate structure using a van der Waals bonding process.
[0047] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the thickness of the underlying silicon has been reduced according to an embodiment of this application. The underlying silicon 10 has been reduced in thickness from the back side.
[0048] In this embodiment, a portion of the thickness of the underlying silicon 10 is thinned from the back side of the underlying silicon 10 using a chemical mechanical polishing process.
[0049] In another embodiment, a portion of the thickness of the underlying silicon 10 is thinned from the back side of the underlying silicon 10 using a dry etching process.
[0050] Finally, perform step S5: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of a semiconductor structure after the remaining thickness of the bottom silicon 10 is removed and the process stops on the back side of the intermediate insulating layer, according to an embodiment of this application. The remaining thickness of the bottom silicon 10 is removed and the process stops on the back side of the intermediate insulating layer 20.
[0051] In this application, a second substrate structure is used as a new substrate for the radio frequency device, and the intermediate insulating layer in the first substrate structure is used as a removal stop layer to thin and remove the underlying silicon. This can significantly reduce the parasitic capacitance of the first substrate structure, effectively eliminate the negative effects of substrate parasitic capacitance, eliminate the coupling effect of substrate capacitance, reduce signal leakage, improve the overall breakdown voltage uniformity of the radio frequency switch, improve power handling capability, and thus improve the radio frequency performance of the radio frequency switching device.
[0052] Based on the same inventive concept, this application also provides a radio frequency device, see reference. Figure 6 The radio frequency device includes:
[0053] A first substrate structure includes: an intermediate insulating layer 20 and a top silicon 30 located on the intermediate insulating layer 20. A plurality of gate structures, a first dielectric layer 70, and a plurality of independent metal interconnect structures are formed on the surface of the top silicon 30. The first dielectric layer 70 covers the gate structures. The metal interconnect structures are located in the first dielectric layer. A plurality of source regions and a plurality of drain regions are formed in the top silicon 30. A source region and a drain region are located on both sides of the top silicon 30 of a gate structure. At least one segment of the metal interconnect structure is connected to the source region, and at least another segment of the metal interconnect structure is connected to the drain region.
[0054] The second substrate structure is formed by inverting and bonding the semiconductor structure on which the first substrate is located onto the second substrate structure.
[0055] Specifically, this embodiment takes the formation of two gate structures on the surface of the top silicon 30 as an example, namely a first gate structure and a second gate structure. Specifically, the first gate structure includes: a first gate oxide layer 41, a first polysilicon gate 42, and a first sidewall structure 43. The first gate oxide layer 41 is located on the top silicon 30, the first polysilicon gate 42 covers the first gate oxide layer 41, and the first sidewall structure 43 is located on both sides of the first polysilicon gate 42. The second gate structure includes: a second gate oxide layer 51, a second polysilicon gate 52, and a second sidewall structure 53. The second gate oxide layer 51 is located on the top silicon 30, the second polysilicon gate 52 covers the second gate oxide layer 51, and the second sidewall structure 53 is located on both sides of the second polysilicon gate 52.
[0056] The top silicon 30 also has a plurality of shallow trench isolation structures 11, which are used to isolate different first gate structures and second gate structures.
[0057] Furthermore, the first source region 32 and the first drain region 33 are located in the top layer silicon 30 on both sides of the first polysilicon gate 42, and the second source region 34 and the second drain region 35 are located in the top layer silicon 30 on both sides of the second polysilicon gate 52.
[0058] In this embodiment, the first metal interconnect structure 81, the second metal interconnect structure 82, the third metal interconnect structure 83, and the fourth metal interconnect structure 84 are located in the first dielectric layer 70. The first metal interconnect structure 81 is connected to the first source region 32, the second metal interconnect structure 82 is connected to the first drain region 33, the third metal interconnect structure 83 is connected to the second source region 34, and the fourth metal interconnect structure 84 is connected to the second drain region 35.
[0059] Furthermore, the second substrate structure includes a silicon substrate 91 and a second dielectric layer 92 located on the silicon substrate 91.
[0060] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a radio frequency device, characterized in that, include: A first substrate structure is provided, the first substrate structure comprising: a bottom silicon, an intermediate insulating layer on the bottom silicon and a top silicon on the intermediate insulating layer, wherein a plurality of gate structures, a first dielectric layer and a plurality of mutually independent metal interconnect structures are formed on the surface of the top silicon, the first dielectric layer covers the gate structures, the metal interconnect structures are located in the first dielectric layer, a plurality of source regions and a plurality of drain regions are formed in the top silicon, one source region and one drain region are respectively located in the top silicon on both sides of a gate structure, at least one segment of the metal interconnect structure is connected to the source region, and at least another segment of the metal interconnect structure is connected to the drain region; Provide a second substrate structure; The semiconductor structure containing the first substrate structure is inverted, and the inverted semiconductor structure is bonded to the second substrate structure; From the back side of the underlying silicon, a portion of the thickness of the underlying silicon is reduced; Remove the remaining thickness of the underlying silicon and stop on the back side of the intermediate insulating layer.
2. The method for fabricating a radio frequency device according to claim 1, characterized in that, The second substrate structure includes a silicon substrate and a second dielectric layer located on the silicon substrate.
3. The method for fabricating a radio frequency device according to claim 1, characterized in that, The thickness of the underlying silicon is reduced from the back side using a chemical mechanical polishing process.
4. The method for fabricating a radio frequency device according to claim 1, characterized in that, The thickness of the underlying silicon is reduced from the back side using a dry etching process.
5. The method for fabricating a radio frequency device according to claim 1, characterized in that, The inverted semiconductor structure is bonded to the second substrate structure using a van der Waals force bonding process.
6. The method for fabricating a radio frequency device according to claim 1, characterized in that, The thickness of the underlying silicon is greater than 0 μm and less than or equal to 1000 μm.
7. The method for fabricating a radio frequency device according to claim 1, characterized in that, Each of the gate structures includes: a gate oxide layer, a polysilicon gate, and a sidewall structure, wherein the gate oxide layer is located on the top silicon layer, the polysilicon gate covers the gate oxide layer, and the sidewall structure is located on both sides of the polysilicon gate.
8. A radio frequency device, characterized in that, include: A first substrate structure includes: an intermediate insulating layer and a top silicon layer located on the intermediate insulating layer. A plurality of gate structures, a first dielectric layer, and a plurality of independent metal interconnect structures are formed on the surface of the top silicon layer. The first dielectric layer covers the gate structures. The metal interconnect structures are located in the first dielectric layer. A plurality of source regions and a plurality of drain regions are formed in the top silicon layer. A source region and a drain region are located on both sides of the top silicon layer of a gate structure. At least one segment of the metal interconnect structure is connected to the source region, and at least another segment of the metal interconnect structure is connected to the drain region. The second substrate structure is formed by inverting and bonding the semiconductor structure containing the first substrate structure onto the second substrate structure.