System and method for improving integrated circuit yield

Abstract

A system and method for improving the yield of manufactured integrated circuits by providing remedial circuit elements including alternating planar transistors manufactured by a mid-pass process and / or a post-pass process to improve the yield of the integrated circuits according to in-operation monitoring by post-fabrication testing of the integrated circuits and / or by circuit operation. Remedial circuit elements that provide additional circuit functionality are enabled and disabled when needed. The system and method may address the distribution of power and signals, such as clock signals and / or high speed I / O signals, through areas of problems caused by sub-optimal design, circuit aging, and / or faults due to manufacturing process variations.

Description

Technical Field

[0001] This invention relates to a system and method for improving the manufacturing yield of integrated circuits. More specifically, this invention relates to using alternating planar transistors and circuit elements to enhance the performance of integrated circuits and / or correct erroneous behavior in integrated circuits. Background Technology

[0002] Semiconductor manufacturers refer to Moore's Law to describe the continuous reduction in the size and corresponding increase in the density of semiconductor components (such as transistors and interconnect structures) on integrated circuits. Moore's Law states that the number of transistors on a chip die roughly doubles every two years.

[0003] To achieve this scale of growth, significant technological efforts have been invested in shrinking the size of the components that make up semiconductor integrated circuits. However, despite the significant reduction in component size, the overall size of many integrated circuits still increases significantly as device functionality and performance continue to improve, leading to ever-larger die sizes. For example, the Apple M1 processor used in some Apple devices reportedly has 11.8 billion transistors and a die size of approximately 120 square millimeters, while the Apple M1 Max processor reportedly has 57 billion transistors and a die size of approximately 490 square millimeters. Other advanced semiconductor devices have similar numbers of transistors and die sizes.

[0004] This combination of integrating smaller components onto a larger die presents numerous challenges for semiconductor designers and manufacturers. In fact, a significant proportion of manufactured devices fail to operate properly or at the expected speed due to a variety of factors, including: minute, undesirable variations in the manufacturing process; overly optimistic design rules in the software used to design the circuits, leading to design flaws; errors by the circuit designer; and so on.

[0005] Therefore, the manufacturing yield of these semiconductor devices (the percentage of manufactured devices operating within specified acceptable parameters, as determined by post-manufacturing testing) is typically lower than expected. For integrated circuits whose designs have reached the limits of fabrication technology, the yield can be far below the expected yield. Decreasing yields mean reduced profits for manufacturers, and the supply of such advanced devices may be lower than expected. Summary of the Invention

[0006] The purpose of this invention is to provide a novel method and system for improving the yield of manufactured integrated circuits, which eliminates or mitigates at least one disadvantage of the prior art.

[0007] According to a first aspect of the invention, a system for improving the yield of manufactured integrated circuits is provided, each integrated circuit comprising: a set of designed circuits implemented as circuit elements manufactured by a front-end process, including at least one front-end process circuit element as a remedial element; at least one transistor manufactured as an alternating planar transistor and operable to selectively activate or deactivate at least one remedial front-end process circuit element after the manufacture of the integrated circuit based on the results of tests performed on the integrated circuit.

[0008] Preferably, the remedial circuitry includes an additional buffer to amplify the signal at at least one front-end element. Also preferably, the system further includes a programmable memory element for controlling the selective activation and deactivation of at least one remedial front-end process circuitry element.

[0009] According to another aspect of the present invention, an integrated circuit is provided, comprising: at least two circuits, each circuit being configured to implement a function, wherein a first circuit of the at least two circuits is configured to implement an optional function; at least one alternating planar transistor operable to selectively enable and disable the first circuit of the at least two circuits; and a programmable means for controlling the at least one alternating planar transistor to enable and disable the first circuit of the at least two circuits.

[0010] According to another aspect of the present invention, a method for manufacturing an integrated circuit is provided, the method comprising the steps of: designing necessary circuitry to implement the desired function of the integrated circuit; reviewing the design of the necessary circuitry to identify regions where operational problems may occur due to variations in the manufacturing process; adding remedial elements to the design of the necessary circuitry to provide remedial circuitry performance at the identified regions; performing front-end process fabrication of the designed integrated circuit; fabricating alternating planar transistors for at least each identified region, the alternating planar transistors being operable to selectively enable and disable the remedial circuitry in the identified regions; completing the manufacturing process to obtain a finished integrated circuit; and testing the finished integrated circuit to identify designated regions that do not meet predefined test criteria of the identified regions, and for each identified designated region, programming a transistor associated with each identified designated region to enable the corresponding remedial element.

[0011] Preferably, the testing of the finished integrated circuit is performed dynamically during circuit operation.

[0012] According to another aspect of the present invention, a method for improving yield in the manufacture of integrated circuits is provided, the method comprising the steps of: designing a MOS logic integrated circuit; identifying at least one possible circuit fault point in the designed MOS logic integrated circuit; modifying the design of the MOS logic integrated circuit by adding a remedial element to the design of the MOS logic integrated circuit at the identified at least one possible fault point, the remedial element being located on a plane of the MOS logic integrated circuit, the plane being different from the plane of the MOS logic integrated circuit in which the MOS logic is located; manufacturing the MOS logic integrated circuit using the modified design; testing the manufactured integrated circuit to determine whether the at least one possible fault point is a fault point, thereby detecting whether the at least one possible fault point is a fault point; and connecting the remedial element to the identified fault point in the manufactured MOS logic to correct the fault.

[0013] Preferably, the remedial element is connected to the identified fault point via a transistor formed on the plane of the MOS logic integrated circuit, which is different from the plane where the MOS logic is located.

[0014] The present invention provides a system and method for improving the yield of manufactured integrated circuits by providing transistors fabricated on alternating planes of a die to enable and disable redundant circuit elements, which provide additional circuit functionality as needed, based on determinations made during post-fabrication testing of the integrated circuit or dynamically determined during operation of the integrated circuit. Attached Figure Description

[0015] Preferred embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1 A schematic example of a prior art clock tree for integrated circuits is shown; and Figure 2 A schematic diagram of a buffer for use in an integrated circuit according to an aspect of the present invention is shown; and Figure 3a and Figure 3b It shows Figure 2 A schematic diagram of two variants of the buffer; Figure 4 A schematic example of a clock tree employing a buffer in an integrated circuit according to an aspect of the present invention is shown; Figure 5 A block diagram of a clock management system according to one aspect of the present invention is shown; Figure 6 A power supply decoupling according to one aspect of the present invention is shown; and Figure 7 A flowchart of a method according to one aspect of the present invention is shown. Detailed Implementation

[0016] As briefly discussed above, the current trend is to reduce the size of circuit components in integrated circuits while increasing the number of circuit elements and the size of the dies that make up the circuits. This trend leads to challenges in manufacturing these integrated circuit instances that can function properly.

[0017] This invention addresses these challenges by providing remedial circuit elements fabricated on a plane of an integrated circuit, unlike the planes conventionally used for forming MOS logic. As described below, these remedial elements can resolve one or more common causes of circuit failures and can switch to MOS logic circuitry as needed, or in some cases, switch out of the logic circuitry.

[0018] A common example of the challenges in modern integrated circuit system design is the system clock problem. Typical digital synchronous systems rely heavily on a periodic signal known as the clock (“CLK”), which is available throughout the circuit to ensure fault-free operation. For example, system memory storage elements such as registers and latches are typically updated when the CLK signal arrives.

[0019] A typical ideal clock signal is a square wave, and system components typically respond to either the rising (positive) or falling (negative) side of the square wave pulse. For example, a register might be designed to update its output when the positive edge of the CLK signal arrives. Ideally, this clock edge must arrive precisely and simultaneously throughout the entire integrated circuit system; otherwise, it could lead to unexpected operations, including erroneous outputs, race conditions, and so on. Ensuring the distribution and near-simultaneous arrival of clock signals is a significant challenge in designing modern integrated circuits.

[0020] A specially designed clock distribution network (called a clock tree (“CT”) is typically designed and employed to provide clock signals throughout the integrated circuit and to limit the movement of clock signals away from their ideal arrival time (also known as clock skew).

[0021] Sometimes, an alternative clock distribution network called a clock grid (“CM”) is implemented. While it is generally accepted that clock grids offer better skew management compared to clock trees, clock grids consume more power and require a larger area when implemented on the die. Therefore, integrated circuit designers typically have to make trade-offs between performance, available area, power consumption, and product yield when designing clock signal distributions on the die.

[0022] Figure 1The illustration shows a typical example of a particular type of clock distribution network (CT), generally indicated by 20. In the H-tree, the clock signal 24 is input to a set of clock buffers 28 (which are typically just simple inverters), which then distribute the clock pulses to the individual circuit components 32 as needed. Although Figure 1 The ideal example seems like a straightforward solution, but in most practical complex integrated circuits, the H-tree 20 will have to drive different groups of circuit components 32a, 32b, 32c, or 32d at high switching frequencies. These components may have large, uneven, and distributed capacitive loads. Therefore, buffers 28 of varying strengths must be designed into the H-tree (or other CTs) to reliably drive the intended loads of circuit elements 32 (such as registers, latches, and dynamic logic gates).

[0023] This requires the circuit designer to estimate the capacitive load to be applied to each buffer 28, and then design each buffer 28 with sufficient capacity to meet the estimated load. Providing a buffer 28 with greater capacity requires more area on the die and consumes more power. Therefore, the designer must carefully balance the requirements to ensure adequate drive for the capacitive load while avoiding over-designing the buffer 28, thus wasting die area and power.

[0024] Furthermore, while using an optimized H-tree (with appropriately sized and placed buffers) can reduce clock skew, it cannot be eliminated entirely. Adding to the complexity is the fact that manufacturing process variations during integrated circuit fabrication can result in some dies having clock trees that operate according to specifications, while other dies with identical designs fail post-manufacturing testing, thus reducing chip yield.

[0025] Furthermore, sophisticated CT implementations (such as large H-trees) inevitably consume a significant portion of the total power consumed in complex integrated circuits, and in some applications, the CT itself accounts for a quarter or more of the total power consumption of the integrated circuit. This is particularly challenging because power consumption and its associated thermal management issues are significant limiting factors for design.

[0026] Ironically, while synchronous timing circuits (CTs) play a crucial role in synchronous sequential integrated circuits, their functionality is often not directly observable for post-manufacturing testing purposes, presenting yet another challenge. Poorly designed CTs can lead to circuit failures due to timing errors that are extremely difficult to debug. Unfortunately, the distributed nature of CTs and the high complexity of their design can also result in intermittent failures, leading to decreased yield and / or reliability of the integrated circuits, and these problems become more severe as circuit density and die size increase.

[0027] Known attempts to address some of these issues involve using active and / or passive clock deskip circuitry. However, closed-loop deskip techniques also consume valuable and limited die area, consume significant power, and require considerable design effort.

[0028] All manufactured integrated circuits require post-manufacturing testing to ensure they meet specifications. The testing and qualification of integrated circuits are typically completed in several stages and can be both expensive and time-consuming, significantly increasing the overall cost of manufacturing integrated circuits.

[0029] During the testing process, locations where the timing margins of the circuitry on the integrated circuit being tested do not meet specifications can be identified. These locations will cause the integrated circuit to fail, or the circuit will need to be sold at a degraded operating speed or with reduced functionality. Currently, repairing such integrated circuits is technically and economically infeasible.

[0030] Sometimes, integrated circuit designers add additional circuitry to improve timing margins. These techniques include the aforementioned active deskip circuitry, or programmable buffers with non-volatile memory elements. However, all these known techniques must be incorporated early in the integrated circuit design process, thus failing to address timing issues that are only identified after the design is complete. Moreover, as mentioned above, such techniques consume valuable die area that could otherwise be used for other purposes and increase the integrated circuit's power consumption. Therefore, designers attempt to adopt such solutions only when they anticipate timing issues. Consequently, the design process requires designers to make a best-effort estimation of where timing margins might be compromised, which could lead to wasted die area and power, such as over-provisioning of buffers, or cause the device under test to fail to meet specifications.

[0031] The inventors have determined that remedial measures for integrated circuits can be performed after major manufacturing is complete to correct design and fabrication problems (such as clock skew or other errors). Specifically, as disclosed herein, remedial measures for integrated circuits can be performed after MOS transistor-based logic circuits are formed on the integrated circuit die to address such clock skew or other problems.

[0032] As is well known, the traditional fabrication process for integrated circuits is divided into the front-end process (“FEOL”) stage, in which circuits based on MOS transistors are formed on a first plane of the die; the back-end process (“BEOL”) stage, in which other features and requirements, such as metal layers and insulating layers, are added to another plane of the die (usually above the first plane) to complete the integrated circuit; and the middle-end process (“MOL”) stage, which is between the FEOL and BEOL stages, in which other processes are performed.

[0033] In this invention, remedial circuitry (discussed further below) can be added to integrated circuits with identified or potential problems by providing devices fabricated during the MOL or BEOL stage of device fabrication. Such devices have been disclosed in published PCT application WO 2023 / 285936 by Barlage et al. and published PCT application WO 2023 / 285951 by Barlage and Shoute, and are referred to herein as “alternating plane” (“AP”) transistors because they are fabricated on specific planes of a semiconductor die that are located above or below the die planes on which conventional devices are fabricated during the FEOL manufacturing stage.

[0034] Figure 2 A schematic representation of an example of a remedial technique for resolving faults or problems related to clock skew is shown. Figure 2 In this example, the novel buffer is typically designated 100, and in this case, buffer 100 serves as a clock buffer. Buffer 100 comprises two inverters, 104 and 108, with the output of inverter 104 applied to the input of inverter 108 in a manner similar to conventional clock buffers and other signal buffers. However, each inverter 104 and 108 is further paired with corresponding MOS transistors 112 and 116. It is conceivable that inverters 104 and 108, along with their corresponding MOS transistors 112 and 116, together with the logic circuitry supplying the clock, are fabricated on the integrated circuit die during the FEOL stage.

[0035] MOS transistors 112 and 116 each have corresponding control transistors 120 and 124, which are manufactured during the MOL and / or BEOL production stages (by...). Figure 2 The AP transistor (indicated by the dashed line 128 in the diagram) is fabricated during this period. It is also conceivable that control transistors 120 and 124 can be formed as active vias as desired.

[0036] In the operation of clock buffer 100, when control signal CTRL1 is applied to AP transistor 120, the rise time of the positive edge of the clock signal output from buffer 100 can be shortened proportionally to the strength of the combination of transistors 112 and 120. Similarly, when control signal CTRL2 is applied to AP transistor 124, the fall time of the negative edge of the clock signal output from buffer 100 is shortened proportionally to the strength of the combination of transistors 116 and 124.

[0037] As will be apparent, either or both of the control signals CTRL1 and CTRL2 can be applied to buffer 100 as needed to ensure that the clock signal from buffer 100 has the timing / strength required by its driving circuitry. When control signals CTRL1 and / or CTRL2 are not applied to AP transistors 120 and / or 124, MOS transistors 112 and 116 do not consume power. Buffer 100 consumes no additional power only when one or both of the control signals CTRL1 and CTRL2 are applied.

[0038] As will be apparent to those skilled in the art, it is conceivable that, in most cases, control signals CTRL1 and CTRL2 will be DC signals; however, it is also conceivable that, in some cases, either or both of control signals CTRL1 and CTRL2 may be switched at a desired frequency by a square wave or pulse width modulation (PWM) signal. In the latter case, output capability may be provided to buffer 100 intermittently as needed.

[0039] If a certain area of ​​the circuit design only responds to one side (positive or negative) of the clock signal, the required die area on the logic plane can be reduced by removing unnecessary circuitry, thus simplifying the design of the clock buffer 100. Figure 3a This clock buffer 150 is shown in the case where the logic circuit receiving the clock signal does not respond to the negative side of the clock signal, and Figure 3b A clock buffer 170 is shown in the case where the logic circuit receiving the clock signal does not respond to the positive side of the clock signal.

[0040] Therefore, buffers 100, 150, and / or 170 allow integrated circuit designers to provide additional capabilities to clock buffers that are envisioned to require additional strength, while avoiding an additional fixed amount of power consumption. In some cases where the designer's estimate of the required clock buffer capabilities is overly optimistic, CTRL1 and / or CTRL2 of one or more buffers 100 can be asserted for all fabrication instances of the device, providing a remedial design "correction." In other cases, post-manufacturing testing can determine that some identified devices require CTRL1 and / or CTRL2 assertions to ensure proper device operation due to process variations or other influences. As will be apparent, additional power consumption (and associated exacerbated thermal issues) only occur when it is determined during post-manufacturing testing that additional capabilities are required at the outputs of buffers 100, 150, and / or 170.

[0041] In this way, designers of complex integrated circuits can incorporate a certain level of additional latent buffering performance into their designs, and selectively activate this additional capability if and only if it is subsequently determined that additional buffering performance is needed. Complex integrated circuits can have numerous instances of this additional latent buffering capability, thus providing dozens, hundreds, or even more instances of this capability as desired. By employing AP transistors, the use of buffers 100, 150, and / or 170 has a minimal impact on the die area on the fabrication plane of the MOS logic circuit.

[0042] As mentioned above, in some cases, due to design errors (such as optimistic estimates of clock load), this additional buffering capability may be required on all integrated circuits. However, it is conceivable that, more commonly, due to variations in manufacturing processes, this additional buffering capability is required only on a certain percentage of manufactured integrated circuits (determined by post-manufacturing testing).

[0043] Specifically, depending on the integrated circuit design and fabrication, post-production testing of integrated circuits can determine: specific instances that do not require additional buffering capabilities (i.e., the original design size is reasonable and properly implemented); instances where the original design is overly optimistic and always requires some or all of the additional buffering capabilities; or instances where process variations on the silicon wafer, etc., cause some instances of the integrated circuit to require activation of the additional potential buffering capabilities, while other instances do not require activation of the additional potential buffering capabilities. In the last case, as part of the testing process, the appropriate control signals (CTRL1 and / or CTRL2) for each corresponding instance of the additional potential buffering capabilities can be enabled or disabled based on the test results of the specific chip.

[0044] The provision of control signals to activate additional potential buffering capabilities can be accomplished in various ways, such as by burning a "fuse" on the integrated circuit, or by appropriately setting control bits in the SRAM circuitry on the integrated circuit.

[0045] Figure 4An H-tree clock distribution network employing clock buffers 100, 150, and 170 according to an aspect of the invention is shown. As illustrated, clock input 24 is applied to buffer 100a, which distributes the clock signal into the illustrated tree. This buffer can amplify both the rising and falling edges of the clock signal as needed, and therefore has input signals 204 and 208 corresponding to the aforementioned CTRL1 and CTRL2 control signals. In contrast, circuit element 32b responds only to the falling side of the clock signal, so buffer 170b has input 220 corresponding to input CTRL2, and buffer 170b can amplify the falling side of the clock signal when needed and as required. Circuit element 32c has elements that respond to both the rising and falling sides of the clock signal, so buffer 100c can amplify both sides of the clock signal, and has inputs 212 and 216 corresponding to the CTRL1 and CTRL2 inputs to enable this amplification when necessary. The designers of the integrated circuit embodying the clock tree 200 have determined that the circuit element 32d can be properly clocked without the need for an additional boost clock signal, and therefore provides the clock signal to it via the conventional buffer 28.

[0046] As will be apparent to those skilled in the art, by enhancing the rising and / or falling edges of the clock signal, the present invention also addresses clock skew (i.e., timing variations when the rising or falling edge of the clock signal is detected).

[0047] Figure 5 An example of a clock management system 300 is shown, which can generate CTRL1 and / or CTRL2 signals for each buffer 100, 150, and / or 170 to boost the corresponding clock edge and / or resolve clock skew as needed. As shown, system 300 includes a clock signal generator 304 that generates a clock signal 306 for the integrated circuit to which it is mounted. The clock signal 306 is provided to both a clock distribution network 308 (which may be an H-tree, clock grid, or other suitable distribution network) and a clock management controller 312. The clock management controller 312 is connected to the nodes of interest in the clock distribution network 308 (i.e., the nodes to which the chip designer wishes to provide selective boosts) and is provided with measurements 316 of the clock signal 306 from these nodes. In response to the measurements 316, the clock management controller 312 generates appropriate CTRL1 and / or CTRL2 signals 320 to the appropriate instances of buffers 100, 15, and / or 170 on the integrated circuit.

[0048] The clock management controller 312 can be implemented in various ways, as will be apparent to those skilled in the art. For example, the clock management controller 312 may include a set of fuses that are "blown" to enable the CTRL1 and / or CTRL2 signals of the respective buffers 100, 150, and / or 170, thereby resolving clock allocation problems identified by post-fabrication testing. Similarly, the clock management controller 312 may include clock skew detection circuitry implemented by phase-locked loops and / or delay-locked loop circuitry, thermal sensors, and / or other input devices, thereby allowing dynamic identification and subsequent correction of the clock signal 306 by setting relevant signals in the CTRL1 and / or CTRL2 signals.

[0049] Furthermore, this invention is not limited to solving clock signal level problems, but can be used to solve problems related to a wide variety of control signals or other signals in complex integrated circuits. For example, high-speed input / output (I / O) pins have become prevalent in modern chip designs to enable the transfer of large amounts of data between integrated circuits. Some examples of such I / O systems are commonly referred to as serializers and deserializers (“SERDES”). State-of-the-art SERDES and similar systems can achieve data rates exceeding 100 Gb / s. At these speeds, optimizing timing to reduce crosstalk, bit error rate, etc., is extremely challenging.

[0050] Therefore, this I / O utilizes signal processing, noise shaping, and filtering techniques to mitigate the aforementioned timing challenges. However, process variations in manufacturing such integrated circuits and non-ideal modeling / simulation during the design of related circuits can make the practical implementation of such high-speed signal processing circuits difficult. With this invention, multiple sets of buffers (such as buffer 100 described above) can be integrated at critical locations in the high-speed I / O circuit, providing programmable levels of desired or necessary output signal enhancement based on testing of the actual finished integrated circuit. As a result of post-manufacturing testing of the I / O circuit, these buffers will be controlled to provide the necessary signal levels for the specified operation of the I / O circuit. Therefore, once the design is completed and the resulting manufactured instance of the integrated circuit is tested, the signal can be "tuned" by activating or deactivating the signal enhancement of buffer 100 to provide the necessary performance.

[0051] One of the key advantages of using AP transistor-based circuits as described above is that these circuits are still able to implement corrective measures after all FEOL MOS transistors have been integrated, connected, and tested for performance.

[0052] Therefore, as described above, a structured approach for improving the yield of correctly executed integrated circuit instances can be envisioned to include the following steps: identifying regions in the design of the integrated circuit where signals (such as clock signals or other signals on the chip) are believed to be problematic; providing additional latent buffering and / or output capabilities at these identified locations, wherein the additional latent buffering capabilities can be selectively activated as needed; testing each manufactured integrated circuit to determine if there are any test performance problems due to insufficient signal performance (for which additional latent buffering capabilities have already been provided); and, if problems exist, activating the additional latent buffering capabilities to address the identified performance deficiencies, thereby increasing the number of integrated circuits that pass the test requirements (i.e., yield).

[0053] It is also conceivable that the use of AP transistor-based circuits could ensure the continued operation of integrated circuits deployed in the field. Specifically, once deployed, all semiconductor integrated circuits are susceptible to varying degrees of reliability failures throughout their lifespan. These reliability failures are typically caused by various aging mechanisms, such as electromigration, hot carriers, gate oxide damage, and, to name a few, gate oxide damage. These failures usually occur gradually, often preceded by performance degradation. High on-chip current density, high-speed signal switching, and high operating temperature are the main factors accelerating these aging and failure mechanisms. Therefore, high-speed I / O, clock networks, and high-speed on-chip bus drivers are particularly prone to such failures.

[0054] A high-reliability architecture for circuit elements can be achieved by using AP transistor-based circuitry, combined with devices provided in FEOL MOS circuitry for redundancy and / or buffering, or other functions that can be activated in a programmable manner. Such high-reliability circuit elements can include backup drivers, buffers, and transistors that are enabled by AP transistors once the original driver begins to show signs of aging / failure.

[0055] In a preferred embodiment of this high-reliability design, the non-volatile programmable memory can be used in conjunction with AP transistor-based circuitry, allowing the associated circuit elements to be dynamically activated and / or deactivated in the field. However, as will be apparent to those skilled in the art, this architecture can also be deterministically programmed in the field via various mechanisms such as fuses, antifuses, and SRAM cells.

[0056] Therefore, a high-availability system can include one or more AP transistor-based circuits, programmable devices, and MOS circuits, which can be used to mitigate reliability failures in chip circuits.

[0057] Another problem that this invention can solve is efficient power delivery. Implementing power delivery systems on state-of-the-art integrated circuits with billions of transistors is another complex and challenging problem, and poorly designed power delivery networks can lead to voltage drops, power supply noise, and other issues. Such power delivery problems can result in intermittent failures that are difficult or impossible to debug, and can also lead to timing-based failures and other types of faults.

[0058] To address noise in power supply design, traditional integrated circuit designs utilize a large portion of the on-chip area to implement decoupling capacitors to reduce power supply noise. However, these noise reductions and power distribution system designs require a significant amount of design work.

[0059] In traditional integrated circuit manufacturing, the measurement and characterization of power supply noise is one of the test parameters that integrated circuits must typically pass. Despite the efforts of designers, if the power supply noise level tested in a given integrated circuit is still too high to be acceptable, the integrated circuit is usually discarded, resulting in a decrease in the yield of the production batch.

[0060] With this invention, after testing and characterizing an initial fabrication example of an integrated circuit, AP transistors and related devices (such as filter capacitors) can be subsequently integrated onto the BEOL or MOL plane to remedially enhance any circuit regions that testing has indicated have insufficient power delivery. By employing AP transistors and devices, there is no need to redesign the FEOL logic circuitry of the integrated circuit, nor the associated masks and other tools used to fabricate that FEOL logic circuitry. This is believed to be a significant advantage of this invention.

[0061] It is also conceivable that the power supply problem could be solved dynamically, similar to the approach discussed above for clock signals. Specifically, Figure 6 An example of a programmable power decoupling 400 is shown. In this example, a load 404 is connected to a power supply 408 via a power lead 412, and the power decoupling 400 is connected to the power lead 412, preferably close to the load 408. The power decoupling 400 includes a capacitor 416 and an AP transistor 420, which is controlled by a signal CTRL3 applied to its gate. The capacitor 416 can be fabricated using a MOS circuit formed in the FEOL process, but more preferably formed on another plane of the integrated circuit via MOL and / or BEOL processes. In this case, the power decoupling 400 occupies very little (if any) of the die area used for fabricating the FEOLMOS device.

[0062] As will be apparent to those skilled in the art, capacitor 416 can switch to or switch out the power circuit formed between power supply 404 and load 408 by setting or removing the CTRL3 signal to filter noise on power supply lead 412 and / or suppress spikes or voltage drops on the power supply lead.

[0063] It is conceivable that, in many cases, capacitor 416 can be shared by several instances of power supply decouplers 400, any or all of which can be activated or deactivated as needed for a particular integrated circuit. Similar to the CTRL1 and CTRL2 signals discussed above, the CTRL3 signal of each power supply decoupler 400 can be generated in any suitable manner and can be dynamically (as needed) set by a power management system that monitors the power performance at the relevant part of the integrated circuit, or permanently (via fuses or antifuse devices, etc.) set after post-manufacturing testing has identified one or more problem areas on the manufactured integrated circuit under test.

[0064] In another aspect of the invention, it is often desirable to customize integrated circuits that would otherwise be mass-produced for a specific application area. Traditionally, this requires creating and manufacturing various versions of the infrastructure. For example, microprocessors can be optimized for desktop computers, laptops, or server applications. Even within these specific areas, it is known to create multiple variants to cater to various market segments, such as low-cost consumer devices, industrial use cases, server applications, etc.

[0065] Traditional integrated circuit manufacturing processes create various design variants requiring different sets of expensive masks, different test schemes, and so on. In contrast, this invention allows integrated circuits to be manufactured using a conventional MOS transistor architecture with the addition of AP transistors, which can be programmable during the field or testing phases. This allows for the activation or deactivation of functions on the integrated circuit to achieve desired variants. Therefore, a single integrated circuit can be designed, manufactured, and tested, reducing manufacturing costs, such as the need for additional mask sets and / or test systems, while still allowing manufacturers to sell multiple variants.

[0066] Furthermore, it is conceivable that if a manufactured integrated circuit fails a test related to the performance requirements of a variant (e.g., a high-speed server variant), the integrated circuit can be reprogrammed via AP transistors to a variant (e.g., a desktop computer processor) in which the failed test is irrelevant to the successful performance of that variant.

[0067] For example, a server variant might specify a certain number of operational processor cores, while a desktop variant might specify fewer. If an integrated circuit manufactured in a particular case has one or more cores that fail testing, the failed cores can be deactivated by the AP transistor and effectively removed from the integrated circuit, allowing the circuit to be reconfigured for another variant, such as a desktop variant designed to have and provide a reduced number of processing cores. In this case, the AP transistor can, for example, disable the power supply to the core to be disabled. This capability will result in a significantly improved yield, as more manufactured devices can be sold, although perhaps at a lower price.

[0068] Figure 7 A flowchart of a method according to one aspect of the invention is shown. The method begins at step 500, in which a MOS logic circuit is designed. At step 504, points in the designed circuit that may require remediation are identified. This identification can be performed by reviewing the design using simulation tools, designer-guided review, etc., or by fabricating a "first-time silicon" prototype of the integrated circuit using the design, and then testing instances of the first-time silicon prototype to identify areas that may require remediation.

[0069] At step 508, the design of the integrated circuit is modified to add a remedial element at the point determined in step 504. At step 512, an instance of an integrated circuit using the design modified as in step 508 is manufactured.

[0070] At step 516, an instance of the integrated circuit manufactured in step 512 is tested to identify points in the circuit where remedial elements are expected to be activated, and at step 520, the remedial elements at these identified points are connected to the MOS logic circuit of the integrated circuit.

[0071] Although Figure 7 The method aims to improve the yield of manufactured integrated circuits through post-manufacturing verification and remediation. However, as mentioned above, the present invention can also be used to correct faults and defects in integrated circuits in use. Specifically, steps 516 and 520 can be dynamically performed during the use of the integrated circuit to remedy problems and faults caused by aging, environmental conditions, etc.

[0072] The above embodiments of the present invention are intended as examples of the present invention, and those skilled in the art can make changes and modifications to the present invention without departing from the scope of the present invention as defined only by the appended claims.

Claims

1. A system for improving the yield of manufactured integrated circuits, each integrated circuit comprising: A set of designed circuits, said set of designed circuits being implemented as circuit elements manufactured by a front-end process, including at least one front-end process circuit element as a remedial element. At least one transistor, said at least one transistor being manufactured as an alternating planar transistor, and operable to selectively activate or deactivate at least one remedial front-end process circuit element after the manufacture of said integrated circuit, based on the results of tests performed on said integrated circuit.

2. The system as claimed in claim 1, wherein, The remedial circuit element includes an additional buffer to amplify the signal at the at least one front-end element.

3. The system as described in claim 2, wherein, The buffer is a clock buffer.

4. The system as described in claim 3, wherein, The integrated circuit includes at least two remedial front-end circuit elements and at least two alternating planar transistors, wherein a first alternating planar transistor of the at least two alternating planar transistors is operable to selectively activate or deactivate a first remedial front-end circuit element of the at least two remedial front-end circuit elements to increase the speed of the rising edge of the clock signal through the buffer, and a second alternating planar transistor of the at least two alternating planar transistors is operable to selectively activate or deactivate a second remedial front-end circuit element of the at least two remedial front-end circuit elements to increase the speed of the falling edge of the clock signal through the buffer.

5. The system of claim 1, further comprising a programmable memory element for controlling the selective activation and deactivation of the at least one remedial front-end process circuit element.

6. The system as claimed in claim 2, wherein, The redundant front-end process circuit elements are additional enhancement buffers for input / output signals.

7. An integrated circuit, comprising: At least two circuits, each circuit being designed to implement a function, wherein the first circuit of the at least two circuits is designed to implement an optional function; At least one alternating planar transistor, the at least one alternating planar transistor being operable to selectively enable and disable the first circuit of the at least two circuits; And a programmable device for controlling the at least one alternating planar transistor to enable and disable the first circuit of the at least two circuits.

8. The integrated circuit as claimed in claim 7, wherein, When the first circuit of the at least two circuits fails the test, the programmable device disables the first circuit of the at least two circuits in response to the input from the test on the first circuit of the at least two circuits.

9. A method for manufacturing an integrated circuit, the method comprising the following steps: Design the necessary circuitry to implement the desired functionality of the integrated circuit; Review the design of the necessary circuitry to identify areas where operational problems may arise due to variations in the manufacturing process; Add remedial elements to the design of the necessary circuitry to provide remedial circuitry performance in the identified region; Perform front-end process manufacturing of the designed integrated circuits; For at least each defined region, alternating planar transistors are manufactured, the alternating planar transistors being operable to selectively enable and disable the remedial circuitry in the defined regions; The manufacturing process is completed to obtain the finished integrated circuit; as well as The finished integrated circuit is tested to identify designated areas that do not meet the predefined test criteria of the identified areas, and for each identified designated area, the transistor associated with each identified designated area is programmed to enable the corresponding remedial element.

10. The method of claim 9, wherein, The remedial element is a clock buffer.

11. The method of claim 9, wherein, The remedial element is a power supply decoupling device.

12. The method of claim 9, wherein, Testing of the finished integrated circuit is performed dynamically during the operation of the integrated circuit.

13. A method for improving yield in the manufacture of integrated circuits, the method comprising the following steps: Design MOS logic integrated circuits; Identify at least one possible circuit failure point in the designed MOS logic integrated circuit; The design of the MOS logic integrated circuit is modified by adding a remedial element to the design of the MOS logic integrated circuit at at least one identified possible point of failure, the remedial element being located on a plane of the MOS logic integrated circuit that is different from the plane of the MOS logic integrated circuit in which the MOS logic is located; The modified design is used to manufacture the MOS logic integrated circuit; The manufactured integrated circuit is tested to determine whether the at least one possible fault point is a fault point, thereby detecting whether the at least one possible fault point is a fault point; as well as The remedial element is connected to the identified fault point in the manufactured MOS logic to correct the fault.

14. The method of claim 13, wherein, The remedial element is connected to the identified fault point via a transistor formed on the plane of the MOS logic integrated circuit, which is different from the plane in which the MOS logic is located.

15. The method of claim 14, wherein, The transistor connects to the remedial element in response to a dynamic signal.

16. The method of claim 15, wherein, The dynamic signal is provided in response to the measurement function of the MOS logic circuit in operation.

17. The method of claim 13, wherein, The remedial element is a clock buffer.

18. The method of claim 17, wherein, The clock buffer is operable to amplify the rising edge of the clock signal.

19. The method of claim 17, wherein, The clock buffer is capable of operating to amplify the falling edge of the clock signal.

20. The method of claim 16, wherein, The remedial element is a clock buffer, and the dynamic signal is provided by a clock management system, which includes at least one of a phase-locked loop and a delay-locked loop.

21. The method of claim 14, wherein, The remedial element is a decoupling capacitor.

22. The method as described in 14, wherein, The remedial element is a buffer used to enhance the output signal.

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