Self-aligned lithographic-etch-lithographic-etch mandrel cutting process for advanced finfet interconnects

Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor structure having a dielectric stack and a mandrel layer on the dielectric stack. An array of sacrificial mandrel features is patterned into the mandrel layer and on top of the insulating layer of the dielectric stack. A self-aligning non-mandrel cut is formed adjacent one of the sacrificial mandrel features. The sacrificial mandrel feature is removed. One or more self-aligning mandrel cuts are formed in one or more of the plurality of grooves. A non-mandrel opening is formed on top of the insulating layer. The continuity line openings are etched into the dielectric stack, where a non-mandrel cut interrupts a first one of the continuity line openings, and a mandrel cut is disposed to interrupt a second one of the continuity line openings. The metal wire is formed in the continuous wire opening except for the locations where the non-mandrel cut-out and the mandrel cut-out are provided.

Description

Technical Field

[0001] This invention relates generally to semiconductor device manufacturing, and more specifically, to a self-aligned photolithography-etch-photolithography-etch (SALE) mandrel cutting process for advanced FINFET interconnects. Background Technology

[0002] In semiconductor device fabrication, self-aligned multiple patterning is used as a practical solution for manufacturing processes. For example, back-end process (BEOL) interconnect structures can be used to connect device structures that have already been fabricated on a substrate during front-end process (FEOL) processing. The self-aligned patterning process used to form BEOL interconnect structures involves a linear mandrel serving as a sacrificial feature to establish the feature pitch. Non-mandrel axes are arranged as linear spaces between sidewall spacers formed adjacent to the mandrel's sidewalls. After the mandrel is drawn to define the mandrel axis, the sidewall spacers are used as an etch mask to etch the mandrel- and non-mandrel-based patterns into an underlying hard mask. The patterns are then transferred from the hard mask to an interlayer dielectric layer to define trenches, in which lines of the BEOL interconnect structure are formed.

[0003] Mandrel cuts may be formed in the mandrel. Non-mandrel cuts may be formed along the non-mandrel axis and may include portions of spacer material for forming sidewall spacers. The mandrel and non-mandrel cuts are included in a pattern that is transferred to and subsequently removed from a hard mask to form trenches in the interlayer dielectric layer. Summary of the Invention

[0004] Typically, embodiments provide processes and devices for forming mandrel cut features after the mandrel drawing process. Non-mandrel cuts can be formed before mandrel drawing. As will be understood, both mandrel and non-mandrel cuts are self-aligned, but because mandrel cuts are performed after spacer deposition, variations in critical dimensions can be controlled (if not eliminated). For example, a spacer clamping process may not be necessary. Instead, self-aligned techniques can be used to pattern the mandrel and non-mandrel cut portions. Therefore, the pitch spacing between continuity lines and cuts becomes (e.g., set) more uniformly spaced.

[0005] According to embodiments of the present invention, a method for manufacturing a semiconductor device is provided. The method includes providing a semiconductor structure having a dielectric stack and a mandrel layer located on the dielectric stack. An array of sacrificial mandrel features is patterned into the mandrel layer and on top of an insulating layer of the dielectric stack. A self-aligned non-mandrel cut is formed adjacent to one of the sacrificial mandrel features. The sacrificial mandrel feature is removed. Removal of the sacrificial mandrel feature creates a plurality of trenches. After removal of the sacrificial mandrel feature, a self-aligned mandrel cut is formed in one of the trenches. A non-mandrel opening is formed on top of the insulating layer. A continuous line opening is etched into the dielectric stack. The non-mandrel cut is configured to interrupt the first of the continuous line openings. The self-aligned mandrel cut is configured to interrupt a second continuous line opening in the continuous line openings. A metal line is formed in the continuous line opening, except where the self-aligned non-mandrel cut and the self-aligned mandrel cut are located.

[0006] In one embodiment, the axial spacer is formed to be self-aligned on the sidewalls that sacrifice axial features. The thickness of the axial spacer is easily controlled and is unaffected by pinching. Therefore, the edges of the spacer arms become more uniform.

[0007] According to another embodiment of the present invention, a semiconductor chip device is provided. The semiconductor device includes a substrate. A dielectric interconnect layer is positioned on top of the substrate. A plurality of metal lines are located in the dielectric interconnect layer. A self-aligned mandrel cut is present in at least one of the metal lines. A self-aligned non-mandrel cut is present in at least one of the metal lines.

[0008] In one embodiment, the spacing between the plurality of metal wires is uniformly distributed. Uniform spacing avoids unintentional bridging between the metal wires and the cuts within them.

[0009] According to another embodiment of the present invention, a semiconductor device interconnect layer is provided. The semiconductor device interconnect layer includes a dielectric substrate. A first metal line extends in a first direction on the dielectric substrate. A second metal line extends in the first direction. The second metal line is parallel to the first metal line. A first dielectric region is located in a first space between the first metal line and the second metal line. A self-aligned mandrel cut exists in the first metal line. A non-mandrel cut exists in the second metal line.

[0010] In one embodiment, the first dielectric region and the second dielectric region are self-aligned relative to the first metal line and the second metal line. This feature avoids pitch-walking that can occur when the spacer thickness is inconsistent and arbitrary between the cut and the metal line.

[0011] According to embodiments of the present invention, a method for manufacturing a semiconductor device is provided. The method includes providing a semiconductor structure having a dielectric stack, an interconnect layer in the dielectric stack, and a mandrel layer located on the dielectric stack. An array of mandrels is patterned into the mandrel layer and on top of an insulating layer of the dielectric stack. A self-aligned non-mandrel cut is formed adjacent to one of the mandrels. The mandrel is removed, resulting in a plurality of parallel trenches. A self-aligned mandrel cut is formed in one of the trenches. A non-mandrel opening is formed on top of the insulating layer. The non-mandrel opening is parallel to the plurality of trenches. A continuity line is formed in the interconnect layer. The continuity line is formed in the plurality of trenches and the non-mandrel opening. A first continuity line includes the non-mandrel cut. A second continuity line includes the mandrel cut.

[0012] In one embodiment, mandrel cuts and non-mandrel cuts are staggered. This staggered cutting pattern with consistent critical dimensions becomes possible when cuts are formed before and after mandrel drawing. Attempts to use pinch-off methods to stagger cuts typically result in variations in the critical dimensions of the cuts, as future manufacturing scales are performed in the seven-nanometer or smaller range.

[0013] The techniques described herein can be implemented in a variety of ways. Example implementations are provided below with reference to the accompanying drawings. Attached Figure Description

[0014] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Other embodiments may be used additionally or alternatively. Details that may be obvious or unnecessary may be omitted to save space or for more efficient illustration. Some embodiments may be practiced using additional components or steps and / or not using all the components or steps shown. When the same number appears in different drawings, it refers to the same or similar parts or steps.

[0015] Figure 1A This is a cross-sectional schematic diagram of the initial film deposition formation for a semiconductor device, consistent with an embodiment of the present invention.

[0016] Figure 1B yes Figure 1A The top view of the formation.

[0017] Figure 2A This is a cross-sectional schematic diagram of a mandrel forming photolithography process consistent with an embodiment of the present invention.

[0018] Figure 2B yes Figure 2A The top view of the formation.

[0019] Figure 3A This is a cross-sectional schematic diagram of a mandrel etching process consistent with an embodiment of the present invention.

[0020] Figure 3B yes Figure 3A The top view of the formation.

[0021] Figure 4A This is a cross-sectional schematic diagram of a spacer film deposition process consistent with an embodiment of the present invention.

[0022] Figure 4B yes Figure 4A The top view of the formation.

[0023] Figure 5A This is a cross-sectional schematic diagram of a spacer body etch-back process consistent with an embodiment of the present invention.

[0024] Figure 5B yes Figure 5A The top view of the formation.

[0025] Figure 6A This is consistent with the embodiments of the present invention, using a photolithography etch-back process for masking. Figure 5A A schematic diagram of the cross-section formed for NMN cutting.

[0026] Figure 6B yes Figure 6A The top view of the formation.

[0027] Figure 7A This is a cross-sectional schematic diagram of a filling process for NMN cutting, consistent with an embodiment of the present invention.

[0028] Figure 7B yes Figure 7A The top view of the formation.

[0029] Figure 8A This is consistent with the embodiments of the present invention after the application of a chemical vapor deposition process. Figure 7A A schematic diagram of the cross-section formed in the middle.

[0030] Figure 8B yes Figure 7A The top view of the formation.

[0031] Figure 9A This is consistent with the embodiments of the present invention after the application of the mandrel drawing process. Figure 8A A schematic diagram of the cross-section formed in the middle.

[0032] Figure 9B yes Figure 9A The top view of the formation.

[0033] Figure 10A This is consistent with the embodiments of the present invention, using a photolithography etch-back process for masking. Figure 9A A schematic diagram of the cross-section formed for mandrel cutting.

[0034] Figure 10B yes Figure 10A The top view of the formation.

[0035] Figure 11A The filling is consistent with the embodiments of the present invention. Figure 10A A schematic diagram of the cross-section of the mandrel cut.

[0036] Figure 11B yes Figure 11A The top view of the formation.

[0037] Figure 12A It is a mask consistent with the embodiments of the present invention. Figure 11A A schematic diagram of the cross-section formed in the middle.

[0038] Figure 12B yes Figure 12A The top view of the formation.

[0039] Figure 13A This illustrates removal consistent with embodiments of the present invention. Figure 12A A schematic diagram of the cross-section of the mask on the formation.

[0040] Figure 13B yes Figure 13A The top view of the formation.

[0041] Figure 14A This illustrates a process following a reactive ion etching process, consistent with embodiments of the present invention. Figure 13A A schematic diagram of the cross-section formed in the middle.

[0042] Figure 14B yes Figure 14A The top view of the formation.

[0043] Figure 15A This illustrates the process following the interlayer dielectric etching process, consistent with embodiments of the present invention. Figure 14A A schematic diagram of the cross-section formed in the middle.

[0044] Figure 15B yes Figure 15A The top view of the formation.

[0045] Figure 16A This illustrates the process after the mask removal process, consistent with embodiments of the present invention. Figure 15A A schematic diagram of the cross-section formed in the middle.

[0046] Figure 16B yes Figure 16A The top view of the formation.

[0047] Figure 17A This illustrates the process following the electroplating process, consistent with embodiments of the present invention. Figure 16AA schematic diagram of the cross-section formed in the middle.

[0048] Figure 17B yes Figure 17A The top view of the formation. Detailed Implementation

[0049] Overview

[0050] In traditional multi-patterning processes, controlling the mandrel size at different feature locations can be challenging. As manufacturing technologies advance to the 7-nanometer scale, the ability to uniformly control mandrel and non-mandrel features on a wafer becomes highly dependent on controlling the critical dimensions of the mandrel cutouts and providing uniform spacing. Spacer volume features are typically used to define the space between mandrel and non-mandrel lines.

[0051] If the critical size of the mandrel cut is too large, the cut cannot be completely clamped by the spacer. This can result in non-mandrel bridging between features. However, arbitrarily adjusting the spacer thickness is not a reliable solution to prevent variations in the critical size spacing between features (also known as "spacing variation"). If the critical size used for mandrel cutting is too small, the critical size for cutting cannot be patterned. Missing mandrel patterns can also cause mandrel bridging problems. As the scale for patterning decreases, the critical size of the mandrel cut and the spacer thickness can easily vary at each structure patterned across the die throughout the wafer. Variations in the inherent critical size of the notch (hole) can pose further challenges in forming uniformly patterned features.

[0052] Typically, this subject matter disclosure describes a process for providing semiconductor devices that includes forming pillar-based mandrel cuts as non-mandrel features before and after performing mandrel drawing. This process avoids the need for clamping of spacer material between mandrels during conventionally performed mandrel cutting steps. As a result, the mandrel cut and non-mandrel cuts can be self-aligned, providing better consistency in spacing between the cuts and interconnects. Additionally, defects such as scoring of the spacer material that occur during clamping are avoided. Unintended bridging of adjacent structures due to spacer material scoring is also avoided.

[0053] For the sake of brevity, conventional techniques associated with the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process with additional steps or functions not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well-known; therefore, for the sake of brevity, this document will only briefly mention many conventional steps, or omit them entirely, without providing well-known process details.

[0054] In the following detailed description, numerous specific details are illustrated with examples to provide a thorough understanding of the relevant teachings. However, it should be apparent, however, that these teachings can be practiced without these details. In other instances, well-known methods, processes, components, and / or circuits have been described at a relatively high level without detailed description to avoid unnecessarily obscuring aspects of these teachings.

[0055] In one aspect, spatially relative terms such as “front,” “back,” “top,” “bottom,” “below,” “under,” “lower,” “above,” “upper,” “side,” “left,” “right,” etc., are used with reference to the orientation of the described figures. Since components of embodiments of the invention can be positioned in multiple different orientations, these directional terms are used for illustrative purposes and are by no means limiting. Therefore, it will be understood that, in addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will be oriented “above” other elements or features. Thus, for example, the term “below” can cover both above and below orientations. Similarly, an element described as “above” another element can mean that the element is positioned above the element below and is not necessarily in direct contact with the element below. Devices can be oriented in other ways (rotated 90 degrees or viewed or referenced in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0056] As used herein, the terms “lateral,” “planar,” and “horizontal” describe an orientation parallel to a first surface of a chip or substrate. In the disclosure herein, a “first surface” can be the top layer of a semiconductor device, where individual circuit devices are patterned in a semiconductor material.

[0057] As used herein, the term "vertical" describes an orientation that is perpendicular to the first surface arrangement of the chip, chip carrier, chip substrate, or semiconductor body.

[0058] As used herein, the terms “connected” and / or “electrically connected” do not imply that components must be directly coupled together—intermediate components may be provided between “connected” or “electrically connected” components. Conversely, if a component is described as “directly connected” or “directly coupled” to another component, no intermediate component is present. The term “electrically connected” refers to a low-ohm electrical connection between components that are electrically connected together. The phrase “electrically connected” does not necessarily imply that components must be in direct physical contact with each other—intermediate components may be provided between “connected” or “electrically connected” components.

[0059] While the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Describing an element as “first” or “second,” etc., does not necessarily imply any order or priority of elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0060] Example embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of idealized or simplified embodiments (and intermediate structures). Therefore, variations in the shape of the diagrams as a result of, for example, manufacturing techniques and / or tolerances can be expected. Consequently, the areas shown in the figures are schematic in nature, and their shapes do not necessarily represent the actual shape of the areas of the device and are not limiting. It should be understood that the figures and / or accompanying drawings are exemplary, non-limiting, and not necessarily drawn to scale.

[0061] It should be understood that other embodiments may be used, and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not restrictive. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0062] definition

[0063] Mandrel: A linear or ridge-like protrusion formed on a substrate. In this subject matter disclosure, a mandrel defines one of the lines on which interconnects are formed in the underlying layer.

[0064] Interconnector: A structure that electrically connects two or more circuit elements (such as transistors) together.

[0065] Self-alignment: Patterning of a structure relative to another structure.

[0066] Continuous line: a metal or other conductive trace or interconnect.

[0067] Discontinuity: A break or interruption in a continuous line.

[0068] Sacrificial: The structure formed as a placeholder feature that will be removed to define a new or different feature.

[0069] Substrate: The reference to substrate can refer to the material that provides a supporting structure for features in or on top of the substrate material. As used below, more than one substrate may be present in the embodiments shown. Furthermore, since the embodiments below are generally shown in cross-section, it should be understood that the substrate of a layer with patterned features may not be visible in the view in order to highlight the features of that layer.

[0070] Example manufacturing method

[0071] The process described below is a general method for forming semiconductor devices, which uses a pillar-based mandrel cut as a non-mandrel before / after a mandrel drawing process. The fabrication of the devices described below may include a multi-step sequence of steps, such as photolithography and / or chemical processing steps, which facilitates the gradual generation of electronic-based systems, devices, components, and / or circuits in semiconductor and / or superconducting devices (e.g., integrated circuits). For example, device 100 can be fabricated on one or more substrates (e.g., silicon (Si) substrates and / or another substrate) using techniques including but not limited to: photolithography, microlithography, nanolithography, photomask technology, patterning technology, photoresist technology (e.g., positive tint photoresist, negative tint photoresist, mixed tint photoresist and / or another photoresist technology), etching technology (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation and / or another etching technology), evaporation technology, sputtering technology, plasma ashing technology, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation and / or another heat treatment), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), back-side polishing technology and / or another technology for fabricating integrated circuits.

[0072] Figure 1A This is a schematic cross-sectional view of a semiconductor device 100 at an intermediate stage of manufacturing. A substrate 105 and a stack of dielectric layers formed on top of the substrate 105 are present. The stack of dielectric layers includes a first insulating layer 115, a spacer layer 120, and a second insulating layer 125. In some embodiments, an interconnect layer 110 may be formed on the base semiconductor substrate 105 prior to the formation of the first insulating layer 115. The interconnect layer 110 may be made of a silicon carbide (SiCNO) film or other similar dielectric. At the intermediate stage of manufacturing shown, the interconnect layer 110 does not yet include any interconnect structures. As a result of the subject processes disclosed herein, interconnect structures such as continuity lines will be formed.

[0073] In one embodiment, the base semiconductor substrate 105 may be a bulk semiconductor substrate formed of, for example, silicon or other types of semiconductor substrate materials commonly used in bulk semiconductor manufacturing, such as single-crystal Si, silicon-germanium (SiGe), III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulator (SOI). III-V compound semiconductors include, for example, materials having at least one group III element and at least one group V element, such as aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlGaAs), aluminum nitride (AlN), gallium antimonide (GaSb), gallium aluminum antimonide (GaAlSb), gallium arsenide (GaAs), gallium arsenide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and one or more alloy combinations including at least one of the aforementioned materials. The alloy combination may include binary (two elements, such as gallium arsenide (III) (GaAs)), ternary (three elements, such as InGaAs), and quaternary (four elements, such as aluminum gallium indium phosphide (AlInGaP)) alloys. The dielectric layer 130 used to form the core axis may be deposited on top of the second insulating layer 125.

[0074] Figure 2A and Figure 2B The formation of an etch mask is shown to pattern the second insulating layer 125. An organic planarization layer (OPL) or oxide diffusion layer (ODL) 135 may be deposited on top of the dielectric layer 130. A mask row 140 may be formed on top of layer 135. Figure 3A and Figure 3B The result of an etching process is shown, which removes masking row 140 and layer 135 and etches into dielectric layer 130, leaving sacrificial mandrel feature 132. The etching can be stopped at the second insulating layer 125.

[0075] Figure 4A and Figure 4B Conformal deposition of spacer material 138 around sacrificial core feature 132 is shown. Spacer material 138 may be the same material as spacer layer 120, and therefore, the same crosshair pattern is used for both films. Figure 5A and Figure 5BThe result of etching back the spacer material 138 from the top edge of the sacrificial mandrel feature 132 and from the top of the second insulating layer 125 and the space between the sacrificial mandrel feature 132 is shown. The resulting formation provides a mandrel spacer 142 self-aligned with the sidewalls of each sacrificial mandrel feature 132. In some embodiments, the thickness of the mandrel spacer 142 on the sidewalls of the sacrificial mandrel feature 132 is uniformly formed. As can be understood, the thickness of the mandrel spacer 142 can be controlled to provide a uniform and consistent spacing between mandrel cut lines and non-mandrel cut lines to be formed in the spacer layer 120.

[0076] Figure 6A and 6B The process of forming the non-mandrel dicing is illustrated. A temporary insulating layer 145 and an etching mask 150 may enclose the top of the sacrificial mandrel feature 132 (shown as designated by "L", "C", and "R" to indicate the left, center, and right positions of the respective mandrel features), the spacer sidewall 142, and the top of the exposed portion of the second insulating layer 125. A trench 152 may remain open between the central sacrificial mandrel feature 132C and the left sacrificial mandrel feature 132L. The right sacrificial mandrel feature 132R may be completely enclosed. The exposed trench 152 will be used to form a placeholder for the self-aligned non-mandrel dicing. As can be understood, the thickness of the non-mandrel dicing is controlled at this fabrication level by defining the width of the trench 152 and the amount of etching previously performed on the spacer material 138 on the sides of the sacrificial mandrel feature 132.

[0077] Figure 7A and Figure 7B The removal of a temporary insulating layer 145 and an etch mask 150 from the top of the sacrificial mandrel feature 132 and the mandrel spacer 142 is shown. The opening trench 152 can be filled with, for example, an electron beam deposited placeholder material 155 (e.g., a gap-filling material such as SOG, SiOC, or ALD TiOX). Figure 8A and 8B The result is shown by removing the temporary insulating layer 145 and depositing a flowable silicon dioxide layer 160 into the area vacated by the temporary insulating layer 145. A planarization process can be applied to all materials on top of the second insulating layer 125.

[0078] Figure 9A and Figure 9B The result of pulling the sacrificial mandrel feature 132 leaving an empty groove 156 is shown. Figure 10A and 10B A process for forming a self-aligned mandrel cutting line with the adjacent mandrel spacer 142 is shown. This process includes masking the area except for the central groove 156 left by mandrel drawing. An insulating layer 145 and an etch mask 150 (as previously described) can be used. Figure 6A and6B (As shown in the illustration) Repeated masking. The exposed central groove 156 defines a mandrel cut line that is self-aligned relative to the adjacent sidewall of the mandrel spacer 142. In some embodiments, the mandrel cut line may be self-aligned to a sidewall that is not a mandrel cut line. Figure 11A and 11B The diagram shows the central groove 156 of the mandrel cut line filled with placeholder material 165. It can be understood that the critical dimensions of the final mandrel axis are consistently defined by the width of the groove and the controlled thickness of the adjacent mandrel spacers 142. The temporary insulating layer 145 and the etching mask 150 can be removed. (As shown in...) Figure 11B As can be seen more clearly, the critical dimensions of the spindle cutting line and the non-spindle cutting line are controlled relative to the surrounding spindle spacer 142.

[0079] Figure 12A and Figure 12B The process for forming the non-mandrel opening is illustrated. This process includes masking the area except for trench 162 (e.g., using a temporary insulating layer 145), which is formed after selective etching and removal of the flowable silicon dioxide line 160. The placeholder material 155 used for the non-mandrel cutting is resistant to the etching chemicals used, thus remaining protected even upon exposure, as... Figure 12B As shown. The etching process forms a non-mandrel opening down to the second insulating layer 125.

[0080] Figure 13A and Figure 13B The process for forming the additional non-mandrel opening line down to the second insulating layer 125 is shown. Figure 14a and Figure 14B The process of etching downwards for placeholder material 155 for non-mandrel dicing lines, placeholder material 165 for mandrel dicing lines, mandrel spacer 142, and any remaining flowable silicon dioxide 160 is shown. The etching can be formed into and through both the second insulating layer 125 and the spacer layer 120, thereby exposing the first insulating layer 115 along the formed lines.

[0081] Figure 15A and 15B The process of dielectric etching that removes the second insulating layer 125 and forms an opening downward through both the first insulating layer 115 and the substrate 105 is shown. The opening will define a continuity line in the interconnect layer 120. Figure 16A and 16B Further downward etching is shown to remove the first insulating layer 115.

[0082] Figure 17A and 17BMetallization applied to an opening to form a metal line 175 is illustrated. In the illustrated example, first, second, third, fourth, and fifth metal lines 175 are shown. Other embodiments may include more or fewer metal lines 175. Metal lines 175 represent, for example, continuous lines in an interconnect layer 110 (or another layer) within a semiconductor device. The first, second, third, fourth, and fifth metal lines 175 may extend in the same direction. The first, second, third, fourth, and fifth metal lines 175 may be formed parallel to each other. The spacing between the metal lines 175 may be uniformly distributed. The first metal line 175 includes a mandrel cut 185. The second metal line 175 includes a non-mandrel cut 170. The third, fourth, and fifth metal lines 175 may be the result of a previously formed non-mandrel opening and do not include cuts. It should be understood that other embodiments may include cuts on any metal line 175. In some embodiments, metal lines 175 shown as having cuts 170 and 180 may not necessarily have cuts. In yet other embodiments, metal lines 175 may include more than one cut. The resulting non-mandrel cut 170 can be self-aligned relative to the adjacent sidewalls of interconnect layer 110. The resulting mandrel cut 180 can be self-aligned relative to the adjacent sidewalls of interconnect layer 110.

[0083] The dielectric material regions between adjacent metal lines 175 can be uniformly distributed, resulting in a consistent spacing. This can be the result of patterning some non-mandrel axes, such that the final result provides a first dielectric region and a second dielectric region that are self-aligned relative to the first and second metal lines 175. In some embodiments, the width of the first dielectric region is equal to the width of the second dielectric region. In some embodiments, the previously described etching process can provide openings such that the metal lines 175 are arranged in a staggered array. For example, the ends of the first metal lines 175 can be staggered with the ends of the second metal lines 175. It can be seen that the non-mandrel cuts 170 and mandrel cuts 185 cut the metal lines 175 without clamping any adjacent lines or encroaching on the spacing between the metal lines 175. As shown, some embodiments may position the mandrel cuts 185 to stagger with the non-mandrel cuts 170.

[0084] in conclusion

[0085] Various embodiments of the present teachings have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to techniques found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0086] While the content and / or other examples considered to be in their best state have been described above, it should be understood that various modifications may be made therein, and the subject matter disclosed herein can be implemented in various forms and examples, and the teachings can be applied to many applications, of which only a few have been described herein. The appended claims are intended to claim protection for any and all applications, modifications, and variations that fall within the true scope of this teaching.

[0087] The components, steps, features, objects, benefits, and advantages discussed herein are merely illustrative. None of them, and the discussions relating to them, are intended to limit the scope of protection. While various advantages have been discussed herein, it should be understood that not all embodiments are necessarily intended to include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, sizes, dimensions, and other specifications set forth in this specification (including in the appended claims) are approximate, not precise. They are intended to have a reasonable range consistent with the functions they pertain to and with the conventions in the art to which they belong.

[0088] Many other embodiments are also envisioned. These embodiments include those with fewer, additional, and / or different components, steps, features, objects, benefits, and advantages. They also include embodiments in which components and / or steps are arranged and / or ordered differently.

[0089] While the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" means only as an example, and not the best or optimal. Nothing else stated or shown above is intended or should not be construed as causing any component, step, feature, object, benefit, advantage, or equivalent to be offered to the public, whether or not it is recited in the claims.

[0090] It should be understood that the terms and expressions used herein have the general meaning consistent with those in the corresponding fields of investigation and research, unless otherwise specified herein. Relational terms such as "first" and "second" may be used merely to distinguish one entity or action from another, without necessarily requiring or implying any actual such relationship or order between these entities or actions. The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further constraints, an element beginning with "a" or "an" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0091] An abstract of this disclosure is provided to allow the reader to quickly determine the nature of this technical disclosure. It is submitted on the understanding that the abstract will not be used to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen in the foregoing detailed description, various features have been grouped together in various embodiments for the purpose of simplifying this disclosure. The approach of this disclosure should not be construed as reflecting an intention to have more features than expressly recited in each claim of the claimed embodiments. Rather, as reflected in the following claims, the inventive subject matter lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

[0092] In a preferred embodiment of the invention described herein, a semiconductor device interconnect layer is provided, comprising: a dielectric substrate; a first metal line extending in a first direction of the dielectric substrate; a second metal line extending in the first direction, wherein the second metal line is parallel to the first metal line; a first dielectric region in a first space between the first and second metal lines; a self-aligned mandrel cut in the first metal line; and a non-mandrel cut in the second metal line. The non-mandrel cut may be self-aligned relative to adjacent sidewalls of the dielectric substrate. The device may further include: a third metal line extending in the first direction, wherein the third metal line is parallel to the first and second metal lines; and a second dielectric region in a second space between the first or second metal line. The first and second dielectric regions may be self-aligned relative to the first and second metal lines. The width of the first dielectric region may be equal to the width of the second dielectric region.

[0093] In a preferred embodiment of the invention described herein, a method of manufacturing a semiconductor device is provided, comprising: providing a semiconductor structure having a dielectric stack, an interconnect layer in the dielectric stack, and a mandrel layer located on the dielectric stack; patterning an array of mandrels into the mandrel layer and on top of an insulating layer of the dielectric stack; forming a self-aligned non-mandrel cut adjacent to one of the mandrels; removing the mandrel, wherein the removal of the mandrel creates a plurality of parallel trenches; forming the self-aligned mandrel cut in one of the plurality of parallel trenches; forming a non-mandrel opening on top of the insulating layer, wherein the non-mandrel opening is parallel to the plurality of parallel trenches; forming a continuity line in the interconnect layer, wherein: the continuity line is formed in the plurality of parallel trenches and the non-mandrel opening; a first continuity line of the continuity line includes the self-aligned non-mandrel cut; and a second continuity line of the continuity line includes the mandrel cut. The method may further include forming mandrel spacers on the sidewalls of the mandrel. The mandrel spacers on the sidewalls may be configured to uniformly space the continuity lines. The ends of the first continuity line may intersect with the ends of the second continuity line.

Claims

1. A method for manufacturing a semiconductor device, comprising: A semiconductor structure is provided, the semiconductor structure having a dielectric stack and a mandrel layer located on the dielectric stack; An array of sacrificial mandrel features is patterned into the mandrel layer and on top of the insulating layer of the dielectric stack; Form a self-aligned non-axial incision adjacent to one of the sacrificial axial features; Remove the sacrificial mandrel feature, wherein the removal of the sacrificial mandrel feature creates multiple grooves; After removing the sacrificial mandrel feature, one or more self-aligned mandrel cuts are formed in one or more of the plurality of grooves; A non-mandrel opening is formed on the top of the insulating layer; A continuity line opening is etched into the dielectric stack, wherein the self-aligned non-mandrel cut is configured to interrupt the first of the continuity line openings, and the one or more self-aligned mandrel cuts are configured to interrupt the second of the continuity line openings. and A metal wire is formed in the opening of the continuous line, except for the location of the self-aligned non-mandrel cut and the one or more self-aligned mandrel cuts.

2. The method of claim 1, further comprising forming a spindle spacer that is self-aligned on the sidewall of the sacrificial spindle feature.

3. The method of claim 2, further comprising removing the mandrel spacer before etching the continuity line opening.

4. The method of claim 2, wherein the thickness of the axial spacer on the sidewall of the sacrificial axial feature is uniformly formed.

5. The method of claim 1, further comprising filling the self-aligned non-mandrel cut with a first placeholder material.

6. The method of claim 5, further comprising filling the one or more self-aligning mandrel cuts with a second placeholder material.

7. The method of claim 6, further comprising removing the first placeholder material and the second placeholder material.

8. The method of claim 1, further comprising filling one or more of the plurality of trenches with flowable silica.

9. The method of claim 8, further comprising removing the flowable silica to form one or more of the continuous line openings.

10. A semiconductor device, comprising: Substrate; A dielectric interconnect layer is located on top of the substrate; Multiple metal lines are located in the dielectric interconnect layer; A self-aligning mandrel cut in at least one of the metal wires; and A self-aligned non-mandrel cut in at least one of the metal wires.

11. The semiconductor device of claim 10, wherein the first metal line of the plurality of metal lines is disposed parallel to the second metal line of the plurality of metal lines.

12. The semiconductor device of claim 10, wherein the spacing between the plurality of metal lines is uniformly distributed.

13. The semiconductor device of claim 10, wherein the plurality of metal lines are arranged in an alternating array.

14. The semiconductor device of claim 10, wherein the self-aligned mandrel cut is positioned to intersect with the self-aligned non-mandrel cut.

15. The semiconductor device of claim 10, wherein the self-aligned mandrel cut is positioned to be self-aligned relative to the adjacent sidewall of the dielectric interconnect layer.

16. The semiconductor device of claim 10, wherein the dielectric interconnect layer comprises a silicon carbide (SiCNO) film.

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