Storage device, image sensor, and electronic device
By using SRAM to store high-order bits of data and combining it with MRAM or FeRAM to store low-order bits of data in storage devices, the problems of increased storage device size and high data error rate are solved, achieving efficient utilization and improved reliability of storage devices.
Patent Information
- Application Number
- CN202480020617.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-03-30
- Filing Date
- 2024-03-11
- Publication Date
- 2025-11-11
AI Technical Summary
SRAM cells have a large area, which increases the size of storage devices, and its high reliability storage suffers from a high data error rate.
By using SRAM and smaller-cell memory (such as MRAM or FeRAM) to store high-order and low-order bits of data separately, and optionally combining error detection and correction units, the error rate and chip size increase can be reduced.
By separating the storage of high-order and low-order bits, the increase in chip size of the storage device is reduced, while the data error rate is lowered.
Smart Images
Figure CN120937388A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to storage devices, image sensors, and electronic devices. Background Technology
[0002] Electronic devices including storage devices have been proposed that use semiconductor memory such as static random access memory (SRAM) (see, for example, Patent Document 1). Prior art electronic devices (imaging devices) use memory that stores information about defective pixels of the imaging element.
[0003] Reference List
[0004] Patent documents
[0005] Patent Document 1: JP 2013-093685 A Summary of the Invention
[0006] Technical issues
[0007] SRAM is characterized by a low error rate in storing data and is used in storage devices that require high reliability. However, because SRAM has a larger cell area than DRAM and other memory types, it leads to an increase in the size of the storage device.
[0008] Therefore, this disclosure proposes a storage device with reduced size, an image sensor using the storage device, and an electronic device.
[0009] Solution to the problem
[0010] The storage device according to this disclosure includes a first memory and a second memory. The first memory includes SRAM and stores the high-order bits of image data. The second memory includes a memory with a smaller cell area than the SRAM and stores the low-order bits of image data. Attached Figure Description
[0011] Figure 1 This is a diagram illustrating a configuration example of a storage device according to a first embodiment of the present disclosure.
[0012] Figure 2 This is a diagram illustrating another configuration example of a storage device according to a first embodiment of the present disclosure.
[0013] Figure 3 This is a diagram illustrating a configuration example of a storage device according to a second embodiment of the present disclosure.
[0014] Figure 4 This is a diagram illustrating another configuration example of a storage device according to a second embodiment of the present disclosure.
[0015] Figure 5 This is a diagram illustrating a configuration example of an electronic device to which the technology according to embodiments of the present disclosure can be applied.
[0016] Figure 6 This is a diagram illustrating an example configuration of an image sensor to which the techniques according to embodiments of this disclosure can be applied.
[0017] Figure 7 This is a diagram illustrating an example of image data generation in an image sensor to which the techniques according to embodiments of the present disclosure can be applied. Detailed Implementation
[0018] In the following, embodiments of the present disclosure will be described in detail based on the accompanying drawings. The description will be given in the following order. Note that in the various embodiments below, the same reference numerals will be used to refer to the same parts and repeated descriptions will be omitted.
[0019] 1. First Implementation Method
[0020] 2. Second Implementation Method
[0021] 3. Application of electronic devices
[0022] (1. First Implementation Method)
[0023] [Storage device configuration]
[0024] Figure 1 This is a diagram illustrating a configuration example of a storage device according to a first embodiment of the present disclosure. The diagram is a block diagram showing a configuration example of the storage device 100. It is assumed that the storage device 100 is a frame memory that stores image data. Furthermore, it is assumed that the image data is data with a 12-bit width. Here, bit
[11] corresponds to the most significant bit (MSB), and bit [0] corresponds to the least significant bit (LSB). The storage device 100 includes an SRAM 200, an MRAM 300, a temperature sensor 130, and a control circuit 110.
[0025] SRAM 200 is a memory that includes SRAM and stores the high-order bits of image data. Figure 1 The SRAM 200 shown illustrates an example of storing the high-order three bits of image data. SRAM 200 includes a memory cell array 210, word line driver units (in... Figure 1 The description includes WD)230, address decoding unit 240, and data I / O buffer (in... Figure 1 It is described as I / O 250. Note that SRAM 200 is an example of the "first memory" of this disclosure.
[0026] The memory cell array 210 is configured by arranging memory cells, which serve as unit elements for storing data, into a two-dimensional matrix. Word lines and bit lines are routed to the memory cells of the memory cell array 210.
[0027] Address decoding unit 240 selects word lines of memory cell array 210 based on address signals from control circuit 110.
[0028] Word line driving unit 230 drives word lines selected by address decoding unit 240. Word line driving unit 230 includes multiple driving units 231 that drive word lines. Among the multiple driving units 231, the driving unit 231 connected to the word line selected by address decoding unit 240 outputs a driving voltage.
[0029] Data I / O buffer 250 is a bidirectional buffer that exchanges data with bit lines. Figure 1 In the data I / O buffer 250, bits
[11] to [0] represent data bits. As described above, SRAM 200 stores the high three bits of 12-bit image data. In other words, SRAM 200 stores data bits
[11] to [9]. The data I / O buffer 250 is connected to bus 120.
[0030] MRAM 300 is a memory that includes magnetoresistive RAM (MRAM), which is a magnetoresistive memory and stores the low-order bits of image data. Figure 1 The MRAM 300 shown illustrates an example of storing the lower nine bits of image data. The MRAM 300 includes a memory cell array 310, a word line driver unit 330, an address decoding unit 340, and a data I / O buffer 350. Note that the MRAM 300 is an example of a "secondary memory" as described in this disclosure.
[0031] Similar to storage cell array 210, storage cell array 310 is configured by arranging storage cells, which are the unit elements for storing data, into a two-dimensional matrix.
[0032] Similar to address decoding unit 240, address decoding unit 340 selects word lines of memory cell array 310 based on address signals from control circuit 110.
[0033] Similar to word line driver unit 230, word line driver unit 330 drives word lines selected by address decoding unit 340. Word line driver unit 330 includes multiple driver units 331 that drive word lines. Among the multiple driver units 331, the driver unit 331 connected to the word line selected by address decoding unit 340 outputs a drive voltage. Note that the driver unit 331 adjusts the drive voltage based on a signal from temperature sensor 130.
[0034] Similar to data I / O buffer 250, data I / O buffer 350 is a bidirectional buffer that exchanges data with bit lines. As described above, MRAM 300 stores the lower nine bits of 12-bit image data. In other words, MRAM 300 stores data from bits [8] to [0]. Data I / O buffer 350 is connected to bus 120.
[0035] Control circuit 110 controls the entire storage device 100. Control circuit 110 outputs address signals to the address decoding unit 240 of SRAM 200 and the address decoding unit 340 of MRAM 300. Additionally, control circuit 110 inputs and outputs image data between the data I / O buffer 250 of SRAM 200 and the data I / O buffer 350 of MRAM 300 via bus 120. At this time, control circuit 110 performs control to allocate the high-order three bits of the image data to SRAM 200 and to allocate the low-order nine bits of the image data to MRAM 300.
[0036] Temperature sensor 130 measures temperature and outputs a signal corresponding to the measurement result to drive unit 331 of MRAM 300.
[0037] SRAM has a larger cell area than MRAM. Specifically, the cell area ratio of SRAM to MRAM is 9 to 3. Therefore, when the storage device 100 is configured to store all 12 bits of image data in SRAM, the chip size increases. However, both SRAM and MRAM can be arranged in the storage device 100 and the image data can be allocated, thereby reducing the increase in chip size. For example, suppose the storage device 100 has the following configuration: data corresponding to two bits of the image data is allocated to SRAM, and data corresponding to the remaining 10 bits is allocated to MRAM. In this case, the chip size of the storage device 100 can be reduced to half compared to storing all the image data in SRAM.
[0038] Meanwhile, MRAM has a higher error rate for storing data than SRAM. Therefore, by allocating the high-reliability high-bit image data to SRAM and the low-bit image data to MRAM, the impact of the error rate can be reduced.
[0039] Considering the cell area and the aforementioned error rate, a configuration can be adopted in which at least the most significant two bits of the image data are stored in SRAM 200 and the remaining 10 bits of the image data are stored in MRAM 300. As a result, the increase in the chip size of the storage device 100 can be reduced, while simultaneously mitigating the impact of the image data error rate. Figure 1An example of storing the high three bits of data in SRAM 200 is described.
[0040] [Another configuration for the storage device]
[0041] Figure 2 This is a diagram illustrating another configuration example of a storage device according to a first embodiment of the present disclosure. The diagram illustrates a configuration similar to... Figure 1 A block diagram of a configuration instance of storage device 100. The storage device 100 in this diagram is... Figure 1 The difference in the storage device 100 in the figure is that the storage device 100 in this figure includes FeRAM 400 instead of MRAM 300.
[0042] FeRAM 400 is a memory that includes ferroelectric RAM (FeRAM) as a ferroelectric memory and stores the low-order bits of image data. Figure 2 The FeRAM 400 shown herein illustrates an example of storing the lower nine bits of image data. The FeRAM 400 includes a memory cell array 410, a word line driver unit 430, an address decoding unit 440, and a data I / O buffer 450. Note that the FeRAM 400 is an example of a "secondary memory" according to this disclosure.
[0043] Similar to storage cell array 310, storage cell array 410 is configured by arranging storage cells, which are the unit elements for storing data, into a two-dimensional matrix.
[0044] Similar to address decoding unit 340, address decoding unit 440 selects word lines of memory cell array 410 based on address signals from control circuit 110.
[0045] Similar to word line driver unit 330, word line driver unit 430 drives word lines selected by address decoding unit 440. Word line driver unit 430 includes multiple driver units 431 that drive word lines. Driver units 431 adjust the drive voltage based on signals from temperature sensor 130.
[0046] Similar to data I / O buffer 350, data I / O buffer 450 is a bidirectional buffer that exchanges data with bit lines. As described above, FeRAM 400 stores the lower nine bits of 12-bit image data. In other words, FeRAM 400 stores data from bits [8] to [0]. Data I / O buffer 450 is connected to bus 120.
[0047] As described above, the storage device 100 according to the first embodiment of this disclosure uses SRAM 200 to store the high-order bits of image data and MRAM 300 or FeRAM 400 to store the low-order bits of image data. As a result, the increase in the size of the storage device 100 can be reduced, while the impact of the error rate of the image data can be reduced.
[0048] (2. Second Implementation)
[0049] The storage device 100 of the first embodiment described above allocates image data to SRAM 200 and MRAM 300, and causes SRAM 200 and MRAM 300 to store the image data. Meanwhile, the storage device 100 according to the second embodiment of this disclosure differs from the first embodiment in that, in SRAM 200 and MRAM 300, data for error correction processing is further stored along with the image data.
[0050] [Storage device configuration]
[0051] Figure 3 This is a diagram illustrating a configuration example of a storage device according to a second embodiment of the present disclosure. The diagram illustrates a configuration similar to... Figure 1 A block diagram of a configuration instance of storage device 100. The storage device 100 in this diagram is... Figure 1 The difference between the storage device 100 in the figure and the storage device 100 in the figure is that the storage device 100 performs error detection and correction processing of image data.
[0052] Figure 3 The control circuit 110 includes an error detection and correction unit 111. The error detection and correction unit 111 performs error detection and correction code (ECC) conversion and decoding of the image data. The error detection and correction unit 111 generates redundant data, which is obtained by performing error detection and correction code conversion on the image data. The control circuit 110 outputs the redundant data along with the image data to SRAM 200 and MRAM 300.
[0053] Figure 3 The SRAM 200's memory cell array 210 includes redundant areas for storing redundant data. Additionally, Figure 3 The SRAM 200 also includes a data I / O buffer 259. The data I / O buffer 259 provides redundant input and output data.
[0054] Figure 3 The MRAM 300's memory cell array 310 includes a redundant area for storing redundant data. Additionally, Figure 3The MRAM 300 further includes a data I / O buffer 359. The data I / O buffer 359 provides redundant input and output data.
[0055] As mentioned above, Figure 3 The storage device 100 can reduce errors in image data. Note that the storage device 100 can be configured to have I / O redundancy instead of image data error detection and correction processing. In this case, an I / O redundancy control unit is arranged in the control circuit 110, and the data I / O buffers 259 of the storage cell array 210 and 310 of the storage cell array 310 are used for I / O redundancy.
[0056] [Another configuration for the storage device]
[0057] Figure 4 This is a diagram illustrating another configuration example of a storage device according to a second embodiment of the present disclosure. The diagram illustrates a configuration similar to... Figure 3 A block diagram of a configuration instance of storage device 100. The storage device 100 in this diagram is... Figure 3 The difference in the storage device 100 shown in the figure is that the storage device 100 in this figure includes FeRAM 400 instead of MRAM 300. The storage cell array 410 of FeRAM 400 includes a redundant area for storing redundant data. In addition, FeRAM 400 in this figure includes a data I / O buffer 459 corresponding to the redundant data.
[0058] The configuration of the storage device 100 other than that described above is similar to that of the storage device 100 in the first embodiment of this disclosure, and therefore its description will be omitted.
[0059] As described above, the storage device 100 according to the second embodiment of this disclosure can reduce the impact of errors in image data by performing error detection and correction of image data.
[0060] (3. Application of electronic devices)
[0061] The storage device 100 described above can be applied to various products. Electronic devices using the storage device 100 will be described below.
[0062] [Configuration of electronic devices]
[0063] Figure 5 This is a diagram illustrating a configuration example of an electronic device to which the technology according to embodiments of the present disclosure can be applied. The diagram is a block diagram illustrating a configuration example of electronic device 1. Electronic device 1 is an apparatus for generating an image of a subject. Electronic device 1 includes an image sensor 2 and an application processor 3. The image sensor 2 images the subject to generate image data. The application processor 3 processes the image data.
[0064] Image sensor 2 includes a pixel array unit 13 and peripheral circuit units. In the pixel array unit, pixels 12, each comprising a plurality of photoelectric conversion units, are regularly and two-dimensionally arranged on a semiconductor substrate (e.g., a silicon substrate). Each pixel 12 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors may include, for example, three transistors serving as a transfer transistor, a reset transistor, and an amplification transistor. Additionally, a selection transistor may be added to form four transistors.
[0065] The peripheral circuit unit includes a vertical drive circuit 33, an analog-to-digital converter 34, a horizontal drive circuit 35, a sensing amplifier 37, a PLL 42, a control unit 40, a parallel-to-serial conversion circuit 43, a delay line 44, and a transmission circuit 45.
[0066] The vertical driving circuit 33 includes, for example, a shift register, selects a pixel driving line 23, provides pulses for driving the pixel 12 to the selected pixel driving line 23, and drives the pixel 12 row by row. In other words, the vertical driving circuit 33 sequentially selects and scans each pixel 12 of the pixel array unit 13 row by row in the vertical direction, and provides a pixel signal based on the signal charge generated in a photodiode, for example, serving as a photoelectric conversion unit for each pixel 12, to the analog-to-digital conversion unit 34 via the vertical signal line 24.
[0067] For example, an analog-to-digital conversion unit 34 is arranged for each column of pixel 12, and an analog-to-digital conversion is performed on the pixel signal output from a row of pixel 12 and transmitted by the vertical signal line 24 to generate an image signal.
[0068] The horizontal drive circuit 35 includes, for example, a shift register, which sequentially selects each analog-to-digital converter 34 by sequentially outputting horizontal scan pulses, and causes each analog-to-digital converter 34 to output an image signal to the horizontal signal line 38.
[0069] The sensing amplifier 37 performs signal processing on the image signals sequentially provided from each analog-to-digital conversion unit 34 via the horizontal signal line 38, and outputs the processed image signal.
[0070] PLL 42 generates a clock signal and provides the clock signal to control unit 40.
[0071] Control unit 40 controls the entire image sensor 2. Additionally, control unit 40 processes the image signal output from sensing amplifier 37. At this time, control unit 40 causes frame memory 41 included in control unit 40 to temporarily store the image signal. Control unit 40 performs processes such as rearranging the image signals stored in frame memory 41 to generate image data. Control unit 40 reads the generated image data from frame memory 41 and outputs the image data to parallel-to-serial conversion circuit 43.
[0072] Parallel-to-serial conversion circuit 43 performs parallel-to-serial conversion on image data from control unit 40. The converted image data is transmitted to transmission circuit 45 via delay line 44.
[0073] The transmission circuit 45 transmits image data to the application processor 3. For example, a transmission circuit compatible with Low Voltage Differential Signaling (LVDS) can be used in the transmission circuit 45.
[0074] Figure 1 The storage device 100 can be applied to the frame memory 41 of the aforementioned electronic device 1.
[0075] [Image sensor configuration]
[0076] Figure 6 This is a diagram illustrating a configuration example of an image sensor to which the technology according to embodiments of the present disclosure can be applied. The diagram shows a configuration example of an image sensor 2. The image sensor 2 in this diagram shows an example of a stacked first semiconductor substrate 11 on which pixel array units 13 are arranged and a second semiconductor substrate 21 on which peripheral circuit units are arranged. On the second semiconductor substrate 21, a constant current circuit 51 of the peripheral circuit units is arranged. Figure 5 (not shown in the image), analog-to-digital conversion unit (in...) Figure 6 The diagram describes an ADC 34, a frame memory 41, and logic circuitry 50. Note that the constant current circuitry 51 is the circuitry that forms the load of the selection transistor for pixel 12. Constant current circuitry 51 is arranged for each vertical signal line 24. Furthermore, logic circuitry 50 includes other parts of peripheral circuitry units, etc.
[0077] Note that the configuration of image sensor 2 is not limited to this example. For example, pixel array unit 13, constant current circuit 51, analog-to-digital converter unit 34, frame memory 41, and logic circuit 50 can be arranged on a semiconductor substrate.
[0078] Figure 7This diagram illustrates an example of image data generation in an image sensor to which the technology according to embodiments of the present disclosure can be applied. The diagram is a flowchart illustrating an example of image data generation processing in image sensor 2. First, a pixel signal is output from pixel 12 (step S101). Next, analog-to-digital conversion unit 34 performs analog-to-digital conversion of the pixel signal (step S102). Next, control unit 40 causes frame memory 41 to store the image signal (step S103). Next, control unit 40 reads image data from frame memory 41 and outputs the image data (step S104). Through the above processing, the image data can be provided to an external device, such as application processor 3.
[0079] Although embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above embodiments themselves, and various modifications can be made without departing from the spirit of the present disclosure. Furthermore, the constituent elements of different embodiments and variations can be appropriately combined.
[0080] Furthermore, the processes described using flowcharts and sequence diagrams in this specification do not necessarily have to be executed in the order shown. Some processing steps can be executed in parallel. In addition, additional processing steps can be used, and some processing steps can be omitted.
[0081] Note that the effects described in this specification are merely examples and are not limited, and other effects may be provided.
[0082] Note that this technology can also have the following configurations. (1)
[0084] A storage device, comprising:
[0085] The first memory includes SRAM and stores the high-order bits of the image data; and
[0086] The second memory includes a memory with a smaller storage cell area than SRAM, and the second memory stores the low-order bits of the image data. (2)
[0088] According to the storage device of (1) above, the second memory includes a magnetoresistive memory as a memory with a cell area smaller than that of SRAM. (3)
[0090] According to the storage device of (1) above, the second memory includes ferroelectric memory as a memory with a cell area smaller than SRAM. (4)
[0092] According to any one of (1) to (3) above, the storage device wherein the first memory stores at least the high 2 bits of the image data. (5)
[0094] The storage device according to any one of (1) to (4) above further includes an error detection and correction unit that performs error detection and correction processing on the image data stored in the second memory. (6)
[0096] According to the storage device described in (5) above, the error detection and correction unit further performs error detection and generation processing on the image data stored in the first memory. (7)
[0098] An image sensor, comprising:
[0099] Imaging elements generate image data;
[0100] The first memory includes SRAM and stores the high-order bits of the image data; and
[0101] The second memory includes a memory with a smaller storage cell area than SRAM, and the second memory stores the low-order bits of the image data. (8)
[0103] The image sensor according to (7) above further includes:
[0104] A first semiconductor substrate, an imaging element for generating image data disposed on the first semiconductor substrate; and
[0105] A second semiconductor substrate, on which the first memory and the second memory are disposed, and the second semiconductor substrate is stacked on the first semiconductor substrate. (9)
[0107] The image sensor according to (7) further includes a semiconductor substrate, an imaging element that generates image data, a first memory and a second memory disposed on the semiconductor substrate. (10)
[0109] An electronic device, comprising:
[0110] The storage device includes:
[0111] The first memory includes SRAM and stores the high-order bits of the image data, and
[0112] The second memory includes a memory with a smaller cell area than SRAM, and the second memory stores the low-order bits of the image data; and
[0113] The processing unit performs image data processing.
[0114] List of reference numerals
[0115] 1. Electronic equipment
[0116] 2 Image Sensor
[0117] 3 Application Processor
[0118] 11 First Semiconductor Substrate
[0119] 12 pixels
[0120] 21 Second Semiconductor Substrate
[0121] 41-frame memory
[0122] 100 storage devices
[0123] 111 Error Detection and Correction Unit
[0124] 200 SRAM
[0125] 300MRAM
[0126] 400FeRAM.
Claims
1. A storage device, comprising: The first memory includes SRAM and stores the high-order bits of the image data; as well as The second memory includes a memory with a storage cell area smaller than that of the SRAM, and the second memory stores the low-order bits of the image data.
2. The storage device according to claim 1, wherein, The second memory includes a magnetoresistive memory as a memory with a smaller cell area than the SRAM.
3. The storage device according to claim 1, wherein, The second memory includes a ferroelectric memory as a memory with a smaller cell area than the SRAM.
4. The storage device according to claim 1, wherein, The first memory stores at least the high 2 bits of the image data.
5. The storage device according to claim 1, further comprising an error detection and correction unit, the error detection and correction unit performing error detection and correction processing on the image data stored in the second memory.
6. The storage device according to claim 5, wherein, The error detection and correction unit further performs error detection and generation processing on the image data stored in the first memory.
7. An image sensor, comprising: Imaging elements generate image data; The first memory includes SRAM and stores the high-order bits of the image data; as well as The second memory includes a memory with a storage cell area smaller than that of the SRAM, and the second memory stores the low-order bits of the image data.
8. The image sensor according to claim 7, further comprising: A first semiconductor substrate, on which an imaging element that generates the image data is disposed; as well as A second semiconductor substrate, wherein the first memory and the second memory are disposed on the second semiconductor substrate, and the second semiconductor substrate is stacked on the first semiconductor substrate.
9. The image sensor of claim 7, further comprising a semiconductor substrate, wherein the imaging element that generates the image data, the first memory, and the second memory are disposed on the semiconductor substrate.
10. An electronic device, comprising: Storage device, the storage device comprising: The first memory includes SRAM and stores the high-order bits of the image data, and The second memory includes a memory with a smaller storage cell area than the SRAM, and the second memory stores the low-order bits of the image data; and The processing unit performs the processing of the image data.
Citation Information
Patent Citations
Imaging apparatus
JP2013093685A