Microelectronic devices including vertical planar memory cell structures, and related memory devices and electronic systems

Abstract

A method of forming a microelectronic device includes forming a preliminary stack structure having layers of sacrificial material and insulating material over a substrate structure; forming a slot extending vertically through the preliminary stack structure having a first region and a second region; forming a memory cell material, a mask material, and a trim material within the slots; removing a portion of the trim material within the first region of the slot; removing portions of the trim material, the mask material, and the memory cell material within the second region of the slot structure to form a memory string structure; and replacing the sacrificial material of the level of the preliminary stack structure with a conductive material. The first region extends horizontally in a first direction. The second region intersects the first region and extends horizontally in a second direction. The memory string structures are horizontally separated from each other in the second direction.

Description

[0001] Priority Statement

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 424,709, filed January 26, 2024, and the benefit of U.S. Provisional Patent Application No. 63 / 492,290, filed March 27, 2023, pursuant to 35 U.S.SC §119(e), the full disclosure of each of which is hereby incorporated herein by reference. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems. Background Technology

[0004] Microelectronic device designers typically aim to increase the level or density of feature integration within a microelectronic device by reducing the size of individual features and by decreasing the spacing between adjacent features. Furthermore, microelectronic device designers often seek architectures that are not only compact but also offer performance advantages, and they also seek to simplify the design process.

[0005] An example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in computers or other electronic devices. Many types of memory devices exist, including, but not limited to, non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is by utilizing a vertical memory array (also known as a "three-dimensional (3D) memory array") architecture. A conventional vertical memory array comprises strings of memory cells extending vertically through one or more stacked structures, which include layers of conductive structures and insulating material. Each string of memory cells may contain at least one selection device coupled thereto. Compared to structures with a conventional planar (e.g., two-dimensional) transistor arrangement, this configuration allows a greater number of switching devices (e.g., transistors) to be located within a unit die area (i.e., the length and width of the active surface consumed) by building the array upwards (e.g., vertically) on the die.

[0006] Vertical memory array architecture typically includes electrical connections between conductive materials in layers of stacked memory devices (several) and control logic devices (e.g., string drivers), enabling the unique selection of memory cells in the vertical memory array for write, read, or erase operations.

[0007] Unfortunately, with the increase in feature packaging density and the decrease in the margin of forming error, conventional manufacturing methods and resulting structural configurations have led to undesirable defects that may reduce the desired performance, reliability and durability of memory devices. Summary of the Invention

[0008] In some embodiments, a method of forming a microelectronic device includes: forming a preliminary stacked structure having layers over a substrate structure, each layer of the preliminary stacked structure comprising a sacrificial material and an insulating material vertically adjacent to the sacrificial material; forming a slot extending vertically through the preliminary stacked structure, having a first region and a second region; forming memory cell material within the slot; forming a mask material within the slot and over the memory cell material; forming a trimming material within the slot and over the mask material; removing a portion of the trimming material within the first region of the slot; removing portions of the trimming material, the mask material, and the memory cell material within the second region of the slot structure to form a memory string structure; and replacing the sacrificial material of the layers of the preliminary stacked structure with a conductive material after forming the memory string structure. The first region extends horizontally in a first direction. The second region intersects the first region and extends horizontally in at least one second direction at an angle relative to the first direction. The memory string structures extend vertically through the preliminary stacked structure and are horizontally separated from each other in the at least two second directions.

[0009] In an additional embodiment, a microelectronic device includes a stacked structure and a substrate structure vertically subordinate to the stacked structure. The stacked structure has layers, each layer comprising vertically adjacent conductive and insulating materials. The stacked structure is divided into blocks extending horizontally in a first direction. The blocks are separated from each other by insulating slot structures in a second direction. The second direction is orthogonal to the first direction. At least one of the blocks has a slot extending vertically through all the layers and a memory string structure. The slot includes a first region and a second region intersecting the first region. The first region extends horizontally in the first direction. The second region extends horizontally upward in at least one third direction. The third third direction is angled relative to the first and second directions. The memory string structure extends vertically through the stacked structure within the horizontal region of the second region of the slot. The memory string structures are horizontally separated from each other in the at least one third direction. The substrate structure includes a plug structure and additional conductive material. The plug structure is within the horizontal region of the second region of the slot of the at least one of the blocks. The plug structure contacts the memory string structure of the at least one of the blocks. The additional conductive material contacts the side surface of the plug structure.

[0010] In a further embodiment, a memory device has a stacked structure and a substrate structure vertically located below the stacked structure. The stacked structure includes blocks extending parallel in a first horizontal direction. Each block individually includes layers. Each layer has a conductive material and an insulating material vertically adjacent to the conductive material. Each block individually includes at least partially filled slots and vertically extending strings of memory cells. The at least partially filled slots extend vertically through the layers. The at least partially filled slots have a trunk region and rib regions. The trunk region extends substantially linearly in the first horizontal direction. The rib regions intersect the trunk region. The rib regions individually extend substantially linearly in at least one second horizontal direction at an angle relative to the first horizontal direction. The vertically extending strings of memory cells are located in the horizontal region of the rib regions of the at least partially filled slots. The substrate structure includes a plug structure and a laterally extending conductive structure. The plug structure is electrically connected to the vertically extending strings of memory cells. The laterally extending conductive structure contacts the sidewalls of the plug structure. Attached Figure Description

[0011] Figure 1 This is a simplified, partial top view of the structure of a microelectronic device during a processing stage of a method for forming a microelectronic device according to an embodiment of the present disclosure.

[0012] Figures 2A to 2Q These are different processing stages in the methods for forming microelectronic devices. Figure 1 The image shows a simplified, partial perspective cross-sectional view of a portion of the structure of a microelectronic device.

[0013] Figure 2R Is Figure 2Q The diagram shows a simplified, partial perspective cross-sectional view of an additional portion of the microelectronic device structure during the processing stage.

[0014] Figure 3 Is Figure 2Q and 2R A simplified, partial top view of the microelectronic device structure after the processing stage.

[0015] Figure 4 This is a simplified, partial top view of a microelectronic device structure according to an additional embodiment of the present disclosure.

[0016] Figure 5 This is a simplified, partial top view of a microelectronic device structure according to yet another embodiment of the present disclosure.

[0017] Figure 6 This is a simplified, partial top view of a microelectronic device structure according to a further embodiment of the present disclosure.

[0018] Figure 7This is a simplified, partial top view of a microelectronic device structure according to a further embodiment of the present disclosure.

[0019] Figure 8 This is a simplified, partial top view of a microelectronic device structure according to a further embodiment of the present disclosure.

[0020] Figure 9 This is a schematic block diagram illustrating an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0021] The following description provides specific details, such as material composition, shape, and size, to provide an exhaustive description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. The description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions to form a complete microelectronic device from the structures can be performed using conventional manufacturing techniques.

[0022] The accompanying drawings presented herein are for illustrative purposes only and do not represent actual views of any particular material, component, structure, device, or system. Shapes depicted in the drawings are expected to vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but include deviations in shape, for example, due to manufacturing processes. For example, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may include some rough and / or linear characteristics. Furthermore, acute angles may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to represent the precise shapes of the illustrated areas and do not limit the scope of the claims of this invention. The drawings are not necessarily drawn to scale. Additionally, common elements between figures may retain the same reference numerals.

[0023] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, and by way of limiting examples only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0024] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device in a predetermined manner to facilitate the operation of one or more of the structure and the device.

[0025] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surfaces of the structure that have a relatively larger area compared to the other surfaces of the structure. Referring to the figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0026] As used herein, features described as “adjacent” to each other (e.g., areas, structures, devices) represent and include features of the disclosed individuals (or individuals) positioned closest to each other (e.g., closest to each other). Additional features (e.g., additional areas, additional structures, additional devices) of the disclosed individuals (or individuals) that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature of an individual that is different from the individual associated with at least one of the “adjacent” features is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other represent and include features of the disclosed individuals (or individuals) positioned closest to each other (e.g., closest to each other vertically). Furthermore, features described as “horizontally adjacent” to each other represent and include features of the disclosed individuals (or individuals) positioned closest to each other (e.g., closest to each other horizontally).

[0027] As used herein, for ease of description, spatially relative terms (e.g., "below," "under," "bottom," "above," "on top," "top," "front," "back," "left," "right," and the like) may be used to describe the relationship of one element or feature to another element(s), as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to cover different orientations of material, in addition to covering the orientations depicted in the figures. For example, if the material in the figures were inverted, an element described as "below" or "below" or "under" or "below" or "on the bottom of" another element or feature would be oriented "on" or "on top" of another element or feature. Furthermore, if material is formed to cover a surface (e.g., a substantially vertical sidewall of a structure), then the material may be referred to as being formed "above" the surface, even if the material may not be spatially above the covered surface. Similarly, the surface may be referred to as "below" the formed material. Therefore, depending on the context in which the term is used, the term "below" can encompass both orientations of "above" and "below," as will be obvious to a person skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatial relative descriptors used herein shall be interpreted accordingly.

[0028] As used herein, the singular forms “a”, “an” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0029] As used in this article, “and / or” includes any and all combinations of one or more of the items listed in connection with the document.

[0030] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other (e.g., via a direct ohmic connection or via an indirect connection (e.g., via another structure)).

[0031] As used herein, the term "substantially" when referring to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied with varying degrees of variation (e.g., within acceptable tolerances), as would be understood by one of ordinary skill in the art. For example, depending on the specific parameter, property, or condition that is substantially satisfied, it may be satisfied by at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0032] As used herein, “about” or “approximately” when referring to the value of a particular parameter includes the value and the degree of variation of the value within acceptable tolerances for the particular parameter, as would be understood by one of ordinary skill in the art. For example, “about” or “approximately” when referring to a value may include additional values ​​within the range of 90.0% to 110.0% of the value (e.g., from 95.0% to 105.0%, from 97.5% to 102.5%, from 99.0% to 101.0%, from 99.5% to 100.5%, or from 99.9% to 100.1%).

[0033] As used herein, “insulating material” means and includes electrically insulating materials, which include one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon nitride material (e.g., silicon carbon nitride (SiO2)). x C z N y Formulas containing one or more of "x", "y", and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N yThis indicates a material containing, for each atom of one element (e.g., Si, Al, Hf, Nb, Ti), an average ratio of "x" atoms of another element, "y" atoms of another element, and "z" atoms of an additional element (if any). Because this formula represents relative atomic ratios and is not a strict chemical structure, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if any) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes chemical compounds with an elemental composition that cannot be expressed in ratios of well-defined natural numbers and that violate the law of definite proportions. Additionally, "insulating structure" means and includes structures formed from and containing insulating materials.

[0034] As used herein, “sacrificial material” means and includes a material that can be selectively removed relative to one or more other materials (e.g., one or more insulating materials). The sacrificial material can be selectively etched relative to one or more other materials during co-exposure (e.g., collectively, mutually) to a first etchant; and the sacrificial material can be selectively etched relative to the sacrificial material during co-exposure to a second different etchant. As used herein, a material is “selectively etchable” relative to another material if it exhibits an etch rate at least about five times (5x) the etch rate of the other material (e.g., about ten times (10x), about twenty times (20x), or about forty times (40x)). By way of non-limiting example, depending on the material composition of one or more other materials, the sacrificial material can be formed from and include one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxide material (e.g., SiO2). x C y ), and at least one hydrogenated dielectric carbon oxide material (e.g., SiC) x O y H z ), and at least one dielectric carbon nitride material (e.g., SiO2). x Cz N y The sacrificial material can be selectively etched relative to one or more other materials during co-exposure to a wet etchant comprising phosphoric acid (H3PO4). Additionally, "sacrificial structure" refers to and includes structures formed from and containing sacrificial material.

[0035] As used herein, “conductive material” means and includes electrically conductive materials, such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au). The term "conductive structure" refers to and includes structures formed from and containing conductive materials, such as aluminum (Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel), materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), and conductive doped silicon-germanium (SiGe)). Additionally, "conductive structure" indicates and includes structures formed from and containing conductive materials.

[0036] As used herein, the term "semiconductor material" refers to a material having a conductivity between that of insulating and conductive materials. For example, a semiconductor material may have a conductivity between approximately 10⁻⁶ at room temperature. -8 Siemens / cm (S / cm) and about 10 4 S / cm(10 6 Conductivity between S / m. Examples of semiconductor materials include elements found in column IV of the periodic table, such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include (but are not limited to) compound semiconductor materials, such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)) and ternary compound semiconductor materials (e.g., Al). X Ga 1-X As) and quaternary compound semiconductor materials (e.g., Ga) X In 1-X As Y P 1-YCompound semiconductor materials may contain (but are not limited to) combinations of elements from columns III and V of the periodic table (III-V semiconductor materials) or from columns II and VI of the periodic table (II-VI semiconductor materials). Further examples of semiconductor materials include oxide semiconductor materials, such as zinc tin oxide (ZnO). x Sn y O, commonly referred to as "ZTO"), indium zinc oxide (In) x Zn y O, commonly referred to as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly referred to as "IGZO"), indium gallium silicon oxide (In) x Ga y Si z O, commonly referred to as "IGSO"), indium tungsten oxide (In) x W y O, commonly referred to as "IWO"), indium oxide (In) x O), tin oxide (Sn) x O), titanium dioxide (Ti) x O), zinc oxide (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), Zirconia indium zinc (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf) x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc (Al) x Sn y In z Zn a O), silicon indium zinc (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O), Zirconia zinc tin (Zr) x Zn y Sn z O) and other similar materials.

[0037] As used herein, the term "homogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) remain constant throughout different parts of the feature (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "heterogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) vary throughout different parts of the feature. If a feature is heterogeneous, then the amounts of one or more elements contained in the feature may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically). For example, a feature may be formed by and contain a stack of at least two different materials.

[0038] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by a person skilled in the art. Additionally, unless the context otherwise indicates, the removal of the materials described herein can be accomplished by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, planarization (e.g., chemical-mechanical planarization (CMP)), or other known methods.

[0039] Figure 1 and Figures 2A to 2R Various views (described in further detail below) of a microelectronic device structure 100 illustrating different processing stages of a method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) according to embodiments of the present disclosure are provided. From the description provided below, it will be readily apparent to those skilled in the art that the structures (e.g., microelectronic device structure 100) and devices (e.g., microelectronic devices) described herein can be used in a variety of relatively large devices and / or systems. For clarity and ease of understanding of the drawings and associated descriptions, Figure 1 and Figures 2A to 2R One or more of the others not described Figure 1 and Figures 2A to 2R All features (e.g., regions, structures, materials, devices) of the microelectronic device structure 100 described in one or more of them.

[0040] Figure 1A simplified, partial top view of a microelectronic device structure 100 during a processing stage of a method for forming a microelectronic device according to embodiments of the present disclosure is depicted. The microelectronic device structure 100 may be formed to include a preliminary stacked structure 102 over a substrate structure 104. The microelectronic device structure 100 may include contour slots 106 that define voids in the preliminary stacked structure 102. Figure 1 As depicted, the profile slot 106 has a profile defined by a main region 108 (also referred to herein as the "first region") and one or more rib regions 110 (also referred to herein as the "second region") extending horizontally from the main region 108.

[0041] like Figure 1 As shown, the backbone region 108 may have a substantially rectangular profile formed by a portion of the contour slot 106, the backbone region 108 comprising relatively long edges (e.g., along the X direction) and relatively short edges (e.g., along a Y direction substantially orthogonal to the X direction). Rib regions 110 may be individually horizontally spaced from each other (e.g., in the X direction) between approximately 100 nanometers (100 nm) and approximately 150 nanometers (150 nm). Alternatively, rib regions 110 may be individually spaced from each other with a pitch (e.g., in the X direction) between approximately 125 nanometers (125 nm) and approximately 175 nanometers (175 nm). In one embodiment, rib regions 110 are individually spaced from each other with a pitch (e.g., in the X direction) of approximately 146 nanometers (146 nm).

[0042] Rib regions 110 may include multiple substantially linear portions of profiled slots 106 in the initial stacked structure 102. Rib regions 110 may individually extend from opposite sides of opposite long edges (e.g., extending in the X direction) of the main trunk region 108. Individual rib regions 110 may include opposite long edges (e.g., horizontal boundaries) along the direction in which the rib region 110 extends from the main trunk region 108. Multiple rib regions 110 extending individually from each opposite side of the main trunk region 108 (e.g., along the X direction) may collectively form corresponding groups of rib regions 110 (e.g., a first group of ribs 112, a second group of ribs 114). The first group of ribs 112 and the second group of ribs 114 may be mirror images of each other, symmetrical across a transverse centerline of the main trunk region 108 (e.g., extending in the X direction and centered in the Y direction). Alternatively, some rib regions 110 may individually form different angles relative to the main trunk region 108 compared to other rib regions 110. For example, in one embodiment, individual rib regions 110 in the first set of ribs 112 form a first angle relative to the main trunk region 108; while individual rib regions 110 in the second set of ribs 114 form different angles relative to the skeleton region 108. Rib regions 110 may extend from the main trunk region 108 at various angles relative to the main trunk region 108. In one embodiment, rib regions 110 individually extend from the main trunk region 108 at an angle of approximately 80 degrees (80°). In other embodiments, rib regions 110 individually extend from the main trunk region 108 at an angle between approximately 85 degrees (85°) and approximately 75 degrees (75°). In other embodiments, rib regions 110 individually extend from the main trunk region 108 at an angle between approximately 80 degrees (80°) and approximately 90 degrees (90°) (e.g., between approximately 85 degrees (85°) and approximately 90 degrees (90°)). In other embodiments, the rib regions 110 individually extend from the trunk region 108 at an angle of less than approximately 80 degrees (80°), for example, less than 75 degrees (75°), less than 70 degrees (70°), less than 65 degrees (65°), or less than 60 degrees (60°). The rib regions 110 may be spatially arranged relative to the trunk region 108 such that later-formed bit lines (e.g., data lines, digital lines) above the initial stacked structure 102 (e.g., in the Z direction) vertically overlay (e.g., in the Z direction) the later-formed corresponding vertical memory string structure within the outline of the rib region 110, as will be described and shown in further detail below.

[0043] Figure 2A Is Figure 1 The processing stages described in the text revolve around Figure 1 A simplified, partial perspective cross-sectional view of a portion of the microelectronic device structure 100 depicted by the dashed line AA. Figure 2AAs shown, the microelectronic device structure 100 can be formed to include a preliminary stacked structure 102, which includes a vertically alternating (e.g., in the Z direction) sequence of insulating material 202 and sacrificial material 204 arranged in layers 206. The layers 206 of the preliminary stacked structure 102 may individually include vertically adjacent (e.g., directly vertically adjacent in the Z direction) sacrificial material 204 and insulating material 202.

[0044] The insulating material 202 of individual layers 206 of the preliminary stacked structure 102 may be formed of and contain at least one dielectric material, which is one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbon nitride material (e.g., SiO2) x C z N y In some embodiments, the insulating material 202 of each of the layers 206 of the initial stacked structure 102 is formed of and comprises a dielectric oxide material, such as SiO2. x (e.g., SiO2). The insulating material 202 of each of the layers 206 may be substantially homogeneous, or the insulating material 202 of one or more of the layers 206 (e.g., each) may be heterogeneous.

[0045] The sacrificial material 204 of each of the layers 206 of the initial stacked structure 102 may be formed of and comprise at least one material (e.g., at least one insulating material) that can be selectively removed relative to the insulating material 202. The sacrificial material 204 may be selectively etched relative to the insulating material 202 during common (e.g., collectively, mutually) exposure to a first etchant; and the insulating material 202 may be selectively etched relative to the sacrificial material 204 during common exposure to a second different etchant. By way of non-limiting example, depending on the material composition of the insulating material 202, the sacrificial material 204 may be formed of and comprise at least one of the following: at least one dielectric oxide material (e.g., SiO2). xPhosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxide material (e.g., SiO2). x C y ), and at least one hydrogenated dielectric carbon oxide material (e.g., SiC) x O y H z ), and at least one dielectric carbon nitride material (e.g., SiO2). x C z N y And at least one semiconducting material (e.g., polycrystalline silicon). In some embodiments, the sacrificial material 204 of each of the layers 206 of the initial stacked structure 102 is formed of and comprises a dielectric nitride material, such as SiN. y (e.g., Si3N4). The sacrificial material 204 can be selectively etched relative to the insulating material 202, for example, during co-exposure to a wet etchant including phosphoric acid (H3PO4).

[0046] The initial stack structure 102 may be formed to include any desired number of layers 206. By way of non-limiting examples, the initial stack structure 102 may be formed to include sixteen or more (16) layers 206, such as thirty-two (32) layers 206, sixty-four (64) layers 206, one hundred and twenty-eight (128) layers 206, or two hundred and fifty-six (256) layers 206.

[0047] The profile slot 106 can be defined as a negative space within and at least partially defined by the vertical boundary of the initial stacking structure 102. The initial stacking structure 102 may include sidewalls 208 that define the horizontal boundary of the profile slot 106 (e.g., in the X direction, Y direction, or a combination of the X and Y directions in a horizontal direction). Each rib region 110 can be horizontally defined by two opposing sidewalls 208 of the initial stacking structure 102 facing each other. In other words, a pair of opposing sidewalls 208 can form two (2) opposing long horizontal boundaries of the individual rib region 110 of the profile slot 106.

[0048] The sidewalls 208 of the initial stacked structure 102 may be tapered due to a removal process (e.g., a deep dry etching operation) performed on the initial stacked structure 102 to form contour slots 106 therein. Alternatively, the sidewalls 208 may be formed to be substantially vertical. As used in the following description, the sidewalls 208 may comprise substantially vertical surfaces of the initial stacked structure 102 and / or other materials formed above the initial stacked structure 102. Furthermore, the sidewalls 208 may comprise substantially vertical surfaces of the later-formed stacked structure 210 and / or other materials formed above the later-formed stacked structure 210.

[0049] The initial stacked structure 102 can be formed to include one or more layers, each layer including multiple layers 206. For example... Figure 2A As depicted, the initial stacking structure 102 may include a lower stack 212 and an upper stack 214 vertically overlying (e.g., in the Z direction) the lower stack 212. The stacks of the initial stacking structure 102 (e.g., lower stack 212, upper stack 214) may individually include any desired number of layers 206. By way of a non-limiting example, the stacks of the initial stacking structure 102 (e.g., lower stack 212, upper stack 214) may individually include ten (10) layers 206. Alternatively, the stacks of the initial stacking structure 102 may individually include fewer than ten (10) layers 206. As a further non-limiting example, the stack of the initial stack structure 102 may individually contain eight (8) layers 206, such as sixteen (16) layers 206, thirty-two (32) layers 206, sixty-four (64) layers 206, or one hundred and twenty-eight (128) layers 206.

[0050] As will be described in further detail below, the lower stack 212 and the upper stack 214 may be formed individually at different processing stages. Therefore, the upper stack 214 may be partially horizontally offset (e.g., partially horizontally misaligned) relative to the lower stack 212, thereby creating an upper stack overhang 216. The downward-facing lower edge (e.g., in the Z direction) of the upper stack 214 of the initial stack structure 102 may be exposed due to the partial horizontal misalignment between the upper stack 214 and the lower stack 212. Alternatively, the horizontal misalignment between the upper stack 214 and the lower stack 212 of the initial stack structure 102 may form a shoulder between the lower stack 212 and the upper stack 214. In such embodiments, the upward-facing upper edge (e.g., in the Z direction) of the lower stack 212 of the initial stack structure 102 is exposed due to the partial horizontal misalignment between the upper stack 214 and the lower stack 212. In some cases, horizontal misalignment (e.g., in the X and / or Y directions) between the upper stack 214 and the lower stack 212 of the initial stack structure 102 may result in a tapered sidewall 208 of the initial stack structure 102. This tapered sidewall 208 may be positively or negatively tilted. In additional embodiments, the initial stack structure 102 substantially does not exhibit horizontal offset, horizontal misalignment, and / or taper between the lower stack 212 and the upper stack 214.

[0051] like Figure 2A As depicted, the microelectronic device structure 100 includes a bottom dielectric material 218 and a top dielectric material 220 at the bottom and top of the initial stacked structure 102, respectively. Specifically, the top dielectric material 220 and the bottom dielectric material 218 may be located above and below the layer 206, respectively (e.g., in the Z direction). The bottom dielectric material 218 and the top dielectric material 220 may be individually formed of and contain an insulating material. The bottom dielectric material 218 and the top dielectric material 220 may have substantially the same material composition as each other, or they may have different material compositions. The bottom dielectric material 218 and the top dielectric material 220 may be individually thicker in the vertical direction (e.g., in the Z direction) than the insulating material 202 of the individual layer 206 of the initial stacked structure 102. In some embodiments, the top dielectric material 220 is thicker than the bottom dielectric material 218 in the vertical direction (e.g., in the Z direction).

[0052] The microelectronic device structure 100 may further include a substrate structure 104, and a preliminary stacked structure 102 may be formed over the substrate structure 104. The substrate structure 104 may comprise various materials. For example, the substrate structure 104 may include an upper substrate structure material 222, an intermediate substrate structure material 224, a lower substrate structure material 226, and a substrate structure dielectric material 228. The substrate structure 104 may be formed over a substrate 230. The upper substrate structure material 222 and the lower substrate structure material 226 may be formed of and comprise semiconductor materials, such as doped semiconductor materials (e.g., n-type polysilicon). The substrate structure dielectric material 228 may be formed of and comprise dielectric materials. The intermediate substrate structure material 224 may be formed of an additional semiconductor material, such as a substantially undoped semiconductor material (e.g., undoped polysilicon). Figure 2A As depicted, substrate 230 may include a structure or material on which substrate structure 104 is formed. In some embodiments, substrate 230 includes a semiconductor structure (e.g., a semiconductor wafer, such as a silicon wafer). In other embodiments, substrate 230 includes at least one control logic region below substrate structure 104 (e.g., in the Z direction), the control logic region including other features configured to control microelectronic device structure 100 (e.g., ...). Figure 2Q The control logic means for various operations of the vertical memory cell 284 depicted herein. As a non-limiting example, the control logic region of the substrate 230 may further include one or more of the following (e.g., each): a charge pump (e.g., V0). CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuit systems (e.g., ring oscillators), V dd Regulators, drivers (e.g., serial drivers), page buffers, decoders (e.g., local stack-up decoders, column decoders, row decoders), sense amplifiers (e.g., balanced (EQ) amplifiers, isolated (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA), repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh / wear equalization devices, and other chip / stack control circuitry systems. The control logic region of substrate 230 may be coupled to source structures, one or more access line routing structures, one or more select line routing structures, and / or one or more digital line structures. In some embodiments, the control logic region of substrate 230 includes a CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control logic region of substrate 230 may be characterized as having an "under-array CMOS" ("CuA") configuration.

[0053] As mentioned above Figure 1 As described, the profile slot 106 may include a gap space (e.g., trench, opening, slit) extending vertically through the initial stack structure 102. The profile slot 106 may extend vertically (e.g., in the Z direction) through the top dielectric material 220, the layers 206 of the upper stack 214 and the lower stack 212, and the bottom dielectric material 218. The lower boundary of the profile slot 106 (e.g., in the Z direction) may be at least partially defined by the top surface (e.g., the upper surface) of the substrate structure 104.

[0054] The base structure 104 may include a plurality of bottom plug cavities 232. The bottom plug cavities 232 may include partially vertically extending (e.g., in the Z direction) through a void (e.g., opening, trench, passage) in the base structure 104. In some embodiments, the bottom plug cavities 232 extend vertically through the upper base structure material 222 and the intermediate base structure material 224, and partially through the lower base structure material 226. The bottom plug cavities 232 may be formed by removing material from the base structure 104. The bottom plug cavities 232 may individually exhibit a desired horizontal cross-sectional shape, such as an elliptical horizontal cross-sectional shape.

[0055] form Figure 2A The microelectronic device structure 100 depicted may include a substrate structure 104 formed over a substrate 230. Forming the substrate structure 104 over the substrate 230 may include: forming a substrate structure dielectric material 228 over the substrate 230; forming a lower substrate structure material 226 over the substrate structure dielectric material 228; forming an intermediate substrate structure material 224 over the lower substrate structure material 226; and forming an upper substrate structure material 222 over the intermediate substrate structure material 224.

[0056] After the substrate structure 104 is formed over the substrate 230, the bottom plug cavity 232 can be formed by removing material from the upper substrate structure material 222, the intermediate substrate structure material 224, and the lower substrate structure material 226. The horizontal position of the bottom plug cavity 232 can be selected to correspond to the desired position of a vertical memory string structure that is formed later, which can be individually formed within the bottom plug cavity 232 above the subsequently formed bottom plug (e.g., in the Z direction).

[0057] After the bottom plug cavity 232 is formed, sacrificial material may be formed on top of the substrate structure 104 and may fill the bottom plug cavity 232. Then, the portion of the sacrificial material covering the uppermost surface (e.g., in the Z direction) of the substrate structure 104 may be removed (e.g., by a grinding planarization process, such as a CMP process), which exposes the substrate structure 104 and the bottom plug cavity 232 is filled with sacrificial material to a vertical horizontal (e.g., in the Z direction) substantially coplanar with the upper surface of the upper substrate structure material 222.

[0058] After the bottom plug cavity 232 is filled with sacrificial material, a lower stack 212 of the preliminary stack structure 102 can be formed above the substrate structure 104. The lower stack 212 of the preliminary stack structure 102 can be formed by forming a bottom dielectric material 218 above the substrate structure 104, and then sequentially forming a vertical alternating sequence of sacrificial material 204 and insulating material 202.

[0059] After the lower stack 212 of the preliminary stack structure 102 is formed, the lower portion of the profile slot 106 (e.g., in the vertical range of the lower stack 212 along the Z direction) is formed by selectively removing material from the lower stack 212 of the preliminary stack structure 102, thereby forming a gap with a horizontal profile (e.g., when viewed from a top view) having a trunk region 108 and a rib region 110.

[0060] After the lower portion of the profile slot 106 is formed, the lower portion of the profile slot 106 can be filled with a sacrificial material. Then, the portion of the sacrificial material that has been applied to the uppermost surface of the lower stack 212 (e.g., in the Z direction) can be removed (e.g., by a grinding planarization process, such as a CMP process).

[0061] After the lower portion of the profile slot 106 is filled with sacrificial material, an upper stack 214 of the preliminary stack structure 102 can be formed above the lower stack 212 of the preliminary stack structure 102 and above the sacrificial material within the lower portion of the profile slot 106. The upper stack 214 of the preliminary stack structure 102 can be formed by forming a vertical alternating sequence of insulating material 202 and sacrificial material 204 above the lower stack 212 and above the sacrificial material within the lower portion of the profile slot 106. Thereafter, a top dielectric material 220 can be formed above the layer 206 of insulating material 202 and sacrificial material 204.

[0062] After the upper stack 214 of the initial stack structure 102 is formed, the upper part of the profile slot 106 (e.g., in the upper stack 214) can be formed by selectively removing material from the upper stack 214 of the initial stack structure 102, thereby forming a gap with a horizontal profile (e.g., when viewed from a top view) having a trunk region 108 and a rib region 110.

[0063] After the upper portion of the contour slot 106 is formed, the sacrificial material can be removed from the lower portion of the contour slot 106 and from the bottom plug cavity 232, thereby resulting in the contour slot 106 (including its main region 108 and rib region 110) and the bottom plug cavity 232.

[0064] For reference Figure 2B In the formation of Figure 2AFollowing the contoured slot 106 depicted, a barrier oxide material 236 can be formed above the exposed surface of the microelectronic device structure 100. The barrier oxide material 236 can continuously extend above the surface of the microelectronic device structure 100 defining the contoured slot 106 and the bottom plug cavity 232. For example... Figure 2B As shown, the barrier oxide material 236 can extend substantially continuously across and cover the exposed surfaces (e.g., sidewalls 208) of the initial stacked structure 102 and the substrate structure 104. The barrier oxide material 236 can be formed of and comprise a dielectric oxide material (e.g., silicon oxide).

[0065] After the barrier oxide material 236 is formed, a storage nitride material 238 may be formed on top of the barrier oxide material 236. The storage nitride material 238 may substantially cover the barrier oxide material 236 and extend continuously across the barrier oxide material 236. The storage nitride material 238 may conform to the morphology of the upper surface of the barrier oxide material 236. The storage nitride material 238 may be disposed inside and outside the contour slot 106 and the bottom plug cavity 232. The storage nitride material 238 may be formed of and contain a dielectric nitride material (e.g., silicon nitride).

[0066] After the storage nitride material 238 is formed, a band engineering tunnel oxide material 240 may be formed on top of the storage nitride material 238. The band engineering tunnel oxide material 240 may substantially cover the storage nitride material 238 and extend continuously across the storage nitride material 238. The band engineering tunnel oxide material 240 may conform to the morphology of the upper surface of the storage nitride material 238. The band engineering tunnel oxide material 240 may be disposed inside and outside the contour slot 106 and the bottom plug cavity 232. The band engineering tunnel oxide material 240 may be formed of and contain a dielectric oxide material (e.g., silicon oxide).

[0067] After forming the band tunneling oxide material 240, a semiconductor material 242 may be formed on top of the band tunneling oxide material 240. The semiconductor material 242 may substantially cover the band tunneling oxide material 240 and extend continuously across the band tunneling oxide material 240. The semiconductor material 242 may be disposed inside and outside the contour slot 106 and the bottom plug cavity 232. The semiconductor material 242 may substantially fill the portion of the bottom plug cavity 232 that is not filled by the barrier oxide material 236, the storage nitride material 238, and the band tunneling oxide material 240. The semiconductor material 242 may be doped or substantially undoped. In some embodiments, the semiconductor material 242 is formed from and contains polysilicon doped (e.g., lightly doped) with one or more conductivity-enhancing materials, such as N-type polysilicon (e.g., polysilicon doped with one or more N-type conductivity-enhancing materials (e.g., one or more of arsenic, phosphorus, and antimony).

[0068] The formation of semiconductor material 242 may include forming semiconductor material 242 with a thickness substantially greater than the desired final thickness of semiconductor material 242. After the formation of semiconductor material 242, semiconductor material 242 may be partially removed so that a relatively thin remaining portion of semiconductor material 242 extends over the sidewalls 208 of the initial stacked structure 102. In one example, semiconductor material 242 is formed to have an initial thickness of approximately fifteen (15) nanometers (nm). After the partial removal of semiconductor material 242, the remaining portion of semiconductor material 242 within the vertical boundaries of the initial stacked structure 102 may have a thickness ranging from approximately three (3) nm to about seven (7) nm, for example, approximately five (5) nm.

[0069] In this disclosure, the barrier oxide material 236, the storage nitride material 238, the band tunneling oxide material 240, and the semiconductor material 242 can be collectively referred to as memory cell material 244.

[0070] like Figure 2B As described, when forming the barrier oxide material 236, the storage nitride material 238, the band engineering tunnel oxide material 240, and the semiconductor material 242, the barrier oxide material 236, the storage nitride material 238, and the band engineering tunnel oxide material 240 can be sequentially lined in the bottom plug cavity 232, and then filled with the semiconductor material 242 (e.g., by conformal deposition of the semiconductor material). Filling the bottom plug cavity 232 with the semiconductor material 242 enables the formation of a bottom plug 246 within the bottom plug cavity 232.

[0071] For reference Figure 2CAfter forming the semiconductor material 242, a liner nitride material 248 may be formed over the semiconductor material 242. The liner nitride material 248 may substantially cover the semiconductor material 242 and extend continuously across the semiconductor material 242. The liner nitride material 248 may conform to the morphology of the upper surface of the semiconductor material 242. The liner nitride material 248 may be disposed inside and outside the contour slot 106 and may cover the bottom plug 246. The liner nitride material 248 may be formed of and contain a dielectric nitride material (e.g., silicon nitride). The liner nitride material 248 may be formed to have a thickness of less than or equal to approximately ten (10) nm (e.g., in the range from approximately ten (10) nm to about one (1) nm, less than or equal to approximately five (5) nm, or less than or equal to approximately three (3) nm). The liner nitride material 248 may mitigate oxidation of the semiconductor material 242.

[0072] After the lining nitride material 248 is formed, a lining oxide material 250 may be formed over the lining nitride material 248. The lining oxide material 250 may substantially cover the lining nitride material 248 and extend continuously across the lining nitride material 248. The lining oxide material 250 may conform to the morphology of the upper surface of the lining nitride material 248. The lining oxide material 250 may be disposed inside and outside the contoured slot 106. The lining oxide material 250 may be formed of and contain a dielectric oxide material (e.g., silicon oxide). The lining oxide material 250 may be formed to have a thickness of less than or equal to approximately ten (10) nm (e.g., in the range from approximately ten (10) nm to about one (1) nm, less than or equal to approximately five (5) nm, or less than or equal to approximately three (3) nm).

[0073] In this disclosure, the lining nitride material 248 and the lining oxide material 250 can be collectively referred to as lining material 252.

[0074] Next reference Figure 2D After the liner oxide material 250 is formed, a mask material 254 may be formed over the liner oxide material 250. The mask material 254 may substantially cover the liner oxide material 250 and extend continuously across the liner oxide material 250. The mask material 254 may conform to the morphology of the upper surface of the liner oxide material 250. The mask material 254 may be disposed inside and outside the contour slot 106. In some embodiments, the mask material 254 is formed of and contains a semiconductor material, such as polysilicon. The mask material 254 may be doped or undoped. By a non-limiting example, the mask material 254 may be formed of and contains n-type doped polysilicon. The mask material 254 may be formed to have a thickness in the range of approximately five (5) nm to approximately fifteen (15) nm (e.g., approximately ten (10) nm).

[0075] refer to Figure 2E After the mask material 254 is formed, a trimming material 256 may be formed over the mask material 254. The trimming material 256 may substantially cover the mask material 254 and extend continuously across the mask material 254. The trimming material 256 may conform to the morphology of the upper surface of the mask material 254. The trimming material 256 may be disposed inside and outside the contour slot 106. The trimming material 256 may at least partially (e.g., substantially) fill the unfilled portions of the rib regions 110 of the contour slot 106. In some embodiments, the trimming material 256 substantially fills the remaining (e.g., unfilled) portions of the rib regions 110 between the horizontally opposite portions of the initial stack structure 102. The trimming material 256 may at least partially (e.g., substantially) fill the rib regions 110 of the contour slot 106 at least up to the vertical height of the initial stack structure 102 (e.g., in the Z direction). Figure 2E As shown, a portion of the main trunk area 108 of the contour slot 106 may remain substantially unfilled after the trimming material 256 is formed. The trimming material 256 may only partially fill the remaining portion of the main trunk area 108 after the mask material 254 is formed.

[0076] The trimming material 256 may be formed of and comprise at least one material having a different etch selectivity than subsequently formed materials (e.g., sacrificial filler, overlay, mask oxide). In some embodiments, the trimming material 256 is formed of and comprises a dielectric nitride material (e.g., silicon nitride). In additional embodiments, the trimming material 256 is formed of a dielectric nitride material and an additional material (also referred to herein as a core material) having a different material composition on or above the dielectric nitride material.

[0077] Next reference Figure 2F After the trimming material 256 is formed, a portion of the trimming material 256 can be removed (e.g., via a nitride trimming operation) to form a trimming edge 264 at or near the intersection of the main section 108 and the rib section 110 of the profile slot 106. The trimming material 256 can be substantially removed from the main section 108 while remaining in the rib section 110. Figure 2FAs shown, in some embodiments, portions of trimming material 256 within rib region 110 and near trunk region 108 are removed, such that trimming edges 264 of trimming material 256 are positioned within the horizontal boundary of rib region 110. Trimming edges 264 of trimming material 256 may be horizontally offset from trunk region 108. In additional embodiments, trimming edges 264 of trimming material 256 are positioned at or relatively closer to the horizontal boundary of trunk region 108. Material removal processes (e.g., wet etching processes) may disrupt the continuity of trimming material 256 within contour slot 106, such that portions of trimming material 256 within individual rib regions 110 are separated and discontinuous. Additionally, portions of trimming material 256 outside the boundary (e.g., upper vertical boundary) of contour slot 106 may also be removed. Material removal processes may expose surfaces of mask material 254 within trunk region 108 and outside the boundary of contour slot 106.

[0078] Next reference Figure 2G In the part where trimming material 256 is removed to form trimming edge 264 ( Figure 2F Subsequently, a sacrificial filler material 258 may be formed (e.g., non-conformal deposition) within the remaining (e.g., unfilled) portion of the contour slot 106. The sacrificial filler material 258 may substantially fill the main region 108 of the contour slot 106. The sacrificial filler material 258 may also partially extend into the rib region 110 of the contour slot 106. The sacrificial filler material 258 may be formed and comprise at least one material having etch selectivity relative to the trimming material 256 and the mask material 254. In some embodiments, the sacrificial filler material 258 is formed and comprises a carbon-containing material.

[0079] Initially, a sacrificial filler material 258 may be nonconformally formed (e.g., nonconformally deposited) both inside and outside the contour slot 106. Subsequently, portions of the sacrificial filler material 258 outside the contour slot 106 may be removed (e.g., by CMP), such that the remaining portion of the sacrificial filler material 258 is substantially confined within the contour slot 106. During the material removal process (e.g., CMP process), portions of the barrier oxide material 236, storage nitride material 238, band engineering tunnel oxide material 240, semiconductor material 242, liner nitride material 248, liner oxide material 250, mask material 254, and trimming nitride material 256 covering the upper vertical boundary of the contour slot 106 (e.g., in the Z direction) are also removed. In some embodiments, the material removal process also partially removes the top dielectric material 220 (e.g., vertically recesses it). The material removal process can expose the top dielectric material 220 and can form an upper horizontal surface defined by and including a substantially planar surface of a coplanar horizontal surface of a sacrificial filler material 258, a top dielectric material 220, a barrier oxide material 236, a storage nitride material 238, a band engineering tunnel oxide material 240, a semiconductor material 242, a liner nitride material 248, a liner oxide material 250, a mask material 254, and a trimming material 256.

[0080] Next reference Figure 2H After removing sacrificial fill material 258 in contour slot 106 ( Figure 2G Following the upper portion of the exterior, a cover material 260 may be formed over (e.g., in the Z direction) the sacrificial filler material 258, top dielectric material 220, barrier oxide material 236, storage nitride material 238, band engineering tunnel oxide material 240, semiconductor material 242, liner nitride material 248, liner oxide material 250, mask material 254, and trimming material 256. The cover material 260 may be formed on or above a substantially planar upper horizontal surface defined and encompassing the coplanar horizontal surfaces of the sacrificial filler material 258, top dielectric material 220, barrier oxide material 236, storage nitride material 238, band engineering tunnel oxide material 240, semiconductor material 242, liner nitride material 248, liner oxide material 250, mask material 254, and trimming material 256. The cover material 260 may have a substantially planar upper horizontal surface. The cover material 260 may be formed of and comprise a dielectric oxide material (e.g., silicon oxide). In some embodiments, the cover material 260 comprises silicon oxide (e.g., SiO2) formed (e.g., via deposition) using tetraethyl orthosilicate (“TEOS”) as a silicon source.

[0081] After the cover material 260 is formed, a portion of it within the horizontal boundary of the backbone region 108 can be removed (e.g., by an etching process). Figure 2H As shown, removal of the portion of cover material 260 may result in a cover material gap 266 (e.g., a groove, an opening) located within a horizontal region of the main trunk area 108 of the contour slot 106. The cover material gap 266 may have an elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape) and may at least partially expose the sacrificial filler material 258 within the main trunk area 108.

[0082] The cover material gap 266 may have a horizontal span defined as the distance between the relatively long edges of the cover material gap 266 (e.g., in the Y direction), which exposes at least some of the upper surfaces of the sacrificial filler material 258 without exposing the trimming material 256. Furthermore, the cover material gap 266 may not expose any of the top dielectric material 220, barrier oxide material 236, storage nitride material 238, band engineering tunnel oxide material 240, semiconductor material 242, lining nitride material 248, lining oxide material 250, and mask material 254. In some embodiments, the cover material gap 266 exposes only partially (e.g., not completely) the upper surface of the sacrificial filler material 258.

[0083] refer to Figure 2I After the cover material 260 and the cover material gap 266 are formed, the sacrificial filler material 258 can be removed (e.g., excavated) from the contour slot 106. Removing the sacrificial filler material 258 from the contour slot 106 exposes a portion of the mask material 254 in the horizontal region of the main trunk area 108. Removing the sacrificial filler material 258 also exposes additional portions of the mask material 254 in the portion of the rib area 108 near the main trunk area 110.

[0084] After removing the sacrificial filler 258, the trimming material 256 can be further horizontally recessed (e.g., trimmed) to reposition the trimmed edge 264 relatively further away from the main trunk region 108. Exposed portions of the trimming material 256 can be removed (e.g., using thermal phosphoric acid etching) such that the resulting new horizontal position of the trimmed edge 264 is located at the previously referenced position. Figure 2F The horizontal outer edge of the corresponding horizontal position of the trimmed edge 264 in the described processing stage (e.g., relative to the main area 108).

[0085] Figure 2J to 2R A simplified partial perspective view of a microelectronic device structure 100 including a processing stage of a method for forming a microelectronic device, the processing stage as previously referenced. Figure 2I Following the described processing stages. At this point, in Figure 2J to 2RIn each of these figures, for clarity and ease of understanding of the accompanying drawings and related descriptions, the covering material 260 is not depicted. However, it will be understood that in Figure 2J to 2R The processing stage still includes the covering material 260 and the covering material gaps 266 therein and defined by it.

[0086] After removing the sacrificial filler material 258, a series of trimming etch cycles are performed to continuously form one or more preliminary vertical memory string structures 268 on the sidewalls 208 of the preliminary stacked structure 102. Figure 2J to 2M The diagram describes the sequential processing actions of this trimming etch cycle. A preliminary vertical memory string structure 268 can be formed in the rib region 110 of the contour slot 106. The completion of an individual trimming etch cycle results in the formation of an individual vertical memory string structure 268 on the sidewall 208 of the individual rib region 110 of the contour slot 106. After forming a first group of preliminary vertical memory string structures 268 within the rib region 110 by a first trimming etch cycle, a second group of preliminary vertical memory string structures 268 can be formed within the rib region 110 by a second trimming etch cycle, a third group of preliminary vertical memory string structures 268 can be formed within the rib region 110 by a third trimming etch cycle, and so on, until the series of trimming etch cycles is completed. Within an individual rib region 110, each subsequent trimming etch cycle can form an individual vertical memory string structure 268 horizontally positioned relatively further away from the main trunk region 108 than another vertical memory string structure 268 formed by a previous trimming etch cycle.

[0087] exist Figure 2J The processing stage described herein involves forming two (2) preliminary vertical memory string structures 268 on individual sidewalls 208 of individual rib regions 110, which partially define the preliminary stacked structure 102. The two (2) preliminary vertical memory string structures 268, and two (2) other preliminary vertical memory string structures 268 opposite to the two (2) preliminary vertical memory string structures 268, can be formed by referring to... Figure 2J to 2M This is caused by two (2) previous trimming etch cycles performed prior to the start of the described trimming etch cycle. Horizontally adjacent preliminary vertical memory string structures 268 (e.g., in the horizontal direction along the long edge of the corresponding rib region 110) can be separated from each other by preliminary vertical memory string structure spaces 270. The width of each individual preliminary vertical memory string structure 268 and the width of each individual preliminary vertical memory string structure space 270 horizontally adjacent to the individual preliminary vertical memory string structure 268 can be partially determined by the corresponding width of the trimming material 256 removed during the respective trimming etch cycle, as described in further detail below.

[0088] refer to Figure 2JIndividual trimming etch cycles involve removing portions of trimming material 256 within the rib region 110 of the contour slot 106 to expose portions of mask material 254 within the rib region 110. Some of the removed portions of trimming material 256 may herein be referred to as “memory string portions” of trimming material 256, as corresponding to a later-formed preliminary vertical memory string structure 268 formed at the location of the removed portions of trimming material 256. Some exposed portions of mask material 254 may herein be referred to as “memory string portions” of mask material 254, located at the location of the later-formed preliminary vertical memory string structure 268.

[0089] Figure 2J The material removal process can reposition the trimmed edge 264 of the trimmed material 256 more horizontally away from the main trunk region 108 of the contour slot 106. The material removal process can remove the memory string portion of the trimmed material 256. The material removal process may include subjecting the trimmed edge 264 of the trimmed material 256, established during a previous trimming etch cycle, to at least one etchant (e.g., a thermal phosphoric acid etchant). The etchant can be applied through the cover material 260 (…). Figure 2I The gaps in the covering material in ) 266 ( Figure 2I The main section 108 of the contour slot 106 is introduced into the trimming edge 264 within the rib section 110 of the contour slot 106. The cover material 260 can mitigate (e.g., minimize, prevent) etchant from entering the rib section 110 of the contour slot 106 from above (e.g., in the Z direction). In this way, a material removal process can be performed to gradually remove portions of the trimming material 256 (e.g., memory string portions). By selecting the etchant composition according to a predetermined etching rate, by selecting the duration of the material removal process, and / or by selecting other parameters of the material removal process, the horizontal range of trimming material 256 removed (e.g., backward trimming) within individual rib sections 110 can be controlled as desired.

[0090] By removing the memory string portion of trimming material 256, trimming edge 264 can be horizontally backed to a selected new horizontal position to give the desired horizontal width (e.g., in the horizontal direction along the long edge of the corresponding rib region 110) of the individual preliminary vertical memory string structure 268 to be formed by the trimming etch cycle. The horizontal width of the individual preliminary vertical memory string structure 268 (e.g., in the horizontal direction along the long edge of the corresponding rib region 110) can be in the range of about 20 nm to about 150 nm, such as from about 50 nm to about 120 nm, from about 80 nm to about 100 nm, or from about 90 nm to about 100 nm.

[0091] like Figure 2JAs depicted, individual rib regions 110 may be partially demarcated by two opposing sidewalls 208 of the initial stacked structure 102. Thus, within an individual rib region 110, an individual trimming etch cycle may form a pair of initial vertical memory string structures 268 horizontally opposed to each other (e.g., in a horizontal direction perpendicular to the long edge of the corresponding rib region 110) on the opposing sidewalls 208 within the rib region 110. For an initial stacked structure 102 having a profile slot 106 comprising multiple rib regions 110, each trimming etch cycle may result in the formation of two (2) initial vertical memory string structures 268 horizontally opposed to each other (e.g., in a horizontal direction perpendicular to the long edge of the corresponding rib region 110) within each corresponding rib region 110 of the profile slot 106.

[0092] refer to Figure 2K After removing the memory string portion of the trimming material 256 within the rib region 110, the exposed portion of the mask material 254 within the rib region 110 is then exposed. Figure 2J The mask oxide material 262 is transformed into a mask oxide material 262. In some embodiments, the mask oxide material 262 is formed of and comprises a dielectric oxide material, such as silicon oxide (e.g., SiO2). The mask oxide material 262 can be formed by converting the exposed portion of the mask material 254 into an oxide (e.g., by thermal oxidation or plasma oxidation). The mask oxide material 262 can be formed to span a horizontal width (e.g., in the horizontal direction along the long edge of the corresponding rib region 110) between the adjacent initial vertical memory string structure space 270 and the trimmed edge 264. Furthermore, the mask oxide material 262 can span substantially continuously across the entire vertical range (e.g., in the Z direction) of the sidewall 208 of the initial stack structure 102. The mask oxide material 262 can be formed to have a thickness in the range of about 5 nm to about 15 nm (e.g., from about 8 nm to about 12 nm or about 10 nm). Mask oxide material 262 can be used as a suppressor material that can suppress (e.g., slow down, prevent) the subsequent removal of mask material 254 (e.g., via wet etching), as will be referred to below. Figure 2P To explain in further detail. Alternatively, another type of suppressor material, other than the mask oxide material 262, may be formed from the exposed portion of the mask material 254. For example, the suppressor material may include one or more materials formed by vapor-phase doping or silicide formation of the mask material 254.

[0093] Next reference Figure 2L After forming the mask oxide material 262, additional portions of the trimming material 256 can be removed (e.g., via a wet etchant) to allow the trimming edge 264 to recede further horizontally from the main trunk region 108 of the contour slot 106. The additional material removal process may include... Figure 2JThe trimmed edge 264 of the trimmed material 256, established during the processing stage, is subjected to at least one etchant (e.g., a hot phosphoric acid etchant). The etchant can be applied through a covering material 260 ( Figure 2I The gaps in the covering material in ) 266 ( Figure 2I The main area 108 of the profile slot 106 is introduced into the trimming edge 264 within the rib area 110 of the profile slot 106. The cover material 260 can reduce or prevent etchant from entering the rib area 110 of the profile slot 106 from above (e.g., in the Z direction).

[0094] Additional portions of the trimming material 256 can be removed along a desired horizontal range (e.g., in the horizontal direction along the long edge of the corresponding rib 110) of an individual, subsequently formed initial vertical memory string structure space 270 corresponding to a horizontally interposed initial vertical memory string structure 268. The width of the individual initial vertical memory string structure space 270 (e.g., in the horizontal direction along the long edge of the corresponding rib 110) can be greater than zero (0) nm and less than or equal to about 25 nm, for example, in the range of about 5 nm to about 20 nm, from about 10 nm to about 20 nm, or about 15 nm. Additional portions of the trimming material 256 can be removed along substantially the entire vertical range (e.g., in the Z direction) of the sidewall 208 of the initial stack structure 102.

[0095] like Figure 2L As shown, the removal of the extra portion of trimming material 256 can expose (e.g., reveal) the mask material 254 lying beneath the corresponding portion of the removed extra portion of trimming material 256.

[0096] Next reference Figure 2M After removing the additional portion of trimming material 256, the resulting exposed portion of mask material 254 can be selectively removed (e.g., via a tetramethylammonium hydroxide (“TMAH”) wet etching operation) to expose the corresponding portion of the lining oxide material 250. By removing portions of mask material 254, it is possible to... Figure 2K A preliminary vertical memory string structure space 270 is formed between the trimmed edge 264 formed during the processing stage and the preliminary vertical memory string structure 268 that is most horizontally close to (e.g., in the horizontal direction along the long edge of the corresponding rib region 110).

[0097] like Figure 2M As shown in the image, for reference Figure 2J to 2MThe described trimming etch cycle can result in the formation of preliminary vertical memory string structures 268 within individual rib regions 110 of the contour slot 106. Individual preliminary vertical memory string structures 268 can be horizontally demarcated by adjacent preliminary vertical memory string structure spaces 270 (e.g., in the horizontal direction along the long edge of the corresponding rib region 110). Preliminary vertical memory string structure spaces 270 can individually extend horizontally from and between adjacent preliminary vertical memory string structures 268. Preliminary vertical memory string structures 268 can vertically (e.g., in the Z direction) span substantially the entire height of the preliminary stack structure 102, thereby encompassing the vertical span (e.g., in the Z direction) of both the lower stack 212 and the upper stack 214 of the preliminary stack structure 102.

[0098] After completing an individual trimming etch cycle, one or more additional trimming etch cycles can be performed to form additional preliminary vertical memory string structures 268 and additional preliminary vertical memory string structure spaces 270 within the rib region 110 of the contour slot 106. For example... Figure 2N As shown in the previous reference, Figure 2J The described material removal process is similar to a material removal process that removes a portion of the trimming material 256 adjacent to the previously removed portion of the trimming material 256, such as... Figure 2J As shown in the previous reference. Subsequently, additional trimming etch cycles can be implemented similarly to those in the previous reference. Figure 2K to 2M The additional processing actions described are similar to those additional processing actions.

[0099] Figure 2O The image depicts the result of multiple trimming etch cycles forming multiple preliminary vertical memory string structures 268 within the rib region 110 of the contour slot 106. For example... Figure 2O As shown, substantially the entire horizontal span of the trimming material 256 within the rib 110 has been removed (e.g., in the horizontal direction along the long edge of the corresponding rib 110), and the initial vertical memory string structure 268 and the initial vertical memory string structure space 270 collectively extend horizontally across the horizontal span previously occupied by the trimming material 256 within the rib 110.

[0100] The number of preliminary vertical memory string structures 268 within a group of preliminary vertical memory string structures 268 in individual rib regions 110 may be equal to twice (2x) the number of trimming etch cycles performed. The number of preliminary vertical memory string structures 268 in individual rib regions 110 of the contour slot 106 may be determined in part by the horizontal width of the rib region 110 (e.g., in the horizontal direction along the long edge of the corresponding rib region 110), the horizontal width of the preliminary vertical memory string structures 268 (e.g., in the horizontal direction along the long edge of the corresponding rib region 110), and the horizontal width of the preliminary vertical memory string structure space 270 (e.g., in the horizontal direction along the long edge of the corresponding rib region 110). The preliminary vertical memory string structures 268 may each have substantially the same horizontal width as each other, or one or more of the preliminary vertical memory string structures 268 may have a horizontal width different from one or more of the others. Additionally, the initial vertical memory string structure spaces 270 may each have substantially the same horizontal width as each other, or one or more of the initial vertical memory string structure spaces 270 may have a different horizontal width than one or more of the others. In some embodiments, an individual rib region 110 has a group of eight (8) initial vertical memory string structures 268 formed on each of the two (2) opposing sidewalls 208 that partially define the rib region 110 of the initial stacking structure 102. In other embodiments, an individual rib region 110 has seven (7) or fewer initial vertical memory string structures 268 formed on each of the two opposing sidewalls 208 that partially define the rib region 110 of the initial stacking structure 102. In other embodiments, an individual rib region 110 has nine (9) or more initial vertical memory string structures 268 formed on each of the two opposing sidewalls 208 that partially define the rib region 110 of the initial stacking structure 102.

[0101] During individual processing stages of individual trimming etch cycles, multiple ribs 110 of the contour slot 106 can be acted simultaneously (e.g., concurrently). By a non-limiting example, if the multiple ribs 110 are to individually form groups of sixteen (16) vertical memory string structures (e.g., eight (8) vertical memory string structures of each sidewall 208 defining an individual rib 110) therein during individual trimming etch cycles, then two (2) opposing (e.g., in a horizontal direction perpendicular to the long edge of the corresponding rib 110) preliminary vertical memory string structures 268 can be formed in each of the ribs 110 of the contour slot 106. Eight (8) trimming etch cycles can be performed in this manner, thereby forming sixteen (16) preliminary vertical memory string structures 268 in each of the ribs 110.

[0102] Collective Reference Figure 2O and 2PAfter completing the series of trimming etching cycles, the overlapping portions of the liner oxide material 250, liner nitride material 248, semiconductor material 242, bandgap tunneling oxide material 240, and storage nitride material 238 with the initial vertical memory string structure space 270 can be removed by one or more additional material removal processes to form the vertical memory string structure 272. Figure 2P ) and vertical memory string structure space 274 ( Figure 2P The following section describes in further detail the achievement. Figure 2P Such material removal processes are used to configure the microelectronic device structure 100 depicted in the diagram.

[0103] After completing the series of trimming etch cycles, portions of the lining oxide material 250 exposed by the trimming etch cycles can be removed (e.g., via a wet etching process). Figure 2M (As described). Removal of a portion of the lining oxide material 250 can be performed via a preliminary vertical memory string structure space 270, thereby altering the depth of the preliminary vertical memory string structure space 270 (e.g., in a horizontal direction perpendicular to the long edge of the corresponding rib region 110). The removal process can expose the underlying portion of the lining nitride material 248.

[0104] After removing a portion of the liner oxide material 250, the exposed portion of the liner nitride material 248 can be removed by an additional material removal process (e.g., an additional wet etching operation). Alternatively, along with the removal of the portion of the liner oxide material 250, a portion of the liner nitride material 248 can be removed (e.g., using a single processing operation). The removal of the exposed portion of the liner nitride material 248 can be performed through the initial vertical memory string structure space 270, thereby further altering the depth of the initial vertical memory string structure space 270 (e.g., in a horizontal direction perpendicular to the long edge of the corresponding rib region 110). The removal process can expose the underlying portion of the semiconductor material 242.

[0105] After removing the portion of the liner nitride material 248 that overlaps with the initial vertical memory string structure space 270, the exposed portion of the semiconductor material 242 can be removed by an additional material removal process (e.g., an additional wet etching operation). Alternatively, a portion of the semiconductor material 242 can be removed along with one or more of the liner nitride material 248 and the liner oxide material 250 (e.g., using a single processing operation). The removal of the semiconductor material 242 can be performed through the initial vertical memory string structure space 270, thereby further altering the depth of the initial vertical memory string structure space 270 (e.g., in the horizontal direction perpendicular to the long edge of the corresponding rib region 110).

[0106] After removing the portion of the semiconductor material 242 that overlaps with the initial vertical memory string structure space 270, a portion of the band engineering tunnel oxide material 240 can be removed by an additional material removal process (e.g., an additional wet etching operation). Alternatively, a portion of the band engineering tunnel oxide material 240 can be removed (e.g., using a single processing operation) along with the removal of one or more of the doped polysilicon material 242, the liner nitride material 248, and the liner oxide material 250. The removal of the band engineering tunnel oxide material 240 can be performed within the initial vertical memory string structure space 270, thereby further altering the depth of the initial vertical memory string structure space 270 (e.g., in the horizontal direction perpendicular to the long edge of the corresponding rib region 110).

[0107] After removing the portion of the band tunneling oxide material 240 that overlaps with the initial vertical memory string structure space 270, a portion of the storage nitride material 238 can be removed by an additional material removal process (e.g., an additional wet etching operation). Alternatively, a portion of the storage nitride material 238 can be removed (e.g., using a single processing operation) along with the removal of one or more of the band tunneling oxide material 240, semiconductor material 242, liner nitride material 248, and liner oxide material 250. The removal of the storage nitride material 238 can be performed within the initial vertical memory string structure space 270, thereby further altering the depth of the initial vertical memory string structure space 270 (e.g., in the horizontal direction perpendicular to the long edge of the corresponding rib region 110).

[0108] After removing the portion of the storage nitride material 238 that overlaps with the initial vertical memory string structure space 270, a portion of the barrier oxide material 236 may be exposed by the initial vertical memory string structure space 270. The initial vertical memory string structure space 270 may have a depth extending at least to the band engineering tunnel oxide material 240 (e.g., at least to the storage nitride material 240, or at least to the barrier oxide material 236) (e.g., in a horizontal direction perpendicular to the long edge of the corresponding rib region 110).

[0109] With the removal of the portions of the lining oxide material 250, the lining nitride material 248, the semiconductor material 242, the bandgap tunnel oxide material 240, and / or the storage nitride material 238 that overlap with the initial vertical memory string structure space 270, the mask oxide material 262 can be removed from the initial vertical memory string structure 268. Figure 2O ), mask material 254 ( Figure 2J ), Lining oxide material 250 ( Figure 2C ) and lining nitride material 248 ( Figure 2CThe portion of the semiconductor material 242 is exposed. During this removal process, the mask oxide material 262 can suppress (e.g., delay, slow down, prevent) the removal of the mask oxide material 262 overlapping with the initial vertical memory string structure 268 and the material below the mask oxide material 262 (e.g., mask material 254, liner oxide material 250, liner nitride material 248). Therefore, compared to the removal rate of the liner oxide material 250, liner nitride material 248, semiconductor material 242, band engineering tunnel oxide material 240 and / or storage nitride material 238 overlapping with the initial vertical memory string structure space 270, the removal of the mask oxide material 262 overlapping with the initial vertical memory string structure 268 and the material below the mask oxide material 262 can be performed at a slower removal rate.

[0110] like Figure 2P As shown in the image, this serves as a collective reference. Figure 2O and 2P As a result of the aforementioned material removal process, the vertical memory string structure 272 can be derived from the initial vertical memory string structure 268 ( Figure 2O The vertical memory string structure space 274 can be formed from the initial vertical memory string structure space 270. Figure 2O )form.

[0111] The horizontal pitch between the corresponding horizontal centers of adjacent individual vertical memory string structures 272 can be in the range of about 20 nm to about 175 nm, for example, from about 50 nm to about 130 nm, from about 70 nm to about 115 nm or about 90 nm.

[0112] As a result of the material removal process (e.g., wet etching process) used to form the vertical memory string structure 272 and the vertical memory string structure space 274, the vertical memory string structure space 274 may be individually larger than the corresponding initial vertical memory string structure space 270. Figure 2O The vertical memory string structure 274 is relatively wider (e.g., in the horizontal direction along the long edge of the corresponding rib region 110). For example, the width of an individual vertical memory string structure space 274 (e.g., in the horizontal direction along the long edge of the corresponding rib region 110) can be in the range of about 30 nm to about 80 nm, for example, about 55 nm. In addition, the vertical memory string structure 272 can be individually wider than the corresponding initial vertical memory string structure 268 ( Figure 2O The width of an individual vertical memory string structure 272 (e.g., in the horizontal direction along the long edge of the corresponding rib 110) can be in the range of about 20 nm to about 50 nm, for example, about 35 nm.

[0113] Figure 2Q and2R In previous reference Figure 2P A simplified perspective view of a portion of the microelectronic device structure 100 after the described processing stage. Figure 2R Is Figure 2Q Part B of the microelectronic device structure 100 depicting the processing stage. Figure 2Q A simplified, partial perspective cross-sectional view (drawn using dashed lines).

[0114] refer to Figure 2Q After forming the vertical memory string structure 272 and the vertical memory string structure space 274, the covering material 260 can be removed. Figure 2I (e.g., by an etching process). The cover material 260 can be substantially completely removed from above (e.g., in the Z direction) the top dielectric material 220, the barrier oxide material 236, the storage nitride material 238, the band engineering tunnel oxide material 240, and the semiconductor material 242.

[0115] Still referencing Figure 2Q A top plug 286 can be formed to contact the upper portion of the vertical memory string structure 272. The top plug 286 can be formed in a recess in the substrate structure 104 before forming the semiconductor material 285, as described below. The top plug 286 can be patterned using conventional photolithography techniques to form corresponding cavities for the top plug 286, and then the semiconductor material is formed within the top plug cavity. In some embodiments, the top plug 286 is formed of polysilicon doped (e.g., lightly doped) with one or more conductivity-enhancing materials, such as N-type polysilicon (e.g., polysilicon doped with one or more N-type conductivity-enhancing materials, such as arsenic, phosphorus, and antimony, or more). Figure 2Q As shown, individual top plugs 286 can contact (e.g., physically or electrically) multiple (e.g., several) horizontally adjacent vertical memory string structures 272. In some embodiments, individual top plugs 286 contact four (4) vertical memory string structures 272 within individual rib regions 110 of the profile slot 106. Top plugs 286 can be used as drain-side contact structures for the vertical memory string structures 272.

[0116] After forming the top plug 286, at least one trench 276 (e.g., slot, slit, opening) may be formed to extend vertically through the initial stack structure 102. The trench 276 may be formed by removing a portion of the initial stack structure 102 (including the layer 206 containing the insulating material 202 and its sacrificial material 204). The trench 276 may be horizontally offset from the profile slot 106 (e.g., in the Y direction) and may extend horizontally substantially parallel to the main section 108 of the profile slot 106. The trench 276 may have an elongated horizontal cross-sectional shape (e.g., including a dimension in the X direction greater than the dimension in the Y direction). Additionally, the trench 276 may further extend vertically (e.g., in the Z direction) through at least a portion of the upper base structure material 222 and the intermediate base structure material 224 of the base structure 104. In some embodiments, the trench 276 extends vertically downward (e.g., in the Z direction) through the lower base structure material 226. In some embodiments, the trench 276 extends vertically downwards to or beyond the substrate dielectric material 228.

[0117] After trench 276 is formed, the intermediate base structure material 224 of base structure 104 can be removed (e.g., excavated). Figure 2P At least a portion thereof is formed to extend from the level of the groove 276 (e.g., in the Y direction) to the bottom plug 246. Figure 2P The notch is formed. Subsequently, portions of the barrier oxide material 236, storage nitride material 238, and band engineering tunnel oxide material 240 at the vertical height of the notch and horizontally surrounding the semiconductor material 242 of the bottom plug 246 can be removed to expose the semiconductor material 242. (As shown) Figure 2Q As shown, individual bottom plugs 246 may contact (e.g., physically or electrically) multiple (e.g., several) horizontally adjacent vertical memory string structures 272. In some embodiments, individual bottom plugs 246 contact four (4) vertical memory string structures 272 within individual rib regions 110 of the profile slot 106. The bottom plugs 246 may be used as source contact structures for the vertical memory string structures 272.

[0118] After the bottom plug 246 is exposed, the notch in the substrate structure 104 can be backfilled with semiconductor material 285 through trench 276. Semiconductor material 285 may contact semiconductor material 242 of the bottom plug 246. Semiconductor material 285 may have substantially the same material composition as semiconductor material 242, or may have a different material composition. In some embodiments, semiconductor material 285 is formed of and contains doped polysilicon, such as n-type polysilicon (e.g., polysilicon doped with one or more n-type conductivity-enhancing materials, such as one or more of arsenic, phosphorus, and antimony).

[0119] After the semiconductor material 285 is formed, a portion of the semiconductor material 285 within the trench 276 can be removed (e.g., by isotropic etching), and a trench oxide material 288 can be formed at the bottom portion of the trench 276. The trench oxide material 288 can cover the surface of the substrate structure 104 exposed at the bottom of the trench 276. For example, the trench oxide material 288 can be formed on or above the surfaces of the upper substrate structure material 222, the semiconductor material 285, and the lower substrate structure material 226.

[0120] After forming the contacts between the top plug 286, the trench oxide material 288, and the bottom plug 246 and the semiconductor material 285, the microelectronic device structure 100 can be subjected to a replacement gate process. The replacement gate process can at least partially (e.g., substantially) replace the sacrificial material 204 of the layer 206 of the initial stacked structure 102 with conductive material 280. By doing so, the replacement gate process can transform the initial stacked structure 102 into a stacked structure 210. The stacked structure 210 may include a vertically alternating (e.g., in the Z direction) sequence of insulating material 202 and conductive material 280 arranged as layer 278. During the replacement gate process, the trench oxide material 288 can protect portions of the substrate structure 104 in the horizontal region of the trench 276 from removal.

[0121] The conductive material 280 of layer 278 of the stacked structure 210 may be formed from and comprise one or more of the following: at least one metal, at least one alloy, at least one conductive metal material (e.g., at least one conductive metal nitride, at least one conductive metal silicide, at least one conductive metal carbide, at least one conductive metal oxide), and at least one conductive doped semiconductor material (e.g., conductive doped polysilicon). In some embodiments, the conductive material 280 is formed from and comprises W. Optionally, at least one lining material (e.g., at least one insulating lining material, at least one conductive lining material) may be formed around the conductive material 280. The lining material may be formed from and comprise one or more of the following, for example: metals (e.g., titanium, tantalum), alloys, metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), and metal oxides (e.g., aluminum oxide). In some embodiments, the lining material comprises at least one conductive material used as a seed material for forming the conductive material 280. In some embodiments, the lining material comprises titanium nitride (TiN). x (e.g., TiN). In a further embodiment, the gate replacement process further includes forming a dielectric liner, such as depositing aluminum oxide (AlO2). x (e.g., Al2O3). As a non-limiting example, for each of the layers 278 of the stacked structure 210, AlO3... x (For example, Al2O3) can be formed directly adjacent to the insulating material 2O2, TiNx (For example, TiN) can be directly adjacent to AlO x Formation, and W can be directly adjacent to TiN x Formation. For clarity and ease of understanding of this description, Figure 2Q and 2R The lining material is not specified, but it will be understood that the lining material may be placed around the conductive material 280.

[0122] Collective Reference Figure 2P and 2Q The replacement gate processing used to form the stacked structure 210 may include treating the microelectronic device structure 100 with at least one wet etchant, said wet etchant being formulated to selectively remove portions of the sacrificial material 204 of the layer 206 of the initial stacked structure 102 through trench 276. The wet etchant may be selected to remove portions of the sacrificial material 204 without substantially removing portions of the insulating material 202 of the layer 206 of the initial stacked structure 102, and without substantially removing the barrier oxide material 236, liner oxide material 250, and cover material 260. Figure 2I The sacrificial material 204 comprises a portion of the trench oxide material 288. The sacrificial material 204 includes a dielectric nitride material (e.g., SiN). y The insulating material 202 includes dielectric oxide materials (e.g., Si3N4) and the insulating material 202 includes dielectric oxide materials (e.g., SiO2). x In some embodiments, such as SiO2, a wet etchant including H3PO4 can be used to selectively remove sacrificial material 204 of layer 206 of the initial stacked structure 102. After selectively removing portions of the sacrificial material 204, the resulting notches can be filled with conductive material 280 to form a stacked structure 210 (including its layers 278). Thereafter, the conductive material 280 can be isotropically recessed to provide electrical separation between layers 278. After forming the stacked structure 210, trenches 276 can be filled with dielectric material, thereby forming a trench-filled structure (see below). Figure 3 (To be described in further detail).

[0123] In an alternative embodiment, the initial stack structure 102 is initially formed by a vertically alternating (e.g., in the Z direction) sequence of insulating material 202 and conductive material 280 arranged as layer 278, rather than by a sequence of insulating material 202 and sacrificial material 204 arranged as layer 206 as described above. The layers 278 of the initial stack structure 102 may individually comprise vertically adjacent (e.g., directly vertically adjacent in the Z direction) conductive material 280 and insulating material 202. In this embodiment, no subsequent gate replacement processing is performed.

[0124] refer to Figure 2QAlternating layers 278 of insulating material 202 and conductive material 280 vertically cover the bottom plug 246. The stack structure 210 includes a vertical memory string region 282, which contains vertical memory cells 284 located at the intersection of the vertical memory string structure 272 and the conductive material 280 of the layer 278. Some of the conductive material 280 may be used as the access line structure (e.g., word line structure) of the vertical memory cells 284. One or more of the layers 278 near the bottom plug 246 (e.g., in the Z direction) may be used as select gate source (SGS) structures, and one or more of the layers 278 near the top plug 286 (e.g., in the Z direction) may be used as select gate drain (SGD) structures.

[0125] Therefore, according to embodiments of this disclosure, a method of forming a microelectronic device includes: forming a preliminary stacked structure having layers over a substrate structure, each layer of the preliminary stacked structure comprising a sacrificial material and an insulating material vertically adjacent to the sacrificial material; forming a slot extending vertically through the preliminary stacked structure, having a first region and a second region; forming memory cell material within the slot; forming a mask material within the slot and over the memory cell material; forming a trimming material within the slot and over the mask material; removing a portion of the trimming material within the first region of the slot; removing portions of the trimming material, the mask material, and the memory cell material within the second region of the slot structure to form a memory string structure; and replacing the sacrificial material of the layers of the preliminary stacked structure with a conductive material after forming the memory string structure. The first region extends horizontally in a first direction. The second region intersects the first region and extends horizontally in at least one second direction at an angle relative to the first direction. The memory string structures extend vertically through the preliminary stacked structure and are horizontally separated from each other in the at least two second directions.

[0126] According to other embodiments of this disclosure, a microelectronic device includes a stacked structure and a substrate structure vertically resting on the stacked structure. The stacked structure has layers, each layer comprising vertically adjacent conductive and insulating materials. The stacked structure is divided into blocks extending horizontally in a first direction. The blocks are separated from each other by insulating slot structures in a second direction. The second direction is orthogonal to the first direction. At least one of the blocks has a slot extending vertically through all the layers and a memory string structure. The slot includes a first region and a second region intersecting the first region. The first region extends horizontally in the first direction. The second region extends horizontally upward in at least one third direction. The third third direction is angled relative to the first and second directions. The memory string structure extends vertically through the stacked structure within the horizontal region of the second region of the slot. The memory string structures are horizontally separated from each other in the at least one third direction. The substrate structure includes a plug structure and additional conductive material. The plug structure is within the horizontal region of the second region of the slot of the at least one of the blocks. The plug structure contacts the memory string structure of the at least one of the blocks. The additional conductive material contacts the side surface of the plug structure.

[0127] According to another embodiment of this disclosure, a memory device has a stacked structure and a substrate structure vertically located below the stacked structure. The stacked structure includes blocks extending parallel in a first horizontal direction. Each block individually includes layers. Each layer has a conductive material and an insulating material vertically adjacent to the conductive material. Each block individually includes at least partially filled slots and vertically extending strings of memory cells. The at least partially filled slots extend vertically through the layers. The at least partially filled slots have a trunk region and rib regions. The trunk region extends substantially linearly in the first horizontal direction. The rib regions intersect the trunk region. The rib regions individually extend substantially linearly in at least one second horizontal direction at an angle relative to the first horizontal direction. The vertically extending strings of memory cells are located in the horizontal region of the rib regions of the at least partially filled slots. The substrate structure includes a plug structure and a laterally extending conductive structure. The plug structure is electrically connected to the vertically extending strings of memory cells. The laterally extending conductive structure contacts the sidewalls of the plug structure.

[0128] Figure 3 It is for reference Figure 2R and 2Q A simplified, partial top view of the microelectronic device structure 100 after the described processing stage. (See attached image.) Figure 2RAs depicted, the microelectronic device structure 100 includes a vertical memory string structure 272 located within a rib region 110 of a contour slot 106, wherein the vertical memory string structure 272 is horizontally adjacent to the stacked structure 210 and partially defines the sidewall of the rib region 110. Figure 3 The diagram also shows that the top plug 286 and the bottom plug 246 are vertically offset from the vertical memory string structure 272 (e.g., vertically located above and below the vertical memory string structure 272, respectively) and electrically connected to the vertical memory string structure 272.

[0129] like Figure 3 The diagram also shows that the microelectronic device structure 100 includes a filled trench structure 302, which is achieved by filling the stacked structure 210 in the microelectronic device structure 100 with a dielectric material (e.g., a dielectric oxide material, such as silicon oxide). Figure 2Q Groove 276 in ) Figure 2Q The filled groove structure 302 may extend horizontally (e.g., in the X direction) substantially parallel to the main region 108 of the profile slot 106. Additionally, the filled groove structure 302 may have a horizontal length (e.g., in the X direction) substantially equivalent to the horizontal length (e.g., in the X direction) of the main region 108 of the profile slot 106.

[0130] like Figure 3 As shown, each rib region 110 of the profile slot 106 is horizontally interposed (e.g., in the X direction) between two horizontally adjacent portions of the stacked structure 210. The horizontal dimensions of the individual rib regions 110 of the profile slot 106 can be selected to promote sufficient structural stability of the stacked structure 210, as previously referenced herein. Figure 1 and Figures 2A to 2R The shape and configuration are essentially maintained during the described processing stages. Preliminary stacked structure 102 ( Figure 2P ) and stacked structure 210 ( Figure 2R The configuration of portions between individual rib zones 110 can prevent (e.g., substantially prevent) the initial stacked structure 102. Figure 2P ) and stacked structure 210 ( Figure 2R The collapse of part of it.

[0131] As mentioned above Figure 2J to 2O As described, the trimming etching cycle can start from the end of the individual rib region 110 closest to the main region 108 of the contour slot 106, and can proceed away from the main region 108 of the contour slot 106. Figure 3 Describe the general horizontal direction 304 that subsequent trimming etch cycles may follow (e.g., extending to the opposite side away from the main trunk 108).

[0132] The stacked structure 210 of the microelectronic device structure 100 can be divided (e.g., segmented, partitioned) into blocks 306 that are separated from each other (e.g., in the Y direction) by the filled trench structure 302. Alternatively, the stacked structure 210 of the microelectronic device structure 100 can be divided into electrically separated blocks (e.g., the size of the blocks is as follows) by the filled trench structure 302 and the trunk region 108. Figure 3 (Approximately half the size of block 306 shown in the diagram). The filled trench structure 302 can extend individually and completely vertically (e.g., in the Z direction) through the stacked structure 210.

[0133] At least some of the blocks 306 of the stacked structure 210 may extend horizontally, substantially parallel to each other, in the X direction. Each of the blocks 306 of the stacked structure 210 may exhibit substantially the same geometric configuration as each of the other blocks 306 (e.g., substantially the same size and substantially the same shape), or one or more of the blocks 306 may exhibit a different geometric configuration than one or more of the other blocks 306 (e.g., one or more different sizes and / or different shapes). Additionally, each pair of horizontally adjacent blocks 306 of the stacked structure 210 may be horizontally separated from each other by a distance substantially the same as that of each other pair of horizontally adjacent blocks 306 of the stacked structure 210 (e.g., corresponding to the width of the individual filled trench structure 302 in the Y direction), or at least one pair of horizontally adjacent blocks 306 of the stacked structure 210 may be horizontally separated from each other by a distance different from the separation distance of at least one other pair of horizontally adjacent blocks 306 of the stacked structure 210. In some embodiments, the blocks 306 of the initial stacked structure 102 are sized, shaped and spaced relative to each other in a substantially uniform manner (e.g., substantially unchanged, substantially equal, substantially consistent).

[0134] Block 306 can be further subdivided into sub-blocks 308, each sub-block 308 being defined by the horizontal outline of a corresponding rib 110. Thus, sub-blocks 308 can be included in a vertical memory string structure 272 on the two (2) opposite sidewalls 208 of the stacked structure 210, which is partially defined by the individual ribs 110 in the stacked structure 210.

[0135] Although Figure 1 , 2A Figures 2R and 3 depict the configuration of the contour slot 106 according to an embodiment of the present disclosure; however, in additional embodiments, the microelectronic device structure 100 may be formed to have different contour slot configurations. Reference is made below. Figures 4 to 7 Non-limiting examples of such different profile slot configurations are described in further detail. For example... Figures 4 to 8As shown, microelectronic device structures 400, 500, 600, 700, and 800 can be formed to have contour slots 406, 506, 606, 706, and 806, respectively, each of which has a horizontal profile different from the horizontal profile of the contour slot 106 of the microelectronic device structure 100 (e.g., as viewed from a top view). Microelectronic device structures 400, 500, 600, 700, and 800 can have different contour slots 406, 506, 606, 706, and 806, respectively, and microelectronic device structures 400, 500, 600, 700, and 800 can withstand the same conditions as previously referenced. Figures 2A to 2R The processing stages described are similar to those processing stages used to form the desired microelectronic device of this disclosure.

[0136] refer to Figure 4 The initial stacking structure 402 (for example, corresponding to the initial stacking structure 102) Figure 1 and 2A The 2P) can be formed to have a contoured slot 406, the contoured slot 406 including a first region 408 extending in a first horizontal direction (e.g., the X direction) and a second region 410 intersecting the first region 408 and extending parallel to it in a second horizontal direction at an angle relative to the first horizontal direction. The first region 408 may have the same shape as described above. Figure 1 , 2A The second region 410 has a similar function to the main region 108 of the profiled slot 106 described in 2R and 3; and can exhibit a single, elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape). The second region 410 may have the same function as the previously referenced... Figure 1 , 2A It has a similar function to the rib region 110 of the contour slot 106 described in 2R and 3, and can individually exhibit a single, elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape) that partially overlaps with the first region 408.

[0137] To form the profile slot 406, a second region 410 may be formed in the initial stacked structure 402 (e.g., by a material removal process, such as an etching process), and then a first region 408 may be formed in the initial stacked structure 402 (e.g., by an additional material removal process, such as an additional etching process). The first region 408 may be formed after the formation of the second region 410 (e.g., following the formation of the second region 410). After the profile slot 406 is formed, the microelectronic device structure 400 may be subjected to the same conditions as previously referenced for the microelectronic device structure 100. Figures 2A to 2R The described additional processing is similar to the additional processing described above. The subsequent trimming etch cycle employed during the additional processing (e.g., as in the previous reference) Figure 2J to 2O The trimming etch cycles described are similar and can follow a generally horizontal direction 412 away from the first zone 408.

[0138] refer to Figure 5 The initial stacked structure 502 (for example, corresponding to the initial stacked structure 102) Figure 1 and 2A The 2P) can be formed by creating a plurality of profile slots 506, each individually comprising a first region 508 and a second region 510 intersecting the first region 508. The first regions 508 of the plurality of profile slots 506 can be separated from each other, can be formed in a row extending in a first horizontal direction (e.g., the X direction), and can be substantially aligned with each other in a second horizontal direction orthogonal to the first horizontal direction (e.g., the Y direction). The second regions 510 of the plurality of profile slots 506 can be separated from each other and can extend parallel to each other in a third horizontal direction angled relative to the first and second horizontal directions. The first region 508 of the individual profile slots 506 can have a shape similar to that of the previously referenced... Figure 1 , 2A The main region 108 of the profile slot 106 described in 2R and 3 has a similar function to that of the main region 108; and can exhibit the desired horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape, a square horizontal cross-sectional shape, a circular horizontal cross-sectional shape). The second region 510 of the individual profile slot 506 may have the same function as described in the previous references. Figure 1 , 2A The rib region 110 of the contoured slot 106 described in 2R and 3 has a similar function and can exhibit a single, elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape) that partially overlaps horizontally with the first region 508.

[0139] To form the profile slot 506, a second region 510 may be formed in the initial stacked structure 502 (e.g., by a material removal process, such as an etching process), and then a first region 508 may be formed in the initial stacked structure 502 (e.g., by an additional material removal process, such as an additional etching process). The first region 508 may be formed after the formation of the second region 510 (e.g., following the formation of the second region 510). After the profile slot 506 is formed, the microelectronic device structure 500 may be subjected to the same conditions as previously referenced for the microelectronic device structure 100. Figures 2A to 2R The described additional processing is essentially similar to the previous additional processing. The subsequent trimming etching cycle employed during the additional processing (e.g., similar to the previous reference) Figure 2J to 2O The trimming etch cycles described are similar and can follow a generally horizontal direction 512 away from the corresponding first zone 508.

[0140] refer to Figure 6 The initial stacking structure 602 (for example, corresponding to the initial stacking structure 102) Figure 1 and 2AThe 2P) can be formed by creating a plurality of contour slots 606, each individually comprising a first region 608 and a second region 610 intersecting the first region 608. The first regions 608 of the plurality of contour slots 606 can be separated from each other and can form multiple rows of first regions 608 extending individually in a first horizontal direction (e.g., the X direction). The first regions 608 within individual rows can be substantially aligned with each other in a second horizontal direction (e.g., the Y direction) orthogonal to the first horizontal direction. The first regions 608 within different rows can be horizontally offset from each other in the second horizontal direction. The second regions 610 of the plurality of contour slots 606 can be separated from each other and can extend parallel to each other in a third horizontal direction angled relative to the first and second horizontal directions. Contour slots 606 adjacent to each other in the first horizontal direction can be partially offset from each other in the third horizontal direction. For example, the second regions 610 of two (2) contour slots 606 adjacent to each other in the first horizontal direction may partially overlap each other in the third horizontal direction; and the first regions 608 of the two (2) contour slots 606 may be completely offset from each other in the third horizontal direction. Figure 6 As shown, some profile slots 606 are substantially aligned with each other in a third horizontal direction, such that some profile slots 606 extend in series with each other in the third horizontal direction. A portion of the initial stacked structure 602 is situated between some profile slots 606 that are substantially aligned with each other in the third horizontal direction.

[0141] The first region 608 of the individual profile slot 606 may have the same characteristics as the previously referenced region. Figure 1 , 2A The main region 108 of the profile slot 106 described in 2R and 3 has a similar function to that of the main region 108; and can exhibit the desired horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape, a square horizontal cross-sectional shape, a circular horizontal cross-sectional shape). The second region 610 of the individual profile slot 606 may have the same function as described in the previous references. Figure 1 , 2A The rib region 110 of the contoured slot 106 described in 2R and 3 has a similar function and can exhibit a single, elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape) that partially overlaps with the first region 608.

[0142] To form the profile slot 606, a second region 610 may be formed in the initial stacked structure 602 (e.g., by a material removal process, such as an etching process), and then a first region 608 may be formed in the initial stacked structure 602 (e.g., by an additional material removal process, such as an additional etching process). The first region 608 may be formed after the formation of the second region 610 (e.g., following the formation of the second region 610). After the profile slot 606 is formed, the microelectronic device structure 600 may be subjected to the same conditions as previously referenced for the microelectronic device structure 100. Figures 2A to 2RThe described additional processing is essentially similar to the previous additional processing. The subsequent trimming etching cycle employed during the additional processing (e.g., similar to the previous reference) Figure 2J to 2O The trimming etch cycles described are similar and can follow a generally horizontal direction 612 away from the corresponding first region 608.

[0143] refer to Figure 7 The initial stacked structure 702 (for example, corresponding to the initial stacked structure 102) Figure 1 and 2A The 2P) can be formed by creating a plurality of contour slots 706, each individually comprising a first region 708 and a second region 710 intersecting the first region 708. The first regions 708 of the plurality of contour slots 706 can be separated from each other and can form multiple rows of first regions 708 extending individually in a first horizontal direction (e.g., the X direction). The first regions 708 within individual rows can be substantially aligned with each other in a second horizontal direction (e.g., the Y direction) orthogonal to the first horizontal direction. The first regions 708 within different rows can be horizontally offset from each other in the second horizontal direction. The second regions 710 of the plurality of contour slots 706 can be separated from each other and can extend parallel to each other in a third horizontal direction angled relative to the first and second horizontal directions. Contour slots 706 adjacent to each other in the first horizontal direction can be partially offset from each other in the third horizontal direction. For example, the second regions 710 of two (2) contour slots 706 adjacent to each other in the first horizontal direction may partially overlap each other in the third horizontal direction; and the first regions 708 of the two (2) contour slots 706 may be completely offset from each other in the third horizontal direction. Figure 7 As shown, some profile slots 706 are substantially aligned with each other in a third horizontal direction, such that some profile slots 706 extend in series with each other in the third horizontal direction. A portion of the initial stacked structure 702 is situated between some profile slots 706 that are substantially aligned with each other in the third horizontal direction.

[0144] The first region 708 of the individual profile slot 706 may have the same characteristics as the previously referenced region. Figure 1 , 2A The main region 108 of the profile slot 106 described in 2R and 3 has a similar function to that of the main region 108; and can exhibit the desired horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape, a square horizontal cross-sectional shape, a circular horizontal cross-sectional shape). The second region 710 of the individual profile slot 706 may have the same function as described in the previous references. Figure 1 , 2A The rib region 110 of the contoured slot 106 described in 2R and 3 has a similar function and can exhibit a single, elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape) that partially overlaps with the first region 708.

[0145] To form the profile slot 706, its first region 608 and second region 610 can be formed in the initial stacked structure 602 substantially at the same time (e.g., substantially simultaneously). After the profile slot 706 is formed, the microelectronic device structure 700 can be subjected to the same conditions as previously referenced for the microelectronic device structure 100. Figures 2A to 2R The described additional processing is essentially similar to the previous additional processing. The subsequent trimming etching cycle employed during the additional processing (e.g., similar to the previous reference) Figure 2J to 2O The trimming etch cycles described are similar and can follow a generally horizontal direction 712 away from the corresponding first zone 708.

[0146] refer to Figure 8 The initial stacked structure 802 (for example, corresponding to the initial stacked structure 102) Figure 1 and 2A The 2P)) can be formed to have a profile slot 806, the profile slot 806 comprising: a plurality of first regions 808 extending parallel to a first horizontal direction (e.g., the X direction) and offset from each other in a second horizontal direction orthogonal to the first horizontal direction (e.g., the Y direction); and a plurality of second regions 810 intersecting the first regions 808 and extending parallel to each other in a third horizontal direction at an angle relative to the first and second horizontal directions. The first regions 808 may individually be offset from the midpoint of the profile slot 806 in the third horizontal direction. For example, two (2) first regions 808 may be positioned along the profile slot 806 in the third horizontal direction at approximately one-quarter and approximately three-quarters of the length positions, respectively. The first regions 808 of the profile slot 806 may individually have a previously referenced Figure 1 , 2A The main region 108 of the profile slot 106 described in 2R and 3 has a similar function to that of the main region 108; and may individually exhibit an elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape). The second region 810 of the profile slot 806 may have the same function as described in the previous references. Figure 1 , 2A The rib region 110 of the contoured slot 106 described in 2R and 3 has a similar function and can individually exhibit an elongated horizontal cross-sectional shape (e.g., a rectangular horizontal cross-sectional shape) that horizontally overlaps with each of the first regions 808.

[0147] To form the profile slot 806, a second region 810 may be formed in the initial stacked structure 802 (e.g., by a material removal process, such as an etching process), and then a first region 808 may be formed in the initial stacked structure 802 (e.g., by an additional material removal process, such as an additional etching process). The first region 808 may be formed after the formation of the second region 810 (e.g., following the formation of the second region 810). In an additional embodiment, the first region 808 and the second region 810 are formed substantially simultaneously with each other to form the profile slot 806. After the profile slot 806 is formed, the microelectronic device structure 800 may be subjected to the same conditions as previously referenced for the microelectronic device structure 100. Figures 2A to 2R The described additional processing is essentially similar to the previous additional processing. The subsequent trimming etching cycle employed during the additional processing (e.g., similar to the previous reference) Figure 2J to 2O The trimming etch cycles described are similar and can follow a generally horizontal direction 812 away from the corresponding first region 808.

[0148] Microelectronic device structures according to embodiments of the present disclosure (e.g., previously referenced) Figures 1 to 8 The microelectronic device structures (100, 400, 500, 600, 700, 800) described in one or more of the present disclosure can be used in embodiments of the electronic systems of this disclosure. For example, Figure 9 This is a block diagram of an illustrative electronic system 900 according to embodiments of the present disclosure. The electronic system 900 may include, for example, a computer or computer hardware component, a server or other network hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities, for example, tablet computers Tablet computers, e-books, navigation devices.

[0149] Electronic system 900 includes at least one memory device 902. Memory device 902 may include, for example, microelectronic device structures previously described herein (e.g., previously referenced...). Figures 1 to 8 The electronic system 900 may further include at least one electronic signal processor device 904 (generally referred to as a “microprocessor”). The electronic signal processor device 904 may optionally include the microelectronic device structures previously described herein (e.g., previously referenced...). Figures 1 to 8 The microelectronic device architectures 100, 400, 500, 600, 700, and 800 are described in one or more of the above. Although the memory device 902 and the electronic signal processor device 904 are in Figure 9While depicted as two (2) separate devices, in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of a memory device 902 and an electronic signal processor device 904 may be included in the electronic system 900. In such embodiments, the memory / processor device may comprise the microelectronic device architecture previously described herein (e.g., previously referenced...). Figures 1 to 8 The electronic system 900 may further include one or more input devices 906 for a user to input information into the electronic system 900, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 900 may further include one or more output devices 908 for outputting information (e.g., visual or audio output) to a user, such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 906 and the output device 908 include a single touchscreen device that can be used to both input information into the electronic system 900 and output visual information to a user. The input device 906 and the output device 908 may be in electrical communication with one or more of the memory device 902 and the electronic signal processor device 904.

[0150] Compared to conventional structures, devices, and methods, the structures, devices, and methods of this disclosure advantageously promote one or more of the following: improved microelectronic device performance, reduced cost (e.g., manufacturing cost, material cost), increased component miniaturization, and greater packaging density. Compared to conventional structures, devices, and methods, the structures, devices, and methods of this disclosure also improve scalability, efficiency, and simplicity.

[0151] Additional, non-limiting examples of embodiments of this disclosure are described below.

[0152] Example 1: A method of forming a microelectronic device, comprising: forming a preliminary stacked structure over a substrate structure, the preliminary stacked structure including layers each comprising a first material and an insulating material vertically adjacent to the first material; forming a slot extending vertically through the preliminary stacked structure and including: a first region extending horizontally in a first direction; and a second region intersecting the first region and extending horizontally in at least one second direction at an angle relative to the first direction; forming memory cell material within the slot; forming a mask material within the slot and over the memory cell material; forming a trimming material within the slot and over the mask material; removing a portion of the trimming material within the first region of the slot; and removing portions of the trimming material, the mask material, and the memory cell material within the second region of the slot to form a memory string structure extending vertically through the preliminary stacked structure and horizontally separated from each other in the at least one second direction.

[0153] Example 2: According to the method of Example 1, removing portions of the trimming material, the mask material, and the memory cell material within the second region of the slot includes individually performing a trimming etch cycle, the trimming etch cycle comprising: removing portions of the trimming material within the second region of the slot to expose portions of the mask material within the second region of the slot; forming a suppressing material from the portions of the mask material within the second region of the slot; removing additional portions of the trimming material adjacent to the suppressing material to expose additional portions of the mask material within the second region of the slot; and removing the additional portions of the mask material.

[0154] Example 3: The method according to Example 2 further includes, after completing the trimming etch cycle, partially removing the portion of the memory cell material that overlaps horizontally with the notch caused by the removal of the additional portion of the mask material.

[0155] Example 4: According to the method of Example 3, partially removing a portion of the memory cell material includes: selectively etching a portion of the semiconductor material of the memory cell material to expose a portion of the oxide material of the memory cell material; selectively etching the exposed portion of the oxide material of the memory cell material to expose a portion of the nitride material of the memory cell material; and selectively etching the exposed portion of the nitride material of the memory cell material to expose an additional portion of the oxide material of the memory cell material.

[0156] Example 5: The method according to Example 4 further includes: forming a dielectric liner material within the slot and over the memory cell material before forming the mask material; and removing portions of the dielectric liner material exposed by removing the additional portions of the mask material before selectively etching the portions of the semiconductor material of the memory cell material.

[0157] Example 6: The method according to any one of Examples 1 to 5, wherein the first material of the layer of the preliminary stacked structure includes a sacrificial material, and the method further includes replacing the sacrificial material of the layer with a conductive material after forming the memory string structure.

[0158] Example 7: The method according to any one of Examples 1 to 5 further includes: forming a plug opening in a horizontal region of the second area of ​​the slot and extending vertically into the substrate structure; and filling the plug opening with the memory cell material before forming the mask material in the slot, wherein a portion of the memory cell material in the slot is continuous with an additional portion of the memory cell material in the plug opening.

[0159] Example 8: The method according to Example 7 further includes: forming the substrate structure to include a sacrificial material vertically inserted between the semiconductor material and an additional semiconductor material; and forming the additional portion of the memory cell material in contact with the sacrificial material of the substrate structure.

[0160] Example 9: The method according to Example 8 further includes: forming an additional slot extending vertically through the initial stacked structure and into the substrate structure, the additional slot exposing a side surface of the sacrificial material of the substrate structure; after forming the additional slot to form a notch that partially exposes the additional portion of the memory cell material filling the plug opening, at least partially removing the sacrificial material of the substrate structure; after forming the notch, extending the notch laterally into the additional portion of the memory cell material to expose a semiconductor material of the additional portion of the memory cell material; and filling the laterally extended notch with a conductive doped semiconductor material.

[0161] Example 10: The method according to any one of Examples 1 to 5 further includes, before removing the trimming material from the portion within the first region of the slot: after forming the trimming material within the slot, filling the remaining portion of the first region of the slot with a sacrificial filler material; forming an additional masking material that extends substantially continuously horizontally over and covers the horizontal region of the initial stacked structure and the slot; forming an opening that extends completely vertically through the additional masking material and is defined within the horizontal boundary of the first region of the slot; and selectively excavating the sacrificial filler material through the opening in the additional masking material.

[0162] Example 11: The method according to any one of Examples 1 to 10 further includes selecting the memory cell material comprising: a first dielectric oxide material substantially covering the sidewalls of the initial stacked structure; a dielectric nitride material substantially covering the first dielectric oxide material; a second dielectric oxide material substantially covering the dielectric nitride material; and a semiconductor material extending substantially covering the second dielectric oxide material.

[0163] Example 12: The method according to any one of Examples 1 to 11 further includes: selecting the mask material comprising polycrystalline silicon; and selecting the trimming material comprising silicon nitride.

[0164] Example 13: A microelectronic device comprising: a stacked structure including layers each comprising vertically adjacent conductive and insulating materials, the stacked structure being divided into blocks extending horizontally in a first direction and separated from each other by insulating slot structures in a second direction orthogonal to the first direction, at least one of the blocks including: a slot extending vertically through all the layers and including: a first region extending horizontally in the first direction; and a second region intersecting the first region and extending horizontally upward at least a third direction at an angle relative to the first and second directions; and a memory string structure extending vertically through the stacked structure and extending into the horizontal region of the second region of the slot, the memory string structures being horizontally separated from each other upward at the at least a third direction.

[0165] Example 14: The microelectronic device according to Example 13, wherein each of the memory string structures comprises: a first dielectric oxide material of a certain volume on the sidewall of the stacked structure that partially defines the slot; a dielectric nitride material of a certain volume on the first dielectric oxide material; a second dielectric oxide material of a certain volume on the dielectric nitride material; and a semiconductor material of a certain volume on the second dielectric oxide material.

[0166] Example 15: The microelectronic device according to Example 14 further includes a substrate structure that lies vertically beneath the stacked structure and includes: a source contact structure that contacts the memory string structure of the at least one of the slots in the block within the horizontal region of the second region of the slot in the block; and additional conductive material that contacts the side surface of the source contact structure.

[0167] Example 16: The microelectronic device according to Example 15, wherein the source contact structure individually includes: an additional volume of the first dielectric oxide material; an additional volume of the dielectric nitride material on the additional volume of the first dielectric oxide material; an additional volume of the second dielectric oxide material on the additional volume of the dielectric nitride material; and an additional volume of the semiconductor material on the additional volume of the second dielectric oxide material, wherein the additional volume of the semiconductor material is continuous with a certain volume of semiconductor material in each of the memory string structures.

[0168] Example 17: A microelectronic device according to Example 16, wherein the additional conductive material of the substrate structure directly and physically contacts the additional volume of the semiconductor material in each of the source contact structures.

[0169] Example 18: The microelectronic device according to Example 17, wherein each of the source contact structures horizontally overlaps and contacts multiple of the memory string structures.

[0170] Example 19: A microelectronic device according to any of Examples 13 to 18, further comprising a drain contact structure, the drain contact structure being located in the horizontal region of the second region of the slot and contacting the memory string structure, the drain contact structure being vertically superimposed on the source contact structure and horizontally overlapping the source contact structure.

[0171] Example 20: A memory device comprising: a stacked structure including: a block extending parallel in a first horizontal direction and individually comprising layers each including a conductive material and an insulating material vertically adjacent to the conductive material, the block individually including: at least partially filled slots extending vertically through the layers and including: a trunk region extending substantially linearly in the first horizontal direction; and rib regions intersecting the trunk region and extending substantially linearly in at least one second horizontal direction at an angle relative to the first horizontal direction; vertically extending strings of memory cells in the horizontal region of the rib regions of the at least partially filled slots; and a substrate structure vertically located below the stacked structure and including: a source contact structure electrically connected to the vertically extending strings of memory cells; and a laterally extending conductive structure contacting a sidewall of the source contact structure.

[0172] While this disclosure is subject to various modifications and alternatives, specific embodiments have been shown by way of example in the accompanying drawings and described in detail herein. However, this disclosure is not limited to the particular forms disclosed. In fact, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims and their legal equivalents. For example, elements and features disclosed in one embodiment of this disclosure may be combined with elements and features disclosed in other embodiments of this disclosure.

Claims

1. A method for forming a microelectronic device, comprising: A preliminary stacked structure is formed on top of a substrate structure, the preliminary stacked structure comprising layers each including a first material and an insulating material vertically adjacent to the first material; Forming a slot that extends vertically through the initial stacked structure and includes the following: The first zone extends horizontally in the first direction; and The second region intersects with the first region and extends horizontally in at least one second direction at an angle relative to the first direction; Memory cell material is formed within the slot; A mask material is formed within the slot and above the memory cell material; A trimming material is formed within the slot and above the mask material; Remove a portion of the trimming material within the first area of ​​the slot; and Remove portions of the trimming material, the mask material, and the memory cell material within the second region of the slot to form a memory string structure that extends vertically through the initial stacking structure and is horizontally separated from each other in at least one second direction.

2. The method of claim 1, wherein removing portions of the trimming material, the mask material, and the memory cell material within the second region of the slot comprises individually performing trimming etch cycles, the trimming etch cycle comprising: Remove a portion of the trimming material within the second area of ​​the slot to expose a portion of the masking material within the second area of ​​the slot; The mask material forms a suppressive material in the second region of the slot; Remove the extra portion of the trimming material adjacent to the suppressing material to expose the extra portion of the masking material within the second region of the slot; and Remove the extra portion of the mask material.

3. The method of claim 2, further comprising, after completing the trimming etch cycle, partially removing the portion of the memory cell material that overlaps horizontally with the notch caused by the removal of the additional portion of the mask material.

4. The method of claim 3, wherein partially removing a portion of the memory cell material comprises: Selectively etch portions of the semiconductor material of the memory cell material to expose portions of the oxide material of the memory cell material; Selectively etch the exposed portion of the oxide material of the memory cell material to expose the portion of the nitride material of the memory cell material; and Selectively etch the exposed portion of the nitride material of the memory cell material to expose portions of additional oxide material of the memory cell material.

5. The method of claim 4, further comprising: Before forming the mask material, a dielectric liner material is formed within the slot and above the memory cell material; and Before selectively etching the portion of the semiconductor material of the memory cell material, the portion of the dielectric liner material exposed by removing the additional portion of the mask material is removed.

6. The method according to any one of claims 1 to 5, wherein the first material of the layer of the preliminary stacked structure comprises a sacrificial material, the method further comprising replacing the sacrificial material of the layer with a conductive material after forming the memory string structure.

7. The method according to any one of claims 1 to 5, further comprising: A plug opening is formed in the horizontal region of the second area of ​​the slot and extends vertically into the base structure; and The plug opening is filled with the memory cell material before the mask material is formed in the slot, wherein the portion of the memory cell material in the slot is continuous with an additional portion of the memory cell material in the plug opening.

8. The method of claim 7, further comprising: The substrate structure is formed to include a sacrificial material vertically inserted between the semiconductor material and an additional semiconductor material; and The additional portion of the memory cell material that forms in contact with the sacrificial material of the substrate structure.

9. The method of claim 8, further comprising: An additional slot is formed that extends vertically through the initial stacked structure and into the substrate structure, the additional slot exposing the side surface of the sacrificial material of the substrate structure; After forming the additional slot to form a notch that partially exposes the additional portion of the memory cell material filling the plug opening, the sacrificial material of the substrate structure is at least partially removed; After forming the notch, the notch is extended laterally into the additional portion of the memory cell material to expose the semiconductor material of the additional portion of the memory cell material; and The laterally extended notch is filled with a conductive doped semiconductor material.

10. The method according to any one of claims 1 to 5, further comprising, before removing the trimming material from the portion within the first region of the slot: After the trimming material is formed in the slot, the remaining portion of the first area of ​​the slot is filled with sacrificial filler material; Additional masking material is formed to extend horizontally and substantially continuously over and cover the horizontal region of the initial stacked structure and the slot; An opening is formed that extends vertically through the additional mask material and is defined within the horizontal boundary of the first area of ​​the slot; and The sacrificial filler material is selectively excavated through the opening in the additional mask material.

11. The method according to any one of claims 1 to 5, further comprising selecting the memory cell material comprising: A first dielectric oxide material, which substantially covers the sidewalls of the initial stacked structure; A dielectric nitride material that substantially covers the first dielectric oxide material; A second dielectric oxide material, which substantially covers the dielectric nitride material; and Semiconductor material, the extension of which substantially covers the second dielectric oxide material.

12. The method according to any one of claims 1 to 5, further comprising: The mask material is selected to include polycrystalline silicon; and The trimming material includes silicon nitride.

13. A microelectronic device comprising: A stacked structure comprising layers, each containing vertically adjacent conductive and insulating materials, the stacked structure being divided into blocks extending horizontally in a first direction and separated from each other by insulating slot structures in a second direction orthogonal to the first direction, at least one of the blocks comprising: A slot, which extends vertically through all said layers and includes: The first region extends horizontally in the first direction; and A second region, which intersects with the first region and extends horizontally upward at least in a third direction at an angle relative to both the first and second directions; and A memory string structure that extends vertically through the stacked structure and into the horizontal region of the second area of ​​the slot, the memory string structures being horizontally separated from each other upwards at least third.

14. The microelectronic device of claim 13, wherein each of the memory string structures comprises: A certain volume of first dielectric oxide material is placed on the sidewall of the stacked structure that partially defines the slot; A certain volume of dielectric nitride material is disposed on the certain volume of the first dielectric oxide material; A certain volume of second dielectric oxide material, disposed on the certain volume of dielectric nitride material; and A semiconductor material of a certain volume, disposed on the second dielectric oxide material of the same certain volume.

15. The microelectronic device of claim 14, further comprising a substrate structure vertically subordinate to the stacked structure and comprising: A source contact structure that contacts the memory string structure of the at least one of the at least one of the slots in the block within the horizontal region of the second area of ​​the slot in the block; and Additional conductive material that contacts the side surface of the source contact structure.

16. The microelectronic device of claim 15, wherein the source contact structure individually comprises: Additional volume of the first dielectric oxide material; The additional volume of the dielectric nitride material, which is on the first dielectric oxide material in the additional volume; The additional volume of the second dielectric oxide material, which is on the additional volume of the dielectric nitride material; and The additional volume of semiconductor material is on the second dielectric oxide material of the additional volume, and the additional volume of semiconductor material is continuous with the certain volume of semiconductor material of each of the memory string structures.

17. The microelectronic device of claim 16, wherein the additional conductive material of the substrate structure directly and physically contacts the additional volume of the semiconductor material of each of the source contact structures.

18. The microelectronic device of claim 17, wherein each of the source contact structures horizontally overlaps and contacts multiple of the memory string structures.

19. The microelectronic device according to any one of claims 13 to 18, further comprising a drain contact structure in the horizontal region of the second region of the slot and contacting the memory string structure, the drain contact structure vertically overlying the source contact structure and horizontally overlapping the source contact structure.

20. A memory device comprising: The stacked structure includes: A block, extending parallel in a first horizontal direction and individually comprising layers each including a conductive material and an insulating material vertically adjacent to the conductive material, the block individually comprising: A slot that is at least partially filled, extending vertically through the layer and comprising: The main trunk area extends substantially linearly in the first horizontal direction; and Rib regions intersect with the main trunk region and extend substantially linearly in at least one second horizontal direction at an angle relative to the first horizontal direction. A vertically extending string of memory cells within the horizontal region of the rib area of ​​the at least partially filled slot; and A base structure, which is vertically located below the stacked structure and includes: A source contact structure, which is electrically connected in series with the vertically extending memory cell; and A laterally extending conductive structure contacts the sidewall of the source contact structure.

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