Active clamping circuit and semiconductor device

Abstract

This active clamp circuit is provided with: a clamp voltage control switch (20), the first main electrode of which is electrically connected to the main electrode of a main switch (Q1) and the second main electrode of which is electrically connected to the control electrode of the main switch (Q1); and a clamp voltage determination unit (30), one terminal of which is electrically connected to the first main electrode of the clamp voltage control switch (20) and the other terminal of which is electrically connected to the control electrode of the clamp voltage control switch (20), the clamp voltage determination unit (30) comprising: a diode unit (36) in which a plurality of groups (31) are connected in series; the group 31 is connected in series with a Zener diode 33 and a diode 34 with opposite polarities; and a temperature characteristic adjustment resistor 35 connected in series with the diode section 36. According to the active clamping circuit of the invention, the surge voltage can be absorbed and the voltage can be clamped without using a large-scale diode, and the operation of a switching circuit can be more stable.

Description

Technical Field

[0001] This invention relates to active clamping circuits and semiconductor devices. Background Technology

[0002] In the past, in switching circuits (especially high-frequency switching circuits), parasitic inductance in the wiring would generate surge voltages during switching. Various countermeasures were previously adopted to prevent problems such as damage to the main switch caused by these surge voltages.

[0003] Figure 16 This is a circuit diagram of the first switching circuit 800, which was used as a conventional technology. Figure 16 In the diagram, Vcc represents the external power supply, C represents the input capacitor, T1, T2, and T3 represent the output terminals, and VBH and VBL represent the terminals used to send signals to the gate electrodes G1 and G2 of the main switches Q1 and Q2 to turn the main switches on or off.

[0004] In the conventional first switching circuit 800, to clamp the surge voltage during switching, an additional clamping circuit 810 is required. This clamping circuit 810 requires clamping diodes 812 and 814, with voltage ratings slightly lower or approximately equal to those of Q1 and Q2, to be connected in parallel to the first main switch Q1 and the second main switch Q2, respectively. The anode of clamping diode 812 is connected to the connection point of the first main switch Q1 and the second main switch Q2, and the cathode of clamping diode 812 is connected to the drain electrode D1 of the first main switch Q1. The anode of clamping diode 814 is connected to the source electrode S2 of the second main switch Q2, and the cathode of clamping diode 814 is connected to the connection point of the first main switch Q1 and the second main switch Q2.

[0005] According to the conventional first switching circuit 800, since it has clamping diodes 812 and 814, it is possible to absorb surge voltage and clamp the drain-source voltage of the first main switch Q1 and the second main switch Q2.

[0006] [Preliminary Technology Documents]

[0007] [Patent Document 1] Japanese Patent No. 4054155

[0008] However, in the conventional first switching circuit 800, the drain-source voltage is clamped by bypassing the current flowing through the main switches Q1 and Q2 to the clamping circuit 810, thus increasing the current flowing through the clamping circuit 810. Therefore, clamping diodes 812 and 814 in the clamping circuit 810, capable of withstanding large currents, are required; that is, large diodes are needed. Furthermore, due to the large current flowing through the clamping diodes 812 and 814, the clamping voltage variation caused by the operating resistance (impedance) of the clamping diodes 812 and 814 (see reference) is significant. Figure 6 The dotted line will become larger, the temperature rise of the clamping diodes 812 and 814 will increase, and the fluctuation of the clamping voltage will increase. Therefore, the clamping surge voltage function may not operate as intended, ultimately leading to instability in the operation of the switching circuit. Therefore, the conventional second switching circuit 900 (refer to) has a known active clamping circuit 910 between the drain electrodes D1 and D2 of the main switches Q1 and Q2 and the gate electrodes G1 and G2. Figure 17 (a). For example, see patent document 1).

[0009] Figure 17 This is a circuit diagram showing the previous second switch circuit 900. Among them, Figure 17 (a) is the circuit diagram of the conventional second switching circuit 900. Figure 17 (b) is a circuit diagram of the active clamping circuit 910. In the conventional second switching circuit 900, the active clamping circuit 910 includes a group 941 of multiple Zener diodes 943 and 944 connected with opposite characteristics (see...). Figure 17 (b)).

[0010] In the conventional second switching circuit 900, when the drain-source voltage of the main switch Q1 (Q2) is greater than the sum of the Zener voltage of Zener diode 943, the forward voltage VF of diode 944, and the threshold voltage VTH of the gate electrode G1 (G2) of the main switch Q1 (Q2), the feedback capacitor of the main switch Q1 (Q2) is charged, and the main switch Q1 (Q2), which was turned off at the time when the drain-source voltage begins to increase, is turned on again. Therefore, drain current flows through the main switch Q1 (Q2) under the condition of applied drain-source voltage, thus absorbing surge voltage with a smaller current flowing into the clamping circuit than in the conventional first switching circuit 800.

[0011] However, in the fields of inverter circuits and power supplies, there is a need for active clamping circuits that can further reduce the current flowing through the clamping diodes and make the operation of the switching circuits more stable.

[0012] Therefore, the present invention was made in view of the above circumstances, and its object is to provide an active clamping circuit and semiconductor device that can absorb surge voltage and clamp voltage even without using a large diode, and can make the operation of the switching circuit more stable. Summary of the Invention

[0013] The first active clamping circuit of the present invention is connected between the control electrode and the main electrode of a main switch for controlling the clamping voltage of the main switch. It is characterized by comprising: a clamping voltage control switch having a first main electrode, a second main electrode, and a control electrode, wherein the second main electrode is electrically connected to the main electrode of the main switch, and the first main electrode is electrically connected to the control electrode of the main switch; and a clamping voltage determining unit, one end of which is electrically connected to the second main electrode of the clamping voltage control switch, and the other end of which is electrically connected to the control electrode of the clamping voltage control switch, wherein the clamping voltage determining unit comprises: a diode section having a plurality of groups consisting of at least Zener diodes and diodes connected in series with opposite polarities; and a temperature characteristic adjustment resistor connected in series with the diode section.

[0014] The second active clamping circuit of the present invention is connected between the control electrode and the main electrode of a main switch for controlling the clamping voltage of the main switch. It is characterized by comprising: a bypass diode having an anode and a cathode, the anode being electrically connected to the control electrode of the main switch, and the cathode being electrically connected to the main electrode of the main switch; and a clamping voltage determining unit, one terminal of which is electrically connected to the cathode of the bypass diode, and the other terminal of which is electrically connected to the anode of the bypass diode and the control electrode of the main switch. The clamping voltage determining unit comprises: a diode section having multiple groups consisting of at least Zener diodes and diodes connected in series with opposite polarities; and a temperature characteristic adjusting resistor connected in series with the diode section.

[0015] The first semiconductor device of the present invention is connected between a control electrode and a main electrode of a main switch, constituting an active clamping circuit for controlling the clamping voltage of the main switch. It is formed on a semiconductor substrate defining a device region and a voltage-resistant separation region formed around the device region. The device region includes: the semiconductor substrate; a first main electrode formed on the surface of the semiconductor substrate; a gate pad formed on the surface of the semiconductor substrate at a position separate from the first main electrode; and a second main electrode formed on the back surface of the semiconductor substrate. A MOS structure is formed in the region where the first main electrode is formed. The voltage separation region includes: the semiconductor substrate; the second main electrode formed on the back surface of the semiconductor substrate; an insulating film formed on the surface of the semiconductor substrate; and a clamping voltage determining part disposed on the insulating film in a region surrounding the device region when viewed from above, one end of which is electrically connected to the gate pad and the other end of which is electrically connected to the second main electrode. The clamping voltage determining part includes: a plurality of first conductivity type regions and a plurality of first conductivity type regions arranged adjacent to each other and alternately; and a temperature characteristic adjusting resistor connected in series with the diodes, the temperature characteristic adjusting resistor having a temperature characteristic corresponding to the temperature characteristic of the diodes.

[0016] The second semiconductor device of the present invention is connected between the control electrode and the main electrode of a main switch, constituting an active clamping circuit for controlling the clamping voltage of the main switch. It is formed on a semiconductor substrate defining a device region and a voltage-resistant separation region formed around the device region. The device region includes: the semiconductor substrate; a first main electrode formed on the surface of the semiconductor substrate; and a second main electrode formed on the back surface of the semiconductor substrate. A diode structure is formed in the region where the first main electrode is formed. The voltage-resistant separation region includes: the semiconductor substrate; and the... A second main electrode is formed on the surface of the back side of the semiconductor substrate; an insulating film is formed on the surface of the semiconductor substrate; and a clamping voltage determining portion is disposed on the insulating film in a region surrounding the device area when viewed from above, one end of which is electrically connected to the gate pad and the other end of which is electrically connected to the second main electrode. The clamping voltage determining portion includes: a plurality of first first conductivity type regions and a plurality of first second conductivity type regions that are adjacent to each other and alternately arranged; and a temperature characteristic adjusting resistor connected in series with the diodes, the temperature characteristic adjusting resistor having a temperature characteristic corresponding to the temperature characteristic of the diodes.

[0017] Invention Effects

[0018] The first active clamping circuit according to the present invention, having a clamping voltage control switch and a clamping voltage determining unit with one terminal electrically connected to the second main electrode and the other terminal electrically connected to the control electrode, is capable of absorbing surge voltages, similar to conventional switching circuits. Furthermore, the clamping voltage control switch functions as a driver that sends a conduction signal to the control electrode of the main switch. Therefore, the drive current is small, reducing the current flowing through the clamping voltage determining unit that determines the trigger cutoff voltage. Since the main switch can be used as a current path for voltage clamping during surge voltage generation when the clamping voltage control switch or the main switch is turned on, a large diode is not required.

[0019] The second active clamping circuit according to the present invention, having a bypass diode and a clamping voltage determining unit with one terminal electrically connected to the cathode of the bypass diode and another terminal electrically connected to the anode of the bypass diode and the control electrode of the main switch, can absorb surge voltage and clamp voltage, just like conventional switching circuits. Furthermore, in addition to reducing the current flowing through the clamping voltage determining unit, it can also use the main switch as a current path for voltage clamping during surges caused by turning on the main switch, thus eliminating the need for a large diode.

[0020] Furthermore, in the first and second active clamping circuits according to the present invention, since they include a switch or bypass diode for clamping voltage control and a clamping voltage determining unit, as described above, the current flowing through the clamping circuit decreases, and the operating resistance (impedance) of the Zener diode also decreases. Therefore, the change in clamping voltage caused by the operating resistance (impedance) of the Zener diode (see reference) Figure 6 The dotted line in the diagram also becomes smaller. Furthermore, because the current flowing through the clamping circuit decreases, the temperature rise of the Zener diode decreases, reducing fluctuations in the clamping voltage. Therefore, the clamping surge voltage function can be activated according to the set target, thereby stabilizing the operation of the switching circuit.

[0021] According to the first and second active clamping circuits of the present invention, since the clamping voltage determining part has a temperature characteristic adjusting resistor, the influence of the temperature characteristic of the diode's forward voltage (which decreases with temperature rise) can be offset by the temperature characteristic of the temperature characteristic adjusting resistor (which increases with temperature rise), thereby suppressing temperature fluctuations in the clamping voltage.

[0022] According to the first semiconductor device of the present invention, since a MOS structure is formed in the region where the first main electrode is formed, and a clamping voltage determining section is provided in the voltage-resistant separation region, wherein a plurality of first first conductivity type regions and a plurality of first second conductivity type regions are adjacent to each other and alternately arranged, it is possible to construct an active clamping circuit having a clamping voltage control switch; and a clamping voltage determining section, one terminal of which is electrically connected to the first main electrode of the clamping voltage control switch, and the other terminal of which is electrically connected to the control electrode of the clamping voltage control switch. Therefore, like the first active clamping circuit, it can absorb surge voltage. In addition, since the clamping voltage control switch (MOS structure) has the function of a driver that sends a conduction signal to the control electrode of the main switch, the drive current is small, which can reduce the current flowing through the clamping voltage determining section that determines the trigger cutoff voltage. Since the main switch can be used as a current path for voltage clamping during surge voltage generation when the clamping voltage control switch or the main switch is turned on, a large diode is not required. In other words, by implementing these devices and functions on a single chip, miniaturization can be further achieved by suppressing the deviations between individual Zener diodes, diodes, and temperature-adjusting resistors. Therefore, it is possible to achieve not only high precision, power saving, and low cost, but also a reduction in the installation area.

[0023] According to the second semiconductor device of the present invention, since a diode structure is formed in the region where the first main electrode is formed, and a clamping voltage determining section is included, comprising a plurality of first first conductivity type regions and a plurality of first second conductivity type regions arranged adjacent to each other and alternately, an active clamping circuit can be constructed that includes a bypass diode and a clamping voltage determining section, one terminal of which is electrically connected to the first main electrode of the bypass diode and the other terminal of which is electrically connected to the second electrode of the bypass diode. Therefore, surge voltage can be absorbed to clamp the voltage. In addition, since the current flowing into the clamping voltage determining section can also be reduced, the main switch can be used as a current path for voltage clamping during a surge generated when the main switch is turned on, and a large diode can be eliminated. That is, by implementing these devices and functions on a single chip, miniaturization can be further achieved by suppressing the deviation between individual Zener diodes, diodes, and temperature adjustment resistors, thus achieving not only high precision, power saving, and low cost, but also a reduced installation area.

[0024] According to the first and second semiconductor devices of the present invention, a MOS structure or a diode structure is formed in the region where the first main electrode is formed, and a clamping voltage determining part is included in the voltage-resistant separation region, comprising a plurality of first first conductivity type regions and a plurality of first second conductivity type regions arranged adjacent to each other and alternately. Therefore, the current flowing through the active clamping circuit and the Zener diode is reduced in the clamping voltage determining part, and thus the operating resistance (impedance) of the Zener diode is reduced, preventing fluctuations in the clamping voltage caused by the operating resistance (impedance) of the Zener diode (see reference). Figure 6 (The dashed line in the diagram). Furthermore, the reduced temperature rise of the Zener diode decreases the clamping voltage fluctuations caused by its temperature rise. Therefore, the clamping surge voltage function can be activated as intended, stabilizing the operation of the switching circuit.

[0025] According to the first and second semiconductor devices of the present invention, since the clamping voltage determining unit has a diode section with a plurality of first first conductivity type regions and a plurality of first second conductivity type regions adjacent to each other and alternately arranged, and a temperature characteristic adjusting resistor connected in series with the diode section, and the temperature characteristic adjusting resistor has a temperature characteristic corresponding to the temperature change of the diode section, the influence of the temperature characteristic (characteristic that decreases with temperature rise) of the forward voltage of the diode formed between the first first conductivity type region and the first second conductivity type region can be offset by the temperature characteristic (characteristic that increases with temperature rise) of the internal resistance of the first first conductivity type region, thereby suppressing the temperature change of the clamping voltage. Attached Figure Description

[0026] Figure 1 This is a circuit diagram showing the switching circuit 1 and the active clamping circuit 10 in Embodiment 1.

[0027] Figure 2 It is a graph and curve showing the temperature characteristics of the temperature characteristic adjustment resistor 35, the forward voltage of diode 34, the Zener voltage of Zener diode 33, and the clamping voltage of active clamping circuit 10 in embodiment 1.

[0028] Figure 3 This is a plan view of the semiconductor device 100 according to Embodiment 1.

[0029] Figure 4 yes Figure 3 A-A' cross-sectional view.

[0030] Figure 5 yes Figure 3 The B-B' cross-sectional view.

[0031] Figure 6 This is a schematic diagram illustrating the relationship between the clamping voltage and the diode current in an active clamping circuit.

[0032] Figure 7 This is a circuit diagram of the active clamping circuit 10a in embodiment 2.

[0033] Figure 8 This is a plan view of the semiconductor device 101 according to Embodiment 2.

[0034] Figure 9 This is a plan view of the semiconductor device 102 according to Embodiment 3.

[0035] Figure 10 This is a plan view of the semiconductor device 103 according to Embodiment 4.

[0036] Figure 11 This is a plan view of the semiconductor device 104 according to Embodiment 5.

[0037] Figure 12 This is a plan view of the semiconductor device 105 according to Embodiment 6.

[0038] Figure 13 This is a plan view of the semiconductor device 106 according to Embodiment 7.

[0039] Figure 14 This is a circuit diagram of the active clamping circuit 10b in embodiment 8.

[0040] Figure 15 This is a plan view of the semiconductor device 200 according to embodiment 8.

[0041] Figure 16 This is the circuit diagram of the previous first switch circuit 800.

[0042] Figure 17 This is the circuit diagram of the previous second switch circuit 900. Detailed Implementation

[0043] The active clamping circuit and semiconductor device of the present invention will now be described based on the embodiments shown in the accompanying drawings. The embodiments described below do not limit the invention as claimed in the appended claims. Furthermore, not all elements and combinations thereof described in the embodiments are essential to the solutions of the present invention.

[0044] [Implementation Method 1]

[0045] 1. Structure of switch circuit 1 in implementation method 1

[0046] Figure 1 This is a circuit diagram showing the switching circuit 1 and the active clamping circuit 10 in Embodiment 1. Wherein, Figure 1 (a) is a circuit diagram representing switch circuit 1. Figure 1 (b) is a circuit diagram representing the active clamping circuit 10. Symbol 50 represents a pull-down resistor, symbol Vcc represents an external power supply, symbols T1, T2 and T3 represent output terminals, and symbols VBH and VBL represent terminals used to send turn-on / turn-off signals to the gates G1 and G2 of the main switches Q1 and Q2.

[0047] The switching circuit 1 involved in Implementation Method 1 is as follows: Figure 1As shown in (a), the circuit includes a first main switch Q1 on the high side, a second main switch Q2 on the low side connected in series with the first main switch Q1, an input capacitor C, and two active clamping circuits 10. The main switches Q1 and Q2 can be appropriate transistors such as MOSFETs or IGBTs. The source electrode S1 of the first main switch Q1 is connected to the drain electrode D2 of the second main switch Q2, and the drain electrode D1 of the first main switch Q1 is connected to an external power supply Vcc. The source electrode S2 of the second main switch Q2 is connected to a reference potential.

[0048] 2. Configuration of the active clamping circuit 10 in Implementation Method 1

[0049] Two active clamping circuits 10 are connected at one end to the drain electrodes D1 and D2 of the main switches Q1 and Q2, respectively, and at the other end to the gate electrodes G1 and G2 of the main switches Q1 and Q2, respectively. Furthermore, since both active clamping circuits 10 have the same characteristics, the description of the active clamping circuit 10 connected to the first main switch Q1 will be given thereafter, and the description of the active clamping circuit 10 connected to the second main switch Q2 will be omitted.

[0050] The active clamping circuit 10 clamps the drain-source voltage of the first main switch Q1. For example... Figure 1 As shown in (b), the active clamping circuit 10 includes a clamping voltage control switch 20, a clamping voltage determination unit 30, and a gate protection unit 40.

[0051] The clamping voltage control switch 20 is a switching element having three terminals: a drain electrode D3 (first main electrode), a source electrode S3 (second main electrode), and a gate electrode G3 (control electrode). In Embodiment 1, although a MOSFET is used, an IGBT or other suitable switching element can also be used. In the clamping voltage control switch 20, the drain electrode D3 is electrically connected to the external power supply Vcc and the drain electrode D1 of the first main switch Q1, and the source electrode S3 is electrically connected to the gate electrode G1 of the first main switch Q1.

[0052] One terminal of the clamping voltage determining unit 30 is electrically connected to the drain electrode D3 of the clamping voltage control switch 20, the external power supply Vcc, and the drain electrode D1 of the first main switch Q1; the other terminal is electrically connected to the gate electrode G3 of the clamping voltage control switch 20. The clamping voltage determining unit 30 includes: a diode section 36 with multiple groups 31 connected in series, wherein Zener diodes 33 and 34 are connected in series with opposite polarities; and a temperature characteristic adjusting resistor 35 connected in series with the diode section 36.

[0053] In the clamping voltage determination unit 30, a temperature characteristic adjustment resistor 35 whose resistance (voltage drop caused by resistance) is positively correlated with temperature rise, a diode 34 whose forward voltage is negatively correlated with temperature rise, and a Zener diode 33 whose Zener voltage is positively or negatively correlated with temperature rise are combined to adjust the temperature coefficient of the voltage applied to the clamping voltage determination unit 30, thereby making the temperature characteristic of the clamping voltage determination unit 30 approximately constant with temperature rise (see below). Figure 2 In other words, the temperature-adjusting resistor 35 has a temperature characteristic that reduces the temperature change of the superimposed voltage after superimposing the Zener voltage of each group 31 Zener diode 33 with the forward voltage of diode 34.

[0054] One end of the gate protection section 40 is connected to the gate electrode G3 of the clamping voltage control switch 20, and the other end is connected to the source electrode S3 of the clamping voltage control switch 20 and the gate electrode G1 of the main switch Q1. The gate protection section 40 includes multiple groups 41, each group consisting of a gate protection temperature-adjusting resistor 42, a gate protection Zener diode 43 connected to one end of the gate protection temperature-adjusting resistor 42, and a gate protection diode 44 connected to the other end of the gate protection temperature-adjusting resistor 42 with characteristics opposite to those of the gate protection Zener diode 43. These groups are connected in series with the gate protection Zener diode 43 located on the gate electrode G3 side. The gate protection section 40 connects the groups 41 in series with the necessary number of stages to ensure that the voltage is greater than or equal to the gate drive voltage used on the gate oxide film and that the gate insulating film is not damaged (preventing damage to the gate insulating film used on the gate electrode G3 of the clamping voltage control switch 20). Figure 4 The symbol 122 in the middle was destroyed by static electricity.

[0055] The active clamping circuit 10 operates as follows: Regarding the drain-source voltage of the first main switch Q1, when the voltage set by the clamping voltage determination unit 30 is greater than or equal to "(Zener voltage of Zener diode 33 + forward voltage VF of diode 34) × number of stages + voltage drop of temperature characteristic adjustment resistor 35 + threshold voltage of clamping voltage control switch 20", the clamping voltage control switch 20 becomes on, and by driving the gate of the main switch Q1 while suppressing further voltage rise, the main switch Q1 also becomes on, thereby suppressing the rise of drain voltage, i.e., it becomes a voltage clamping state.

[0056] In this way, the drain-source voltage of the first main switch Q1 can be clamped, and the current flowing through the clamping voltage determination unit 30 can be reduced.

[0057] 3. Regarding the temperature characteristic adjustment resistor 35 in Implementation Method 1

[0058] Next, the temperature characteristic adjustment resistor 35 of the clamping voltage determination unit 30 will be explained in detail. Figure 2 These are graphs and curves showing the temperature characteristics of the temperature-adjusting resistor 35 (R), the forward voltage VF of diode 34, the Zener voltage Vz of Zener diode 33, and the clamping voltage of the active clamping circuit 10 in Embodiment 1. Figure 2 (a) Indicates the temperature characteristic of the resistance value R of the temperature characteristic adjustment resistor 35. Figure 2 (b) shows the temperature characteristic of the forward voltage VF of diode 34. Figure 2 (c) represents the temperature characteristic of the Zener voltage Vz of Zener diode 33. Figure 2 (d) The configuration of the clamping voltage determining unit 30 is shown. Figure 2 (e) indicates the temperature characteristics of the clamping voltage of the clamping voltage determining unit 30.

[0059] Since the clamping voltage determining unit 30 is a group 31 consisting of multiple Zener diodes 33 and diodes 34 connected in series (see reference 31) Figure 2 (d) The diode section 36 and the temperature characteristic adjustment resistor 35 are connected in series. Therefore, the clamping voltage is determined by superimposing the resistance value R (voltage drop caused by resistance) of the temperature characteristic adjustment resistor 35, the forward voltage VF of the diodes 34 in each group 31, and the Zener voltage Vz of the Zener diode 33. As a result, the temperature characteristic of the clamping voltage is also affected by the temperature characteristics of the above three factors.

[0060] The temperature characteristic of the forward voltage VF of diode 34 decreases to the right as the temperature increases (refer to...). Figure 2 (b) Therefore, by making the temperature characteristic adjustment resistor 35 have a temperature characteristic that increases to the right as the temperature rises, it is possible to make it have a temperature characteristic that reduces the temperature change of the forward voltage of the diode 34. In this way, the temperature change of the clamping voltage of the clamping voltage determining unit 30 can be reduced.

[0061] Furthermore, the temperature characteristic of the Zener voltage Vz of Zener diode 33 varies depending on the characteristics of the Zener diode (see reference). Figure 2 (c) Therefore, by utilizing the temperature characteristics of the Zener voltage Vz of the Zener diode 33 to change the slope of the temperature characteristic adjustment resistor 32 relative to the temperature change, the temperature change of the clamping voltage of the clamping voltage determination unit 30 can be further reduced, thereby maintaining the clamping voltage approximately constant even at high temperatures (see reference). Figure 2 (e)).

[0062] Specifically, when the Zener voltage Vz of Zener diode 33 exhibits a temperature characteristic that increases upwards and to the right with increasing temperature, this cancels out the temperature characteristic of the forward voltage VF of diode 34, which decreases downwards and to the right with increasing temperature. Therefore, the resistance value of temperature characteristic adjustment resistor 35 is reduced (refer to...). Figure 2 (a) The “small” curve), thus fine-tuning the temperature characteristics after adding the aligner voltage Vz and the forward voltage VF.

[0063] Given that the Zener voltage Vz of Zener diode 33 exhibits a temperature characteristic that remains approximately constant even as temperature increases, the forward voltage VF of diode 34 in each group 31 decreases to the lower right. Therefore, slightly increasing the resistance value of the temperature characteristic adjustment resistor 35 (refer to...) Figure 2 (a) The curve of “middle” in the middle) thereby offsets the temperature characteristics of the positive voltage VF and reduces the temperature change of the clamping voltage of the clamping voltage determination unit 30.

[0064] When the Zener voltage Vz of Zener diode 33 exhibits a temperature characteristic that decreases to the right as temperature increases, the temperature characteristics of the forward voltage VF of diode 34, which also decreases to the right as temperature increases, mutually reinforce each other. Therefore, increasing the resistance value of temperature characteristic adjustment resistor 35 (refer to...) Figure 2 (a) The “large” curve), thereby eliminating the temperature characteristics of the diode section 36 and reducing the temperature variation of the clamping voltage of the clamping voltage determining section 30.

[0065] 4. Structure of the semiconductor device 100 in Embodiment 1

[0066] The structure of the active clamping circuit 10 is described below. In the conventional first switching circuit 800 and the conventional second switching circuit 900, it was also considered to insert the clamping circuit and the main switch Q1 into a single chip, but this resulted in a corresponding increase in the chip size of the main switch Q1. In particular, when the main switch is a wide-gap semiconductor such as SiC or GaN, the surrounding area is relatively narrow, and when the clamping circuit is formed, the voltage-break separation area becomes unnecessarily wide, thus making the chip size excessively large. Furthermore, since wide-gap semiconductors are expensive, by separately constructing the clamping circuit and the main switch Q1, the cost increase of the main switch Q1 can be suppressed. Therefore, in Embodiment 1, the active clamping circuit 10 is constructed on a different chip than the main switch Q1 to prevent the chip size of the main switch Q1 from increasing.

[0067] Figure 3This is a plan view illustrating the semiconductor device 100 of Embodiment 1. The clamping voltage determining unit 180 has a structure in which multiple first N-type regions 182 and multiple first P-type regions 184 are adjacent to each other and alternately arranged. However, for the sake of simplicity, only the first P-type region 184 closest to device region A1 and the adjacent first N-type region 182, and the first P-type region 184 and the adjacent first N-type region 182 located in the middle position are shown in the illustration, while the other first P-type regions 184 and first N-type regions 182 are omitted. Similarly, only two gates 120 are shown, and the illustrations of other gates are omitted. In addition, in the source 130 and gate pad 140, the pad portion for external connection is shown in white, and the other portions (polysilicon portions) are drawn with shaded lines. Furthermore, in Figure 3 In the middle, the gate wiring appears to be a single line, but as Figure 4 As shown, it is separate from the first gate wiring 145 and the second gate wiring 147. Figure 4 yes Figure 3 A-A' cross-sectional view.

[0068] like Figure 3 As shown, the semiconductor device 100 of Embodiment 1 is formed in a semiconductor substrate 110. A device region A1 formed in the center of the semiconductor substrate 110 and a voltage-resistant separation region A2 formed around the device region A1 are defined. A clamping voltage control switch 20 is formed in the device region A1, and a clamping voltage determining unit 30 is formed in the voltage-resistant separation region A2. That is, the semiconductor device 100 of Embodiment 1 is connected between the gate electrode and drain electrode of the main switches Q1 and Q2, forming an active clamping circuit 10 for controlling the clamping voltage of the main switches Q1 and Q2, and realizing the function of a device.

[0069] (1) Regarding device region A1

[0070] Device region A1 forms the clamping voltage control switch 2. Device region A1 consists of an active region A11 (refer to) where a MOS structure is formed in the region overlapping with the source electrode 130. Figure 4 ), and a peripheral region A12 formed around the active region A11 and having a gate pad 140, a first gate wiring 145, and a second gate wiring 147 (see reference). Figure 4 and Figure 5 )constitute.

[0071] (1-1) Regarding the active region A11

[0072] In the active region A11 of device region A1, such as Figure 3 and Figure 4As shown, the semiconductor device 100 of Embodiment 1 includes a semiconductor substrate 110, a gate electrode 120, a gate insulating film 122, an interlayer insulating film 124, a source electrode 130 (first main electrode), a drain electrode 150 (second main electrode), and a protective insulating film 160. The semiconductor device 100 of Embodiment 1 is a planar gate MOSFET with a MOS structure having a gate electrode 120, a gate insulating film 122, and a semiconductor substrate 110 in the region where the source electrode 130 of the device region A1 is formed. Alternatively, a trench gate MOSFET may be used instead of a planar gate MOSFET.

[0073] like Figure 4 As shown, the semiconductor substrate 110 has: an N+ type low-resistance semiconductor layer 111, an N-type drift layer 112 formed above the low-resistance semiconductor layer 111, a P-type base region 113 formed in a predetermined area on the surface of the drift layer 112, and an N+ type source region 114 formed on a portion of the surface of the base region 113 and separated from the drift layer 112. Silicon can be used as the material for the semiconductor substrate 110, but materials such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3) capable of high-speed switching are also suitable.

[0074] The thickness of the low-resistivity semiconductor layer 111 is, for example, in the range of 100 μm to 400 μm, and the impurity concentration of the low-resistivity semiconductor layer 111 is, for example, 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness of the drift layer 112 is, for example, in the range of 5 μm to 120 μm. The impurity concentration of the drift layer 112 is, for example, 5 × 10⁻⁶. 13 cm -3 ~1×10 16 cm -3 Within this range. The deepest part of the base region 113 is, for example, in the range of 0.5 μm to 4.0 μm, and the impurity concentration of the base region 113 is, for example, 5 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 Within a certain range. The deepest part of the source region 114 is, for example, in the range of 0.1 μm to 1.5 μm, and the impurity concentration of the source region 114 is, for example, 5 × 10⁻⁶. 19 cm -3 ~2×10 20 cm -3 Within the range.

[0075] The gate electrode 120 is disposed on the semiconductor substrate 110 through a gate insulating film 122, and is opposite the base region 113, which is sandwiched between the source region 114 and the drift layer 112, through the gate insulating film 122. Figure 3 As shown, the gate electrode 120 is arranged in a stripe pattern on the semiconductor substrate 110 at predetermined intervals when viewed from above, and its two ends are connected via lead-out wiring 146 (see below). Figure 4 It is connected to the first gate wiring 145.

[0076] An interlayer insulating film 124 is formed on the upper and side portions of the gate electrode 120, thereby insulating the gate electrode 120 from the source electrode 130. The interlayer insulating film 124 may be, for example, an insulating film formed by CVD with a thickness of 0.5 μm to 2.0 μm of phosphorus or an oxide film containing phosphorus and boron, but other suitable insulating films may also be used.

[0077] The source electrode 130 is formed on the interlayer insulating film 124 and is connected to the source region 114 and the base region 113 on the surface of the semiconductor substrate 110 via contact grooves or the like formed on the interlayer insulating film 124. The source electrode 130 is, for example, made of an Al film or an Al alloy film (e.g., an AlSi film), and the thickness of the source electrode 130 is 1 μm to 10 μm (e.g., 3 μm).

[0078] The drain electrode 150 is disposed on the entire surface of the back side of the semiconductor substrate 110 (the entire surface of the low-resistance semiconductor layer 111). The drain electrode 150 is composed of a multilayer film formed by sequentially stacking Ti, Ni, and Au (or Ag) from the semiconductor substrate 110 side, and the thickness of the drain electrode 150 is 0.2 μm to 1.5 μm (e.g., 1 μm).

[0079] Protective insulating film 160 is formed on the surface of semiconductor substrate 110, excluding the pad portion of source electrode 130. Figure 3 The white rectangular portion in the center and the entire surface outside the cut area of ​​the chip separated from the gate pad 140. The material of the protective insulating film 160 is, for example, polyimide.

[0080] (1-2) Regarding the surrounding area A12

[0081] Figure 5 yes Figure 3 The B-B' cross-sectional view. In the peripheral region A12 of device region A1, as shown... Figures 3 to 5 As shown, a gate pad 140, a first gate wiring 145, and a second gate wiring 147 are disposed on a semiconductor substrate 110. An interlayer insulating film 124 is formed on the lead-out wiring 146 and the gate protection portion 142. Figure 3As shown, the gate pad 140 is positioned outside one short side of the rectangular source electrode and is located separately from the source electrode 130. The first gate wiring 145 and the second gate wiring 147 are arranged such that the inner periphery of the first gate wiring 145 is the first gate wiring 145 and the outer periphery of the second gate wiring 147 are the second gate wiring 147, which substantially surround the source electrode 130 (see reference). Figure 3 and Figure 4 ), and connected to the gate pad 140.

[0082] Gate pad 140 is configured with a polysilicon layer 141 formed on field insulating film 170 as a buffer (see reference). Figure 3 and Figure 5 The gate pad 140 is connected to the source electrode 130 via the polysilicon layer 141 and the gate protection portion 142 (described later). Furthermore, the gate pad 140 is also connected to the first gate wiring 145 and the second gate wiring 147. Additionally, the polysilicon layer 141 is incorporating N-type impurities into the polysilicon layer formed by CVD, for example, through ion implantation.

[0083] The first gate wiring 145 is disposed on the lead wiring 146 disposed on the interlayer insulating film 124 (see reference). Figure 4 Lead-out wiring 146 is connected to the end of the gate electrode 120, which is configured in a stripe pattern. First gate wiring 145 is connected to lead-out wiring 146 and is connected to the gate electrode 120 via lead-out wiring 146. Incidentally, lead-out wiring 146 is formed by introducing impurities into polysilicon.

[0084] The second gate wiring 147 is connected to the clamping voltage determining part 180 of the withstand voltage separation region A2. The gate pad 140, the first gate wiring 145, and the second gate wiring 147 are formed together with the source electrode 130.

[0085] In the peripheral region A12 of device region A1, such as Figure 5 As shown, the semiconductor device 100 of Embodiment 1 includes a semiconductor substrate 110, a field insulating film 170, a gate protection portion 142, a drain electrode 150, and a protective insulating film 160. The drain electrode 150 and the protective insulating film 160 have the same configuration as the active region A11.

[0086] like Figure 5 As shown, the semiconductor substrate 110 has an N+ type low-resistance semiconductor layer 111, an N-type semiconductor layer 115 formed above the low-resistance semiconductor layer 111, and a P-type semiconductor layer 119. The N+ type low-resistance semiconductor layer 111 has the same structure as the low-resistance semiconductor layer 111 of the active region A11. The N-type semiconductor layer 115 has the same structure as the drift layer 112 of the active region A11. The P-type semiconductor layer 119 has the same depth as the base region 113 of the active region A11.

[0087] The field insulating film 170 is an oxide film and other suitable insulating films formed on the surface of the semiconductor substrate 110.

[0088] On the field insulating film 170, when viewed from above, the gate protection portion 142 is disposed in the area surrounding the gate pad 140 (strictly speaking, the polysilicon layer 141 beneath the gate pad 140). Therefore, the gate pad 140 is electrically connected to the source electrode 130 via the gate protection portion 142 (see reference). Figure 5 (on the right side), and electrically connected to the first gate wiring 145 through the gate protection part 142 (illustration omitted).

[0089] At least one second N-type region 143 and at least two second P-type regions 144 of the gate protection portion 142 are adjacent to each other and alternately arranged. In the gate protection portion 142, the total amount of impurities in the second P-type region 144 sandwiched between the two second N-type regions 143 is smaller than the total amount of impurities in any one of the two second N-type regions 143 adjacent to the second P-type region 144. Therefore, the internal resistance of the second P-type region 144 can be used as the temperature characteristic adjustment resistor 42 for gate protection. Furthermore, a Zener diode 43 for gate protection can be formed by the second P-type region 144 and one second N-type region 143, and a gate protection diode 44 can be formed by the second P-type region 144 and another second N-type region 143.

[0090] (2) Regarding the pressure-resistant separation area A2

[0091] The withstand voltage separation region A2 is the region in which the clamping voltage determining part 30 is formed.

[0092] like Figures 3-5 As shown, the semiconductor device 100 of Embodiment 1 includes a semiconductor substrate 110, a field insulating film 170, a clamping voltage determining portion 180, a channel blocking electrode 190, and a drain electrode 150 in the voltage-resistant separation region A2. The drain electrode 150 and the field insulating film 170 have the same configuration as the device region A1. In addition, an interlayer insulating film 124 is formed on the clamping voltage determining portion 180.

[0093] The semiconductor substrate 110 has an N+ type low-resistance semiconductor layer 111, an N-type semiconductor layer 115 formed above the low-resistance semiconductor layer 111, a P-type surface electric field reducing region 116 formed on the surface of the N-type semiconductor layer 115, and a channel blocking region 117 in the voltage-break separation region A2. Additionally, a P-type boundary semiconductor region 118 is formed from the device region A1 to the voltage-break separation region A2, covering the end of the base region 113. Furthermore, the N+ type low-resistance semiconductor layer 111 has the same structure as the low-resistance semiconductor layer 111 in the device region A1. The N-type semiconductor layer 115 has the same structure as the drift layer 112 in the active region A11. The depth of the boundary semiconductor region 118 is formed to a depth deeper than the base region 113, but it can also be the same depth as the base region 113.

[0094] A surface electric field reduction region 116 is formed in a region that overlaps at least with the clamping voltage determining portion 180, and its depth is equal to or shallower than that of the P-type region 118. The ends of the surface electric field reduction region 116 are connected to the base region 113 and the P-type boundary semiconductor region 118 of the device region A1. The channel blocking region 117 is an N+ type semiconductor region formed on the outermost peripheral surface of the semiconductor substrate 110 and is connected to the channel blocking electrode 190.

[0095] like Figure 3 As shown, the clamping voltage determining unit, when viewed from above at 180°, covers the entire circumference of the device region A1, and as... Figure 4 As shown, the clamping voltage determining part 180 is connected to the second gate wiring 147 on the device region A1 side, and to the channel blocking electrode 190, which is structurally at the same potential as the drain electrode 150, on the outermost peripheral side. Therefore, one end (device region A1 side) of the clamping voltage determining part 180 is connected to the gate pad 140 through the second gate wiring 147, and the other end (outermost peripheral side) is electrically connected to the drain electrode 150.

[0096] The clamping voltage determining unit 180 is formed on the field insulating film 170, and it has a diode part 186 and a temperature characteristic adjustment resistor 185. The clamping voltage determining unit 180 has a structure corresponding to the clamping voltage determining unit 30 of the active clamping circuit 10.

[0097] The diode section 186 has a plurality of first P-type regions 184 and a plurality of first N-type regions 182 that are adjacent to each other and alternately arranged. A diode 34 is formed between the first P-type region 184 and the first P-type region 184 located on the device region A1 side, and a Zener diode 33 is formed between the first P-type region 184 and the first P-type region 184 located on the outer periphery side.

[0098] A temperature-adjustable resistor 185 is formed on the outer periphery of the diode portion 186 and connected in series with the diode portion 186. The temperature-adjustable resistor 185 is constructed from a polysilicon layer with P-type impurities. The internal resistance of the temperature-adjustable resistor 185 is determined by the impurity concentration of the temperature-adjustable resistor 185 and the length of the temperature-adjustable resistor 185 along the current path direction. Figure 4 The lateral length of the resistor and the cross-sectional area of ​​the temperature characteristic adjustment resistor 185 relative to the current path (the cross-sectional area of ​​the surface orthogonal to the current path) are determined.

[0099] The first N-type region 182, the first P-type region 184, and the temperature characteristic adjustment resistor 185 of the clamping voltage determining unit 180 are formed by introducing P-type impurities or N-type impurities into predetermined regions of the same polysilicon layer. Furthermore, in Embodiment 1, the clamping voltage determining unit 180, the polysilicon layer 141, the lead-out wiring 146, and the gate protection unit 142 are formed together.

[0100] The internal resistance of the temperature characteristic adjustment resistor 185 has a temperature characteristic that can cancel out the temperature change of the voltage after the forward voltage of the diode formed by the first P-type region 184 in the diode section and the first N-type region 182 adjacent to one side of the first P-type region 184 overlaps with the Zener voltage of the Zener diode formed by the first P-type region 184 and the first N-type region 182 adjacent to the other side of the first P-type region 184.

[0101] The channel blocking electrode 190 is formed around the outermost periphery of the semiconductor substrate 110 and is electrically connected to the drain electrode 150.

[0102] 5. Effects of the active clamping circuit 10 and semiconductor device 100 in Embodiment 1

[0103] According to the active clamping circuit 10 of Embodiment 1, since it includes a clamping voltage control switch 20 and a clamping voltage determination unit 30 with one terminal electrically connected to the drain electrode and the other terminal electrically connected to the gate electrode, it can absorb surge voltages, just like conventional switching circuits. Furthermore, since the clamping voltage control switch 20 functions as a driver to send conduction signals to the gate electrodes G1 and G2 of the main switches Q1 and Q2, in addition to having a small drive current, it can also use the main switches Q1 and Q2 as current paths for voltage clamping during surges caused by turning on the clamping voltage control switch or the main switches, thus eliminating the need for large diodes.

[0104] Figure 6 This is a schematic graph showing the relationship between clamping voltage and diode current in the active clamping circuit of Embodiment 1 and conventional active clamping circuits. Figure 6The dashed line represents the relationship between the clamping voltage and the diode current in a conventional active clamping circuit, while the solid line represents the relationship between the clamping voltage and the diode current in the active clamping circuit of Implementation Method 1.

[0105] In the conventional active clamping circuit 910, because the current flowing through the main switch Q1 is bypassed and clamped, the current flowing through the Zener diode 943 increases, and the operating resistance (impedance) of the Zener diode also increases. Therefore, the clamping voltage variation caused by the operating resistance (impedance) of the Zener diode (see reference) Figure 6 The dashed curve (symmetric about voltage level) becomes larger. Furthermore, the temperature rise of the Zener diode also increases, leading to greater fluctuations in the clamping voltage. Therefore, it becomes difficult to ensure the clamping surge voltage function operates as intended, making it challenging to stabilize the switching circuit.

[0106] In contrast, according to the active clamping circuit 10 of Embodiment 1, since it includes a clamping voltage control switch 20 and a clamping voltage determining unit 30, the current flowing through the clamping voltage determining unit 30 and the Zener diode 33 is reduced, and the operating resistance (impedance) of the Zener diode is reduced. Therefore, the change in clamping voltage caused by the operating resistance (impedance) of the Zener diode 33 can be reduced (see...). Figure 6 (Solid line in the diagram). Furthermore, since the current flowing into the clamping voltage determining unit 30 and the Zener diode 33 decreases, the temperature rise of the Zener diode decreases, thus reducing clamping voltage fluctuations. Therefore, the clamping surge voltage function can be activated according to the target, stabilizing the operation of the switching circuit.

[0107] According to the active clamping circuit 10 of Embodiment 1, since it has a temperature-adjusting resistor 35, the effect of the decrease in the forward voltage of the diode 34, which has a characteristic that decreases with increasing temperature, and the effect of the increase in the resistance value of the temperature-adjusting resistor 35, which has a characteristic that increases with increasing temperature, are mutually canceled out, thereby suppressing temperature fluctuations in the clamping voltage (see reference). Figure 6 ).

[0108] According to the active clamping circuit 10 of Embodiment 1, since it has a temperature characteristic adjustment resistor 35, it is possible to adjust the temperature tendency of any clamping voltage to counteract the temperature characteristic of the threshold voltage of the next-stage main switch Q1. For example, if the threshold voltage VTH of the main switch Q1 has a temperature characteristic of -100mV, by setting the temperature characteristic adjustment resistor 35 to +100mV, the temperature dependence can be counteracted as the overall operation of the circuit.

[0109] According to the active clamping circuit 10 of embodiment 1, since the gate protection section 40 has a group of gate protection Zener diode 43 and gate protection diode 44 connected with opposite polarities, it is possible to prevent the transmission of erroneous signals to the gate electrode due to the surge voltage of the switch, thereby improving the damage tolerance.

[0110] According to the active clamping circuit 10 of Embodiment 1, since the group 41 of the gate protection section 40 has a structure in which a gate protection temperature characteristic adjustment resistor 42 is provided between the gate protection Zener diode 43 and the gate protection diode 44, the gate protection section 40 can also absorb the fluctuation of the clamping voltage caused by temperature changes. As a result, even if there is a temperature change, the gate is not easily damaged.

[0111] According to the active clamping circuit 10 of Embodiment 1, since the temperature characteristic adjustment resistor 35 has a temperature characteristic that reduces the temperature change of the voltage applied to the diode section 36, the effect of the reduction of the forward voltage of the diodes in each group 31 of the diode section 36, which has a characteristic of decreasing with increasing temperature, can be mutually canceled out with the effect of the resistance value of the temperature characteristic adjustment resistor 35, which has a characteristic of increasing with increasing temperature. Moreover, it can also adapt to the temperature characteristic of the Zener voltage of the clamping diode 33, thereby more effectively suppressing the temperature variation of the clamping voltage of the clamping voltage determination unit 30.

[0112] According to the semiconductor device 100 of Embodiment 1, since a MOS structure is formed in the region where the active electrode 130 is formed, and a clamping voltage determining unit 180 is included in the voltage withstand separation region A2, comprising a plurality of N-type regions 182 and a plurality of P-type regions 184 arranged adjacent to each other and alternately, an active clamping circuit can be constructed that includes a clamping voltage control switch and a clamping voltage determining unit, one terminal of which is electrically connected to the first main electrode of the clamping voltage control switch, and the other terminal of which is electrically connected to the control electrode of the clamping voltage control switch. Therefore, surge voltage can be absorbed. In addition, since the clamping voltage control switch (MOS structure) has the function of a driver that sends a conduction signal to the control electrode of the main switch, the drive current is small, and the current flowing through the clamping voltage determining unit, which is used as a trigger, can also be reduced. Thus, the main switch can be used as the current path for voltage clamping only during surge generation, without the need for a large diode. In other words, by implementing these devices and functions on a single chip, miniaturization can be further achieved by suppressing the deviations between individual Zener diodes, diodes, and temperature-adjusting resistors. Therefore, it is possible to achieve not only high precision, power saving, and low cost, but also a reduction in the installation area.

[0113] According to the semiconductor device 100 of Embodiment 1, since a MOS structure is formed in the region where the active electrode 130 is formed, and a clamping voltage determining unit 180 with multiple N-type regions 182 and multiple P-type regions 184 adjacent to each other and alternately arranged is provided in the voltage withstand separation region A2, a clamping voltage control switch 20 and a clamping voltage determining unit 30 of an active clamping circuit can be configured. Therefore, since the current flowing through the active clamping circuit 10 and the Zener diode is reduced, the operating resistance (impedance) of the Zener diode 33 is reduced, and the fluctuation of the clamping voltage caused by the operating resistance (impedance) of the Zener diode 33 can be reduced. Figure 6 (The dashed line). Furthermore, because the current flowing through the active clamping circuit 10 and the Zener diode decreases, the temperature rise of the Zener diode 33 decreases, thus reducing clamping voltage fluctuations. Therefore, the clamping surge voltage function can be activated as intended, stabilizing the operation of the switching circuit.

[0114] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the clamping voltage determining unit 180 has a plurality of first P-type regions 184 and a plurality of first N-type regions 182 arranged adjacent to each other and alternately, and a temperature characteristic adjusting resistor 185 connected in series with the diodes 186, and the temperature characteristic adjusting resistor 185 has a temperature characteristic corresponding to the temperature change of the diodes 186, the influence of the temperature characteristic (characteristic that decreases with temperature rise) of the forward voltage of the diode formed between the first P-type regions 184 and the first N-type regions 182 can be offset by the temperature characteristic (characteristic that increases with temperature rise) of the internal resistance of the temperature characteristic adjusting resistor 185, thereby suppressing the temperature electrodynamics of the clamping voltage.

[0115] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the region surrounding the gate pad 140 on the field insulating film 170, when viewed from above, has a gate protection portion 142 in which at least one second N-type region 143 and at least two second P-type regions 144 are adjacent to each other and alternately arranged, the electrostatic discharge tolerance can be improved. In addition, as the device becomes smaller, the electrostatic discharge tolerance of the gate voltage may decrease, but since the gate protection portion 142 is provided, the electrostatic discharge tolerance can be maintained even when the device is reduced in size.

[0116] According to the semiconductor device 100 of Embodiment 1, since the total amount of impurities in the second P-type region 144 sandwiched between the two second N-type regions 143 is smaller than the total amount of impurities in any one of the two second N-type regions 143 adjacent to the second P-type region 144, the internal resistance of the second P-type region 144 is increased, and the internal resistance of the second P-type region 144 becomes a temperature characteristic adjustment resistor for gate protection. Therefore, the influence of the temperature characteristic (a characteristic that decreases with increasing temperature) of the forward voltage of the diode formed between the second P-type region 144 and the second N-type region 143 can be offset by the temperature characteristic (a characteristic that increases with increasing temperature) of the internal resistance of the second P-type region 144, thereby suppressing temperature fluctuations in the protection voltage of the gate protection section 142.

[0117] According to the semiconductor device 100 of Embodiment 1, since the resistance value of the temperature characteristic adjustment resistor 185 has a temperature characteristic, this temperature characteristic can cancel out the temperature change of the voltage after the overlap of the forward voltage of the diode formed by the first P-type region 184 in the diode section 186 and the first N-type region 182 adjacent to one side of the first P-type region 284 and the Zener voltage of the Zener diode formed by the first P-type region 184 and the first N-type region 182 adjacent to the other side of the first P-type region 184, so that the temperature change of the clamping voltage can be suppressed with higher precision.

[0118] According to the semiconductor device 100 of Embodiment 1, since the clamping voltage determining unit 180 covers the entire device region A1 when viewed from above, the cross-sectional area of ​​the current path (the cross-sectional area from the center to the outer periphery) is larger, allowing a larger current to flow. Therefore, the impedance is smaller, making it less likely for the clamping voltage to rise. In this way, a clamping voltage that is closer to the desired range can be applied.

[0119] However, in the breakdown voltage separation region A2, when multiple P-type guard rings are formed on the surface of the semiconductor substrate 110, electric field concentration can easily occur in the areas between adjacent guard rings where there are no guard rings, potentially leading to uneven electric field density and a decrease in peripheral breakdown voltage. To prevent this, the spacing between the guard rings needs to be reduced, but it is practically difficult to form guard rings with such a small spacing. Furthermore, there is a problem that this could affect the Zener voltage of the clamping voltage determining portion 180 on the field insulating film 170. In contrast, according to the semiconductor device 100 of Embodiment 1, since a P-type region for reducing surface electric field is formed on the surface of the semiconductor substrate 110 in the breakdown voltage separation region A2, the potential distribution becomes smoother, and electric field concentration is less likely to occur, thus achieving a stable peripheral breakdown voltage.

[0120] According to the semiconductor device 100 of Embodiment 1, since a P-type boundary semiconductor region 118 is formed to cover the boundary between the base region 113 and the reduced surface electric field region 116, the potential distribution near the boundary between the device region A1 and the breakdown voltage separation region A2 becomes gentler, making it easier to maintain the breakdown voltage. Furthermore, since it is formed at the same or deeper depth as the reduced surface electric field region 116, the potential distribution near the boundary becomes even gentler, making it easier to maintain the breakdown voltage.

[0121] According to the semiconductor device 100 of Embodiment 1, since the temperature characteristic adjustment resistor 185 is composed of a polycrystalline silicon layer with P-type impurities introduced, the resistance value can be easily adjusted by changing the impurity concentration and volume of the P-type impurities. Furthermore, it can be formed together with the first P-type region 184 and the first N-type region 182 of the diode section 186, as well as the gate protection section 142 and the lead-out wiring 146.

[0122] [Implementation Method 2]

[0123] Figure 7 This is a circuit diagram of the active clamping circuit 10a according to the second embodiment. Figure 8 This is a plan view of the semiconductor device 101 according to Embodiment 2.

[0124] The active clamping circuit 10a of Embodiment 2 has a configuration that is basically the same as that of the active clamping circuit 10 according to Embodiment 1, but it differs from the active clamping circuit 10 of Embodiment 1 in that the structure of the clamping voltage determining unit is different. For example Figure 7 As shown, in the active clamping circuit 10a of Embodiment 2, the diode section 36a of the clamping voltage determining section 30 further includes a second temperature characteristic adjusting resistor 32.

[0125] The diode section 36a has multiple groups 31. In each group 31, a Zener diode 33 is connected to one end of the second temperature characteristic adjustment resistor 32 (the drain electrode D1 side of the main switch Q1), and a diode 34 is connected to the other end of the second temperature characteristic adjustment resistor 32 (the gate electrode G1 side of the main switch Q1) in a manner opposite to the polarity of the Zener diode 33. The groups 31 are connected in series.

[0126] The semiconductor device 101 of Embodiment 2 has essentially the same structure as the semiconductor device 100 of Embodiment 1, but differs from the semiconductor device 100 of Embodiment 1 in the structure of the clamping voltage determining section. In the clamping voltage determining section 180 of the semiconductor device 101 of Embodiment 2, the total amount of impurities in the first P-type region 184 sandwiched between the two first N-type regions 182 is less than the total amount of impurities in any one of the two first N-type regions 182 adjacent to the first P-type region 184. Thus, the first P-type region 184 sandwiched between the two first N-type regions 182 has a resistive component and can constitute a second temperature-adjustable resistor 32.

[0127] In Embodiment 2, the impurity concentration of the first P-type region 184 is lower than that of the first N-type region 182. Therefore, due to the reduced number of charge carriers, the internal resistance of the first P-type region 184 is greater than that of the first N-type region 182 from the viewpoint of impurity concentration. Furthermore, the first P-type region 184... Figure 3 and Figure 5 The lateral width (radial length = current path length) of the first P-type region 184 is longer than that of the first N-type region 182. This is because it is not easy to strictly control the internal resistance by adjusting the impurity concentration introduced into the first P-type region 184. Therefore, the impurity concentration in the first P-type region 184 is adjusted by adjusting the lateral width (radial length = current path length) of the first P-type region 184. Therefore, although the lateral width (radial length = current path length) of the first P-type region 184 is longer than that of the first N-type region 182, from the viewpoint of internal resistance, the internal resistance of the first P-type region 184 is greater than that of the first N-type region 182.

[0128] In the clamping voltage determination section, the internal resistance of the first P-type region 184 sandwiched between two first N-type regions 182 has a temperature characteristic that, together with the temperature characteristic adjustment resistor 185, can cancel out the temperature change of the voltage after the overlap of the forward voltage of the diode formed by the first P-type region 184 and the first N-type region 182 adjacent to one side of the first P-type region 184 and the Zener voltage of the Zener diode formed by the first P-type region 184 and the first N-type region 182 adjacent to the other side of the first P-type region 184.

[0129] As described above, although the active clamping circuit 10a and semiconductor device 101 of Embodiment 2 differ from the active clamping circuit 10 and semiconductor device 100 of Embodiment 1 in the structure of the clamping voltage determination section, they are similar to Embodiment 1 in that they also have a clamping voltage control switch 20 and a clamping voltage determination section 30 with one terminal electrically connected to the drain electrode and the other terminal electrically connected to the gate electrode. Therefore, like conventional switching circuits, they can absorb surge voltages. In addition, since the clamping voltage control switch 20 has the function of sending a conduction signal to the gate electrodes G1 and G2 of the main switches Q1 and Q2, the drive current is small, and the current flowing through the clamping voltage determination section that determines the turn-off voltage as a trigger can be reduced. Furthermore, after the clamping voltage control switch and the main switches are turned on, the main switches Q1 and Q2 can be used as current paths for voltage clamping during the surge period, so large diodes can be eliminated.

[0130] According to the active clamping circuit 10a and semiconductor device 101 of embodiment 2, since the diode section 36a has multiple groups 31, in each group 31, a Zener diode 33 is connected to one end of the second temperature characteristic adjustment resistor 32 (the drain electrode D1 side of the main switch Q1), and a diode 34 is connected to the other end of the second temperature characteristic adjustment resistor 32 (the gate electrode G1 side of the main switch Q1) in a manner opposite to the polarity of the Zener diode 33. The groups 31 are connected in series, so the temperature change of the voltage after the forward voltage of the diode 34 and the Zener voltage of the Zener diode 33 are superimposed can be canceled by the temperature characteristic adjustment resistor 35 and the second temperature characteristic adjustment resistor 32 of each group 31.

[0131] Since the active clamping circuit 10a and semiconductor device 101 of Embodiment 2 have the same configuration as the active clamping circuit 10 and semiconductor device 100 of Embodiment 1, except for the structure of the clamping voltage determining unit, they also have the same effects as the active clamping circuit 10 and semiconductor device 100 of Embodiment 1.

[0132] [Implementation methods 3 to 7]

[0133] Figure 9 This is a plan view of the semiconductor device 102 according to Embodiment 3. Figure 10 This is a plan view of the semiconductor device 103 according to Embodiment 4. Figure 11 This is a plan view of the semiconductor device 104 according to Embodiment 5. Figure 12 This is a plan view of the semiconductor device 105 according to Embodiment 6. Figure 13 This is a plan view of the semiconductor device 106 according to Embodiment 7.

[0134] Semiconductor devices 102 to 106 in embodiments 3 to 7 basically have the same structure as semiconductor devices 100 and 101 in embodiments 1 and 2, but the structure of the clamping voltage determining unit differs from that of semiconductor devices 100 and 101 in embodiments 1 and 2. Figures 9 to 13 Although the diagram is based on Embodiment 2 (the embodiment with the second temperature characteristic adjustment resistor 32), the second temperature characteristic adjustment resistor 32 may also be omitted.

[0135] In the semiconductor device 102 of Embodiment 3, such as Figure 9 As shown, the temperature characteristic adjustment resistor 185 is formed on the inner peripheral side of the diode section 186.

[0136] The semiconductor device 103 in embodiment 4 is as follows Figure 10 As shown, it also has a metal channel barrier wire 190 formed on the outermost periphery, and a metal wire 192 formed on the inner side of the channel barrier wire 190, separated from the channel barrier wire 190 and forming a ring around the diode portion 186. The temperature characteristic adjustment resistor is composed of an outer peripheral P-type region 187 formed in the area between the channel barrier wire 190 and the metal wire 192. The channel barrier wire 190 and the metal wire 192 are connected by a connection wire 194 made of a conductive member (e.g., Al-Si).

[0137] Because the connecting wiring 194 prevents a short circuit between the channel blocking wiring 190 and the metal wiring 192, it is used to stop the outer peripheral first conductive region 187 from functioning as a temperature characteristic adjustment resistor. Therefore, by cutting the connecting wiring 194 with laser fusing or current fusing, based on the temperature characteristics of the Zener diode, the diode, and the main switch Q1, the outer peripheral first conductive region 187 can function as a temperature characteristic adjustment resistor, and the temperature characteristic adjustment function of the outer peripheral first conductive region 187 can be stopped while the connecting wiring 194 remains short-circuited (e.g., suitable when the temperature remains stable without needing to adjust the temperature characteristics). In other words, by choosing whether to cut the connecting wiring after the chip completion reaches a certain level, it is possible to choose whether to utilize or stop the temperature characteristic adjustment function, thereby allowing the temperature characteristics to be adjusted after the chip is completed.

[0138] In the semiconductor device 104 of embodiment 5, such as Figure 11As shown, the temperature characteristic adjustment resistor 188 introduces a P-type impurity that is different from the P-type impurity introduced into the first P-type region 184. Different P-type impurities refer to, for example, impurities with different impurity elements, or even the same impurity but different impurity concentrations and introduced impurity amounts. Furthermore, in Embodiment 5, the same impurity element (e.g., boron) is used, but the impurity amount is changed before introduction. This provides the advantage that the impurity amount and temperature coefficient can be adjusted simply by changing the impurity concentration. Additionally, in the semiconductor device 105 of Embodiment 6, as... Figure 12 As shown, a temperature-adjustable resistor 188 is formed on the inner circumference side.

[0139] In the semiconductor device 106 of embodiment 7, such as Figure 13 As shown, the temperature-adjusting resistor 189 introduces P-type impurities only in a designated region of the polysilicon layer surrounding device region A1 on the inner peripheral side of the diode portion 186. In this way, the cross-sectional area of ​​the temperature-adjusting resistor 189 relative to the current flow direction becomes smaller, and it becomes a resistive component, thus enabling it to function as a temperature-adjusting resistor.

[0140] As described above, although the structure of the clamping voltage determining section of the semiconductor devices 102 to 106 in embodiments 3 to 7 differs from that of the semiconductor devices 100 and 101 in embodiments 1 and 2, they are similar to embodiments 1 and 2 in that they also have a clamping voltage control switch 20 and a clamping voltage determining section 30 with one terminal electrically connected to the drain electrode and the other terminal electrically connected to the gate electrode. Therefore, like conventional switching circuits, they can absorb surge voltages. In addition, since the clamping voltage control switch 20 has the function of sending a conduction signal to the gate electrodes G1 and G2 of the main switches Q1 and Q2, the drive current is small, and the current flowing through the clamping voltage determining section that determines the turn-off voltage as a trigger can be reduced. Furthermore, after the clamping voltage control switch and the main switches are turned on, the main switches Q1 and Q2 can be used as current paths for voltage clamping during the surge period, so large diodes can be eliminated.

[0141] Since the semiconductor devices 102 to 106 of embodiments 3 to 7 have the same configuration as the semiconductor devices 100 and 101 of embodiments 1 and 2 except for the structure of the clamping voltage determining unit, they also have the same effects as the semiconductor devices 100 and 102 of embodiments 1 and 2.

[0142] [Implementation Method 8]

[0143] Figure 14 This is a circuit diagram of the active clamping circuit 10b in embodiment 8. Figure 15 This is a plan view of the semiconductor device 200 according to embodiment 8. Figure 15(a) is a plan view of semiconductor device 200. Figure 15 (b) is Figure 15 (a) Cross-sectional view. In Figure 15 In the diagram, symbol 213 represents the anode region, symbol 230 represents the positive electrode, and symbol 250 represents the negative electrode.

[0144] The active clamping circuit 10b and semiconductor device 200 of Embodiment 8 have a configuration that is basically the same as that of the active clamping circuit 10 and semiconductor device 100 of Embodiment 1. However, the difference between Embodiment 8 and Embodiment 1 is that a bypass diode is used instead of the lamp voltage control switch (see [reference]). Figures 14 to 15 In the active clamping circuit 10b according to embodiment 8, there is no gate protection section 40 or resistor 50.

[0145] The bypass diode 60 has an anode A and a cathode K. The anode A is electrically connected to the gate electrode G1 of the main switch Q1, and the cathode K is electrically connected to the drain electrode D1 of the main switch Q1. One end of the clamping voltage determining unit 30 is electrically connected to the cathode K of the bypass diode 60, and the other end is electrically connected to the anode A of the bypass diode 60.

[0146] The semiconductor device 200 of embodiment 8 does not have a gate pad 140, a first gate wiring 145, and a second gate wiring 147 in device region A1 (see reference). Figure 15 ).

[0147] In device region A1, such as Figure 15 As shown, the semiconductor substrate 210 has a low-resistance semiconductor layer 211, an N-type semiconductor region 212 (drift region) and a P-type anode region 213, and has a diode structure located between the anode region 213 and the drift region 212.

[0148] In the withstand voltage separation region A2, the clamping voltage determining part 280 is on the field insulating film 270, and multiple N-type regions 282 and multiple P-type regions 284 are arranged adjacent to each other and alternately. The N-type region 282 closest to the device region A1 is electrically connected to the anode, and the N-type region 282 furthest from the device region A1 is electrically connected to the cathode.

[0149] As described above, although the active clamping circuit 10a and semiconductor device 200 of Embodiment 8 differ from the active clamping circuit 10 and semiconductor device 100 of Embodiment 1 in that a bypass diode is used instead of a clamping voltage control switch, it still has the following features: a bypass diode 60; and a clamping voltage determining unit 30, one terminal of which is electrically connected to the anode A of the bypass diode 60, and the other terminal of which is electrically connected to the cathode K of the bypass diode 60. Therefore, it can absorb surge voltage and clamp the voltage. In addition, the current flowing through the clamping voltage determining unit 30 can be reduced, and the main switch can be used as a current path for voltage clamping during the period when the main switch is turned on and a surge is generated, thus eliminating the need to use a large diode.

[0150] According to the semiconductor device 200 of Embodiment 8, since a diode structure is formed in the region where the anode 230 is formed, and a clamping voltage determining unit 280 is provided with a plurality of first P-type regions 284 and a plurality of first N-type regions 282 arranged adjacent to each other and alternately, it can be used as an active clamping circuit 10a having a bypass diode 60; one terminal is electrically connected to the anode A of the bypass diode 60, and the other terminal is electrically connected to the cathode K of the bypass diode 60. Therefore, surge voltage can be absorbed to clamp the voltage. In addition, the current flowing through the clamping voltage determining unit 30 can be reduced, and the main switch can be used as a current path for voltage clamping during the period when the main switch is turned on and a surge voltage is generated, so it is not necessary to use a large diode.

[0151] Since the active clamping circuit 10b and semiconductor device 200 of Embodiment 8 have the same configuration as the active clamping circuit 10 and semiconductor device 100 of Embodiment 1, they have the same effect as the active clamping circuit 10 and semiconductor device 100 of Embodiment 1, except for the difference of having a bypass diode instead of a clamping voltage control switch.

[0152] The present invention has been described above based on the embodiments described above, but the present invention is not limited to the embodiments described above. It can be implemented in various ways without departing from the concept, for example, the following modifications can be made.

[0153] (1) The positions, connections, quantities, etc. described in the above embodiments are only examples and can be changed within the scope of not impairing the effect of the present invention.

[0154] (2) Although a gate protection section is provided in embodiments 1 to 7 described above, the present invention is not limited thereto. A gate protection section may not be provided. In addition, a temperature-adjustable resistor is used as the resistor for the gate protection section, but a regular resistor without temperature-adjustable function may also be used, or no resistor may be used at all.

[0155] (3) In the above embodiments, a boundary semiconductor region is formed by connecting the base region to the reduced surface electric field region and covering the boundary between the base region and the reduced surface electric field region. However, the present invention is not limited to this. The base region may also not be in contact with the reduced surface electric field region. In this case, the boundary semiconductor region is formed between the base region and the reduced surface electric field region. In this case, the depth of the boundary semiconductor region is preferably the same as or deeper than the depth of the reduced surface electric field region. This is because, in this way, the potential distribution near the boundary between the device region and the breakdown voltage separation region becomes gentler, making it easier to maintain the breakdown voltage.

[0156] [Symbol Explanation]

[0157] 1…Switching circuit; 10, 10a, 10b…Active clamping circuit; 20…Clamping voltage control switch; 30, 30a…Clamping voltage determining unit; 31…Group; 32…Second temperature characteristic adjusting resistor; 33…Zener diode; 34…Zener diode; 35…Temperature characteristic adjusting resistor; 36…Diode section; 40…Gate protection section; 41…Group; 42…Temperature characteristic adjusting resistor; 43…Zener gate protection diode; 44…Gate protection diode Diode; 50… Resistor; 60… Bypass diode; 100, 101, 102, 103, 104, 105, 106, 200… Semiconductor device; 110… Semiconductor substrate; 111, 211… Low-resistance semiconductor layer; 112, 212… Drift layer; 113… Base region; 114… Source region; 115… N-type semiconductor layer; 116… Region with reduced surface electric field; 117… Channel blocking region; 118… Boundary semiconductor region ; 119…P-type semiconductor layer; 120…Gate electrode; 122…Gate insulating film; 124…Interlayer insulating film; 130…Source electrode; 140…Gate pad; 141…Polysilicon layer; 142…Gate protection portion; 143…Second N-type region; 144…Second P-type region; 145…Gate wiring; 146…Gate lead wiring; 147…Second gate wiring; 150…Drain electrode; 160…Protective insulating film; 170, 270…Field insulation Film; 172… Polycrystalline silicon layer; 180, 280… Clamping voltage determining part; 182, 282… First N-type region; 184, 284… First P-type region; 186… Third P-type region; 190… Channel blocking electrode; 213… Anode region; 230… Anode; A1… Device region; A11… Active region; A12… Peripheral region; A2… Withstand voltage separation region; Q1… First main switch; Q2… Second main switch; Vcc… External power supply.

Claims

1. An active clamping circuit, connected between the control electrode and the main electrode of a main switch, for controlling the clamping voltage of the main switch, characterized in that, include: A clamping voltage control switch has a first main electrode, a second main electrode, and a control electrode, wherein the second main electrode is electrically connected to the main electrode of the main switch, and the first main electrode is electrically connected to the control electrode of the main switch. as well as The clamping voltage determining unit has one end electrically connected to the second main electrode of the clamping voltage control switch, and the other end electrically connected to the control electrode of the clamping voltage control switch. The clamping voltage determining unit includes: a diode unit, which is connected in series with a plurality of groups consisting of at least Zener diodes and diodes connected in series with opposite polarities; and a temperature characteristic adjusting resistor, which is connected in series with the diode unit.

2. The active clamping circuit according to claim 1, characterized in that... Further includes: The gate protection section has one end connected to the control electrode of the clamping voltage control switch, and the other end electrically connected to the control electrode of the main switch and the first main electrode of the clamping voltage control switch. The gate protection section includes at least one group of gate protection Zener diodes and gate protection diodes connected with opposite polarities.

3. The active clamping circuit according to claim 2, characterized in that: in, The group of gate protection sections each has a structure in which a gate protection temperature characteristic adjustment resistor is electrically connected between the gate protection Zener diode and the gate protection diode.

4. An active clamping circuit, connected between the control electrode and the main electrode of a main switch, for controlling the clamping voltage of the main switch, characterized in that, include: A bypass diode having an anode and a cathode, wherein the anode is electrically connected to the control electrode of the main switch, and the cathode is electrically connected to the main electrode of the main switch; as well as The clamping voltage determining unit has one terminal electrically connected to the cathode of the bypass diode, and the other terminal electrically connected to the anode of the bypass diode and the control electrode of the main switch. The clamping voltage determining unit includes: a diode unit, which is connected in series with a plurality of groups consisting of at least Zener diodes and diodes connected in series with opposite polarities; and a temperature characteristic adjusting resistor, which is connected in series with the diode unit.

5. The active clamping circuit according to any one of claims 1 to 4, characterized in that: in, The temperature-adjustable resistor has a temperature characteristic that reduces the temperature change of the voltage applied to the diode.

6. A semiconductor device connected between a control electrode and a main electrode of a main switch, constituting an active clamping circuit for controlling the clamping voltage of the main switch, formed on a semiconductor substrate defining a device region and a voltage-resistant separation region formed around the device region, characterized in that: The device region includes: The semiconductor substrate; The first main electrode is formed on the surface of the semiconductor substrate. A gate pad is formed on the surface of the semiconductor substrate at a location separate from the first main electrode; and The second main electrode is formed on the surface of the back side of the semiconductor substrate. A MOS structure is formed in the region where the first main electrode is formed, and the breakdown voltage separation region includes: The semiconductor substrate; The second main electrode is formed on the surface of the back side of the semiconductor substrate; An insulating film is formed on the surface of the semiconductor substrate; and A clamping voltage determining part, which is disposed on the insulating film in the region surrounding the device area when viewed from above, has one end electrically connected to the gate pad and the other end electrically connected to the second main electrode. The clamping voltage determining unit includes: a diode section in which multiple first conductivity type regions and multiple first conductivity type regions are adjacent to each other and alternately arranged; and a temperature characteristic adjusting resistor connected in series with the diode section. The temperature-adjusting resistor has a temperature characteristic that corresponds to the temperature characteristic of the diode section.

7. The semiconductor device according to claim 6, characterized in that, Further includes: A gate protection portion, wherein, when viewed from above, on the region surrounding the gate pad on the insulating film, at least one second first conductivity type region is adjacent to and alternately arranged with at least two second second conductivity type regions.

8. The semiconductor device according to claim 7, characterized in that: in, In the gate protection section, the total amount of impurities in the second first conductivity type region sandwiched between the two second second conductivity type regions is less than the total amount of impurities in either of the two second second conductivity type regions adjacent to the second first conductivity type region.

9. A semiconductor device connected between a control electrode and a main electrode of a main switch, constituting an active clamping circuit for controlling the clamping voltage of the main switch, formed on a semiconductor substrate defining a device region and a voltage-resistant separation region formed around the device region, characterized in that: The device region includes: The semiconductor substrate; A first main electrode is formed on the surface of the semiconductor substrate; and The second main electrode is formed on the surface of the back side of the semiconductor substrate. A diode structure is formed in the region where the first main electrode is formed, and the voltage-resistant separation region includes: The semiconductor substrate; The second main electrode is formed on the surface of the back side of the semiconductor substrate; An insulating film is formed on the surface of the semiconductor substrate; and A clamping voltage determining part, which is disposed on the insulating film in the region surrounding the device area when viewed from above, has one end electrically connected to the first main electrode and the other end electrically connected to the second main electrode. The clamping voltage determining unit includes: a diode section in which multiple first conductivity type regions and multiple first conductivity type regions are adjacent to each other and alternately arranged; and a temperature characteristic adjusting resistor connected in series with the diode section. The temperature-adjusting resistor has a temperature characteristic that corresponds to the temperature characteristic of the diode section.

10. The semiconductor device according to any one of claims 6 to 9, characterized in that: in, The temperature characteristic adjustment resistor has a temperature characteristic that cancels out the temperature change of the voltage formed by the forward voltage of the diode formed by the first first conductivity type region in the diode section and the first second conductivity type region adjacent to one side of the first first conductivity type region, and the voltage of the Zener diode formed by the first first conductivity type region and the first second conductivity type region adjacent to the other side of the first first conductivity type region.

11. The semiconductor device according to any one of claims 6 to 9, characterized in that: in, The clamping voltage determining part covers the entire area surrounding the device when viewed from above.

12. The semiconductor device according to any one of claims 6 to 9, characterized in that: in, In the pressure-resistant separation region, a first conductivity type reduced surface electric field region is formed on the surface of the semiconductor substrate.

13. The semiconductor device according to claim 12, characterized in that: in, A first conductivity type region is formed on the surface of the device region. Furthermore, a boundary semiconductor region of a first conductivity type is formed, which is formed in such a way that it covers the boundary between the surface first conductivity type region and the surface electric field reduction region.

14. The semiconductor device according to claim 12, characterized in that: in, A first conductivity type region is formed on the surface of the device region. Between the first conductivity type region on the surface and the reduced surface electric field region, a boundary semiconductor region of the first conductivity type is formed, which is formed to the same depth as or deeper than either the first conductivity type region on the surface or the reduced surface electric field region of the semiconductor substrate.

15. The semiconductor device according to any one of claims 6 to 9, characterized in that: in, The temperature-adjustable resistor is composed of a polycrystalline silicon layer with P-type impurities introduced into it.

16. The semiconductor device according to any one of claims 6 to 9, characterized in that: in, The temperature characteristic adjustment resistor is formed after introducing a second conductivity impurity that is different from the second conductivity impurity in the first and second conductivity regions.

17. The semiconductor device according to any one of claims 6 to 9, characterized in that, Further includes: Metal channels formed on the outermost periphery prevent wiring; as well as Metallic wiring, which is separated from the channel blocking wiring inside the channel blocking wiring and surrounds the circumference of the diode portion, The temperature-adjusting resistor is composed of a first conductive region on the outer periphery of the region formed between the channel barrier wiring and the metal wiring. The channel blocking wiring is connected to the metal wiring via a connecting wiring made of conductive components.

18. The semiconductor device according to any one of claims 6 to 9, characterized in that: in, The temperature-adjustable resistor is formed only in a specified portion around the device region.

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