Semiconductor device

Abstract

A semiconductor device includes: a chip having a main surface; a high-concentration region of a first conductivity type formed on a surface layer portion of the main surface on the inner side of the chip; and a low-concentration region of the first conductivity type, which is formed on the surface layer portion of the main surface on the peripheral edge portion side of the chip, and which has an impurity concentration lower than that of the high-concentration region.

Description

Technical Field

[0001] This application claims priority to Japan Patent Application No. 2023-056618, filed on March 30, 2023, the entire contents of which are incorporated herein by reference. This disclosure relates to a semiconductor device. Background Technology

[0002] Patent document 1 (US2008 / 0277669A1) discloses a semiconductor device having a termination structure in the outer peripheral region of a drift layer.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2008 / 0277669 Summary of the Invention

[0006] This disclosure provides a semiconductor device with a novel structure.

[0007] This disclosure provides a semiconductor device, comprising: a chip having a main surface; a high-concentration region of a first conductivity type formed on a surface portion of the main surface on an inner side of the chip; and a low-concentration region of the first conductivity type formed on a surface portion of the main surface on a peripheral side of the chip, having an impurity concentration lower than that of the high-concentration region.

[0008] This disclosure provides a semiconductor device, comprising: a chip having a main surface; an active region disposed on an inner portion of the main surface; an outer peripheral region disposed on a peripheral portion of the main surface; a high-concentration region of a first conductivity type formed in the active region on a surface portion of the main surface; and a low-concentration region of a first conductivity type formed in the outer peripheral region on a surface portion of the main surface, having an impurity concentration lower than that of the high-concentration region.

[0009] The above or other objects, features, and effects become clear from the detailed description with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a top view of a semiconductor device in the first configuration.

[0011] Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown.

[0012] Figure 3 From Figure 2 The cross-sectional view shown is the cross-sectional view after removing the structures other than the chip.

[0013] Figure 4 This is a top view showing an example layout of the first main face.

[0014] Figure 5 This is a top view showing a layout example of high-concentration and low-concentration areas.

[0015] Figure 6 It is an enlarged top view showing the main part of the first main surface.

[0016] Figure 7 This is an enlarged top view showing another major part of the first main surface.

[0017] Figure 8 It is along Figure 7 The cross-sectional view of line VIII-VIII shown.

[0018] Figure 9 It means Figure 8 Enlarged sectional view of the main part.

[0019] Figure 10 It is along Figure 7 The sectional view shown is along line XX.

[0020] Figure 11 It means Figure 10 Enlarged sectional view of the main part.

[0021] Figure 12 This is a cross-sectional view showing the main parts of the semiconductor device of the second type.

[0022] Figure 13 It is a cross-sectional view showing the main parts of a third-party semiconductor device.

[0023] Figure 14 It means Figure 13 A cross-sectional view of a modified example of the semiconductor device shown.

[0024] Figure 15 This is a cross-sectional view showing the main parts of a fourth-mode semiconductor device.

[0025] Figure 16 This is an enlarged top view showing the main parts of the fifth type of semiconductor device.

[0026] Figure 17 It is along Figure 16 A cross-sectional view of line XVII-XVII shown.

[0027] Figure 18 This is a top view of a semiconductor device representing the sixth method.

[0028] Figure 19 It is along Figure 18The cross-sectional view of the XIX-XIX line shown.

[0029] Figure 20 This is a cross-sectional view showing a semiconductor device in the seventh configuration.

[0030] Figure 21 This is a cross-sectional view showing the semiconductor device in the eighth configuration.

[0031] Figure 22 This is a cross-sectional view of a semiconductor device in the ninth configuration.

[0032] Figure 23 This is a cross-sectional view showing a modified example of the outer main body area.

[0033] Figure 24 It is a cross-sectional view showing a deformed example of the field region.

[0034] Figure 25 This is a cross-sectional view showing a first modified example of the source pad electrode.

[0035] Figure 26 This is a cross-sectional view showing a second modified example of the source pad electrode. Detailed Implementation

[0036] The specific methods are explained in detail below with reference to the accompanying drawings. The drawings are schematic diagrams, not strict illustrations; relative positions, scales, ratios, angles, etc., may not be consistent. Corresponding structures in the drawings are labeled with the same reference symbols, and repeated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions preceding the omission or simplification shall apply.

[0037] When the term "substantially" is used in this specification, it includes not only the numerical value (method) that is equal to the numerical value (method) of the comparison object, but also a numerical error (method error) within ±10% of the numerical value (method) of the comparison object. In the following description, terms such as "first," "second," and "third" are used, but these are notations assigned to the names of each structure to clarify the order of description, and are not intended to limit the names of the structures.

[0038] In the following description, "p-type" or "n-type" is used to refer to the conductivity type of the semiconductor (impurity), but "p-type" can also be called the "first conductivity type" and "n-type" the "second conductivity type." Conversely, "n-type" can also be called the "first conductivity type" and "p-type" the "second conductivity type." "P-type" is the conductivity type originating from trivalent elements, and "n-type" is the conductivity type originating from pentavalent elements. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0039] Figure 1 This is a top view of the semiconductor device 1A in the first configuration. Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown. Figure 3 From Figure 2 The cross-sectional view shown is the cross-sectional view after removing the structures other than the chip. Figure 4 This is a top view showing a layout example of the first main face 3. Figure 5 This is a top view showing a layout example of high-concentration region 10 and low-concentration region 11.

[0040] Figure 6 This is an enlarged top view showing the main part of the first main surface 3. Figure 7 This is an enlarged top view showing another major part of the first main surface 3. Figure 8 It is along Figure 7 The cross-sectional view of line VIII-VIII shown.

[0041] Figure 9 It means Figure 8 Enlarged sectional view of the main part. Figure 10 It is along Figure 7 The sectional view shown is along line XX. Figure 11 It means Figure 10 Enlarged sectional view of the main part.

[0042] Reference Figures 1 to 11 Semiconductor device 1A is a semiconductor switching device having an insulated-gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1A is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 can also be referred to as a "SiC chip" or a "semiconductor chip".

[0043] In this embodiment, chip 2 is constructed from hexagonal SiC single crystals and formed into a cuboid shape. Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. This embodiment shows an example where chip 2 is constructed from 4H-SiC single crystals, but chip 2 can also be constructed from other polymorphs.

[0044] Chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are quadrilateral in shape when viewed from above (hereinafter referred to as "top view") in the vertical direction Z. The vertical direction Z is also the thickness direction of chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 can also be square or rectangular in the top view.

[0045] The first main surface 3 and the second main surface 4 are preferably formed from the c-plane of a SiC single crystal. In this case, the first main surface 3 is preferably formed from the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed from the carbon surface ((000-1) surface) of the SiC single crystal.

[0046] The first side surface 5A and the second side surface 5B extend along the first main surface 3 in a first direction X and are opposite each other along the first main surface 3 in a second direction Y that intersects the first direction X. Specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and are opposite each other in the first direction X.

[0047] In this method, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X can be the a-axis direction of the SiC single crystal, and the second direction Y can be the m-axis direction of the SiC single crystal.

[0048] Chip 2 (first main surface 3 and second main surface 4) has a deviation angle that is tilted at a predetermined angle in a predetermined deviation direction relative to the c-plane of the SiC single crystal. That is, the amount of the deviation angle by which the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical axis toward the deviation direction. In addition, the amount of the deviation angle by which the c-plane of the SiC single crystal is tilted relative to the horizontal plane.

[0049] The deviation direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The deviation angle can be greater than 0° and less than 10°. The deviation angle can have a value belonging to at least one of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0050] The deviation angle is preferably 5° or less. Particularly preferred is a deviation angle of 2° or more but less than 4.5°. The deviation angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a deviation angle of 0° (i.e., the first main surface 3 is facing the front relative to surface c).

[0051] In this configuration, chip 2 has a stacked structure including a first semiconductor layer 6 and a second semiconductor layer 7. The first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal) and has the aforementioned offset direction and offset angle. The first semiconductor layer 6 forms a second main surface 4 and a portion of the first to fourth side surfaces 5A to 5D.

[0052] The first semiconductor layer 6 may also have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value belonging to at least one of the following ranges: 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0053] The second semiconductor layer 7 is composed of an epitaxial layer including a SiC single crystal (semiconductor single crystal), and is stacked on the first semiconductor layer 6. The second semiconductor layer 7 has the aforementioned offset direction and offset angle. The second semiconductor layer 7 forms a first main surface 3 and a portion of the first to fourth side surfaces 5A to 5D. The second semiconductor layer 7 preferably has a thickness less than that of the first semiconductor layer 6. Of course, the thickness of the second semiconductor layer 7 can also be greater than that of the first semiconductor layer 6.

[0054] The thickness of the second semiconductor layer 7 can be 5 μm or more and 50 μm or less. The thickness of the second semiconductor layer 7 can have a value belonging to at least one of the following ranges: 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, and 45 μm or more and 50 μm or less.

[0055] Semiconductor device 1A includes an active region 8 disposed on chip 2 (first main surface 3). The active region 8 is disposed on the inner side of chip 2 (first main surface 3). The active region 8 is a region that includes a device structure (transistor structure Tr) and generates output current (drain current).

[0056] The active region 8 is disposed on the inner side of the chip 2 at intervals from the periphery (first to fourth sides 5A to 5D) of the chip 2 when viewed from above. The active region 8 is configured to be a polygon with four sides parallel to the periphery of the chip 2 when viewed from above (in this configuration, it is a quadrilateral shape). The planar area of ​​the active region 8 is preferably 50% or more and 90% or less of the planar area of ​​the first main surface 3.

[0057] Semiconductor device 1A includes an outer peripheral region 9 disposed in chip 2 outside the active region 8. The outer peripheral region 9 is a region excluding device structures (transistor structures Tr). The outer peripheral region 9 is disposed at the periphery of chip 2 (first main surface 3). That is, in a top view, the outer peripheral region 9 is disposed in the region between the periphery of chip 2 and the active region 8. The outer peripheral region 9 extends in a strip along the active region 8 in a top view, and is configured as a polygonal ring surrounding the active region 8 (in this case, a quadrilateral ring).

[0058] Semiconductor device 1A includes an n-type high-concentration region 10 formed on the surface portion of a first main surface 3, having a relatively high first impurity concentration. A drain potential, serving as a high potential (first potential), is assigned to the high-concentration region 10. The high-concentration region 10 may also be referred to as a "first region," "first drift region," or "first high-concentration drift region," etc. The first impurity concentration can be 1 × 10⁻⁶. 16 cm -3 Above and 5×10 17 cm -3 the following.

[0059] A high-concentration region 10 is formed on the inner side of the chip 2. Specifically, the high-concentration region 10 is formed in the surface portion of the first main surface 3 within the active region 8, extending in layers along the first main surface 3. The high-concentration region 10 is formed as a low-resistance region (first low-resistance region) with a relatively low resistance value within the active region 8. The high-concentration region 10 is preferably formed over the entire area of ​​the active region 8. The high-concentration region 10 may also extend substantially perpendicular to the first main surface 3 in cross-section.

[0060] In this configuration, the high-concentration region 10 extends from the active region 8 to the peripheral region 9, and the peripheral region 9 has a portion located on the surface of the first main surface 3. The high-concentration region 10 extends from the active region 8 to the peripheral region 9 over the entire circumference and is formed at intervals from the periphery of the first main surface 3 inward.

[0061] The high-concentration region 10 is preferably formed in a spaced-inward manner from at least one of the first to fourth side surfaces 5A to 5D. In this manner, the high-concentration region 10 is formed in a spaced-inward manner from the entire circumference of the first to fourth side surfaces 5A to 5D, and has a peripheral portion surrounding the active region 8.

[0062] In this configuration, the high-concentration region 10 is formed on the second semiconductor layer 7. For example, the high-concentration region 10 can also be formed by introducing an n-type impurity into the surface portion of the second semiconductor layer 7 (e.g., an n-type second semiconductor layer 7). The high-concentration region 10 is formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and is opposed to the first semiconductor layer 6 across a portion of the second semiconductor layer 7.

[0063] The high-concentration region 10 is preferably formed by spacing from a depth position in the middle of the second semiconductor layer 7 toward the first main surface. That is, the thickness of the high-concentration region 10 is preferably less than half the thickness of the second semiconductor layer 7. Of course, the high-concentration region 10 may also extend across the depth position in the middle of the second semiconductor layer 7 in the thickness direction. That is, the thickness of the high-concentration region 10 may also be greater than half the thickness of the second semiconductor layer 7.

[0064] The high-concentration region 10 may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the high-concentration region 10 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0065] Semiconductor device 1A has a second impurity concentration that is lower than the first impurity concentration of the high-concentration region 10, including an n-type low-concentration region 11 formed on the surface portion of the first main surface 3. The low-concentration region 11 may also be referred to as a "second region," a "second drift region," or a "first low-concentration drift region," etc. The second impurity concentration can be 1 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 the following.

[0066] The low-concentration region 11 is formed on the peripheral side of the chip 2 relative to the high-concentration region 10. Specifically, the low-concentration region 11 is formed in the outer peripheral region 9 on the surface of the first main surface 3, extending in layers along the first main surface 3. The low-concentration region 11 is located in the region between the periphery of the first main surface 3 and the high-concentration region 10. The low-concentration region 11 is formed in the outer peripheral region 9 as a high-resistance region (first high-resistance region) with a higher resistance value than the high-concentration region 10.

[0067] The low-concentration region 11 extends in a strip along the high-concentration region 10 (active region 8) when viewed from above. The low-concentration region 11 has a portion extending in a strip along a first direction X and a portion extending in a strip along a second direction Y when viewed from above, thus dividing the high-concentration region 10 (active region 8) from multiple directions. In this configuration, the low-concentration region 11 is formed in a ring shape (specifically a quadrilateral ring) surrounding the high-concentration region 10 (active region 8) when viewed from above.

[0068] The low-concentration region 11 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the low-concentration region 11 is connected to the peripheral portion of the high-concentration region 10. Thus, the low-concentration region 11 and the high-concentration region 10 are electrically connected. In this configuration, the low-concentration region 11 is connected to the high-concentration region 10 in the outer peripheral region 9. Preferably, the outer edge portion of the low-concentration region 11 is exposed from at least one of the first to fourth side surfaces 5A to 5D. In this configuration, the outer edge portion of the low-concentration region 11 is fully exposed from all of the first to fourth side surfaces 5A to 5D.

[0069] In this configuration, the low-concentration region 11 is formed at a depth that extends across the bottom of the high-concentration region 10 in the thickness direction, and is deeper than the high-concentration region 10. That is, the low-concentration region 11 has a bottom located below the bottom of the high-concentration region 10 (on the side of the second main surface 4). The low-concentration region 11 forms the boundary portion 12 of the region extending in the thickness direction of the chip 2 between the high-concentration region 10 and the chip 2 (see reference). Figure 10 In this manner, the regional boundary portion 12 is formed at intervals from the bottom of the low concentration region 11 toward the first main surface 3.

[0070] The region boundary portion 12 is formed substantially perpendicular to the first main surface 3. Specifically, the region boundary portion 12 has an upper end portion, a lower end portion, and an extension portion. The upper end portion is located on the side of the first main surface 3. The lower end portion is located on the side of the second main surface 4 and is located on substantially the same straight line as the upper end portion in the thickness direction. The extension portion extends substantially perpendicular to the first main surface 3 between the upper end portion and the lower end portion.

[0071] In this configuration, a low-concentration region 11 is formed in the second semiconductor layer 7. The low-concentration region 11 is preferably located at a depth that traverses the middle portion of the second semiconductor layer 7 in the thickness direction. That is, the thickness of the low-concentration region 11 is preferably more than 1 / 2 of the thickness of the second semiconductor layer 7. In this configuration, the low-concentration region 11 is formed within the second semiconductor layer 7 over the entire thickness range between the first main surface 3 and the bottom (first semiconductor layer 6) of the second semiconductor layer 7, and is connected to the first semiconductor layer 6.

[0072] For example, the high-concentration region 10 can also be formed by introducing an n-type impurity into the surface portion of the second semiconductor layer 7 (e.g., an n-type second semiconductor layer 7). In this manner, the low-concentration region 11 is formed using the n-type second semiconductor layer 7 and has a thickness corresponding to the thickness of the second semiconductor layer 7. In this manner, the semiconductor device 1A has a single-layer structure composed of the low-concentration region 11 at the periphery (outer peripheral region 9) of the second semiconductor layer 7.

[0073] Semiconductor device 1A includes an n-type inner low-concentration region 13 formed on the surface portion of the first main surface 3, below the high-concentration region 10. The inner low-concentration region 13 may also be referred to as a "third region," "third drift region," or "second low-concentration drift region," etc. The third impurity concentration can be 1 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 the following.

[0074] The inner low-concentration region 13 is formed on the inner side of the chip 2 relative to the low-concentration region 11. Specifically, the inner low-concentration region 13 is formed in the active region 8 below the high-concentration region 10. The inner low-concentration region 13 is formed as a high-resistance region (second high-resistance region) in the active region 8 with a higher resistance value than the high-concentration region 10. The inner low-concentration region 13 extends in a layer along the high-concentration region 10 and is connected to the high-concentration region 10 in the thickness direction. Thus, the inner low-concentration region 13 is electrically connected to the high-concentration region 10.

[0075] The inner low-concentration region 13 is preferably formed over the entire region below the high-concentration region 10, and is connected to the entire region of the high-concentration region 10 in the thickness direction. In this manner, the inner low-concentration region 13 is formed over the entire region of the active region 8. The inner low-concentration region 13 is further extended from the active region 8 to the outer peripheral region 9, where it is connected to the region on the bottom side of the low-concentration region 11.

[0076] Thus, the inner low-concentration region 13 is electrically connected to the low-concentration region 11. In this configuration, the inner low-concentration region 13 extends from the active region 8 to the outer peripheral region 9 throughout the entire circumference and is connected to the inner edge of the low-concentration region 11 throughout the entire circumference. The third impurity concentration of the inner low-concentration region 13 is preferably approximately equal to the second impurity concentration of the region on the bottom side of the low-concentration region 11.

[0077] In this configuration, an inner low-concentration region 13 is formed in the second semiconductor layer 7. The inner low-concentration region 13 is formed within the second semiconductor layer 7 over the entire thickness range between the high-concentration region 10 and the bottom of the second semiconductor layer 7 (the first semiconductor layer 6), and is connected to the first semiconductor layer 6.

[0078] For example, the inner low-concentration region 13 can also be formed by introducing an n-type impurity into the surface portion of the second semiconductor layer 7 (e.g., an n-type second semiconductor layer 7). In this manner, the inner low-concentration region 13 is formed using a portion (the bottom-side region) of the n-type second semiconductor layer 7. The semiconductor device 1A has a multilayer structure including a high-concentration region 10 and an inner low-concentration region 13 in the inner portion (active region 8) of the second semiconductor layer 7.

[0079] Semiconductor device 1A includes an n-type base region 14 formed in a region (surface layer) on the side of the second main surface 4 within chip 2. The base region 14 may also be referred to as a "fourth region," "drain region," etc. The base region 14 has a fourth impurity concentration that is higher than the first impurity concentration of the high-concentration region 10. The fourth impurity concentration can be 5 × 10⁻⁶. 17 cm -3 Above and 3×10 19 cm -3 the following.

[0080] The base region 14 is formed on the inner side of the chip 2 below the high-concentration region 10 and is electrically connected to the high-concentration region 10. The base region 14 extends from the region below the high-concentration region 10 to the peripheral side of the chip 2, and has a portion located below the low-concentration region 11. The base region 14 is electrically connected to the low-concentration region 11 on the peripheral side of the chip 2.

[0081] That is, the base region 14 has a portion that is electrically connected to the high-concentration region 10 in the active region 8. In this configuration, the base region 14 is connected to the inner low-concentration region 13 in the active region 8, and is electrically connected to the high-concentration region 10 via the inner low-concentration region 13. Furthermore, the base region 14 extends from the active region 8 to the outer peripheral region 9, where it has a portion that is electrically connected to the low-concentration region 11. The base region 14 is formed as a low-resistance region with relatively low resistance values ​​in both the active region 8 and the outer peripheral region 9.

[0082] The base region 14 extends in layers along the second main surface 4, is exposed from the second main surface 4 of the chip 2, and is also exposed from a portion of the first side surfaces 5A to 5D of the chip 2. The base region 14 has a thickness greater than that of the high-concentration region 10, the low-concentration region 11, and the inner low-concentration region 13.

[0083] In this configuration, a base region 14 is formed on the first semiconductor layer 6. The base region 14 is formed over the entire thickness range between the lower end (second main surface 4) and the upper end (second semiconductor layer 7) of the first semiconductor layer 6, and is connected to the second semiconductor layer 7. In this configuration, the base region 14 is formed using an n-type first semiconductor layer 6 and has a thickness corresponding to the thickness of the first semiconductor layer 6.

[0084] Semiconductor device 1A includes a plurality of p-type main regions 20 formed in the surface portion of a first main surface 3 in an active region 8. The plurality of main regions 20 are formed in the surface portion of a high-concentration region 10. The plurality of main regions 20 are given a source potential that is a low potential (second potential) different from a high potential (first potential).

[0085] Multiple main regions 20 are arranged at intervals along the first direction X, forming stripes extending along the second direction Y. That is, the multiple main regions 20 are arranged in a stripe-like pattern extending along the second direction Y. In addition, the extension direction of the multiple main regions 20 is consistent with the offset direction of the SiC single crystal.

[0086] Multiple main regions 20 are formed spaced apart from the bottom of the high-concentration region 10 toward the first main surface 3, and are opposite to the inner low-concentration region 13 (base region 14) across a portion of the high-concentration region 10. Preferably, the multiple main regions 20 are formed spaced apart from the middle portion of the high-concentration region 10 toward the first main surface 3. Alternatively, the multiple main regions 20 may extend across the depth of the middle portion of the high-concentration region 10 in the thickness direction. The multiple main regions 20 are exposed from the first main surface 3.

[0087] The multiple main body regions 20 may each have a width of 1 μm or more and 10 μm or less. The width of the main body region 20 may have a value belonging to at least one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. Preferably, the width of the main body region 20 is 2 μm or more and 5 μm or less.

[0088] The multiple main regions 20 may each have a thickness (depth) of 0.1 μm or more and 2.5 μm or less. The thickness of the main region 20 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, and 2 μm or more and 2.5 μm or less. The thickness of the main region 20 is preferably 0.5 μm or more and 1.5 μm or less.

[0089] Multiple body regions 20 consist of a high-concentration region 10 and a pn junction (pn junction diode: body diode). When a reverse bias voltage is applied to the pn junction, the multiple body regions 20 cause the depletion layer to extend toward the high-concentration region 10. The depletion layer extends from the high-concentration region 10 side toward the low-concentration region 11 in a horizontal direction along the first main surface 3.

[0090] That is, the extent of the depletion layer extends towards the periphery of the chip 2 through the low-concentration region 11. In the case of a device structure with a vertical structure, a lateral breakdown voltage is required on the periphery side (outer peripheral region 9 side) of the chip 2. In this regard, according to the low-concentration region 11, the breakdown voltage on the periphery side (outer peripheral region 9 side) of the chip 2 is increased, and the breakdown voltage is increased.

[0091] In this configuration, the depletion layer extends from the high-concentration region 10 towards the inner low-concentration region 13 in the thickness direction of chip 2. That is, the extent of the depletion layer is expanded through the inner low-concentration region 13. In the case of a device structure with a vertical orientation, a longitudinal breakdown voltage is required on the inner side (active region 8) of chip 2. Regarding this, the breakdown voltage is increased on the inner side (active region 8 side) of chip 2, and the breakdown voltage is increased, based on the inner low-concentration region 13.

[0092] Semiconductor device 1A includes a p-type outer body region 21 formed in the outer peripheral region 9 on the surface layer of a first main surface 3. The outer body region 21 is formed in either or both of the surface layer of a high-concentration region 10 and the surface layer of a low-concentration region 11. In this configuration, the outer body region 21 is formed in the surface layer of the high-concentration region 10.

[0093] The outer main body region 21 preferably has a p-type impurity concentration that is approximately equal to that of the main body region 20. Of course, the p-type impurity concentration of the outer main body region 21 can be lower or higher than that of the main body region 20.

[0094] The outer main body region 21 is formed at intervals on the surface of the high concentration region 10 from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a strip along the active region 8. The outer main body region 21 has a portion that extends in a strip along the first direction X and a portion that extends in a strip along the second direction Y when viewed from above, thus dividing the active region 8 in multiple directions.

[0095] In this configuration, the outer main body region 21 surrounds the active region 8 when viewed from above, and is divided into a polygonal ring with four sides parallel to the periphery of the first main surface 3 (in this configuration, a quadrilateral ring). That is, the outer main body region 21 forms the boundary between the active region 8 and the outer peripheral region 9. The outer main body region 21 may also have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y in a circular arc shape (preferably a quarter-circular arc shape) when viewed from above (see reference). Figure 6 ).

[0096] The outer main body region 21 has an inner edge portion on the side of the active region 8 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer main body region 21 is connected to a plurality of main body regions 20 in the portion extending along the first direction X. That is, the outer main body region 21 is electrically connected to a plurality of main body regions 20 in the surface portion of the high concentration region 10.

[0097] The outer edge of the outer main body region 21 is formed at intervals from the periphery of the high concentration region 10 toward the active region 8. That is, the outer edge of the outer main body region 21 is formed at intervals from the low concentration region 11. In addition, the entire region of the outer main body region 21 is located within the high concentration region 10. The edge of the outer main body region 21 is located on the surface of the high concentration region 10.

[0098] The outer main body region 21 preferably has a width greater than that of the main body region 20. The width of the main body region 20 is the width in a direction orthogonal to the extension direction (i.e., the first direction X). The width of the outer main body region 21 is the width in a direction orthogonal to the extension direction. Of course, the width of the outer main body region 21 can be approximately equal to the width of the main body region 20, or it can be less than the thickness of the main body region 20.

[0099] The ratio of the width of the outer main body region 21 to the width of the main body region 20 can be 1 or more and 50 or less. The width ratio can have a value belonging to at least one of the following ranges: 1 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less. The width ratio is preferably 10 or more. The width ratio is preferably 20 or more and 40 or less.

[0100] The outer main body region 21 is formed at intervals from the bottom of the high-concentration region 10 toward the first main surface 3, and is opposite the inner low-concentration region 13 (base region 14) across a portion of the high-concentration region 10. Preferably, the outer main body region 21 is formed at intervals from the middle portion of the high-concentration region 10 toward the first main surface 3. Alternatively, the outer main body region 21 may extend through the depth of the middle portion of the high-concentration region 10 in the thickness direction. The outer main body region 21 is exposed from the first main surface 3.

[0101] The outer main body region 21 preferably has a thickness (depth) that is approximately equal to that of the main body region 20. Of course, the thickness of the outer main body region 21 can be less than or greater than the thickness of the main body region 20.

[0102] The outer body region 21 forms a high-concentration region 10 and a pn junction (pn junction diode: body diode). When a reverse bias voltage is applied to the pn junction, the depletion layer of the outer body region 21 extends towards the high-concentration region 10. The depletion layer of the outer body region 21 is integrated with the depletion layers of the plurality of body regions 20, extending in both the horizontal and thickness directions. The extent of the depletion layer of the outer body region 21 extends towards the periphery of the chip 2 through the low-concentration region 11. As a result, the breakdown voltage is increased at the periphery (outer peripheral region 9) of the chip 2.

[0103] In this configuration, the depletion layer of the outer body region 21 extends from the high-concentration region 10 to the inner low-concentration region 13 in the thickness direction of the chip 2. That is, the extent of the depletion layer of the outer body region 21 extends through the inner low-concentration region 13. As a result, the breakdown voltage is increased on the inner side (active region 8 side) of the chip 2.

[0104] Semiconductor device 1A includes a plurality of n-shaped surface drift regions 22 formed on the surface portion of a first main surface 3. The plurality of surface drift regions 22 are respectively divided into regions between a plurality of adjacent main body regions 20 in a first direction X on the surface portion of the high concentration region 10. Specifically, the plurality of surface drift regions 22 are respectively divided in the surface portion of the high concentration region 10 by the plurality of main body regions 20 and an outer main body region 21.

[0105] In this manner, the multiple surface drift regions 22 are each composed of a portion of the high concentration region 10. Of course, the multiple surface drift regions 22 may have either a higher or lower n-type impurity concentration compared to the n-type impurity concentration of the high concentration region 10.

[0106] Multiple surface drift regions 22 are arranged at intervals in the first direction X, forming stripes extending in the second direction Y. That is, the multiple surface drift regions 22 are formed as stripes extending in the second direction Y. The multiple surface drift regions 22 and the multiple main regions 20 located on both sides form an n-type (pnp-type) JFET structure. The JFET resistance component of the JFET structure is reduced through the high-concentration region 10.

[0107] The multiple surface drift regions 22 may also have a width of 0.1 μm or more and 5 μm or less. The width of the surface drift region 22 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0108] Semiconductor device 1A includes multiple n-type source regions 23, 24 formed on the surface portion of multiple body regions 20. The multiple source regions 23, 24 have an n-type impurity concentration higher than that of the high-concentration region 10. Source potentials are assigned to the multiple source regions 23, 24.

[0109] Multiple source regions 23 and 24 on the surface of each main body region 20 include a first source region 23 located on one side (third side 5C side) in the first direction X and a second source region 24 located on the other side (fourth side 5D side) in the first direction X. In this configuration, in the first direction X, a first source region 23 is formed at one end of the main body region 20, and a second source region 24 is formed at the other end of the main body region 20.

[0110] The first source region 23 is formed at intervals from one end of the main body region 20 to the other end, extending in a strip shape along the extension direction of the main body region 20. The first source region 23 is formed at intervals from the outer main body region 21 in the second direction Y. That is, the first source region 23 is not formed in the outer main body region 21. The first source region 23 is formed at intervals from the bottom of the main body region 20 toward the first main surface 3, and is opposite the high concentration region 10 across a portion of the main body region 20.

[0111] The second source region 24 is formed spaced apart from the first source region 23 toward the other end of the main body region 20. The second source region 24 is also formed spaced apart from the other end of the main body region 20 toward one end, extending in a strip shape along the extension direction of the main body region 20. The second source region 24 is also formed spaced apart from the outer main body region 21 in the second direction Y. That is, the second source region 24 is not formed in the outer main body region 21. The second source region 24 is formed spaced apart from the bottom of the main body region 20 toward the first main surface 3, and is opposite the high concentration region 10 across a portion of the main body region 20.

[0112] When multiple first source regions 23 are formed in a main body region 20, the multiple first source regions 23 may also be formed at intervals along the extension direction of the main body region 20. In this case, each first source region 23 may also be formed as a strip extending in the second direction Y. Similarly, when multiple second source regions 24 are formed in a main body region 20, the multiple second source regions 24 may also be formed at intervals along the extension direction of the main body region 20. In this case, each second source region 24 may also be formed as a strip extending in the second direction Y.

[0113] Semiconductor device 1A includes multiple p-type contact regions 25 formed in the surface portion of multiple body regions 20 within an active region 8. The contact regions 25 may also be referred to as "back gate regions". A source potential is assigned to the multiple contact regions 25. The contact regions 25 have a higher p-type impurity concentration compared to the p-type impurity concentration of the body regions 20.

[0114] In this configuration, a contact region 25 is located on the surface of the corresponding main body region 20, between the first source region 23 and the second source region 24. The contact region 25 extends in a strip shape along the extension direction of the main body region 20 (source regions 23, 24).

[0115] The contact area 25 is formed at intervals from the outer body region 21 in the second direction Y. That is, the contact area 25 is not formed in the outer body region 21. The contact area 25 is formed at intervals from the bottom of the body region 20 toward the first main surface 3, and is opposite the high concentration region 10 across a portion of the body region 20.

[0116] When multiple contact areas 25 are formed in a single main body region 20, the multiple contact areas 25 may also be formed at intervals along the extending direction of the main body region 20. In this case, each contact area 25 may also be formed as a strip extending along the second direction Y.

[0117] Semiconductor device 1A includes a plurality of p-type channel regions 26, 27 formed on the surface portion of a first main surface 3. The plurality of channel regions 26, 27 are respectively divided on the surface portion of a plurality of main body regions 20 into regions between the ends of the plurality of main body regions 20 (a plurality of surface drift regions 22) and the peripheries of a plurality of source regions 23, 24. In this configuration, the plurality of channel regions 26, 27 are arranged at intervals in a first direction X, and are respectively formed as stripes extending in a second direction Y. That is, the plurality of channel regions 26, 27 are arranged as stripes extending along the second direction Y.

[0118] The multiple channel regions 26 and 27 include multiple first channel regions 26 and multiple second channel regions 27. The multiple first channel regions 26 are respectively divided into regions between one end of multiple main regions 20 (surface drift regions 22) and multiple first source regions 23, forming a current path extending horizontally. The multiple second channel regions 27 are respectively divided into regions between the other end of multiple main regions 20 (surface drift regions 22) and multiple second source regions 24, forming a current path extending horizontally.

[0119] Semiconductor device 1A includes a plurality of planar electrode-type gate structures 30 disposed on a first main surface 3 in an active region 8. The plurality of gate structures 30 are arranged at intervals in a first direction X and are each formed into a strip shape extending in a second direction Y. That is, the plurality of gate structures 30 are arranged in a stripe shape extending along the second direction Y. In addition, the extension direction of the plurality of gate structures 30 is consistent with the offset direction of the SiC single crystal.

[0120] Each gate structure 30 is disposed on at least one channel region 26, 27. In this configuration, each gate structure 30 is arranged to traverse a surface drift region 22 and span two adjacent main regions 20, covering multiple channel regions 26, 27.

[0121] Specifically, each gate structure 30 is configured to span a first source region 23 on one side of the main body region 20 and a second source region 24 on the other side of the main body region 20, covering the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0122] The structure of a gate structure 30 is described below. The gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32. The insulating film 31 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. The insulating film 31 is particularly preferably made of a silicon oxide film composed of an oxide of the chip 2.

[0123] An insulating film 31 covers the first main surface 3 in a film-like manner and is disposed on at least one channel region 26, 27. In this manner, the insulating film 31 is disposed in a manner that traverses a surface drift region 22 and spans two adjacent main body regions 20, covering multiple channel regions 26, 27.

[0124] Specifically, the insulating film 31 is configured to span a first source region 23 on one side of the main body region 20 and a second source region 24 on the other side of the main body region 20, covering the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0125] The insulating film 31 partially covers the first source region 23 at intervals from the contact region 25, such that a portion of the first source region 23 and the contact region 25 are exposed from the first main surface 3. The insulating film 31 partially covers the second source region 24 at intervals from the contact region 25, such that a portion of the second source region 24 and the contact region 25 are exposed from the first main surface 3.

[0126] The insulating film 31 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the insulating film 31 may have a value falling within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. Preferably, the thickness of the insulating film 31 is 25 nm or more and 75 nm or less.

[0127] A gate electrode 32 is disposed on an insulating film 31, facing at least one channel region 26, 27 across the insulating film 31. A gate potential, serving as a control potential, is applied to the gate electrode 32. The gate electrode 32 may also comprise either or both of p-type and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved.

[0128] The gate electrode 32 is formed as a strip extending in the second direction Y. In this configuration, the gate electrode 32 is formed spaced inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 is disposed on the insulating film 31 in such a way that it traverses a surface drift region 22 and spans two adjacent main body regions 20, and is opposed to a plurality of channel regions 26, 27 through the insulating film 31.

[0129] Specifically, the gate electrode 32 is configured to span a first source region 23 on one side of the main body region 20 and a second source region 24 on the other side of the main body region 20, and is positioned opposite the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26 and the second channel region 27 through the insulating film 31.

[0130] The gate electrode 32 controls the inversion and non-inversion of the channel regions 26 and 27 in response to the gate potential. When a gate potential is applied to the gate electrode 32, the channel regions 26 and 27 become conductive, and the drain current flows through the channel regions 26 and 27 (main body region 20) between the high-concentration region 10 and the source regions 23 and 24. As described above, a planar gate transistor structure Tr, including the high-concentration region 10, is formed in the inner part (active region 8) of the chip 2.

[0131] Reference Figures 6 to 11 The semiconductor device 1A includes a p-type terminal region 40 formed on a first main surface 3 in the peripheral region 9. The terminal region 40 may also be referred to as a "well region," "terminal well region," etc. The terminal region 40 is formed in the peripheral region 9 on either or both of the surface portion of the high-concentration region 10 and the surface portion of the low-concentration region 11. In this configuration, the terminal region 40 is formed in the surface portion of the high-concentration region 10 in the peripheral region 9.

[0132] The terminal region 40 may also have a different p-type impurity concentration than the main region 20. The p-type impurity concentration in the terminal region 40 may also be higher than that in the main region 20. Alternatively, the p-type impurity concentration in the terminal region 40 may be lower than that in the main region 20. Of course, the p-type impurity concentration in the terminal region 40 may also be approximately equal to that in the main region 20.

[0133] The terminal region 40 may also have a different p-type impurity concentration than the outer body region 21. The p-type impurity concentration in the terminal region 40 may also be higher than that in the outer body region 21. Alternatively, the p-type impurity concentration in the terminal region 40 may be lower than that in the outer body region 21. Of course, the p-type impurity concentration in the terminal region 40 may also be approximately equal to that in the outer body region 21.

[0134] Terminal region 40 is formed at intervals from the periphery of the first main surface 3 inward between the periphery of the first main surface 3 and the outer main body region 21. Terminal region 40 extends in a strip-like shape along the outer main body region 21 when viewed from above. Terminal region 40 has a portion extending in a strip-like shape along a first direction X and a portion extending in a strip-like shape along a second direction Y when viewed from above, thus dividing the active region 8 from multiple directions.

[0135] In this configuration, the terminal region 40, when viewed from above, surrounds the outer main body region 21 and is divided into a polygonal ring with four sides parallel to the periphery of the first main surface 3 (in this configuration, a quadrilateral ring). The terminal region 40 may also have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y when viewed from above into an arc shape (preferably a quarter arc shape) (see reference). Figure 6 ).

[0136] The terminal region 40 is formed spaced apart from the bottom of the high-concentration region 10 toward the first main surface 3, and is opposite the inner low-concentration region 13 across a portion of the high-concentration region 10. Preferably, the terminal region 40 is formed spaced apart from the middle portion of the high-concentration region 10 toward the first main surface 3. Alternatively, the terminal region 40 may extend across the middle portion of the high-concentration region 10 in the thickness direction. The terminal region 40 may also have a thickness (depth) approximately equal to that of the outer main body region 21. The thickness of the terminal region 40 may be greater than or less than the thickness of the outer main body region 21.

[0137] The terminal region 40 has an inner edge portion on the side of the active region 8 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the terminal region 40 is connected to the outer edge portion of the outer main body region 21 at the surface portion of the high concentration region 10. Thus, the terminal region 40 is electrically connected to the outer main body region 21. That is, in this manner, the terminal region 40 is electrically connected to a plurality of main body regions 20 via the outer main body region 21.

[0138] In this configuration, the inner edge of the terminal region 40 is connected to the outer edge of the outer body region 21 over its entire circumference. When the terminal region 40 has a p-type impurity concentration approximately equal to that of the outer body region 21, the terminal region 40 can also be considered as part of the outer body region 21 (lead-out portion).

[0139] The terminal region 40 (inner edge) has an overlapping region 41 on the surface of the high-concentration region 10 that overlaps with the outer edge of the outer body region 21. The overlapping region 41 is a high-concentration region including both the outer edge of the outer body region 21 and the inner edge of the terminal region 40. That is, the overlapping region 41 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the terminal region 40, and has a higher p-type impurity concentration than both the p-type impurity concentrations of the outer body region 21 and the terminal region 40.

[0140] The p-type impurity concentration in the overlapping region 41 is higher than that in the main region 20. The p-type impurity concentration in the overlapping region 41 can also be lower than that in the contact region 25. Alternatively, the p-type impurity concentration in the overlapping region 41 can also be higher than that in the contact region 25.

[0141] The overlapping region 41 extends in a strip shape along the outer main body region 21 when viewed from above. The overlapping region 41, when viewed from above, has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y, dividing the active region 8 from multiple directions. In this configuration, the overlapping region 41 is divided into a polygonal ring shape (in this configuration, a quadrilateral ring shape) with four sides parallel to the periphery of the first main surface 3.

[0142] The overlapping region 41 may also have an edge that connects the portion extending in the first direction X and the portion extending in the second direction Y when viewed from above into an arc shape (preferably a quarter arc shape) (see reference). Figure 6 The width of the overlapping region 41 is preferably greater than the width of the main region 20. Of course, the width of the overlapping region 41 can also be less than the width of the main region 20.

[0143] The termination region 40 forms a high-concentration region 10 and a pn junction (pn junction diode: body diode). When a reverse bias voltage is applied to the pn junction, the depletion layer in the termination region 40 extends towards the high-concentration region 10. The depletion layer of the termination region 40 is integrated with the depletion layers of the multiple body regions 20 and the depletion layer of the outer body region 21, extending in both the horizontal and thickness directions. The extent of the depletion layer in the termination region 40 extends towards the periphery of the chip 2 through the low-concentration region 11. As a result, the breakdown voltage is increased at the periphery (outer peripheral region 9) of the chip 2.

[0144] In this configuration, the depletion layer of the terminal region 40 extends from the high-concentration region 10 towards the inner low-concentration region 13 in the thickness direction of the chip 2. The extent of the depletion layer of the terminal region 40 also extends through the inner low-concentration region 13 in the outer peripheral region 9. As a result, the breakdown voltage is increased at the periphery (outer peripheral region 9) of the chip 2.

[0145] Preferably, the outer edge of the terminal region 40 extends across the periphery of the high-concentration region 10 and is located in the low-concentration region 11. That is, preferably, the terminal region 40 is located on the surface of the low-concentration region 11 within the outer peripheral region 9, and has a portion (outer edge) that forms a pn junction with the low-concentration region 11 (see reference). Figure 10 The edge of the outer edge of the terminal region 40 is located on the surface of the low concentration region 11.

[0146] According to this structure, the depletion layer extends directly from the terminal region 40 to the low-concentration region 11. Therefore, the extent of the depletion layer appropriately extends to the periphery (outer peripheral region 9) of the chip 2. Of course, the outer edge of the terminal region 40 can also be formed at intervals from the periphery of the high-concentration region 10 toward the active region 8 and located within the high-concentration region 10.

[0147] Semiconductor device 1A may also replace the overlapping region 41 with a well region 46 having a relatively high concentration of p-type impurities. In this case, the well region 46 has a higher p-type impurity concentration than both the outer body region 21 and the terminal region 40. The p-type impurity concentration of the well region 46 is higher than that of the body region 20.

[0148] The p-type impurity concentration in the well region 46 can be approximately equal to the p-type impurity concentration in the contact region 25. Of course, the p-type impurity concentration in the well region 46 can be either less than or higher than the p-type impurity concentration in the contact region 25.

[0149] The trap region 46 can also be formed on either or both of the surface portion of the outer body region 21 and the surface portion of the terminal region 40. Such a structure is effective when the terminal region 40 has a p-type impurity concentration that is approximately equal to that of the outer body region 21 and is formed as part of the outer body region 21 (lead-out portion).

[0150] Semiconductor device 1A includes at least one p-type field region 42 formed in the outer peripheral region 9 on the surface portion of the first main surface 3. Multiple field regions 42 may also be formed in an electrically floating state. Multiple field regions 42 may also be fixed at the source potential.

[0151] The number of field regions 42 is arbitrary. The number of field regions 42 can be more than one and less than 20. The number of field regions 42 can have values ​​belonging to at least one of the following ranges: more than one and less than five, more than five and less than ten, more than ten and less than fifteen, and more than fifteen and less than twenty. Typically, the number of field regions 42 is more than one and less than eight. In this embodiment, the semiconductor device 1A includes three field regions 42.

[0152] Multiple field regions 42 are formed on the surface of the low-concentration region 11. Multiple field regions 42 are formed at intervals from the periphery of the first main surface 3 inwards in the region between the periphery of the first main surface 3 and the active region 8. Multiple field regions 42 are formed in the region between the periphery of the first main surface 3 and the outer main body region 21.

[0153] Specifically, multiple field regions 42 are arranged at intervals from the high-concentration region 10 toward the periphery of the first main surface 3 in the region between the periphery of the first main surface 3 and the high-concentration region 10. More specifically, multiple field regions 42 are arranged at intervals from the terminal region 40 toward the periphery of the first main surface 3 in the region between the periphery of the first main surface 3 and the terminal region 40. That is, multiple field regions 42 are not formed in the high-concentration region 10.

[0154] Multiple field regions 42 are formed as a strip extending along the active region 8 (terminal region 40) when viewed from above. Each of the multiple field regions 42 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y. In this configuration, the multiple field regions 42 are formed as a polygonal ring (in this configuration, a quadrilateral ring) surrounding the active region 8 (terminal region 40) when viewed from above.

[0155] Multiple field regions 42 may also have an edge portion that connects the portions extending along the first direction X and the portions extending along the second direction Y in an arc shape (preferably a quarter arc shape) (see reference). Figure 6 The edges of the multiple field regions 42 are located on the surface of the low concentration region 11. The multiple field regions 42 are formed at intervals from the bottom of the low concentration region 11 toward the first main surface 3, and are opposite to the base region 14 across a portion of the low concentration region 11.

[0156] Multiple field regions 42 are formed at intervals from a depth position at the bottom of the high-concentration region 10 toward the first main surface 3. Preferably, the multiple field regions 42 are formed at intervals from a depth position at the middle of the high-concentration region 10 toward the first main surface 3. Of course, the multiple field regions 42 may also traverse the depth position at the middle of the high-concentration region 10 in the thickness direction.

[0157] Multiple field regions 42 respectively form a low-concentration region 11 and a pn junction (pn junction diode). When a reverse bias voltage is applied, the depletion layer of the multiple field regions 42 extends toward the low-concentration region 11. The depletion layer of the multiple field regions 42 is integrated with the depletion layer of the terminal region 40, extending in both the horizontal and thickness directions. The extent of the depletion layer of the multiple field regions 42 is expanded through the low-concentration region 11. As a result, the breakdown voltage is increased at the periphery (outer peripheral region 9) of the chip 2.

[0158] Based on the low-concentration region 11, the extent of the depletion layer is expanded, thus reducing the number of field regions 42. This reduces the area occupied by the peripheral region 9 of chip 2 and increases the area occupied by the active region 8 of chip 2. Therefore, the electrical characteristics of the transistor structure Tr (device structure) formed in the active region 8 are improved. Such a structure is also effective in achieving miniaturization of chip 2.

[0159] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 42 are arbitrary and can be set to various values ​​according to the electric field to be mitigated. The width of the multiple field regions 42 can be approximately constant or non-uniform. The width of the multiple field regions 42 can also gradually increase towards the periphery of the first main surface 3. Alternatively, the width of the multiple field regions 42 can gradually decrease towards the periphery of the first main surface 3.

[0160] The depth of the multiple field regions 42 can be approximately constant or non-uniform. The depth of the multiple field regions 42 can also gradually increase towards the periphery of the first main surface 3. Alternatively, the depth of the multiple field regions 42 can gradually decrease towards the periphery of the first main surface 3. Of course, the multiple field regions 42 can also have relatively shallow portions and deeper portions than those shallow portions. Alternatively, the shallow portions can be formed on the inner side, and the deep portions on the periphery. Alternatively, the shallow portions can be formed on the periphery, and the deep portions on the inner side.

[0161] The spacing between the multiple field regions 42 can be approximately constant or non-uniform. The spacing between the multiple field regions 42 can also gradually increase towards the periphery of the first main surface 3. Alternatively, the spacing between the multiple field regions 42 can gradually decrease towards the periphery of the first main surface 3.

[0162] The concentration of p-type impurities in the multiple field regions 42 can be approximately constant or non-uniform. The concentration of p-type impurities in the multiple field regions 42 can also gradually increase towards the periphery of the first main surface 3. Alternatively, the concentration of p-type impurities in the multiple field regions 42 can gradually decrease towards the periphery of the first main surface 3.

[0163] The p-type impurity concentrations in multiple field regions 42 can be approximately equal to those in the main body region 20 (outer main body region 21). The p-type impurity concentrations in multiple field regions 42 can be higher or lower than those in the main body region 20 (outer main body region 21). The p-type impurity concentrations in multiple field regions 42 can also be approximately equal to those in the terminal region 40. The p-type impurity concentrations in multiple field regions 42 can be higher or lower than those in the terminal region 40.

[0164] Semiconductor device 1A includes a peripheral insulating film 43 covering a first main surface 3 in its peripheral region 9. The peripheral insulating film 43 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this configuration, the peripheral insulating film 43 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the peripheral insulating film 43 comprises a silicon oxide film composed of an oxide of the chip 2. The peripheral insulating film 43 is preferably composed of an insulating material of the same type as the insulating material of the insulating film 31. The peripheral insulating film 43 preferably has a thickness substantially equal to that of the insulating film 31.

[0165] The peripheral insulating film 43 covers the first main surface 3 in a film-like manner in the peripheral region 9. The peripheral insulating film 43 also covers the high concentration region 10, the low concentration region 11, the outer main body region 21, the terminal region 40, and multiple field regions 42. The peripheral insulating film 43 is connected to multiple insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 43 is integrally formed with the multiple insulating films 31, forming a single insulating film with the multiple insulating films 31.

[0166] Semiconductor device 1A includes a gate wiring 44 disposed on a first main surface 3 in an outer peripheral region 9. The gate wiring 44 is selectively wound on the first main surface 3 and has portions extending in directions different from those of a plurality of gate electrodes 32. The gate wiring 44 is connected to the plurality of gate electrodes 32 and imparts gate signals to the plurality of gate electrodes 32. The gate wiring 44 may also be referred to as a "second gate electrode", etc.

[0167] The gate wiring 44 may also include either or both of p-type and n-type conductive polysilicon. Preferably, the gate wiring 44 has the same conductivity type as the gate electrode 32.

[0168] Gate wiring 44 is disposed on the peripheral insulating film 43 in the peripheral region 9, spaced apart from the periphery of the first main surface 3 toward the active region 8. Specifically, the gate wiring 44 is disposed in a spaced-apart manner from the low-concentration region 11 toward the active region 8 when viewed from above. In this manner, the gate wiring 44 is disposed in a spaced-apart manner from the terminal region 40 toward the active region 8, on a portion of the peripheral insulating film 43 covering the outer main body region 21.

[0169] That is, the gate wiring 44 is opposed to the outer body region 21 through the outer peripheral insulating film 43. In addition, the gate wiring 44 is opposed to the high concentration region 10 (inner low concentration region 13) in the stacking direction, but not to the low concentration region 11 in the stacking direction. The gate wiring 44 may also be partially opposed to the terminal region 40 in the stacking direction.

[0170] The gate wiring 44 extends in a strip shape along the active region 8 when viewed from above. The gate wiring 44, when viewed from above, has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y, dividing the active region 8 from multiple directions. In this configuration, the gate wiring 44 surrounds the active region 8 when viewed from above and is divided into a polygonal ring shape (in this configuration, a quadrilateral ring shape) with four sides parallel to the periphery of the first main surface 3. The gate wiring 44 can also be terminal or ring-shaped.

[0171] In this configuration, the gate wiring 44 extends in a strip shape (in this configuration, a ring shape) along the outer body region 21 when viewed from above, and the entire region extending in the direction of extension is separated from the outer body region 21 by an outer peripheral insulating film 43 in the stacking direction. The gate wiring 44 may also have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) (see reference). Figure 6 ).

[0172] The gate wiring 44 is formed to be narrower than the outer body region 21 when viewed from above, and is disposed on the outer body region 21 at intervals from the inner edge and outer edge of the outer body region 21. That is, in this manner, a plurality of gate electrodes 32 are led out onto the outer body region 21, and the gate wiring 44 is connected to the plurality of gate electrodes 32 on the outer body region 21.

[0173] The thickness of the gate wiring 44 is preferably approximately equal to the thickness of the gate electrode 32. The width of the gate wiring 44 is preferably greater than the width of the gate electrode 32. The width of the gate wiring 44 is the width in a direction orthogonal to the extension direction. For example, the ratio of the width of the gate wiring 44 to the width of the gate electrode 32 may be greater than 1 and less than 50.

[0174] The width ratio can have a value belonging to at least one of the following ranges: 1 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less. The width ratio can be 5 or more. The width ratio can be 20 or more and 40 or less. Of course, the width of the gate wiring 44 can also be less than or equal to the width of the gate electrode 32. The width of the gate wiring 44 can also be greater than the width of the outer body region 21.

[0175] Semiconductor device 1A includes an insulating interlayer film 50 covering a first main surface 3. The interlayer film 50 may also be referred to as an "interlayer insulating film," "intermediate insulating film," etc. The interlayer film 50 has an insulating surface 51 extending along the first main surface 3. The interlayer film 50 covers both the active region 8 and the peripheral region 9 on the first main surface 3.

[0176] Interlayer film 50 covers multiple gate structures 30 in the active region 8. Interlayer film 50 covers the high-concentration region 10, low-concentration region 11, outer main body region 21, terminal region 40, and multiple field regions 42 in the outer peripheral region 9, separated by an outer peripheral insulating film 43. Interlayer film 50 covers gate wiring 44 in the outer peripheral region 9. Interlayer film 50 is connected to the first to fourth side surfaces 5A to 5D. Interlayer film 50 can also be formed with gaps extending inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3 (low-concentration region 11).

[0177] In this configuration, the interlayer film 50 has a stacked structure comprising a first oxide film 52 (first insulating film) and a second oxide film 53 (second insulating film) sequentially stacked from the first main surface 3. Specifically, the interlayer film 50 has an insulating surface 51 formed by the second oxide film 53. The first oxide film 52 has a monolayer structure composed of an undoped silicon oxide film. The first oxide film 52 can also be referred to as an NSG film (Nondoped Silicate Glass film). In this configuration, the first oxide film 52 has a thickness less than that of the gate electrode 32. Of course, the thickness of the first oxide film 52 can also be greater than that of the gate electrode 32.

[0178] The first oxide film 52 covers both the active region 8 and the peripheral region 9. The first oxide film 52 covers multiple gate structures 30 in the active region 8. The first oxide film 52 covers both sides of the insulating film 31 and the gate electrode 32 with respect to each gate structure 30 in a film-like manner.

[0179] The first oxide film 52 has a portion that covers the insulating film 31 (first main surface 3) in a film-like manner along the horizontal direction. The first oxide film 52 covers the insulating film 31 at intervals from the height position of the electrode surface (upper end) of the gate electrode 32 toward the insulating film 31. The first oxide film 52 has a portion that extends in a film-like manner along the sidewall of the gate electrode 32 in the stacking direction.

[0180] The first oxide film 52 has a portion that covers the electrode surface of the gate electrode 32 in a film-like manner along the horizontal direction. Preferably, the first oxide film 52 has a rounded corner portion that is curved into an arc shape at the corner portion covering the gate electrode 32. The rounded corner portion may also have a center of curvature on the gate electrode 32 side.

[0181] The first oxide film 52 covers the high-concentration region 10, the low-concentration region 11, the outer body region 21, the terminal region 40, and multiple field regions 42 in the outer peripheral region 9, separated by the outer peripheral insulating film 43. The first oxide film 52 covers the gate wiring 44 in the outer peripheral region 9.

[0182] The first oxide film 52 has a portion that covers the outer peripheral insulating film 43 (first main surface 3) in a film-like manner along the horizontal direction. The first oxide film 52 covers the outer peripheral insulating film 43 at intervals from the height position of the wiring surface (upper end) of the gate wiring 44 toward the outer peripheral insulating film 43. The first oxide film 52 has a portion that extends in a film-like manner along the sidewall of the gate wiring 44 in the stacking direction.

[0183] The first oxide film 52 has a portion that covers the wiring surface of the gate wiring 44 in a film-like manner along the horizontal direction. Preferably, the first oxide film 52 has a rounded corner portion that is curved into an arc shape at the corner of the gate wiring 44. The rounded corner portion may also have a center of curvature on the gate wiring 44 side.

[0184] The second oxide film 53 may also have a single-layer structure composed of a phosphorus-containing silicon oxide film, or a multilayer structure including a phosphorus-containing silicon oxide film. The phosphorus-containing silicon oxide film may contain boron. The phosphorus-containing silicon oxide film may also be called a PSG film (Phosphorus Silicon Glass film). A silicon oxide film containing both phosphorus and boron may also be called a BPSG film (Boron Phosphorus Silicon Glass film).

[0185] The second oxide film 53 may also have a single-layer structure consisting of a PSG film or a BPSG film stacked on the first oxide film 52. Alternatively, the second oxide film 53 may have a laminated structure including a PSG film stacked on the first oxide film 52 and a BPSG film stacked on the PSG film. The second oxide film 53 may also have a laminated structure including a BPSG film stacked on the first oxide film 52 and a PSG film stacked on the BPSG film.

[0186] In this embodiment, as an example, the second oxide film 53 has a single-layer structure composed of a PSG film. The thickness of the second oxide film 53 can also be greater than the thickness of the first oxide film 52. Alternatively, the second oxide film 53 can have a thickness less than the thickness of the first oxide film 52. The thickness of the second oxide film 53 can also be greater than the thickness of the gate electrode 32. Alternatively, the second oxide film 53 can have a thickness less than the thickness of the gate electrode 32.

[0187] The second oxide film 53 covers the first oxide film 52 in a film-like manner, and together with the first oxide film 52, covers the active region 8 and the outer peripheral region 9. The second oxide film 53 covers multiple gate structures 30 in the active region 8 together with the first oxide film 52. Specifically, the second oxide film 53 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with respect to the first oxide film 52.

[0188] The second oxide film 53 has a portion that covers the insulating film 31 through the first oxide film 52. The second oxide film 53 extends in a film-like manner along the sidewall of the gate electrode 32 in the stacking direction, having a portion that covers the sidewall of the gate electrode 32 through the first oxide film 52. The second oxide film 53 also extends in a film-like manner along the electrode surface of the gate electrode 32 in a horizontal direction, having a portion that covers the electrode surface of the gate electrode 32 through the first oxide film 52. Preferably, the second oxide film 53 has a rounded corner portion that is curved into an arc shape at the corner of the gate electrode 32. The rounded corner portion may also have a center of curvature on the gate electrode 32 side.

[0189] The second oxide film 53 covers the high concentration region 10, the low concentration region 11, the outer body region 21, the terminal region 40, and multiple field regions 42 in the outer peripheral region 9, separated by the outer peripheral insulating film 43 and the first oxide film 52. The second oxide film 53 covers the gate wiring 44 in the outer peripheral region 9, separated by the first oxide film 52.

[0190] The second oxide film 53 has a portion that covers the outer peripheral insulating film 43 through the first oxide film 52. The second oxide film 53 extends in a film-like manner along the sidewall of the gate wiring 44 in the stacking direction, having a portion that covers the sidewall of the gate wiring 44 through the first oxide film 52. The second oxide film 53 extends in a film-like manner along the wiring surface of the gate wiring 44 in the horizontal direction, having a portion that covers the wiring surface of the gate wiring 44 through the first oxide film 52. Preferably, the second oxide film 53 has a rounded corner portion that is curved into an arc shape at the corner of the gate wiring 44. The rounded corner portion may also have a center of curvature on the gate wiring 44 side.

[0191] Semiconductor device 1A includes a plurality of source openings 54 formed in an interlayer film 50 in an active region 8. The plurality of source openings 54 are formed at intervals from a plurality of gate electrodes 32 in regions on the sides of the plurality of gate electrodes 32, exposing a first main surface 3 (chip 2). Specifically, the plurality of source openings 54 penetrate the insulating film 31 and the interlayer film 50 in the region between the plurality of gate electrodes 32.

[0192] Multiple source openings 54 penetrate both the first oxide film 52 and the second oxide film 53, and have walls defined by the first oxide film 52 and the second oxide film 53. Each of the multiple source openings 54 has an opening end defined by the rounded corner of the interlayer film 50. The multiple source openings 54 expose corresponding multiple source regions 23, 24 and contact region 25.

[0193] In this configuration, a plurality of source openings 54 are formed at intervals in the first direction X, and are respectively formed as stripes extending in the second direction Y. That is, the plurality of source openings 54 are formed as stripes extending in the second direction Y. The plurality of source openings 54 are formed at intervals from the gate wiring 44 in the second direction Y. That is, the plurality of source openings 54 are formed in the region surrounded by the plurality of gate electrodes 32 and the gate wiring 44.

[0194] Multiple source openings 54 can also be formed in the region between two adjacent gate structures 30 in the first direction X. In this case, the multiple source openings 54 can also be arranged in a row with spacing in the second direction Y. Moreover, in this case, each source opening 54 can also be formed in a quadrilateral shape (square), a rectangular shape extending along the first direction X, a rectangular shape extending along the second direction Y, a hexagonal shape, a circular shape, etc. when viewed from above.

[0195] The source opening 54 may have a width W of 0.1 μm or more and 3 μm or less. The width W of the source opening 54 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less. The width W of the source opening 54 is preferably 0.2 μm or more and 1 μm or less.

[0196] The source opening 54 may have a depth D of 0.1 μm or more and 2 μm or less. The depth D of the source opening 54 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The depth D of the source opening 54 is preferably 0.5 μm or more and 1 μm or less.

[0197] The source opening 54 preferably has an aspect ratio D / W of 0.5 or more and 3 or less. The aspect ratio D / W is defined by the ratio of the depth D of the source opening 54 to the width W of the source opening 54. The aspect ratio D / W may have a value belonging to at least one of the following ranges: 0.5 or more and 0.75 or less, 0.75 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 3 or less.

[0198] The aspect ratio D / W is preferably greater than 1. That is, the plurality of source openings 54 preferably have a depth D greater than the width W, and are respectively formed into an elongated shape in cross-section. According to this structure, the plurality of gate structures 30 are arranged with a narrow pitch. The aspect ratio D / W of the elongated source openings 54 is preferably greater than 1 and less than 2.

[0199] The semiconductor device 1A includes a plurality of source recesses 55 formed on the first main surface 3 in portions exposed from a plurality of source openings 54. The semiconductor device 1A is not required to have source recesses 55. Therefore, a structure without source recesses 55 may also be used.

[0200] Multiple source recesses 55 each have a planar shape matching the planar shape of a corresponding source opening 54, and are recessed from the first main surface 3 toward the second main surface 4. The multiple source recesses 55 are formed at intervals from the bottom of the corresponding main body region 20 toward the first main surface 3, exposing the corresponding multiple source regions 23, 24 and contact regions 25. Specifically, the multiple source recesses 55 are formed at intervals from the bottom of the corresponding multiple source regions 23, 24 (contact regions 25) toward the first main surface 3.

[0201] Semiconductor device 1A includes at least one (or multiple) external openings 56 formed in an interlayer film 50 in a peripheral region 9. The multiple external openings 56 are formed in the interlayer film 50 in portions covering a terminal region 40. The multiple external openings 56 penetrate the interlayer film 50, exposing the terminal region 40. In this embodiment, the multiple external openings 56 are formed in portions of an overlapping region 41 of the interlayer film 50 covering the terminal region 40, exposing the overlapping region 41.

[0202] Multiple external openings 56 may replace the terminal region 40 (overlapping region 41) or, based on this, expose the outer main body region 21. The multiple external openings 56 have walls that penetrate both the first oxide film 52 and the second oxide film 53 and are defined by both the first oxide film 52 and the second oxide film 53. Each of the multiple external openings 56 has an opening end defined by the rounded corner of the interlayer film 50.

[0203] Multiple external openings 56 are formed at intervals along the terminal region 40 (overlapping region 41) (see reference). Figure 6 and Figure 7 The multiple external openings 56 can also be formed in a quadrilateral (square), rectangular, hexagonal, or circular shape when viewed from above. The multiple external openings 56 can also be formed in a strip shape extending along the terminal region 40 (overlapping region 41) when viewed from above. The external openings 56 and the source openings 54 can have the same aspect ratio D / W (=0.5 or more and 3 or less: preferably greater than 1).

[0204] The semiconductor device 1A may also have a single external opening 56. The single external opening 56 may also be formed as a strip extending along the terminal region 40 (overlapping region 41). The single external opening 56 may also have a portion extending in a strip shape along a first direction X and a portion extending in a strip shape along a second direction Y when viewed from above.

[0205] The single outer opening 56 can also be formed as a polygonal ring with four sides parallel to the periphery of the first main surface 3, either end-shaped or ring-shaped (in this case, a quadrilateral ring). The single outer opening 56 can also have an edge portion that, when viewed from above, connects the portion extending in the first direction X (overlapping region 41) and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) (see reference). Figure 6 ).

[0206] Semiconductor device 1A includes a plurality of external recesses 57 formed in portions of a plurality of external openings 56 in the first main surface 3. Semiconductor device 1A does not necessarily need to have external recesses 57. Therefore, a structure without external recesses 57 may also be adopted.

[0207] Multiple external grooves 57 each have a planar shape matching the planar shape of a corresponding external opening 56, recessed from the first main surface 3 toward the second main surface 4. The multiple external grooves 57 are formed spaced apart from the bottom of the terminal region 40 (overlapping region 41) toward the first main surface 3, exposing the terminal region 40 (overlapping region 41) respectively. The external grooves 57 may also have a depth approximately equal to the depth of the source groove 55. In the case of a single external opening 56, a single external groove 57 is formed that matches the planar shape of the single external opening 56.

[0208] Semiconductor device 1A includes at least one (in this case, multiple) gate openings 58 formed in an interlayer film 50 in an outer peripheral region 9. The multiple gate openings 58 are formed in the interlayer film 50 covering a portion of a gate wiring 44. The multiple gate openings 58 penetrate the interlayer film 50, exposing the gate wiring 44. The multiple gate openings 58 penetrate both a first oxide film 52 and a second oxide film 53, having walls defined by both the first oxide film 52 and the second oxide film 53. Each of the multiple gate openings 58 has an opening end defined by an arcuate corner of the interlayer film 50.

[0209] Multiple gate openings 58 are formed at intervals along gate wiring 44 (see reference) Figure 6 as well as Figure 7 The multiple gate openings 58 can also be formed in a quadrilateral (square), rectangular, hexagonal, circular, or other shapes when viewed from above. The multiple gate openings 58 can also be formed in a strip shape that extends along the gate wiring 44 when viewed from above. The gate openings 58 and the source openings 54 can have the same aspect ratio D / W (=0.5 or more and 3 or less: preferably greater than 1).

[0210] Semiconductor device 1A may also have a single gate opening 58. The single gate opening 58 may also be formed as a strip extending along the gate wiring 44. The single gate opening 58 may also have a portion extending in a strip shape along a first direction X and a portion extending in a strip shape along a second direction Y when viewed from above.

[0211] A single gate opening 58 can also be formed as a polygonal ring with four sides parallel to the periphery of the first main surface 3, either end-shaped or annular (in this case, a quadrilateral ring). A single gate opening 58 can also have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y, mimicking the gate wiring 44 in a circular arc (preferably a quarter-circular arc), when viewed from above (see reference). Figure 6 ).

[0212] Reference Figure 1 Semiconductor device 1A includes a source pad electrode 60 disposed on an interlayer film 50. The source pad electrode 60 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 60 may also be referred to as a "first pad electrode", "first main surface electrode", "first terminal electrode", etc.

[0213] The source pad electrode 60 is disposed on a portion of the interlayer film 50 covering the active region 8. The source pad electrode 60 covers a plurality of gate electrodes 32 through the interlayer film 50 and is electrically separated from the plurality of gate electrodes 32 through the interlayer film 50. The source pad electrode 60 is electrically connected to a plurality of body regions 20, an outer body region 21, a plurality of source regions 23, 24, a contact region 25, etc., via a plurality of source openings 54.

[0214] In this configuration, the source pad electrode 60 has a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c. The first pad portion 60a has a relatively large planar area and forms the main body of the source pad electrode 60. In this configuration, the first pad portion 60a is formed into a polygonal shape (quadrilateral shape in this configuration) with four sides parallel to the periphery of the chip 2 when viewed from above, and is offset towards the fourth side surface 5D relative to the center of the active region 8. The first pad portion 60a covers multiple gate electrodes 32 through the interlayer film 50 and is electrically connected to multiple main body regions 20 via multiple source openings 54.

[0215] The second pad portion 60b has a planar area smaller than that of the first pad portion 60a, and extends in a strip shape (quadrilateral shape) from one end of the first pad portion 60a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C side. The second pad portion 60b covers a plurality of gate electrodes 32 through the interlayer film 50, and is electrically connected to a plurality of body regions 20 via a plurality of source openings 54.

[0216] The third pad portion 60c has a planar area smaller than that of the first pad portion 60a. It extends in a strip (quadrilateral shape) from the other end of the first pad portion 60a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C side, and is opposite to the second pad portion 60b in the second direction Y. The third pad portion 60c covers a plurality of gate electrodes 32 through the interlayer film 50 and is electrically connected to a plurality of body regions 20 via a plurality of source openings 54.

[0217] The planar area of ​​the third pad portion 60c can also be approximately equal to the planar area of ​​the second pad portion 60b. Of course, the planar area of ​​the third pad portion 60c can be larger or smaller than the planar area of ​​the second pad portion 60b. Either or both of the second pad portion 60b and the third pad portion 60c can be used as a terminal portion for current monitoring.

[0218] The source pad electrode 60 does not necessarily need to have both the second pad portion 60b and the third pad portion 60c simultaneously. The source pad electrode 60 may also have only either the second pad portion 60b or the third pad portion 60c. Of course, the source pad electrode 60 may also be composed only of the first pad portion 60a, without the second pad portion 60b and the third pad portion 60c.

[0219] Reference Figure 8 as well as Figure 9The source pad electrode 60 includes a first base electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63. The first base electrode film 61 can also be referred to as the "source base electrode film", the first buried electrodes 62 as the "source buried electrodes", and the first main electrode film 63 as the "source main electrode film".

[0220] The first base electrode film 61 forms the lower layer of the source pad electrodes 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c), and covers the interlayer film 50 in the active region 8. The first base electrode film 61 covers the region in the interlayer film 50 where multiple source openings 54 are formed in a film-like manner, and extends from the insulating surface 51 into the multiple source openings 54.

[0221] The first base electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surface of the plurality of source openings 54 in a film-like manner. The first base electrode film 61 may also have a portion that covers the gate wiring 44 through the interlayer film 50. The first base electrode film 61 may also be formed at intervals from the gate wiring 44 inward when viewed from top.

[0222] In this configuration, the first substrate electrode film 61 has a laminated structure comprising a first electrode film 64 laminated on the interlayer film 50 and a second electrode film 65 laminated on the first electrode film 64. In this configuration, the first electrode film 64 comprises a Ti film, and the second electrode film 65 comprises a TiN film. The first substrate electrode film 61 does not necessarily need to have a laminated structure; it can also have a single-layer structure composed of either the first electrode film 64 (Ti film) or the second electrode film 65 (TiN film).

[0223] The thickness of the first electrode film 64 can be 10 nm or more and 100 nm or less. The thickness of the first electrode film 64 can have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0224] The thickness of the second electrode film 65 can be 50 nm or more and 200 nm or less. The thickness of the second electrode film 65 can have a value within at least one of the following ranges: 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. Preferably, the thickness of the second electrode film 65 is greater than the thickness of the first electrode film 64.

[0225] The first electrode film 64 covers the region in the interlayer film 50 where multiple source openings 54 are formed in a film-like manner, and extends into the multiple source openings 54 from the insulating surface 51. The first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surface of the multiple source openings 54 in a film-like manner. The first electrode film 64 directly covers the insulating surface 51 (second oxide film 53) and is opposed to the multiple gate electrodes 32 through the interlayer film 50.

[0226] The first electrode film 64 covers the rounded corner of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the source opening 54. The first electrode film 64 has a portion that extends in an arc shape at the rounded corner. As a result, the film-forming properties of the first electrode film 64 are improved relative to the interlayer film 50 (the wall surface of the source opening 54).

[0227] The first electrode film 64 extends along the wall of the source opening 54, covering the insulating film 31, the first oxide film 52, and the second oxide film 53. The first electrode film 64 is opposed to the sidewall of the gate electrode 32 through the interlayer film 50. The first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the first main surface 3. Specifically, the first electrode film 64 has a portion at the bottom of each source opening 54 that covers the source groove 55 in a film-like manner and is electrically connected to the plurality of source regions 23, 24 and the contact region 25.

[0228] The first electrode film 64 may also cover the source groove 55 in a film-like manner from the height position of the first main surface 3 toward the bottom side of the source groove 55 at intervals. The first electrode film 64 may also have a portion located at the bottom side of the source groove 55 relative to the height position of the first main surface 3, and a portion located on the side of the insulating film 31 relative to the height position of the first main surface 3.

[0229] The second electrode film 65 covers the region in the interlayer film 50 where multiple source openings 54 are formed on the first electrode film 64 in a film-like manner. The second electrode film 65 has a portion that covers the insulating surface 51 in a film-like manner through the first electrode film 64, and a portion that covers the wall surface of the multiple source openings 54 in a film-like manner through the first electrode film 64.

[0230] The second electrode film 65 is positioned opposite the plurality of gate electrodes 32, separated from the first electrode film 64 and the interlayer film 50, in the portion covering the insulating surface 51. The second electrode film 65, mimicking the first electrode film 64, covers the rounded corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the source opening 54. The second electrode film 65 has a portion extending in an arc shape at the rounded corners of the interlayer film 50. This improves the film-forming properties of the second electrode film 65 relative to the interlayer film 50 (the wall of the source opening 54).

[0231] The second electrode film 65 extends along the wall of the source opening 54, covering the insulating film 31, the first oxide film 52, and the second oxide film 53 through the first electrode film 64. The second electrode film 65 is opposed to the sidewall of the gate electrode 32 through the first electrode film 64 and the interlayer film 50. The second electrode film 65 has a portion that covers the source groove 55 in a film-like manner at the bottom of each source opening 54 through the first electrode film 64, and is electrically connected to the plurality of source regions 23, 24 and the contact region 25 through the first electrode film 64.

[0232] When the first electrode film 64 is located at the bottom side of the source groove 55 relative to the first main surface 3, the second electrode film 65 may also have a portion located within the source groove 55. When the first electrode film 64 has a portion located above the first main surface 3, the entire second electrode film 65 is located above the source groove 55.

[0233] Multiple first buried electrodes 62 form the middle layer of the source pad electrodes 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c), and are respectively buried in multiple source openings 54. The first buried electrodes 62 include a conductive material different from the conductive material of the first substrate electrode film 61. The first buried electrodes 62 include at least one of tungsten, molybdenum, tungsten alloy, and molybdenum alloy. In this configuration, the first buried electrodes 62 include tungsten.

[0234] In this configuration, multiple first embedded electrodes 62 are embedded in multiple source openings 54 in a one-to-one correspondence, separated by a single first base electrode film 61. The multiple first embedded electrodes 62 are electrically connected to the first main surface 3 (chip 2) within the multiple source openings 54. Specifically, the first embedded electrodes 62 are electrically connected to multiple source regions 23, 24 and contact region 25 via the first base electrode film 61. The structure of one first embedded electrode 62 will be described below.

[0235] The first embedded electrode 62 has a first embedded electrode surface 66 exposed from the source opening 54, thus exposing the insulating surface 51. The first embedded electrode surface 66 may also be referred to as the "source embedded electrode film". The first embedded electrode 62 is embedded in the source opening 54 at intervals from the insulating surface 51 toward the first main surface 3, thus exposing the portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51.

[0236] The first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 through the first base electrode film 61. The first buried electrode 62 is positioned horizontally opposite the sidewall of the gate electrode 32. When the first base electrode film 61 is located on the bottom side of the source recess 55 relative to the first main surface 3, the first buried electrode 62 may also have a portion located within the source recess 55. When the first base electrode film 61 has a portion located above the first main surface 3, the entire first buried electrode 62 is located above the source recess 55.

[0237] The first buried electrode surface 66 is located closer to the first main surface 3 than the insulating surface 51, and does not have a portion in the stacking direction (vertical direction Z) that faces the electrode surface of the gate electrode 32 across the interlayer film 50. In this configuration, the first buried electrode surface 66 has a portion that covers the arcuate corner of the interlayer film 50 across the first base electrode film 61.

[0238] Of course, the first buried electrode surface 66 can also be located below the arcuate corner of the interlayer film 50. The first buried electrode surface 66 is located on the insulating surface 51 side at a height position above the first oxide film 52. The first buried electrode surface 66 is preferably located above the electrode surface of the gate electrode 32.

[0239] The first buried electrode surface 66 has a recessed portion in its central part that is recessed toward the first main surface 3 (chip 2). Preferably, the bottom of the recess is located on the insulating surface 51 side relative to the height of the electrode surface of the gate electrode 32. Of course, a portion (e.g., the recess) or all of the first buried electrode surface 66 may also be located below the electrode surface of the gate electrode 32. A portion (e.g., the recess) or all of the first buried electrode surface 66 may also be located on the insulating surface 51 side relative to the height of the first oxide film 52.

[0240] The first main electrode film 63 forms the upper layer of the source pad electrodes 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c), and covers the first base electrode film 61 and the plurality of first buried electrodes 62 in a film-like manner. The first main electrode film 63 includes a conductive material that is different from the conductive material of the first base electrode film 61 and the conductive material of the first buried electrodes 62.

[0241] The first main electrode film 63 may also include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 63 has a thickness greater than the thickness (total thickness) of the first substrate electrode film 61. The first main electrode film 63 has a thickness greater than the thickness of the first embedded electrode 62.

[0242] The thickness of the first main electrode film 63 may also be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 63 may also have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0243] The first main electrode film 63 is mechanically and electrically connected to the first base electrode film 61 in the portion covering the insulating surface 51, and is positioned opposite to the plurality of gate electrodes 32 through the first base electrode film 61 and the interlayer film 50. The first main electrode film 63 is mechanically and electrically connected to the plurality of first buried electrodes 62 in the portion covering the plurality of source openings 54. Thus, the first main electrode film 63 is electrically connected to the plurality of main body regions 20, the outer main body region 21, the plurality of source regions 23, 24, and the contact region 25 via the first base electrode film 61 and the plurality of first buried electrodes 62.

[0244] The first main electrode film 63 is connected to the first embedded electrode surface 66 at a height relative to the insulating surface 51 on the first main surface 3 side. The first main electrode film 63 has a portion that covers the recessed portion of the first embedded electrode surface 66. The first main electrode film 63 may also have a portion that covers the rounded corner portion of the interlayer film 50 through the first base electrode film 61.

[0245] The first main electrode film 63 is connected to the first buried electrode surface 66 at a height position higher than the first oxide film 52. In this configuration, the first main electrode film 63 is connected to the first buried electrode surface 66 at a height position higher than the electrode surface of the gate electrode 32. That is, the first main electrode film 63 does not have a portion that faces the gate electrode 32 in the horizontal direction. When the first buried electrode surface 66 is located at a height position lower than the electrode surface of the gate electrode 32 and the height position of the first oxide film 52, the first main electrode film 63 may also have a portion that faces the gate electrode 32 in the horizontal direction.

[0246] The film-forming properties of the first main electrode film 63 relative to the plurality of source openings 54 are improved by the plurality of first buried electrodes 62. This appropriately ensures the current path between the first main surface 3 and the first main electrode film 63. Such a structure is effective in suppressing poor film formation caused by the plurality of source openings 54 and reducing wiring resistance.

[0247] Semiconductor device 1A includes a plurality of first silicide portions 67 formed on the surface portions of a plurality of source openings 54 in a first main surface 3. The plurality of first silicide portions 67 are formed in a film shape along the walls (sidewalls and bottom walls) of a plurality of source recesses 55 and are mechanically and electrically connected to a first substrate electrode film 61. That is, the plurality of first silicide portions 67 are formed on the surface portions of a plurality of main body regions 20, and a plurality of first buried electrodes 62 are electrically connected to the plurality of main body regions 20 via the first substrate electrode film 61.

[0248] The first silicide portion 67 may include at least one selected from Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The first silicide portion 67 is preferably composed of Ti silicide, Ni silicide, or Co silicide.

[0249] Semiconductor device 1A includes source finger electrodes 68 extending from source pad electrode 60 to an outer peripheral region 9. The source finger electrodes 68 transfer the source potential applied to the source pad electrode 60 to the outer peripheral region 9. In this manner, the source finger electrodes 68 are wound from a portion of the source pad electrode 60 (first pad portion 60a) on the fourth side 5D side to a portion of the interlayer film 50 covering the outer peripheral region 9.

[0250] Source finger electrodes 68 are led out onto the terminal region 40. In this configuration, the source finger electrodes 68 are formed at intervals from the low-concentration region 11 toward the active region 8 when viewed from above, and are opposite to the high-concentration region 10 (inner low-concentration region 13) in the stacking direction. The source finger electrodes 68 are not opposite to the low-concentration region 11 in the stacking direction. Alternatively, the source finger electrodes 68 may have a portion that leads from a region on the high-concentration region 10 toward a region on the low-concentration region 11 and is opposite to the low-concentration region 11 in the stacking direction.

[0251] The source finger electrode 68 is electrically connected to the terminal region 40 via a plurality of external openings 56. Specifically, the source finger electrode 68 is electrically connected to the overlapping region 41 of the terminal region 40 via the plurality of external openings 56. The source finger electrode 68 extends in a strip shape along the terminal region 40 (overlapping region 41). The source finger electrode 68, when viewed from above, has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y.

[0252] In this configuration, the source finger electrode 68 is formed as a polygonal ring (in this configuration, a quadrilateral ring) with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 60. The source finger electrode 68 may also have an edge portion (see reference) where the portion extending in the first direction X and the portion extending in the second direction Y, when viewed from above, are connected in an arc shape (preferably a quarter arc shape). Figure 6 ).

[0253] The source finger electrode 68, like the source pad electrode 60, includes a first base electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63. The first base electrode film 61 forms the lower layer of the source finger electrode 68 and covers the interlayer film 50 in the outer peripheral region 9. The first base electrode film 61 covers the region in the interlayer film 50 where a plurality of external openings 56 are formed in a film-like manner, extending from the insulating surface 51 into the plurality of external openings 56. The first base electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surface of the plurality of external openings 56 in a film-like manner.

[0254] The first base electrode film 61, like the source pad electrode 60, has a stacked structure including a first electrode film 64 and a second electrode film 65. The first electrode film 64 covers the region in the interlayer film 50 where multiple external openings 56 are formed in a film-like manner, and enters the multiple external openings 56 from the insulating surface 51. The first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surface of the multiple external openings 56 in a film-like manner.

[0255] The first electrode film 64 covers the rounded corner of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the outer opening 56. The first electrode film 64 has a portion that extends in an arc shape at the rounded corner. As a result, the film-forming properties of the first electrode film 64 are improved relative to the interlayer film 50 (the wall surface of the outer opening 56). The first electrode film 64 extends along the wall surface of the outer opening 56, covering the outer peripheral insulating film 43, the first oxide film 52, and the second oxide film 53.

[0256] The first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each external opening 56 and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 64 has a portion at the bottom of each external opening 56 that covers the external groove 57 in a film-like manner, and is electrically connected to the terminal region 40 (overlapping region 41) within the external groove 57.

[0257] The first electrode film 64 may also be spaced apart from the height position of the first main surface 3 toward the bottom side of the outer groove 57 to cover the outer groove 57 in a film-like manner. The first electrode film 64 may have a portion located at the bottom side of the outer groove 57 relative to the height position of the first main surface 3, and a portion located on the side of the outer peripheral insulating film 43 relative to the height position of the first main surface 3.

[0258] The second electrode film 65 covers the region in the interlayer film 50 where multiple external openings 56 are formed on the first electrode film 64 in a film-like manner. The second electrode film 65 has a portion that covers the insulating surface 51 in a film-like manner through the first electrode film 64, and a portion that covers the wall surface of the multiple external openings 56 in a film-like manner through the first electrode film 64.

[0259] The second electrode film 65, mimicking the first electrode film 64, covers the rounded corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the outer opening 56. The second electrode film 65 has a portion extending in an arc shape at the rounded corners of the interlayer film 50 (second oxide film 53). This improves the film-forming properties of the second electrode film 65 relative to the interlayer film 50 (the wall of the outer opening 56). The second electrode film 65 extends along the wall of the outer opening 56, covering the outer peripheral insulating film 43, the first oxide film 52, and the second oxide film 53 through the first electrode film 64.

[0260] The second electrode film 65 has a portion at the bottom of each external opening 56 that covers the outer groove 57 in a film-like manner through the first electrode film 64, and is electrically connected to the terminal region 40 (overlapping region 41) via the first electrode film 64. When the first electrode film 64 is located on the bottom side of the outer groove 57 relative to the first main surface 3, the second electrode film 65 may also have a portion located within the outer groove 57. When the first electrode film 64 has a portion located above the first main surface 3, the entire second electrode film 65 is located above the outer groove 57.

[0261] Multiple first embedded electrodes 62 form the middle layer of the source finger electrode 68 and are respectively embedded in multiple external openings 56. In this configuration, the multiple first embedded electrodes 62 are embedded in the multiple external openings 56 in a one-to-one correspondence with a single first base electrode film 61. The multiple first embedded electrodes 62 are electrically connected to the terminal region 40 (overlapping region 41) via the first base electrode film 61.

[0262] The first embedded electrode 62 has a first embedded electrode surface 66 exposed from the external opening 56, thus exposing the insulating surface 51. Specifically, the first embedded electrode 62 is embedded in the external opening 56 at intervals from the insulating surface 51 toward the first main surface 3, thus exposing a portion of the first base electrode film 61 (second electrode film 65) covering the insulating surface 51. That is, the first embedded electrode surface 66 is located on the first main surface 3 side compared to the insulating surface 51.

[0263] The first embedded electrode 62 covers the first oxide film 52 and the second oxide film 53 through the first base electrode film 61. The first embedded electrode 62 has a portion that covers the arcuate corner of the interlayer film 50 through the first base electrode film 61. The first embedded electrode 62 may also be embedded at intervals from the arcuate corner of the interlayer film 50 toward the outer peripheral insulating film 43 side, so that the entire area of ​​the arcuate corner is exposed. The first embedded electrode surface 66 is located on the insulating surface 51 side in the outer opening 56 compared to the height position of the first oxide film 52. Of course, the first embedded electrode surface 66 may also be located on the outer peripheral insulating film 43 side compared to the height position of the first oxide film 52.

[0264] When the first base electrode film 61 is located on the bottom side of the outer groove 57 relative to the first main surface 3, the first embedded electrode 62 may also have a portion located within the outer groove 57. When the first base electrode film 61 has a portion located above the first main surface 3, the entire first embedded electrode 62 is located above the outer groove 57.

[0265] The first main electrode film 63 forms the upper part of the source finger electrode 68, covering the first base electrode film 61 and the plurality of first embedded electrodes 62 in a film-like manner. The first main electrode film 63 is mechanically and electrically connected to the first base electrode film 61 in the portion covering the insulating surface 51, and is mechanically and electrically connected to the plurality of first embedded electrodes 62 in the portion covering the plurality of external openings 56. The first main electrode film 63 is electrically connected to the terminal region 40 (overlapping region 41) via the first base electrode film 61 and the plurality of first embedded electrodes 62.

[0266] The first main electrode film 63 is connected to the first embedded electrode surface 66 at a height relative to the insulating surface 51 on the first main surface 3 side. The first main electrode film 63 is connected to the first embedded electrode surface 66 at a height position higher than that of the first oxide film 52. The first main electrode film 63 has a portion that covers the recessed portion of the first embedded electrode surface 66.

[0267] The first main electrode film 63 may also have a portion with rounded corners that cover the interlayer film 50 across the first base electrode film 61. When the first embedded electrode 62 is located below the first oxide film 52, the first main electrode film 63 may also be connected to the first embedded electrode 62 in a region below the first oxide film 52.

[0268] The film-forming properties of the first main electrode film 63 relative to the plurality of external openings 56 are improved by the plurality of first embedded electrodes 62. This appropriately ensures the current path between the terminal region 40 (overlapping region 41) and the first main electrode film 63. Such a structure is effective in suppressing poor film formation caused by the plurality of external openings 56 and reducing wiring resistance.

[0269] Semiconductor device 1A includes a plurality of second silicide portions 69 formed on the surface portion of a plurality of external openings 56 in a first main surface 3. The plurality of second silicide portions 69 are formed in a film shape along the walls (side walls and bottom walls) of a plurality of external grooves 57 and are mechanically and electrically connected to a first substrate electrode film 61. That is, the plurality of second silicide portions 69 are formed on the surface portion of the terminal region 40 (overlapping region 41), and a plurality of first buried electrodes 62 are electrically connected to the terminal region 40 (overlapping region 41) via the first substrate electrode film 61.

[0270] The second silicide portion 69 may include at least one selected from Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The second silicide portion 69 is preferably composed of Ti silicide, Ni silicide, or Co silicide. The second silicide portion 69 is particularly preferably composed of the same type of silicide as the first silicide portion 67.

[0271] Semiconductor device 1A includes gate finger electrodes 70 selectively wound onto an interlayer film 50. The gate finger electrodes 70 deliver a gate potential to a gate wiring 44. The gate finger electrodes 70 are wound onto a portion of the interlayer film 50 covering the gate wiring 44 (i.e., on the outer peripheral region 9) and electrically connected to the gate wiring 44 via a plurality of gate openings 58.

[0272] The gate finger electrode 70 is disposed spaced apart from the source pad electrode 60 and the source finger electrode 68 in the region between the source pad electrode 60 and the source finger electrode 68. The gate finger electrode 70 extends in a strip shape along the gate wiring 44. When viewed from above, the gate finger electrode 70 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y.

[0273] In this configuration, the gate finger electrode 70 is formed as an ended strip with four sides parallel to the periphery of the first main surface 3, surrounding the source pad electrode 60. The gate finger electrode 70 may also have an edge portion (see reference) where the portion extending in the first direction X and the portion extending in the second direction Y, when viewed from above, are connected in an arc shape (preferably a quarter-arc shape). Figure 6 The gate finger electrode 70 has a pair of open terminals on the fourth side 5D side through which the source finger electrode 68 passes.

[0274] Reference Figure 10 as well as Figure 11 The gate finger electrode 70 includes a second base electrode film 71, at least one (or multiple) second buried electrode 72, and a second main electrode film 73. The second base electrode film 71 may also be referred to as the "gate base electrode film", the second buried electrode 72 as the "gate buried electrode", and the second main electrode film 73 as the "gate main electrode film".

[0275] The second base electrode film 71 forms the lower layer of the gate finger electrode 70 and covers the interlayer film 50 in the outer peripheral region 9. The second base electrode film 71 covers the region in the interlayer film 50 where a plurality of gate openings 58 are formed in a film-like manner and extends from the insulating surface 51 into the plurality of gate openings 58. The second base electrode film 71 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the plurality of gate openings 58 in a film-like manner.

[0276] The second base electrode film 71 has a laminated structure including a first electrode film 74 laminated on the interlayer film 50 and a second electrode film 75 laminated on the first electrode film 74. Preferably, the first electrode film 74 comprises the same conductive material as the first electrode film 64 on the source side, and the second electrode film 75 comprises the same conductive material as the second electrode film 65 on the source side. In this embodiment, the first electrode film 74 comprises a Ti film, and the second electrode film 75 comprises a TiN film.

[0277] The second base electrode film 71 does not necessarily need to have a laminated structure; it can also have a single-layer structure composed of either the first electrode film 74 (Ti film) or the second electrode film 75 (TiN film). The first electrode film 74 can also have a thickness approximately equal to that of the first electrode film 64 on the source side. The second electrode film 75 can also have a thickness approximately equal to that of the second electrode film 65 on the source side.

[0278] The first electrode film 74 covers the region in the interlayer film 50 where multiple gate openings 58 are formed in a film-like manner, and enters the multiple gate openings 58 from the insulating surface 51. That is, the first electrode film 74 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surface of the multiple gate openings 58 in a film-like manner.

[0279] The first electrode film 74 covers the rounded corner of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the gate opening 58. The first electrode film 74 has a portion that extends in an arc shape at the rounded corner. As a result, the film-forming properties of the first electrode film 74 are improved relative to the interlayer film 50 (the wall of the gate opening 58).

[0280] The first electrode film 74 extends along the wall of the gate opening 58, covering the first oxide film 52 and the second oxide film 53. The first electrode film 74 covers the gate wiring 44 in a film-like manner at the bottom of each gate opening 58 and is electrically connected to the gate wiring 44.

[0281] The second electrode film 75 covers the region in the interlayer film 50 where the plurality of gate openings 58 are formed in a film-like manner on the first electrode film 74. That is, the second electrode film 75 has a portion that covers the insulating surface 51 in a film-like manner through the first electrode film 74, and a portion that covers the wall surface of the plurality of gate openings 58 in a film-like manner through the first electrode film 74.

[0282] The second electrode film 75, mimicking the first electrode film 74, covers the rounded corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the gate opening 58. The second electrode film 75 has a portion that extends in an arc shape at the rounded corners of the interlayer film 50 (second oxide film 53). This improves the film-forming properties of the second electrode film 75 relative to the interlayer film 50 (the wall surface of the gate opening 58).

[0283] The second electrode film 75 extends along the wall of the gate opening 58 and covers the first oxide film 52 and the second oxide film 53 through the first electrode film 74. The second electrode film 75 has a portion at the bottom of each gate opening 58 that covers the gate wiring 44 in a film-like manner through the first electrode film 74, and is electrically connected to the gate wiring 44 through the first electrode film 74.

[0284] Multiple second buried electrodes 72 form the middle layer of the gate finger electrode 70 and are respectively buried in multiple gate openings 58. The second buried electrodes 72 include a conductive material different from the conductive material of the second base electrode film 71. The second buried electrodes 72 include at least one of tungsten, molybdenum, tungsten alloys, and molybdenum alloys. Preferably, the second buried electrodes 72 include the same conductive material as the first buried electrode 62. In this embodiment, the second buried electrodes 72 include tungsten.

[0285] In this configuration, multiple second buried electrodes 72 are embedded in multiple gate openings 58 in a one-to-one correspondence, separated by a single second base electrode film 71. The multiple second buried electrodes 72 are electrically connected to the gate wiring 44 within the multiple gate openings 58 via the second base electrode film 71.

[0286] The second buried electrode 72 has a second buried electrode surface 76 exposed from the gate opening 58, thus exposing the insulating surface 51. The second buried electrode surface 76 may also be referred to as the "gate buried electrode surface". The second buried electrode 72 is buried in the gate opening 58 at intervals from the insulating surface 51 toward the first main surface 3, thus exposing the portion of the second base electrode film 71 (second electrode film 75) covering the insulating surface 51. That is, the second buried electrode surface 76 is located on the side of the first main surface 3 compared to the insulating surface 51.

[0287] The second buried electrode 72 covers the first oxide film 52 and the second oxide film 53 through the second base electrode film 71. The second buried electrode 72 has a portion that covers the arcuate corner of the interlayer film 50 through the second base electrode film 71. The second buried electrode 72 may also be buried at intervals from the arcuate corner of the interlayer film 50 toward the gate wiring 44 side, exposing the entire area of ​​the arcuate corner. The second buried electrode surface 76 is located on the insulating surface 51 side at a height position higher than the first oxide film 52. Of course, the second buried electrode surface 76 may also be located on the gate wiring 44 side at a height position higher than the first oxide film 52.

[0288] The second main electrode film 73 forms the upper portion of the gate finger electrode 70, covering the second base electrode film 71 and the plurality of second buried electrodes 72 in a film-like manner. The second main electrode film 73 includes a conductive material that is different from the conductive material of the second base electrode film 71 and the conductive material of the second buried electrodes 72.

[0289] The second main electrode film 73 may also include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. Preferably, the second main electrode film 73 includes the same conductive material as the conductive material of the first main electrode film 63. The second main electrode film 73 may also have a thickness approximately equal to that of the first main electrode film 63.

[0290] The second main electrode film 73 is mechanically and electrically connected to the second base electrode film 71 in the portion covering the insulating surface 51, and is mechanically and electrically connected to the plurality of second buried electrodes 72 in the portion covering the plurality of gate openings 58. Thus, the second main electrode film 73 is electrically connected to the gate wiring 44 via the second base electrode film 71 and the plurality of second buried electrodes 72.

[0291] The second main electrode film 73 is connected to the second embedded electrode 72 at a height relative to the insulating surface 51 on the first main surface 3 side. The second main electrode film 73 is connected to the second embedded electrode surface 76 at a height position higher than that of the first oxide film 52. The second main electrode film 73 has a portion that covers the recessed portion of the second embedded electrode surface 76.

[0292] The second main electrode film 73 may also have a portion that covers the arcuate corner of the interlayer film 50 through the second base electrode film 71. When the second embedded electrode 72 is located below the first oxide film 52, the second main electrode film 73 may also be connected to the second embedded electrode 72 in a region below the first oxide film 52.

[0293] The film-forming properties of the second main electrode film 73 relative to the plurality of gate openings 58 are improved by the plurality of second buried electrodes 72. This appropriately ensures the current path between the gate wiring 44 and the second main electrode film 73. Such a structure is effective in suppressing poor film formation caused by the plurality of gate openings 58 and reducing wiring resistance.

[0294] Semiconductor device 1A includes a gate pad electrode 80 disposed on an interlayer film 50. The gate pad electrode 80 is a terminal electrode to which a gate potential is imparted from the outside. The gate pad electrode 80 may also be referred to as a "second pad electrode," "second main surface electrode," "second terminal electrode," etc. The gate pad electrode 80 is disposed in the region between the source pad electrode 60 and the source finger electrode 68, spaced apart from the source pad electrode 60 and the source finger electrode 68.

[0295] In this configuration, the gate pad electrode 80 is positioned relative to the first pad portion 60a in the region on the third side surface 5C and is sandwiched between the second pad portion 60b and the third pad portion 60c. That is, the gate pad electrode 80 is opposite to the first pad portion 60a in the first direction X, and opposite to the second pad portion 60b and the third pad portion 60c in the second direction Y.

[0296] The gate pad electrode 80, when viewed from above, is formed as a polygon with four sides parallel to the periphery of the chip 2 (in this case, a quadrilateral shape). The gate pad electrode 80 has an area smaller than the planar area of ​​the source pad electrode 60 (first pad portion 60a). The gate pad electrode 80 may also have a planar area smaller than the planar area of ​​the second pad portion 60b (third pad portion 60c).

[0297] The gate pad electrode 80 is disposed on the portion covering the active region 8 and the outer peripheral region 9 and is connected to the gate finger electrode 70. The gate pad electrode 80 may cover multiple gate electrodes 32 through the interlayer film 50, or it may cover the gate wiring 44 through the interlayer film 50.

[0298] The gate pad electrode 80, like the gate finger electrode 70, includes a second base electrode film 71 and a second main electrode film 73. The second base electrode film 71 forms the lower layer of the gate pad electrode 80, covering the interlayer film 50 in a film-like manner. Like the gate finger electrode 70, the second base electrode film 71 has a stacked structure including a first electrode film 74 and a second electrode film 75. The first electrode film 74 covers the interlayer film 50 in a film-like manner, and the second electrode film 75 covers the first electrode film 74 in a film-like manner. The second main electrode film 73 forms the upper layer of the gate pad electrode 80, covering the second base electrode film 71 in a film-like manner.

[0299] Although specific illustrations are omitted, the gate pad electrode 80 may also have a plurality of second buried electrodes 72, similar to the gate finger electrode 70. In this case, the gate pad electrode 80 may also be electrically connected to the gate wiring 44 via a plurality of second buried electrodes 72, similar to the gate finger electrode 70.

[0300] When multiple gate electrodes 32 are disposed below the gate pad electrode 80, the gate pad electrode 80 may also be electrically connected to the multiple gate electrodes 32 via multiple second buried electrodes 72. Of course, the gate pad electrode 80 may also not have multiple second buried electrodes 72. That is, the gate pad electrode 80 may also not have electrical connection portions relative to the multiple gate electrodes 32 and electrical connection portions relative to the gate wiring 44 in the area directly below it.

[0301] The gate potential applied to the gate pad electrode 80 is applied to the gate wiring 44 via the gate finger electrode 70. The gate potential is transmitted to the plurality of gate electrodes 32 via the wiring path (current path) along the gate wiring 44. As a result, the plurality of gate electrodes 32 become in the on state, controlling the on and off state of the plurality of channel regions 26, 27.

[0302] Semiconductor device 1A includes a drain pad electrode 85 covering a second main surface 4. The drain pad electrode 85 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 85 may also be referred to as a "third pad electrode," "third main surface electrode," "third terminal electrode," etc. The drain pad electrode 85 is electrically connected to the base region 14.

[0303] The drain pad electrode 85 has a portion facing the high-concentration region 10 (inner low-concentration region 13) across the base region 14, and a portion facing the low-concentration region 11 across the base region 14. The drain pad electrode 85 may also cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. Alternatively, the drain pad electrode 85 may partially cover the second main surface 4, exposing the periphery of the second main surface 4.

[0304] The breakdown voltage that can be applied between the source pad electrode 60 and the drain pad electrode 85 (between the first main surface 3 and the second main surface 4) can be 500V or higher and 3000V or lower. The breakdown voltage can have a value belonging to at least one of the following ranges: 500V or higher and 1000V or lower, 1000V or higher and 1500V or lower, 1500V or higher and 2000V or lower, 2000V or higher and 2500V or lower, and 2500V or higher and 3000V or lower.

[0305] The semiconductor device 1A includes a chip 2, an n-type high-concentration region 10, and an n-type low-concentration region 11. The chip 2 has a first main surface 3. The high-concentration region 10 has a relatively high first impurity concentration and is formed on the surface layer of the first main surface 3 on the inner side of the chip 2. The low-concentration region 11 has a second impurity concentration lower than the first impurity concentration of the high-concentration region 10 and is formed on the surface layer of the first main surface 3 on the peripheral side of the chip 2.

[0306] According to this structure, a semiconductor device 1A with a novel structure can be provided. According to this semiconductor device 1A, the resistance value of the inner side of the chip 2 can be reduced by utilizing the high-concentration region 10, and the withstand voltage of the peripheral part of the chip 2 can be improved by utilizing the low-concentration region 11.

[0307] Chip 2 preferably includes SiC, which is an example of a wide-bandgap semiconductor. In the case of chip 2 including SiC, when an extremely high voltage is applied to its characteristics (physical properties), the breakdown voltage may decrease due to the electric field at the periphery of chip 2. In this regard, in the case of semiconductor device 1A, a low-concentration region 11 is used to improve the breakdown voltage at the periphery of chip 2 including SiC.

[0308] Chip 2 may also have first to fourth sides 5A to 5D. In this case, the high-concentration region 10 may also be formed spaced apart from at least one of the first to fourth sides 5A to 5D. The low-concentration region 11 may also be exposed from at least one of the first to fourth sides 5A to 5D. According to this structure, the formation area of ​​the low-concentration region 11 extends to the range exposed from at least one of the first to fourth sides 5A to 5D. As a result, the withstand voltage of the peripheral portion of chip 2 is appropriately improved.

[0309] The low-concentration region 11 preferably extends in a strip shape along the high-concentration region 10 when viewed from above. According to this structure, the low-concentration region 11 extending in a strip shape improves the withstand voltage at the periphery of the chip 2. The low-concentration region 11 preferably surrounds the high-concentration region 10 when viewed from above. According to this structure, the withstand voltage at the periphery of the chip 2 is improved throughout the entire circumference of the high-concentration region 10.

[0310] The low-concentration region 11 is preferably connected to the high-concentration region 10. This structure ensures electrical continuity between the high-concentration region 10 and the low-concentration region 11. Therefore, discontinuities in the electric field between the high-concentration region 10 and the low-concentration region 11 are suppressed, and the withstand voltage at the periphery of the chip 2 is appropriately improved. In this case, the low-concentration region 11 forms a region boundary 12 extending in the thickness direction of the chip 2, corresponding to the high-concentration region 10. The region boundary 12 may also extend substantially perpendicularly to the first main surface 3.

[0311] Semiconductor device 1A may also include an n-type inner low-concentration region 13. The inner low-concentration region 13 may also have a third impurity concentration lower than the first impurity concentration of the high-concentration region 10, and is formed in the inner portion of the chip 2 below the high-concentration region 10. According to this structure, the high-concentration region 10 can be used to reduce the resistance value on the inner side of the chip 2, and the inner low-concentration region 13 can be used to improve the breakdown voltage on the inner side of the chip 2.

[0312] In this configuration, the inner low-concentration region 13 is preferably connected to the low-concentration region 11 in the periphery of the chip 2. This structure ensures electrical continuity between the low-concentration region 11 and the inner low-concentration region 13. Consequently, discontinuities in the electric field between the low-concentration region 11 and the inner low-concentration region 13 are suppressed, and the withstand voltage of the periphery of the chip 2 is appropriately increased.

[0313] Semiconductor device 1A may also include a p-type body region 20 (first impurity region) formed on the surface of the high-concentration region 10 in a region on the inner side of the high-concentration region 10. The body region 20 forms a pn junction with the high-concentration region 10, and the depletion layer extends toward the high-concentration region 10 when a reverse bias voltage is applied. According to this structure, the extent of the depletion layer extends toward the periphery of the chip 2 through the low-concentration region 11. As a result, the breakdown voltage at the periphery of the chip 2 is appropriately increased.

[0314] Semiconductor device 1A may also include a p-type outer body region 21 (second impurity region) formed in the peripheral region of chip 2 on either or both of the surface layer of high concentration region 10 and low concentration region 11. The outer body region 21 may also be formed in the surface layer of high concentration region 10, forming a pn junction with high concentration region 10.

[0315] In this case, when a reverse bias voltage is applied, the depletion layer extends towards the high-concentration region 10 in the outer body region 21. According to this structure, the extent of the depletion layer extends towards the periphery of the chip 2 through the low-concentration region 11. Consequently, the breakdown voltage at the periphery of the chip 2 is appropriately increased.

[0316] The outer host region 21 can also be formed as a depletion layer extension that integrates with the depletion layer of the host region 20. The outer host region 21 can also be connected to the host region 20. The outer host region 21 can also have a p-type impurity concentration that is approximately equal to that of the host region 20.

[0317] Semiconductor device 1A may also include a p-type terminal region 40 (third impurity region) formed on the surface layer of either or both of the high-concentration region 10 and the low-concentration region 11. The terminal region 40 may also be formed on the high-concentration region 10, forming a pn junction with it. In this case, when a reverse bias voltage is applied, the terminal region 40 causes the depletion layer to extend towards the high-concentration region 10. According to this structure, the extent of the depletion layer extends towards the periphery of the chip 2 through the low-concentration region 11. Therefore, the breakdown voltage at the periphery of the chip 2 is appropriately increased.

[0318] The terminal region 40 may also be formed as an extended depletion layer integrated with the depletion layer of the main body region 20. Alternatively, the terminal region 40 may be formed as an extended depletion layer integrated with the depletion layer of the outer main body region 21. The terminal region 40 may also be connected to the outer main body region 21. The terminal region 40 may also have a p-type impurity concentration different from that of the main body region 20.

[0319] The terminal region 40 may also have a lead-out portion extending from the high-concentration region 10 to the low-concentration region 11. The lead-out portion of the terminal region 40 forms a pn junction with the low-concentration region 11, causing the depletion layer to extend into the low-concentration region 11 when a reverse bias voltage is applied. According to this structure, the depletion layer appropriately extends from the terminal region 40 to the low-concentration region 11. As a result, the breakdown voltage on the peripheral side of the chip 2 is appropriately increased.

[0320] Semiconductor device 1A may also include a p-type field region 42 (fourth impurity region) formed on the surface portion of the low-concentration region 11. The field region 42 forms a pn junction with the low-concentration region 11, and the depletion layer extends into the low-concentration region 11 when a reverse bias voltage is applied. The extent of the depletion layer of the field region 42 is extended through the low-concentration region 11. As a result, the breakdown voltage on the peripheral side of the chip 2 is appropriately improved.

[0321] Field region 42 is preferably formed by spacing from high concentration region 10 toward the periphery of chip 2. Field region 42 is preferably formed by spacing from main body region 20 toward the periphery of chip 2. Field region 42 is preferably formed by spacing from outer main body region 21 toward the periphery of chip 2. Field region 42 is preferably formed by spacing from terminal region 40 toward the periphery of chip 2.

[0322] Semiconductor device 1A may also include an n-type base region 14. The base region 14 may also have a fourth impurity concentration lower than the first impurity concentration of the high-concentration region 10, and is formed on the inner side of the chip 2 below the high-concentration region 10. The base region 14 may also have a portion extending from the inner side of the chip 2 to the periphery and located below the low-concentration region 11.

[0323] In another viewpoint, semiconductor device 1A includes a chip 2, an active region 8, a peripheral region 9, a high-concentration region 10, and a low-concentration region 11. The chip 2 has a first main surface 3. The active region 8 is disposed on the inner side of the first main surface 3. The peripheral region 9 is disposed on the periphery of the first main surface 3.

[0324] The high-concentration region 10, having a first impurity concentration, is formed in the surface portion of the first main surface 3 within the active region 8. The low-concentration region 11, having a second impurity concentration lower than the first impurity concentration of the high-concentration region 10, is formed in the surface portion of the first main surface 3 within the peripheral region 9. Based on this structure, a semiconductor device 1A with a novel structure can be provided. According to this semiconductor device 1A, the high-concentration region 10 can be used to reduce the resistance value on the active region 8 side, and the low-concentration region 11 can be used to improve the breakdown voltage on the peripheral region 9 side.

[0325] Chip 2 preferably includes SiC, which is an example of a wide-bandgap semiconductor. In the case of chip 2 including SiC, when an extremely high voltage is applied to its characteristics (physical properties), the breakdown voltage may decrease due to the electric field at the periphery of chip 2. In this regard, in the case of semiconductor device 1A, a low-concentration region 11 is used to improve the breakdown voltage on the outer peripheral region 9 side of chip 2 including SiC.

[0326] Chip 2 may also have first to fourth sides 5A to 5D. In this case, the high-concentration region 10 may also be formed spaced apart from at least one of the first to fourth sides 5A to 5D. The low-concentration region 11 may also be exposed from at least one of the first to fourth sides 5A to 5D. According to this structure, the formation area of ​​the low-concentration region 11 extends to the range exposed from at least one of the first to fourth sides 5A to 5D. As a result, the withstand voltage on the peripheral region 9 side is appropriately improved.

[0327] The low-concentration region 11 preferably extends in a strip shape along the high-concentration region 10 when viewed from above. According to this structure, the pressure resistance of the outer peripheral region 9 is improved by utilizing the strip-shaped low-concentration region 11. The low-concentration region 11 preferably surrounds the high-concentration region 10 when viewed from above. According to this structure, the pressure resistance of the outer peripheral region 9 can be improved along the entire circumference of the high-concentration region 10.

[0328] The low-concentration region 11 is preferably connected to the high-concentration region 10. This structure ensures electrical continuity between the high-concentration region 10 and the low-concentration region 11. Consequently, discontinuities in the electric field between the high-concentration region 10 and the low-concentration region 11 are suppressed, and the withstand voltage on the outer peripheral region 9 side is appropriately increased. In this case, the low-concentration region 11 forms a region boundary 12 extending in the thickness direction of the chip 2, corresponding to the high-concentration region 10. The region boundary 12 may also extend substantially perpendicularly to the first main surface 3.

[0329] Semiconductor device 1A may also include an n-type inner low-concentration region 13. The inner low-concentration region 13 may also have a third impurity concentration lower than the first impurity concentration of the high-concentration region 10, and is formed on the active region 8 side below the high-concentration region 10. According to this structure, the resistance value on the active region 8 side can be reduced using the high-concentration region 10, and the breakdown voltage on the active region 8 side can be increased using the inner low-concentration region 13.

[0330] In this configuration, the inner low-concentration region 13 is preferably connected to the low-concentration region 11 on the outer peripheral region 9 side. This structure ensures electrical continuity between the low-concentration region 11 and the inner low-concentration region 13. Consequently, discontinuities in the electric field between the low-concentration region 11 and the inner low-concentration region 13 are suppressed, thereby appropriately increasing the withstand voltage on the outer peripheral region 9 side.

[0331] Semiconductor device 1A may also include a p-type body region 20 (first impurity region) formed on the surface portion of the high-concentration region 10 on the active region 8 side. The body region 20 forms a pn junction with the high-concentration region 10, and the depletion layer extends toward the high-concentration region 10 when a reverse bias voltage is applied. According to this structure, the extent of the depletion layer extends toward the outer peripheral region 9 through the low-concentration region 11. As a result, the breakdown voltage on the outer peripheral region 9 side is appropriately increased.

[0332] Semiconductor device 1A may also include a p-type outer body region 21 (second impurity region) formed in the region on the outer periphery region 9 on either or both of the surface portion of the high concentration region 10 and the surface portion of the low concentration region 11. The outer body region 21 may also be formed in the surface portion of the high concentration region 10, forming a pn junction with the high concentration region 10.

[0333] In this case, when a reverse bias voltage is applied, the depletion layer extends towards the high concentration region 10 in the outer body region 21. According to this structure, the extent of the depletion layer extends towards the outer peripheral region 9 through the low concentration region 11. Thus, the withstand voltage on the outer peripheral region 9 side is appropriately increased.

[0334] The outer host region 21 can also be formed as a depletion layer extension that integrates with the depletion layer of the host region 20. The outer host region 21 can also be connected to the host region 20. The outer host region 21 can also have a p-type impurity concentration that is approximately equal to that of the host region 20.

[0335] Semiconductor device 1A may also include a p-type terminal region 40 (third impurity region) formed in either or both of the surface portions of the high-concentration region 10 and the low-concentration region 11 in the region on the outer peripheral region 9. The terminal region 40 may also be formed in the high-concentration region 10, forming a pn junction with the high-concentration region 10.

[0336] In this case, when a reverse bias voltage is applied, the terminal region 40 causes the depletion layer to extend towards the high concentration region 10. According to this structure, the extent of the depletion layer extends towards the peripheral region 9 through the low concentration region 11. Consequently, the withstand voltage on the peripheral region 9 side is appropriately increased.

[0337] The terminal region 40 may also be formed as a depletion layer extension that is integrated with the depletion layer of the main body region 20. The terminal region 40 may also be formed as a depletion layer extension that is integrated with the depletion layer of the outer main body region 21. The terminal region 40 may also be connected to the outer main body region 21. The terminal region 40 may also have a p-type impurity concentration different from that of the main body region 20.

[0338] The terminal region 40 may also have a lead-out portion extending from the high-concentration region 10 to the low-concentration region 11. The lead-out portion of the terminal region 40 forms a pn junction with the low-concentration region 11, causing the depletion layer to extend into the low-concentration region 11 when a reverse bias voltage is applied. According to this structure, the depletion layer appropriately extends from the terminal region 40 to the low-concentration region 11. Consequently, the withstand voltage on the outer peripheral region 9 side is appropriately increased.

[0339] Semiconductor device 1A may also include a p-type field region 42 (fourth impurity region) formed in the outer peripheral region 9 on the surface portion of the low concentration region 11. The field region 42 forms a pn junction with the low concentration region 11, and the depletion layer extends into the low concentration region 11 when a reverse bias voltage is applied. The extent of the depletion layer in the field region 42 is extended through the low concentration region 11. As a result, the breakdown voltage on the outer peripheral region 9 side is appropriately increased.

[0340] Field region 42 is preferably formed by spacing from high concentration region 10 toward the periphery of chip 2. Field region 42 is preferably formed by spacing from main body region 20 toward the periphery of chip 2. Field region 42 is preferably formed by spacing from outer main body region 21 toward the periphery of chip 2. Field region 42 is preferably formed by spacing from terminal region 40 toward the periphery of chip 2.

[0341] Preferably, the field region 42 extends in a strip shape along the high-concentration region 10 when viewed from above. According to this structure, the depletion layer extends in a strip shape from the field region 42 toward the low-concentration region 11. Thus, the withstand pressure on the outer peripheral region 9 side is appropriately increased. Preferably, the field region 42 surrounds the high-concentration region 10 when viewed from above. According to this structure, the depletion layer extends from the field region 42 toward the low-concentration region 11 in a manner that surrounds the high-concentration region 10. Thus, the withstand pressure on the outer peripheral region 9 side is appropriately increased.

[0342] Multiple field regions 42 can also be formed at intervals on the surface of the low-concentration region 11. According to this structure, multiple depletion layers extend from the multiple field regions 42 toward the low-concentration region 11. Thus, the pressure resistance on the outer peripheral region 9 side is appropriately increased.

[0343] Semiconductor device 1A may also include an n-type base region 14. The base region 14 may also have a fourth impurity concentration lower than the first impurity concentration of the high-concentration region 10, and is a region formed in the active region 8 below the high-concentration region 10. The base region 14 may also have a portion of a region extending from the active region 8 to the peripheral region 9 and located below the low-concentration region 11.

[0344] Semiconductor device 1A may also include a transistor structure Tr formed in the active region 8 as an example of a device structure. In this case, the transistor structure Tr may include a high-concentration region 10. According to this structure, the resistance value of the transistor structure Tr can be reduced by utilizing the high-concentration region 10, and the breakdown voltage of the transistor structure Tr can be increased by utilizing the low-concentration region 11.

[0345] Figure 12 This is a cross-sectional view of the semiconductor device 1B according to the second embodiment. The semiconductor device 1B has a layout that deforms the high-concentration region 10 of the semiconductor device 1A. Specifically, the high-concentration region 10 is formed within the second semiconductor layer 7 over the entire thickness range between the first main surface 3 and the bottom (first semiconductor layer 6) of the second semiconductor layer 7, and is connected to the first semiconductor layer 6. That is, in this embodiment, the semiconductor device 1B does not have an inner low-concentration region 13.

[0346] In this method, the high-concentration region 10 is formed to be substantially perpendicular to the first main surface 3 in cross-section. For example, the high-concentration region 10 can also be formed by introducing n-type impurities into the entire thickness range of the n-type second semiconductor layer 7.

[0347] The low-concentration region 11 is formed in the same layout as in the semiconductor device 1A. In this configuration, the inner edge of the low-concentration region 11 is connected to the periphery of the high-concentration region 10 over the entire thickness range of the high-concentration region 10. That is, the region boundary 12 extends across the depth of the middle portion of the second semiconductor layer 7 in the thickness direction. In this configuration, the lower end of the region boundary 12 is connected to the first semiconductor layer 6.

[0348] Figure 13 This is a cross-sectional view representing a third-party semiconductor device 1C. Figure 14 It means Figure 13 A cross-sectional view of a modified example of the semiconductor device 1C shown. The semiconductor device 1C has a layout that deforms the high-concentration region 10 of the semiconductor device 1B.

[0349] Specifically, the high-concentration region 10, when viewed in cross-section, is formed into a tapered shape whose width in the horizontal direction gradually increases from the first main surface 3 towards the thickness direction. That is, the periphery of the high-concentration region 10 slopes downward from the inner side of the chip 2 (active region 8) toward the periphery of the chip 2 (outer peripheral region 9). The periphery of the high-concentration region 10 (sloping periphery) is located in the outer peripheral region 9.

[0350] This structure is effective in reducing the resistance of the current propagation path when considering the current flowing in the inclined direction between the inner side and the periphery of chip 2 (i.e., current propagation). For example, the inclined portion of the high-concentration region 10 can also be formed by introducing n-type impurities in a direction inclined relative to the first main surface 3 using an inclined ion implantation method.

[0351] The low-concentration region 11 has an inner edge that slopes downwards along the periphery (sloping periphery) of the high-concentration region 10. That is, in cross-section, the low-concentration region 11 is formed as a tapered shape whose width in the horizontal direction gradually decreases from the first main surface 3 towards the thickness direction. This structure effectively reduces the resistance value of the current propagation path and improves the withstand voltage on the periphery side of the chip 2.

[0352] A low-concentration region 11 forms a region boundary 12 that slopes downwards from the high-concentration region 10. The region boundary 12 has an upper end portion on the side of the first main surface 3, a lower end portion on the side of the second main surface 4, and an inclined portion between the upper and lower end portions. The upper end portion is located on the inner side of the chip 2 in the outer peripheral region 9. The lower end portion is located on the peripheral edge side of the chip 2 in the outer peripheral region 9. The inclined portion slopes downwards from the upper end portion toward the lower end portion in the outer peripheral region 9.

[0353] The tilt angle θ (absolute value) of the tilted portion can exceed 0° and be less than 75°. The tilt angle θ is the angle formed between the tilted portion and the imaginary vertical line L when the imaginary vertical line L (imaginary vertical line) perpendicular to the first main surface 3 in cross-section passes through the upper end of the region boundary portion 12.

[0354] The tilt angle θ can have a value belonging to at least one of the following ranges: greater than 0° and less than 15°, greater than 15° and less than 30°, greater than 30° and less than 45°, greater than 45° and less than 60°, and greater than 60° and less than 75°. The tilt angle θ is preferably greater than 20° and less than 60°. The tilt angle θ is particularly preferably greater than 30° and less than 50°.

[0355] At least the innermost field region 42 of the plurality of field regions 42 is preferably formed in the surface portion of the low concentration region 11 at intervals from the upper end of the high concentration region 10 (the upper end of the region boundary portion 12) toward the periphery of the chip 2. The innermost field region 42 may also be opposite the inclined portion of the high concentration region 10 (the inclined portion of the region boundary portion 12) in the thickness direction, separated by a portion of the low concentration region 11.

[0356] It is particularly preferred that the multiple field regions 42 are formed at intervals from the lower end of the high concentration region 10 (the lower end of the region boundary 12) toward the periphery of the chip 2 on the surface layer of the low concentration region 11. That is, it is particularly preferred that the multiple field regions 42 are not opposite to the high concentration region 10 in the thickness direction.

[0357] like Figure 14 As shown, semiconductor device 1C may also have an inner low-concentration region 13. That is, the high-concentration region 10 may also be formed similarly to semiconductor device 1A, spaced apart from the bottom of the second semiconductor layer 7 toward the first main surface, and facing the first semiconductor layer 6 across a portion of the second semiconductor layer 7. In this case, the inner low-concentration region 13 is connected to the bottom side region of the low-concentration region 11 in the outer peripheral region 9 below the lower end of the high-concentration region 10 (the lower end of the region boundary portion 12).

[0358] Figure 15 This is a cross-sectional view of a semiconductor device 1D representing a fourth embodiment. The semiconductor device 1D has a layout that deforms the layout within the chip 2 of the semiconductor device 1C. Specifically, in this embodiment, low-concentration regions 11 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, having a bottom located within the second semiconductor layer 7.

[0359] The low-concentration region 11 may also extend across the depth of the middle portion of the second semiconductor layer 7 in the thickness direction. That is, the thickness of the low-concentration region 11 may be more than half the thickness of the second semiconductor layer 7. Of course, the low-concentration region 11 may also be formed at intervals from the depth of the middle portion of the second semiconductor layer 7 toward the first main surface 3. That is, the thickness of the low-concentration region 11 may be less than half the thickness of the second semiconductor layer 7.

[0360] In this configuration, the semiconductor device 1D includes an n-type outer high-concentration region 15 formed on the surface portion of the first main surface 3 below the low-concentration region 11. The outer high-concentration region 15 may also be referred to as a "fifth region," "fourth drift region," or "second high-concentration drift region," etc. The outer high-concentration region 15 has a fifth impurity concentration that is higher than the second impurity concentration of the low-concentration region 11. The fifth impurity concentration can be 1 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 the following.

[0361] The outer high-concentration region 15 is formed on the peripheral side of the chip 2 relative to the high-concentration region 10. The outer high-concentration region 15 extends in a layer along the low-concentration region 11 in the outer peripheral region 9 and is connected to the low-concentration region 11 in the thickness direction. Thus, the outer high-concentration region 15 and the low-concentration region 11 are electrically connected.

[0362] The outer high-concentration region 15 is formed in the outer peripheral region 9 as a low-resistance region (second low-resistance region) with a lower resistance value than the low-concentration region 11. Such a structure is effective in reducing the resistance value of the current expansion path when considering the current flowing in the inclined direction between the inner side of the chip 2 and the peripheral side of the chip 2 (i.e., current expansion).

[0363] The outer high-concentration region 15 is formed in the outer peripheral region 9 between the periphery of the first main surface 3 and the high-concentration region 10, extending in a strip shape along the high-concentration region 10 (active region 8) when viewed from above. The outer high-concentration region 15 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y when viewed from above, dividing the high-concentration region 10 (active region 8) from multiple directions. In this manner, the outer high-concentration region 15 is formed in a ring shape (in this manner, a quadrilateral ring shape) surrounding the high-concentration region 10 (active region 8) when viewed from above. The outer high-concentration region 15 is preferably formed over the entire region below the low-concentration region 11.

[0364] The outer high-concentration region 15 has an outer edge portion on the peripheral side of the first main surface 3 and an inner edge portion on the inner side of the first main surface 3. The inner edge portion of the outer high-concentration region 15 is connected to the peripheral portion of the high-concentration region 10. In this configuration, the outer high-concentration region 15 is connected to the high-concentration region 10 in the outer peripheral region 9. Thus, the outer high-concentration region 15 and the high-concentration region 10 are electrically connected.

[0365] The concentration of the fifth impurity in the outer high-concentration region 15 is preferably approximately equal to the concentration of the first impurity in the region at the bottom side of the high-concentration region 10. The outer edge of the outer high-concentration region 15 is preferably exposed from at least one of the first to fourth side surfaces 5A to 5D. In this configuration, the entire outer edge of the outer high-concentration region 15 is exposed from the first to fourth side surfaces 5A to 5D.

[0366] In this configuration, the outer high-concentration region 15 is formed in the second semiconductor layer 7. That is, the semiconductor device 1D has a multilayer structure including a low-concentration region 11 and an outer high-concentration region 15 in the peripheral portion (outer peripheral region 9) of the second semiconductor layer 7. For example, the outer high-concentration region 15 can also be formed by introducing an n-type impurity into a portion (bottom side region) of the n-type second semiconductor layer 7.

[0367] The outer high-concentration region 15 is formed within the second semiconductor layer 7 over the entire thickness range between the bottom of the second semiconductor layer 7 (first semiconductor layer 6) and the bottom of the low-concentration region 11, and is connected to the first semiconductor layer 6. When the low-concentration region 11 is located at a depth that traverses the middle portion of the second semiconductor layer 7 in the thickness direction, the thickness of the outer high-concentration region 15 is less than half the thickness of the second semiconductor layer 7. When the low-concentration region 11 is formed closer to the first main surface 3 than the middle portion of the second semiconductor layer 7, the thickness of the outer high-concentration region 15 is greater than half the thickness of the second semiconductor layer 7.

[0368] Multiple field regions 42 are formed on the surface portion of the low-concentration region 11 in the same manner as in the semiconductor device 1A. In this manner, multiple field regions 42 are formed at intervals from the bottom of the low-concentration region 11 toward the first main surface 3, and are opposite to the outer high-concentration region 15 across a portion of the low-concentration region 11.

[0369] The plurality of field regions 42 are preferably formed at intervals from the middle portion of the low-concentration region 11 toward the first main surface 3. That is, the thickness of the plurality of field regions 42 may also be less than half the thickness of the low-concentration region 11. Of course, the plurality of field regions 42 may also traverse the middle portion of the low-concentration region 11 in the thickness direction. That is, the thickness of the plurality of field regions 42 may also be more than half the thickness of the low-concentration region 11.

[0370] In this configuration, the drain pad electrode 85 has a portion that faces the high concentration region 10 across the base region 14, and a portion that faces the low concentration region 11 (outer high concentration region 15) across the base region 14.

[0371] Figure 16 This is an enlarged top view showing the main part of the active region 8 of the semiconductor device 1E of the fifth type. Figure 17 It is along Figure 16 A sectional view along line XVII-XVII shown. Figure 17 The example shown illustrates the application of the structure of semiconductor device 1A (high concentration region 10, low concentration region 11, etc.) to semiconductor device 1E. Of course, the structure of semiconductor devices 1B to 1D (high concentration region 10, low concentration region 11, outer high concentration region 15, etc.) can also be applied to semiconductor device 1E.

[0372] Reference Figure 16 as well as Figure 17 Semiconductor device 1E is a semiconductor switching device that has a trench gate transistor structure Tr in the active region 8, which is an example of a device structure, instead of a planar gate transistor structure Tr.

[0373] Semiconductor device 1E has a single main body region 20 instead of multiple main body regions 20. The single main body region 20 is formed in the surface portion of the first main surface 3 over the entire region of the active region 8. The single main body region 20 is formed in the surface portion of the high concentration region 10. The single main body region 20 is formed at intervals from the bottom of the high concentration region 10 toward the first main surface 3, and is opposite to the inner low concentration region 13 (base region 14) across a portion of the high concentration region 10.

[0374] The single main body region 20 is preferably formed at intervals from the middle of the high concentration region 10 toward the first main surface 3. Of course, the single main body region 20 may also extend across the depth of the middle of the high concentration region 10 in the thickness direction. The single main body region 20 is exposed from the first main surface 3.

[0375] The single body region 20 has a high-concentration region 10 and a pn junction (pn junction diode: body diode). When a reverse bias voltage is applied, the single body region 20 causes the depletion layer to extend towards the high-concentration region 10. The depletion layer extends from the high-concentration region 10 to the low-concentration region 11 in a horizontal direction along the first main surface 3.

[0376] Similar to the semiconductor device 1A, the aforementioned outer body region 21 is formed in the outer peripheral region 9 on the surface of the first main surface 3 (high concentration region 10). In this configuration, the outer body region 21 covers the entire circumference of the active region 8 and is connected to the single body region 20. The outer body region 21 can be considered as being formed from the peripheral portion of the single body region 20.

[0377] In the active region 8, the semiconductor device 1E has a plurality of trench electrode-type gate structures 35 instead of planar electrode-type gate structures 30. The plurality of gate structures 35 are arranged at intervals in a first direction X, and are each formed into a stripe extending in a second direction Y. That is, the plurality of gate structures 35 are arranged in a stripe-like pattern extending along the second direction Y. Furthermore, the extension direction of the plurality of gate structures 35 is consistent with the offset direction of the SiC single crystal.

[0378] In this configuration, a plurality of gate structures 35 are formed spaced apart from the bottom of the high-concentration region 10 toward the first main surface 3, and are opposed to the inner low-concentration region 13 (base region 14) across a portion of the high-concentration region 10. That is, the plurality of gate structures 35 are formed shallower than the high-concentration region 10 and are opposed to the low-concentration region 11 in the horizontal direction.

[0379] Multiple gate structures 35 each include a trench 36, an insulating film 31, and a gate electrode 32. The trench 36 is formed on the first main surface 3, dividing the walls (sidewalls and bottom walls) of the gate structure 35. The insulating film 31 covers the walls of the trench 36 in a film-like manner. The gate electrode 32 is embedded in the trench 36 through the insulating film 31.

[0380] The aforementioned multiple source regions 23 and 24 are respectively formed on both sides of the multiple gate structures 35 on the surface of a single main body region 20. The first source region 23 is formed along one sidewall of the corresponding gate structure 35 and is opposed to the gate electrode 32 through the insulating film 31. The second source region 24 is formed along the other sidewall of the corresponding gate structure 35 and is opposed to the gate electrode 32 through the insulating film 31.

[0381] Multiple source regions 23 and 24 extend in a strip shape along the extension direction of multiple gate structures 35. Multiple source regions 23 and 24 are formed at intervals from the bottom of a single main body region 20 toward the first main surface 3, and are opposite to the high concentration region 10 through a part of the single main body region 20.

[0382] The aforementioned multiple contact regions 25 are respectively formed on the surface of a single main body region 20 in the region between multiple source regions 23 and 24. The multiple contact regions 25 extend in a strip shape along the extension direction of the multiple gate structures 35. The multiple contact regions 25 are formed at intervals from the bottom of the single main body region 20 toward the first main surface 3, and are opposite to the high concentration region 10 across a portion of the single main body region 20.

[0383] The aforementioned multiple channel regions 26 and 27 are respectively divided into the bottom of a single main body region 20 (high-concentration region 10) and the region between multiple source regions 23 and 24. The first channel region 26 is divided into the region between the bottom of the single main body region 20 (high-concentration region 10) and the first source region 23, forming a current path extending along the sidewall of the gate structure 35 in the stacking direction. The second channel region 27 is divided into the region between the bottom of the single main body region 20 (high-concentration region 10) and the second source region 24, forming a current path extending along the sidewall of the gate structure 35 in the stacking direction.

[0384] When a gate potential is applied to the gate electrode 32, the channel regions 26 and 27 become conductive, and the drain current flows through the channel regions 26 and 27 (main body region 20) between the high concentration region 10 and the source regions 23 and 24. In this way, a trench gate transistor structure Tr including the high concentration region 10 is formed in the inner part (active region 8) of the chip 2.

[0385] Similar to semiconductor device 1A, semiconductor device 1E includes a terminal region 40 (overlapping region 41), multiple field regions 42, a peripheral insulating film 43, gate wiring 44, an interlayer film 50, multiple source openings 54, multiple source recesses 55, multiple external openings 56, multiple external recesses 57, multiple gate openings 58, source pad electrodes 60, multiple first silicide portions 67, source finger electrodes 68, multiple second silicide portions 69, gate finger electrodes 70, gate pad electrodes 80, and drain pad electrodes 85. Descriptions of these structures are the same as in semiconductor device 1A and are therefore omitted.

[0386] Figure 18 This is a top view of the semiconductor device 1F in the sixth configuration. Figure 19 It is along Figure 18 The cross-sectional view along line XIX-XIX is shown. Semiconductor device 1F is a semiconductor rectifier device that has a diode structure Di as an example of a device structure, instead of a transistor structure Tr. In this configuration, the diode structure Di is an SBD structure (Schottky Barrier Diode structure).

[0387] Reference Figure 18 as well as Figure 19 Similar to semiconductor device 1A, semiconductor device 1F includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, a peripheral region 9, a high-concentration region 10, a low-concentration region 11, a region boundary 12, an inner low-concentration region 13, a terminal region 40, and multiple field regions 42. Descriptions of these structures are the same as in semiconductor device 1A and are therefore omitted.

[0388] Semiconductor device 1F includes an interlayer film 90 selectively covering a first main surface 3. The interlayer film 90 may also have a monolayer structure or a stacked structure including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer film 90 has a monolayer structure including a silicon oxide film.

[0389] The interlayer film 90 covers the low-concentration region 11, the terminal region 40, and multiple field regions 42 in the outer peripheral region 9. In this configuration, the interlayer film 90 is connected to the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D). Alternatively, the interlayer film 90 can be formed at intervals from the periphery of the first main surface 3 inwards, exposing the second semiconductor layer 7 (low-concentration region 11) from the periphery of the first main surface 3.

[0390] Semiconductor device 1F includes a contact opening 91 in an interlayer film 90 that exposes a high-concentration region 10. In this configuration, the contact opening 91 has an opening wall on a terminal region 40, exposing the high-concentration region 10 and the inner edge of the terminal region 40. The opening wall, when viewed from above, is formed as a polygon (in this configuration, a quadrilateral shape) with four sides parallel to the periphery of the chip 2, exposing the entire circumference of the inner periphery of the terminal region 40.

[0391] Semiconductor device 1F includes an anode pad electrode 92 disposed on a first main surface 3. The anode pad electrode 92 is a terminal electrode to which an anode potential is applied from the outside. The anode pad electrode 92 may also be referred to as a "first pad electrode," "first main surface electrode," "first terminal electrode," etc. The anode pad electrodes 92 are disposed at intervals from the periphery of the chip 2 inward. When viewed from above, the anode pad electrodes 92 are formed in a polygonal shape (quadrilateral shape in this case) along the periphery of the chip 2.

[0392] The anode pad electrode 92 enters the contact opening 91 from the interlayer film 90 and is electrically connected to the high-concentration region 10 and the inner edge of the terminal region 40 within the contact opening 91. The anode pad electrode 92 and the high-concentration region 10 form a Schottky junction. This forms a diode structure Di including the high-concentration region 10. The anode pad electrode 92 has a portion within the contact opening 91 that faces the high-concentration region 10 across the terminal region 40.

[0393] The anode pad electrode 92 has a peripheral portion that covers the terminal region 40 through the interlayer film 90. That is, the peripheral portion of the anode pad electrode 92 has a portion that faces the high concentration region 10 in the stacking direction. The peripheral portion of the anode pad electrode 92 may also have a portion that crosses the region boundary portion 12 in the horizontal direction and covers the low concentration region 11 through the interlayer film 90.

[0394] The peripheral portion of the anode pad electrode 92 may also be formed at intervals from the innermost field region 42 inwards. The peripheral portion of the anode pad electrode 92 may also have a portion that covers the innermost field region 42 through the interlayer film 90. The peripheral portion of the anode pad electrode 92 may also cover multiple field regions 42 through the interlayer film 90.

[0395] Semiconductor device 1F includes a cathode pad electrode 93 covering a second main surface 4. The cathode pad electrode 93 is a terminal electrode to which a cathode potential is imparted from the outside. The cathode pad electrode 93 may also be referred to as a "second pad electrode," "second main surface electrode," "second terminal electrode," etc. The cathode pad electrode 93 is electrically connected to the base region 14.

[0396] In this configuration, the cathode pad electrode 93 has a portion opposite the high-concentration region 10 across the base region 14, and a portion opposite the low-concentration region 11 across the base region 14. The cathode pad electrode 93 may also cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. Alternatively, the cathode pad electrode 93 may partially cover the second main surface 4 such that the periphery of the second main surface 4 is exposed.

[0397] The breakdown voltage that can be applied between the anode pad electrode 92 and the cathode pad electrode 93 (between the first main surface 3 and the second main surface 4) can be 500V or more and 3000V or less. The breakdown voltage can have a value belonging to at least one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or less, and 2500V or more and 3000V or less.

[0398] The structures of the semiconductor devices 1B to 1D of the second to fourth methods described above (refer to...) Figures 12-15 The structure of the semiconductor device 1F, which can be applied to the sixth method (see reference). Figure 19 ).exist Figures 20-22 In the text, these structures are represented as the seventh to ninth methods. Figure 20 This is a cross-sectional view representing the semiconductor device 1G of the seventh mode. Figure 21 This is a cross-sectional view of the semiconductor device 1H in the eighth configuration. Figure 22 This is a cross-sectional view of the semiconductor device 1I of the ninth type.

[0399] Reference Figure 20 Semiconductor device 1G has the function of integrating semiconductor device 1B (refer to...) Figure 12 The high-concentration region 10 and the low-concentration region 11 are combined with the semiconductor device 1F. (Refer to...) Figure 21 Semiconductor device 1H has the function of integrating semiconductor device 1C (refer to...) Figure 13 as well as Figure 14 The high-concentration region 10 and the low-concentration region 11 are combined with the semiconductor device 1F. (Refer to...) Figure 22 Semiconductor device 1I has semiconductor device 1D (refer to) Figure 15 The high-concentration region 10, the low-concentration region 11, and the outer high-concentration region 15 are combined with the semiconductor device 1F.

[0400] The following are modified examples of semiconductor devices 1A to 1I applied to the first to ninth methods. Figure 23 This is a cross-sectional view showing a modified example of the outer main body region 21. In Figure 23The example shown illustrates the structure of a modified example applied to a semiconductor device 1A (first embodiment), but the structure of the modified example can be applied to all semiconductor devices 1A to 1I (first to ninth embodiments).

[0401] Of the above methods, an example is shown where the outer body region 21 is formed at intervals from the periphery of the high concentration region 10 inwards. However, as... Figure 23 As shown, the outer edge of the outer main body region 21 can also cross the periphery of the high concentration region 10 and be located in the low concentration region 11.

[0402] That is, the outer body region 21 may also be located on the surface of the low concentration region 11 in the outer peripheral region 9, having a portion (outer edge) that forms a pn junction with the low concentration region 11. In this structure, the depletion layer extends directly from the outer body region 21 to the low concentration region 11. Therefore, the extent of the depletion layer appropriately expands at the periphery (outer peripheral region 9) of the chip 2.

[0403] In this case, the terminal region 40 is located on the periphery of the chip 2 relative to the periphery of the high-concentration region 10, on the surface of the low-concentration region 11. That is, the entire area of ​​the terminal region 40 is located on the surface of the low-concentration region 11. The inner edge of the terminal region 40 is connected to the outer edge of the outer body region 21 on the surface of the low-concentration region 11. That is, the terminal region 40 and the outer body region 21 form an overlapping region 41 on the surface of the low-concentration region 11.

[0404] In this structure, the depletion layer extends directly from the entire terminal region 40 to the low-concentration region 11. Therefore, the extent of the depletion layer appropriately extends to the periphery (outer peripheral region 9) of the chip 2. Of course, the terminal region 40 may also have a p-type impurity concentration approximately equal to that of the outer body region 21, forming a part (lead-out portion) of the outer body region 21.

[0405] Figure 24 This is a cross-sectional view showing a modified example of field region 42. Figure 24 The example shown illustrates a modified structure applied to semiconductor device 1A (first embodiment), but the modified structure can be applied to all semiconductor devices 1A to 1I (first to ninth embodiments). In the aforementioned embodiments, an example is shown where multiple field regions 42 are formed on the surface layer of the low-concentration region 11. However, as... Figure 24 As shown, a single field region 42 can also be formed in the surface layer of the low concentration region 11.

[0406] A single field region 42 is formed at intervals from the periphery of the first main surface 3 between the terminal region 40 and the outer main body region 21. The single field region 42 extends in a strip shape along the terminal region 40 when viewed from above. The single field region 42 has a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y when viewed from above, dividing the active region 8 from multiple directions.

[0407] A single field region 42, when viewed from above, surrounds the terminal region 40 and is divided into a polygonal ring (in this case, a quadrilateral ring) with four sides parallel to the periphery of the first main surface 3. The single field region 42 may also have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above.

[0408] The ratio of the width of a single field region 42 to the width of the low-concentration region 11 can also be greater than 0.1 and less than 1. The width ratio can have a value belonging to at least one of the following ranges: greater than 0.1 and less than 0.2, greater than 0.2 and less than 0.4, greater than 0.4 and less than 0.6, greater than 0.6 and less than 0.8, and greater than 0.8 and less than 1.

[0409] A single field region 42 is formed spaced apart from the bottom of the low-concentration region 11 toward the first main surface 3, and is opposite to the base region 14 across a portion of the low-concentration region 11. A single field region 42 is also formed spaced apart from a depth position at the bottom of the high-concentration region 10 toward the first main surface 3. Preferably, the single field region 42 is formed spaced apart from a depth position at the middle portion of the high-concentration region 10 toward the first main surface 3. Alternatively, the single field region 42 may also extend across the depth position at the middle portion of the high-concentration region 10 in the thickness direction.

[0410] A single field region 42 has an inner edge on the side of the terminal region 40 and an outer edge on the peripheral side of the first main surface 3. In this configuration, the inner edge of the single field region 42 is connected to the outer edge of the terminal region 40. Thus, the single field region 42 is electrically connected to the terminal region 40. In this configuration, the inner edge of the single field region 42 is connected to the outer edge of the terminal region 40 over its entire circumference.

[0411] When a single field region 42 has a p-type impurity concentration approximately equal to that of the terminal region 40, the single field region 42 can also serve as an outlet of the terminal region 40, extending from the terminal region 40 to the surface portion of the low-concentration region 11. That is, the terminal region 40 can also have a single field region 42 serving as an outlet. Of course, the single field region 42 can also be formed at a distance from the terminal region 40.

[0412] Figure 25This is a cross-sectional view showing a first modified example of the source pad electrode 60. Figure 25 The example shown illustrates the structure of a modified example applied to a semiconductor device 1A (first type), but the structure of the modified example can be applied to all semiconductor devices 1A to 1E (first to fifth types).

[0413] In the aforementioned first to fifth methods, multiple first embedded electrodes 62 are embedded in multiple source openings 54 such that the insulating surface 51 is exposed. However, as... Figure 25 As shown, the source pad electrode 60 may also have a plurality of first buried electrodes 62 extending from a plurality of source openings 54 onto an insulating surface 51 and covering the insulating surface 51.

[0414] Multiple first buried electrodes 62 cover a first base electrode film 61 on an insulating surface 51, with portions covering the insulating surface 51 through the first base electrode film 61. Specifically, each of the multiple first buried electrodes 62 has a first buried electrode surface 66 exposed above the insulating surface 51 from multiple source openings 54. The multiple first buried electrodes 62 have portions that face the gate electrode 32 in the stacking direction (vertical direction Z) through the first base electrode film 61 and the interlayer film 50.

[0415] Multiple first embedded electrodes 62 are integrated on the insulating surface 51 to form an intermediate electrode 95. The intermediate electrode 95 (multiple first embedded electrodes 62) covers the entire area of ​​the first base electrode film 61. The electrode surface (first embedded electrode surface 66) of the intermediate electrode 95 is located above the insulating surface 51.

[0416] In this configuration, the first main electrode film 63 is mechanically and electrically connected to the first embedded electrode surfaces 66 of the plurality of first embedded electrodes 62 (intermediate electrodes 95) above the insulating surface 51. The first main electrode film 63 has a portion that faces the insulating surface 51 across the plurality of first embedded electrodes 62 (intermediate electrodes 95). In this configuration, the first main electrode film 63 does not have a mechanical connection portion relative to the first base electrode film 61.

[0417] The structure of the plurality of first buried electrodes 62 (intermediate electrodes 95) in the modified example can also be applied to the plurality of first buried electrodes 62 of the source finger electrode 68. Similarly, the structure of the plurality of first buried electrodes 62 (intermediate electrodes 95) in the modified example can also be applied to the plurality of second buried electrodes 72 of the gate finger electrode 70.

[0418] Figure 26 This is a cross-sectional view showing a second modified example of the source pad electrode 60. Figure 26 The example shown illustrates the structure of a modified example applied to a semiconductor device 1A (first type), but the structure of the modified example can be applied to all semiconductor devices 1A to 1E (first to fifth types).

[0419] In the aforementioned first to fifth methods, the source pad electrode 60 has a plurality of first buried electrodes 62. However, the source pad electrode 60 does not necessarily need to have first buried electrodes 62. In this case, the first main electrode film 63 of the source pad electrode 60 enters a plurality of source openings 54 from the interlayer film 50 and is electrically connected to the main body region 20 within the plurality of source openings 54.

[0420] Similarly, the source finger electrode 68 does not necessarily need to have a first embedded electrode 62. In this case, the first main electrode film 63 of the source finger electrode 68 enters from the interlayer film 50 into a plurality of external openings 56, and is electrically connected to the terminal region 40 (overlapping region 41) within the plurality of external openings 56.

[0421] Similarly, the gate finger electrode 70 does not necessarily need to have a second buried electrode 72. In this case, the second main electrode film 73 of the gate finger electrode 70 enters from the interlayer film 50 into a plurality of gate openings 58 and is electrically connected to the gate wiring 44 within the plurality of gate openings 58.

[0422] Semiconductor devices 1A to 1E may also have a first buried electrode 62 of source pad electrode 60, but without a first buried electrode 62 of source finger electrode 68.

[0423] Semiconductor devices 1A to 1E may also have a first buried electrode 62 of the source pad electrode 60, but without a second buried electrode 72. Semiconductor devices 1A to 1E may also have a second buried electrode 72, but without a first buried electrode 62 of the source pad electrode 60. Semiconductor devices 1A to 1E may also have a first buried electrode 62 of the source finger electrode 68, but without a second buried electrode 72. Semiconductor devices 1A to 1E may also have a second buried electrode 72, but without a first buried electrode 62 of the source finger electrode 68.

[0424] The aforementioned methods (including variations) can also be implemented in other ways. For example, in the above methods, a structure in which the relationship between the a-axis direction and the m-axis direction is reversed can also be used. The specific structure in this case is obtained by reversing the "a-axis direction (offset direction)" and the "m-axis direction (direction orthogonal to the offset direction)" in the foregoing description and figures.

[0425] In the aforementioned methods, a structure can also be adopted in which the conductivity type of the "n-type" semiconductor region is reversed to "p-type" and the conductivity type of the "p-type" semiconductor region is reversed to "n-type". The specific structure in this case is obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the foregoing description and figures.

[0426] In the above embodiments, chip 2, including SiC single crystal, is used. However, chip 2 may also include single crystals of wide-bandgap semiconductors other than SiC single crystals. Wide-bandgap semiconductors are semiconductors with a bandgap larger than that of silicon. Examples of single crystals of wide-bandgap semiconductors include gallium nitride, gallium oxide, and diamond. Of course, chip 2 may also include single-crystal silicon.

[0427] Similarly, the first semiconductor layer 6 may also include a single crystal of a wide-bandgap semiconductor other than SiC. The first semiconductor layer 6 may also include gallium nitride, gallium oxide, diamond, etc. Of course, the first semiconductor layer 6 may also include single-crystal silicon.

[0428] Similarly, the second semiconductor layer 7 may also include a single crystal of a wide-bandgap semiconductor other than SiC. The second semiconductor layer 7 may also include gallium nitride, gallium oxide, diamond, etc. Of course, the second semiconductor layer 7 may also include single-crystal silicon.

[0429] In the first to fifth embodiments described above, an n-type base region 14 is shown. However, a p-type base region 14 may be used instead of an n-type base region 14. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of a MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure. The p-type base region 14 may also include an impurity region containing p-type impurities that is implanted into the surface layer of the second main surface 4 of the chip 2 (n-type chip 2) by ion implantation.

[0430] In the sixth to ninth embodiments described above, an SBD structure (Schottky barrier diode) is shown as an example of diode structure Di. However, diode structure Di may also include at least one of pn junction diode, pin junction diode, Zener diode, and fast recovery diode. In these cases, diode structure Di may also include one or more p-type anode regions that form a pn junction with the surface portion of high concentration region 10.

[0431] The following are examples of features extracted from this specification and accompanying drawings. Hereinafter, alphanumeric characters, etc., denote corresponding constituent elements in the aforementioned embodiments, but are not intended to limit the scope of each claim to the aforementioned embodiments. The term "semiconductor device" in the following item can be replaced as needed with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," "semiconductor rectifier device," etc.

[0432] [A1] A semiconductor device 1A-1I includes: a chip 2 having a main surface 3; a high-concentration region 10 of a first conductivity type (n-type) formed on the surface of the main surface 3 on the inner side of the chip 2; and a low-concentration region 11 of the first conductivity type (n-type) formed on the surface of the main surface 3 on the peripheral side of the chip 2, and having an impurity concentration lower than that of the high-concentration region 10.

[0433] [A2] The semiconductor devices 1A to 1I according to A1, wherein the chip 2 comprises SiC.

[0434] [A3] The semiconductor device 1A to 1I according to A1 or A2, wherein the chip 2 has sides 5A to 5D, the high concentration region 10 is formed at intervals from the sides 5A to 5D, and the low concentration region 11 is exposed from the sides 5A to 5D.

[0435] [A4] Semiconductor devices 1A-1I according to any one of A1 to A3, wherein the low concentration region 11 extends in a strip shape along the high concentration region 10 when viewed from above.

[0436] [A5] Semiconductor devices 1A-1I according to any one of A1 to A4, wherein the low-concentration region 11 surrounds the high-concentration region 10 when viewed from above.

[0437] [A6] Semiconductor devices 1A-1I according to any one of A1 to A5, wherein the low concentration region 11 is connected to the high concentration region 10.

[0438] [A7] The semiconductor device 1A-1I according to any one of A1 to A6 further includes: an inner low-concentration region 13 of a first conductivity type (n-type), which is formed on the inner side of the chip 2 below the high-concentration region 10, and has an impurity concentration lower than that of the high-concentration region 10.

[0439] [A8] In the semiconductor devices 1A to 1I according to A7, the inner low-concentration region 13 is connected to the low-concentration region 11 on the peripheral side of the chip 2.

[0440] [A9] The semiconductor device 1A-1I according to any one of A1 to A8 further includes: an outer high-concentration region 15 of a first conductivity type (n-type), which is formed on the periphery side of the chip 2 below the low-concentration region 11 and has an impurity concentration higher than that of the low-concentration region 11.

[0441] [A10] In the semiconductor devices 1A to 1I according to A9, the outer high-concentration region 15 is connected to the high-concentration region 10 on the inner side of the chip 2.

[0442] [A11] The semiconductor device 1A-1I according to any one of A1 to A10 further includes: a base region 14 of a first conductivity type (n-type), which is formed on the inner side of the chip 2 below the high concentration region 10, and has an impurity concentration higher than that of the high concentration region 10.

[0443] [A12] The semiconductor device 1A to 1I according to any one of A1 to A11 further includes: second conductivity type (p-type) impurity regions 20, 21, 40, which are formed on the surface portion of the high concentration region 10.

[0444] [A13] The semiconductor device 1A to 1I according to any one of A1 to A12 further includes: a second conductivity type (p-type) field region 42 formed on the surface portion of the low concentration region 11.

[0445] [A14] A semiconductor device 1A-1I includes: a chip 2 having a main surface 3; an active region 8 disposed on an inner side of the main surface 3; an outer peripheral region 9 disposed on a periphery of the main surface 3; a high-concentration region 10 of a first conductivity type (n-type) formed in the active region 8 on the surface of the main surface 3; and a low-concentration region 11 of the first conductivity type (n-type) formed in the outer peripheral region 9 on the surface of the main surface 3, having an impurity concentration lower than that of the high-concentration region 10.

[0446] [A15] The semiconductor devices 1A to 1I according to A14, wherein the chip 2 comprises SiC.

[0447] [A16] The semiconductor device 1A to 1I according to A14 or A15 further includes: a second conductivity type (p-type) field region 42, which is formed in the outer peripheral region 9 on the surface portion of the low concentration region 11.

[0448] [A17] In the semiconductor devices 1A to 1I according to A16, the field region 42 is formed at intervals from the high concentration region 10 on the surface portion of the low concentration region 11.

[0449] [A18] The semiconductor device 1A-1I according to any one of A14 to A17 further includes: second conductivity type impurity regions 20, 21, 40, which are formed in the active region 8 on the surface portion of the high concentration region 10.

[0450] [A19] The semiconductor device 1A to 1I according to any one of A14 to A18 further includes: a second conductivity type (p-type) terminal region 40, which is formed in the outer peripheral region 9 in either or both of the surface portion of the high concentration region 10 and the surface portion of the low concentration region 11.

[0451] [A20] The semiconductor device 1A-1I according to any one of A14 to A19 further includes: device structures Tr and Di, which include the high-concentration region 10 and are formed in the active region 8.

[0452] The above details the specific methods, but these are merely specific examples illustrating the technical content. The various technical ideas extracted from this specification are not limited to the order of description, the order of method examples, or the order of variations within the specification; they can be appropriately combined.

[0453] Symbol Explanation

[0454] 1A—Semiconductor device; 1B—Semiconductor device; 1C—Semiconductor device; 1D—Semiconductor device; 1E—Semiconductor device; 1F—Semiconductor device; 1G—Semiconductor device; 1H—Semiconductor device; 1I—Semiconductor device; 2—Chip; 3—First main surface; 5A—First side surface; 5B—Second side surface; 5C—Third side surface; 5D—Fourth side surface; 8—Active region; 9—Outer peripheral region; 10—High concentration region; 11—Low concentration region; 13—Inner low concentration region; 14—Base region; 15—Outer high concentration region; 20—Main region (impurity region); 21—Outer main region (impurity region); 40—Termination region (impurity region); 42—Field region; Tr—Transistor structure (device structure); Di—Diode structure (device structure).

Claims

1. A semiconductor device, characterized in that, include: A chip has a main surface; A high-concentration region of the first conductivity type is formed on the surface of the main surface on the inner side of the chip; and The low-concentration region of the first conductivity type is formed on the surface of the main surface on the periphery side of the chip, and has an impurity concentration lower than that of the high-concentration region.

2. The semiconductor device according to claim 1, characterized in that, The chip includes SiC.

3. The semiconductor device according to claim 1 or 2, characterized in that, The chip has sides, The high-concentration regions are formed at intervals from the side. The low-concentration area is exposed from the side.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The low-concentration region extends in a band along the high-concentration region when viewed from above.

5. The semiconductor device according to claim 4, characterized in that, The low-concentration region surrounds the high-concentration region when viewed from above.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The low-concentration region is connected to the high-concentration region.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, It also includes an inner low-concentration region of a first conductivity type, which is formed on the inner side of the chip below the high-concentration region and has an impurity concentration lower than that of the high-concentration region.

8. The semiconductor device according to claim 7, characterized in that, The inner low-concentration region is connected to the low-concentration region on the peripheral side of the chip.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, It also includes an outer high-concentration region of a first conductivity type, which is formed on the periphery side of the chip below the low-concentration region and has a higher impurity concentration than the impurity concentration of the low-concentration region.

10. The semiconductor device according to claim 9, characterized in that, The outer high-concentration region is connected to the inner high-concentration region on the chip.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, It also includes a base region of a first conductivity type, which is formed on the inner side of the chip below the high concentration region and has an impurity concentration higher than that of the high concentration region.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that, It also includes a second type of impurity region, which is formed on the surface of the high concentration region.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, It also includes a field region of a second conductivity type, which is formed on the surface of the low concentration region.

14. A semiconductor device, characterized in that, include: A chip has a main surface; An active region is located on the inner side of the main surface; The outer peripheral region is located at the periphery of the main surface; A high-concentration region of the first conductivity type is formed in the surface portion of the main surface in the active region; and A low-concentration region of the first conductivity type is formed on the surface portion of the main surface in the outer peripheral region, and has an impurity concentration lower than that of the high-concentration region.

15. The semiconductor device according to claim 14, characterized in that, The chip includes SiC.

16. The semiconductor device according to claim 14 or 15, characterized in that, It also includes a field region of a second conductivity type, which is formed in the outer peripheral region on the surface of the low concentration region.

17. The semiconductor device according to claim 16, characterized in that, The field region is formed at intervals on the surface of the low concentration region, separated from the high concentration region.

18. The semiconductor device according to any one of claims 14 to 17, characterized in that, It also includes a second type of impurity region, which is formed in the surface portion of the high concentration region in the active region.

19. The semiconductor device according to any one of claims 14 to 18, characterized in that, It also includes a second type of conductive terminal region, which is formed in the peripheral region on either or both of the surface portion of the high concentration region and the surface portion of the low concentration region.

20. The semiconductor device according to any one of claims 14 to 19, characterized in that, It also includes a device structure that includes the high-concentration region and is formed in the active region.

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