Nitride semiconductor device

Abstract

This nitride semiconductor device is provided with: a gate layer formed on an electron supply layer; a gate electrode formed on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and having a first opening and a second opening spaced apart from each other in the X direction; and a field plate electrode formed on the passivation layer and electrically connected to the source electrode. The field plate electrode includes a plate extension portion that extends in a region between the gate layer and the drain electrode in plan view and faces the electron supply layer with the passivation layer interposed therebetween. An opening portion is formed in the plate extension portion of the field plate electrode.

Description

Technical Field

[0001] This disclosure relates to a nitride semiconductor device. Background Technology

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter, sometimes simply referred to as "nitride semiconductors") is progressing (see, for example, Patent Document 1).

[0003] This type of nitride semiconductor device includes, for example: an electron transport layer; an electron supply layer formed on the electron transport layer, having a larger band gap compared to the electron transport layer; a gate layer formed on the electron transport layer, containing acceptor-type impurities; a gate electrode formed on the gate layer; and a passivation layer covering the electron supply layer, the gate layer, and the gate electrode. Additionally, the nitride semiconductor device includes: a field plate electrode integrated with the source electrode, extending from the source electrode across the gate layer and the gate electrode toward the drain electrode.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-73506 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] In this structure where field plate electrodes are installed, parasitic capacitance may be generated due to these electrodes. This parasitic capacitance may adversely affect the responsiveness of the switch.

[0009] Solution for solving the problem

[0010] One aspect of this disclosure provides a nitride semiconductor device comprising: an electron transport layer made of a nitride semiconductor; an electron supply layer formed on the electron transport layer and made of a nitride semiconductor having a band gap larger than that of the electron transport layer; a gate layer formed on the electron supply layer and made of a nitride semiconductor containing acceptor-type impurities; a gate electrode formed on the gate layer; and a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and having a first opening and a second opening spaced apart in a first direction, the gate layer being located between the first opening and the second opening. Between the second opening; a source electrode, which is connected to the electron supply layer via the first opening; a drain electrode, which is connected to the electron supply layer via the second opening; and a field plate electrode, which is formed on the passivation layer and electrically connected to the source electrode, the field plate electrode including a plate extension that extends in the region between the gate layer and the drain electrode in plan view and is opposed to the electron supply layer across the passivation layer, an opening being formed in the field plate electrode at at least one of the plate extension and a position overlapping the gate layer in plan view.

[0011] Invention Effects

[0012] According to the nitride semiconductor device as one aspect of this disclosure, it is possible to reduce the parasitic capacitance caused by the field plate electrodes. Attached Figure Description

[0013] Figure 1 This is an exemplary schematic top view of the nitride semiconductor device according to the first embodiment.

[0014] Figure 2 yes Figure 1 The enlarged view of the single-dash frame A1 is a... Figure 1 A schematic top view of the nitride semiconductor device with added passivation layer and field plate electrodes.

[0015] Figure 3 Therefore Figure 2 A schematic cross-sectional view of the nitride semiconductor device cut by the F3-F3 line.

[0016] Figure 4 Therefore Figure 2 A schematic cross-sectional view of the nitride semiconductor device cut by line F4-F4.

[0017] Figure 5 It is Figure 2 A simplified top view of the single-dot dashed frame A2, magnified.

[0018] Figure 6 This schematically represents the state of the depletion layer when a drain / source voltage is applied. Figure 2A simplified top view of the single-dot dashed frame A2, magnified.

[0019] Figure 7 This is a schematic top view of the field plate electrode and its surroundings, magnified, for the nitride semiconductor device of the second embodiment.

[0020] Figure 8 It is along Figure 7 A schematic cross-sectional view showing the cutting of a nitride semiconductor device by lines F8-F8.

[0021] Figure 9 This is a schematic top view of the field plate electrode and its surroundings, magnified, regarding the nitride semiconductor device of the third embodiment.

[0022] Figure 10 Therefore Figure 9 A schematic cross-sectional view of the nitride semiconductor device cut by line F10-F10.

[0023] Figure 11 This is a schematic top view of a modified nitride semiconductor device, showing an enlarged view of the opening of the field plate electrode and its surrounding area.

[0024] Figure 12 This is a schematic top view of a modified nitride semiconductor device, showing an enlarged view of the opening of the field plate electrode and its surrounding area.

[0025] Figure 13 This is a schematic top view of a modified nitride semiconductor device, showing an enlarged view of the opening of the field plate electrode and its surrounding area.

[0026] Figure 14 This is a schematic top view of a modified nitride semiconductor device, showing an enlarged view of the opening of the field plate electrode and its surrounding area.

[0027] Figure 15 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0028] Figure 16 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0029] Figure 17 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0030] Figure 18 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0031] Figure 19This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0032] Figure 20 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0033] Figure 21 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0034] Figure 22 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0035] Figure 23 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0036] Figure 24 This is a schematic top view of a modified nitride semiconductor device, showing the field plate electrode and its surrounding area magnified.

[0037] Figure 25 Therefore Figure 24 A schematic cross-sectional view of the nitride semiconductor device cut by the F25-F25 line.

[0038] Figure 26 This is a schematic cross-sectional view of a modified nitride semiconductor device.

[0039] Figure 27 This is a schematic cross-sectional view of a modified nitride semiconductor device. Detailed Implementation

[0040] Hereinafter, several embodiments of the nitride semiconductor device of this disclosure will be described with reference to the accompanying drawings.

[0041] Furthermore, for the sake of simplicity and clarity, the constituent elements shown in the accompanying drawings are not necessarily depicted at a constant scale. Additionally, for ease of understanding, shading lines are sometimes omitted in sectional views. The accompanying drawings are merely examples of embodiments of this disclosure and should not be considered as limitations thereof.

[0042] The following detailed description includes apparatus, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the implementation of the present disclosure or the application and use of such implementations.

[0043] In the following description, the statement "the dimensions (width, depth, length, distance) of component A are equal to the dimensions (width, depth, length, distance) of component B" or "the dimensions (width, depth, length, distance) of component A are equal to the dimensions (width, depth, length, distance) of component B" means that the absolute value of the difference between the dimensions (width, depth, length, distance) of component A and component B is, for example, within 10% of the dimensions (width, depth, length, distance) of component A.

[0044] <First Implementation Method>

[0045] Reference Figures 1-6 The nitride semiconductor device 10 of the first embodiment will be described. Figure 1 This shows a schematic planar structure of the nitride semiconductor device 10. Figure 2 Indicates will Figure 1 A portion of the enlarged schematic planar structure of the nitride semiconductor device 10. Figure 3 Indicates will Figure 2 The nitride semiconductor device 10 has a schematic cross-sectional structure cut by the F3-F3 line.

[0046] The nitride semiconductor device 10 is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. Examples of nitride semiconductors include gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN), typically represented as Al. x In y Ga 1-x-y N(0≤x≤1,0≤y≤1,0≤x+y≤1).

[0047] Furthermore, unless otherwise explicitly stated otherwise, the term "top view" as used in this disclosure refers to viewing the symmetrical object (nitride semiconductor device 10 or its constituent elements) in the Z direction of the mutually orthogonal XYZ axes shown in the figures.

[0048] [Simplified cross-sectional structure of a nitride semiconductor device]

[0049] like Figure 1 As shown, the nitride semiconductor device 10 includes multiple unit transistors 10A having a HEMT structure using nitride semiconductors. Hereinafter, firstly, referring to... Figure 3 This paper provides a summary description of the HEMT structure of a single unit transistor 10A. Furthermore, this description can also be applied to other unit transistors 10A.

[0050] like Figure 3As shown, the unit transistor 10A (nitride semiconductor device 10) includes a semiconductor substrate 12, a buffer layer 14 formed on the semiconductor substrate 12, an electron transport layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transport layer 16.

[0051] The semiconductor substrate 12 can be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 can be a Si substrate. The thickness of the semiconductor substrate 12 can be, for example, more than 200 μm and less than 1500 μm.

[0052] Buffer layer 14 may be located between semiconductor substrate 12 and electron transport layer 16. In one example, buffer layer 14 may be made of any material that facilitates the epitaxial growth of electron transport layer 16. Buffer layer 14 may comprise one or more nitride semiconductor layers.

[0053] In one example, the buffer layer 14 may comprise at least one of an AlN layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer with different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer with an AlGaN / GaN superlattice structure, a layer with an AlN / AlGaN superlattice structure, or a layer with an AlN / GaN superlattice structure. Furthermore, to suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make it semi-insulating. In this case, the impurities are, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4 × 10⁻⁶. 16 cm -3 above.

[0054] The electron transport layer 16 is made of a nitride semiconductor. For example, the electron transport layer 16 is a GaN layer. The thickness of the electron transport layer 16 is, for example, 0.5 μm or more and 2 μm or less. Furthermore, to suppress leakage current in the electron transport layer 16, impurities can be introduced into a portion of the electron transport layer 16 to make the area outside the surface region of the electron transport layer 16 semi-insulated. In this case, the impurity is, for example, C, and the peak concentration of the impurity in the electron transport layer 16 is, for example, 1 × 10⁻⁶. 19 cm -3 above.

[0055] The electron supply layer 18 is made of a nitride semiconductor having a larger band gap than the electron transport layer 16. The electron supply layer 18 is, for example, an AlGaN layer. In this case, the larger the Al content, the larger the band gap; therefore, the electron supply layer 18, as an AlGaN layer, has a larger band gap than the electron transport layer 16, which is a GaN layer. In one example, the electron supply layer 18 is made of Al... x Ga1-x N is composed of x, where x is 0.1 < x < 0.4, more preferably 0.2 < x < 0.3. The thickness of the electron supply layer 18 is, for example, 5 nm or more and 20 nm or less.

[0056] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor constituting the electron transport layer 16 (e.g., GaN) and the nitride semiconductor constituting the electron supply layer 18 (e.g., AlGaN) form a heterojunction with a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18, and the piezoelectric polarization caused by the stress on the electron supply layer 18 near the heterojunction boundary, the conduction band energy level of the electron transport layer 16 near the heterojunction boundary becomes lower than the Fermi level. Consequently, two-dimensional electron gas (2DEG) 20 diffuses within the electron transport layer 16 at a location near the heterojunction boundary between the electron transport layer 16 and the electron supply layer 18 (e.g., within a few nm from the boundary).

[0057] The unit transistor 10A (nitride semiconductor device 10) further includes a gate layer 22 formed on the electron supply layer 18, a gate electrode 24 formed on the gate layer 22, and a passivation layer 26. The passivation layer 26 is formed on the electron supply layer 18, the gate layer 22, and the gate electrode 24, and includes a first opening 26A and a second opening 26B. The first opening 26A and the second opening 26B are spaced apart in the X direction. Additionally, the nitride semiconductor device 10 includes a source electrode 28 connected to the electron supply layer 18 via the first opening 26A and a drain electrode 30 connected to the electron supply layer 18 via the second opening 26B. Here, the X direction corresponds to the "first direction".

[0058] The gate layer 22 is located between the first opening 26A and the second opening 26B of the passivation layer 26, and is spaced apart from both the first opening 26A and the second opening 26B. The gate layer 22 is located closer to the first opening 26A than the second opening 26B.

[0059] The gate layer 22 has a smaller band gap than the electron supply layer 18 and is made of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 can, for example, be made of any material having a smaller band gap than the electron supply layer 18, which is an AlGaN layer. In one example, the gate layer 22 is a GaN layer doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and C. The maximum concentration of acceptor-type impurities in the gate layer 22 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 the following.

[0060] As described above, by including acceptor-type impurities in the gate layer 22, the energy levels of the electron transport layer 16 and the electron supply layer 18 are enhanced. Therefore, in the region directly below the gate layer 22, the conduction band energy level of the electron transport layer 16 near the heterojunction boundary between the electron transport layer 16 and the electron supply layer 18 is approximately the same as or greater than the Fermi level. Therefore, when no zero bias voltage is applied to the gate electrode 24, the electron transport layer 16 in the region directly below the gate layer 22 does not form 2DEG20. On the other hand, the electron transport layer 16 in the region outside the region directly below the gate layer 22 forms 2DEG20.

[0061] Thus, due to the presence of the gate layer 22 doped with acceptor-type impurities, the 2DEG20 disappears in the region directly below the gate layer 22. As a result, the transistor operates normally off. When an appropriate turn-on voltage is applied to the gate electrode 24, an electron transport layer 16 in the region directly below the gate electrode 24 forms a channel formed by the 2DEG20, thus enabling source-drain conduction.

[0062] The gate electrode 24 is composed of one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may also be composed of a first metal layer and a second metal layer, the first metal layer being formed of a Ti-containing material, and the second metal layer being stacked on top of the first metal layer and formed of a TiN-containing material. The gate electrode 24 can form a Schottky junction with the gate layer 22. The gate electrode 24 can be formed in a region smaller than the gate layer 22 in plan view. The thickness of the gate electrode 24 is, for example, 50 nm or more and 200 nm or less.

[0063] A passivation layer 26 is formed on the electron supply layer 18. The passivation layer 26 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 26 may be made of, for example, any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 26 is thicker than the thickness of the electron supply layer 18. The thickness of the passivation layer 26 is, for example, 300 nm or more and 1000 nm or less. Furthermore, the thickness of the passivation layer 26 can be arbitrarily varied.

[0064] The source electrode 28 and drain electrode 30 are disposed on the upper surface of the electron supply layer 18, sandwiching the gate layer 22. The source electrode 28 and drain electrode 30 may be composed of one or more metal layers. For example, the source electrode 28 and drain electrode 30 may be composed of a combination of two or more metal layers selected from the group consisting of Ti layers, TiN layers, Al layers, AlSiCu layers, and AlCu layers. At least a portion of the source electrode 28 fills the first opening 26A, making a 20-ohm 2DEG contact directly below the electron supply layer 18 via the first opening 26A. Similarly, at least a portion of the drain electrode 30 is filled in the second opening 26B, making a 20-ohm 2DEG contact directly below the electron supply layer 18 via the second opening 26B.

[0065] The unit transistor 10A (nitride semiconductor device 10) also includes a field plate electrode 32 electrically connected to the source electrode 28. In the first embodiment, the field plate electrode 32 is integrated with the source electrode 28. When a drain voltage is applied to the drain electrode 30 in a zero-bias state without applying a gate voltage to the gate electrode 24, the field plate electrode 32 serves to mitigate the electric field concentration near the end of the gate electrode 24 and near the end of the gate layer 22. The detailed structure of the field plate electrode 32 will be described later.

[0066] [Simplified planar structure of a nitride semiconductor device]

[0067] Next, the main references are... Figure 1 The schematic planar structure of the nitride semiconductor device 10 shown is illustrated, and an exemplary schematic planar structure of the nitride semiconductor device 10 will be described. Furthermore, to easily understand the planar structure and arrangement of the gate layer 22, gate electrode 24, source electrode 28, and drain electrode 30, the following description is provided: Figure 1 The passivation layer 26 and the field plate electrode 32 are omitted. Additionally, in... Figure 1 In the diagram, the source electrode 28 and the drain electrode 30 represent the planar structure of the contact portion that is in contact with the electron supply layer 18.

[0068] like Figure 1 As shown, the nitride semiconductor device 10 includes a plurality of source electrodes 28 arranged in the X and Y directions when viewed from above on the electron supply layer 18. Figure 1 In this example, six source electrodes 28 are arranged at intervals, with three columns in the X direction and two columns in the Y direction. Each source electrode 28 is formed into a strip extending along the Y direction when viewed from above.

[0069] Additionally, the nitride semiconductor device 10 includes a plurality of drain electrodes 30 arranged in the X and Y directions when viewed from above on the electron supply layer 18. Figure 1In this example, four drain electrodes 30 are arranged at intervals, two rows in the X direction and two rows in the Y direction. Each drain electrode 30 is formed as a strip extending along the Y direction when viewed from above. Multiple drain electrodes 30 and multiple source electrodes 28 are arranged alternately in the X direction. In this case, for example, the source electrodes 28 are located at both ends in the X direction.

[0070] Additionally, the nitride semiconductor device 10 includes a plurality of gate layers 22 and a plurality of gate electrodes arranged in the X and Y directions when viewed from above on the electron supply layer 18. Figure 1 In this example, six gate layers 22 and gate electrodes 24 are configured, with three columns in the X direction and two columns in the Y direction. Each gate layer 22 and each gate electrode 24 extends in the Y direction and surrounds one of the source electrodes 28 when viewed from above. That is, each gate layer 22 and each gate electrode 24 is formed in a ring shape.

[0071] Furthermore, the term "ring-shaped" as used in this disclosure refers not only to a continuous shape without ends, i.e., any structure forming a ring, but also to a structure with a slit (gap) shape, such as a C-shape. Such "ring-shaped" shapes include not only ellipses, but also any shape including right angles or rounded corners, comprising multiple corners with predetermined angles.

[0072] [Simplified structure of the field plate electrode]

[0073] Next, refer to Figures 2-6 An illustrative general structure of the field plate electrode 32 will be described. Figure 2 express Figure 1 The schematic planar structure of the nitride semiconductor device 10 in the region of the dashed box A1. Figure 2 Indicates in Figure 1 Based on the addition of passivation layer 26 and field plate electrode 32, a portion of the schematic planar structure in the Y direction has been omitted for the purpose of enlarging the attached figure. Figure 4 Indicated by Figure 2 The F4-F4 line represents the approximate cross-sectional structure of the nitride semiconductor device 10. Figure 5 as well as Figure 6 Indicates will Figure 2 The approximate planar structure of the area enlarged from the single-dash box A2.

[0074] like Figure 2 As shown, the field plate electrode 32 is disposed between two drain electrodes 30 spaced apart in the X direction. The field plate electrode 32 is rectangular in shape when viewed from above. The field plate electrode 32 is disposed on both sides of the source electrode 28 in the X direction. When viewed from above, the field plate electrode 32 extends in the region between the gate layer 22 and the drain electrode 30.

[0075] like Figure 3 As shown, the field plate electrode 32 is formed on the passivation layer 26. In one example, the field plate electrode 32 includes a plate extension 34 facing the electron supply layer 18 across the passivation layer 26, and a gate opposing portion 36 facing the gate layer 22 across the passivation layer 26. Additionally, the field plate electrode 32 includes a source connection portion 38 facing the electron supply layer 18 across the passivation layer 26 at a position closer to the source electrode 28 than the gate opposing portion 36. In one example, the plate extension 34, the gate opposing portion 36, and the source connection portion 38 are integrated. The plate extension 34 is disposed on the side opposite to the source electrode 28 in the X direction relative to the gate opposing portion 36. That is, the plate extension 34 is disposed closer to the drain electrode 30 in the X direction than the gate opposing portion 36. Furthermore, the plate extension 34 is spaced apart from the drain electrode 30 in the X direction. The gate opposing portion 36 faces the gate electrode 24 across the passivation layer 26.

[0076] The plate extension 34 has a front end surface 34A that faces the drain electrode 30 when viewed from above. The front end surface 34A extends along the Y direction when viewed from above. The front end surface 34A is disposed between the gate layer 22 and the drain electrode 30 in the X direction. The length of the field plate electrode 32 in the X direction is set according to the position of the front end surface 34A in the X direction. The length of the field plate electrode 32 is appropriately set according to the switching speed and withstand voltage required by the nitride semiconductor device 10. In other words, the position of the front end surface 34A in the X direction is appropriately set according to the switching speed and withstand voltage required by the nitride semiconductor device 10.

[0077] The gate opposition portion 36 is formed by the region of the field plate electrode 32 that overlaps with the gate layer 22 when viewed from above. Therefore, when viewed from above, the length of the gate opposition portion 36 in the X direction is shorter than the length of the plate extension portion 34 in the X direction. When viewed from above, the length of the gate opposition portion 36 in the X direction is equal to the width (length in the X direction) of the gate layer 22 extending along the Y direction.

[0078] The source connection portion 38 is formed by the region between the source electrode 28 in the field plate electrode 32 and the gate opposing portion 36 in the X direction. Here, the source electrode 28 is formed by the portion that contacts the electron supply layer 18. Therefore, the source connection portion 38 can also be described as being formed by the region between the first opening 26A in the field plate electrode 32 and the gate opposing portion 36 in the X direction when viewed from above.

[0079] like Figure 2 As shown, an opening 40 is formed in the field plate electrode 32. In one example, at least a portion of the opening 40 is formed in the plate extension 34. In the first embodiment, the opening 40 is disposed in the plate extension 34. On the other hand, the opening 40 is not formed in the gate opposing portion 36.

[0080] In the first embodiment, the opening 40 is a recess 42 that is recessed from the front end face 34A of the board toward the gate layer 22. The recess 42 extends in the Y direction (width) and X direction (depth) when viewed from above. The recess 42 opens toward the drain electrode 30. Figure 2 In the example shown, multiple recesses 42 are arranged at intervals in the Y direction. The multiple recesses 42 are arranged, for example, at equal intervals. The widths of the multiple recesses 42 are equal to each other. Furthermore, the depths of the multiple recesses 42 are equal to each other.

[0081] like Figure 5 As shown, the recess 42 includes a pair of side surfaces 44 and a bottom surface 46 connecting the pair of side surfaces 44. In a top view, the pair of side surfaces 44 are spaced apart from each other in the Y direction. Each side surface 44 extends along the X direction in a top view. Therefore, the pair of side surfaces 44 are parallel to each other. That is, in Figure 5 In the example, the width of the recess 42 in the Y direction is the same from the opening portion of the front end face 34A of the plate extension 34 to the bottom face 46.

[0082] like Figure 4 as well as Figure 5 As shown, the bottom surface 46 of the recess 42 is positioned in the X direction closer to the drain electrode 30 than the side surface 22X of the gate layer 22. The position of the bottom surface 46 in the X direction, i.e., the depth H of the recess 42, is appropriately set according to the switching speed required by the nitride semiconductor device 10, within the range of being closer to the drain electrode 30 in the X direction than the side surface 22X of the gate layer 22. Here, the depth H can be defined by the distance in the X direction from the front end face 34A of the board to the bottom surface 46 of the recess 42 when viewed from above.

[0083] In one example, the depth H of the recess 42 when viewed from above is greater than the width W of the recess 42. In another example, the depth H of the recess 42 when viewed from above is greater than half the length L in the X direction of the board extension 34. Here, the length L in the X direction of the board extension 34 can be defined by the distance in the X direction from the side closest to the front end face 34A of the gate layer 22 to the front end face 34A of the board when viewed from above.

[0084] exist Figure 5 In the example shown, the width W of the recess 42 is equal to the distance D between the plurality of recesses 42. Here, the distance D between the plurality of recesses 42 can be defined by the distance in the Y direction between the side 44 of one recess 42 that is closer to the other recess 42 and the side 44 of the other recess 42 that is closer to one recess 42 in a pair of side surfaces 4 ...

[0085] Figure 6 The double-dotted line represents the depletion layer formed on the field plate electrode 32 under the condition of applied drain / source voltage. For example... Figure 6 As shown, the distance between a pair of side surfaces 44 in the X direction, i.e. the width W of the recess 42, is set to the dimension connecting the depletion layer extending from the front end face 34A, the bottom face 46, and each side surface 44.

[0086] [Manufacturing Method of Nitride Semiconductor Devices]

[0087] Next, an example of a method for manufacturing the nitride semiconductor device 10 will be described.

[0088] The manufacturing method of the nitride semiconductor device 10 includes: a step of forming a buffer layer 14 on a semiconductor substrate 12; a step of forming an electron transport layer 16 on the buffer layer 14; and a step of forming an electron supply layer 18 on the electron transport layer 16.

[0089] More specifically, a buffer layer 14, an electron transport layer 16, and an electron supply layer 18 are sequentially formed on a semiconductor substrate 12. The semiconductor substrate 12 is, for example, a Si substrate. The buffer layer 14, electron transport layer 16, and electron supply layer 18 are formed, for example, by epitaxial growth using a metal-organic chemical vapor deposition (MOCVD) method. The buffer layer 14 may be, for example, a multilayer buffer layer. The multilayer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 12 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The electron transport layer 16 is, for example, a GaN layer, and the electron supply layer 18 is, for example, an AlGaN layer. Therefore, the electron supply layer 18 is composed of a nitride semiconductor having a larger band gap than the electron transport layer 16.

[0090] The manufacturing method of the nitride semiconductor device 10 further includes: a step of forming a gate layer 22 on an electron supply layer 18; a step of forming a gate electrode 24 on the gate layer 22; and a step of forming a passivation layer 26 on the electron supply layer 18, the gate layer 22, and the gate electrode 24.

[0091] More specifically, a nitride semiconductor layer is formed on the electron supply layer 18. The nitride semiconductor layer can be epitaxially grown using MOCVD. The nitride semiconductor layer can be composed of a nitride semiconductor containing acceptor-type impurities. An example of an acceptor-type impurity is Mg. The nitride semiconductor layer is, for example, a GaN layer. Next, a gate electrode 24 is formed on the nitride semiconductor layer. Then, a mask is formed covering the upper surface, side surfaces, and surrounding area of ​​the gate electrode 24 with the nitride semiconductor layer, and the nitride semiconductor layer is etched using the mask. Thus, the gate layer 22 is formed. Afterward, the mask is removed. The passivation layer 26 can be, for example, a SiN layer formed by low-pressure chemical vapor deposition (LPCVD). Subsequently, the passivation layer 26 is etched to form a first opening 26A and a second opening 26B.

[0092] The manufacturing method of the nitride semiconductor device 10 includes the steps of forming a source electrode 28, a drain electrode 30, and a field plate electrode 32.

[0093] More specifically, a metal layer is formed on the passivation layer 26. The metal layer is formed to fill the first opening 26A and the second opening 26B, and to contact the electron supply layer 18 via the first opening 26A and the second opening 26B. In one example, the metal layer may comprise at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.

[0094] Next, the metal layer is selectively removed by photolithography and etching, thereby forming the source electrode 28, the drain electrode 30, and the field electrode 32. In this process, the opening 40 of the field electrode 32 is formed. After the above processes, the nitride semiconductor device 10 is manufactured.

[0095] Furthermore, the opening 40 is not limited to being formed simultaneously with the source electrode 28 and the drain electrode 30. In one example, the opening 40 may be formed on the metal layer by photolithography and etching after the source electrode 28 and the drain electrode 30 have been formed on the metal layer by photolithography and etching. Alternatively, in another example, the source electrode 28 and the drain electrode 30 may be formed on the metal layer by photolithography and etching after the opening 40 has been formed on the metal layer by photolithography and etching.

[0096] [effect]

[0097] The operation of the nitride semiconductor device 10 in the first embodiment will be explained.

[0098] By increasing the length of the field plate electrode in the X direction, the concentration of the electric field between the drain electrode 30 and the source electrode 28 in the X direction can be mitigated. On the other hand, if the length of the field plate electrode in the X direction is increased, the parasitic capacitance between the field plate electrode and the electron supply layer 18 and the gate layer 22 increases, depending on the area of ​​the field plate electrode. If this parasitic capacitance increases, it may adversely affect the switching responsiveness of the nitride semiconductor device.

[0099] In this regard, in the first embodiment, a plurality of recesses 42 (openings 40) are provided that are recessed in the X direction from the front end face 34A of the field plate electrode 32. This reduces the parasitic capacitance between the field plate electrode 32 and the electron supply layer 18. Furthermore, by setting the width W of the recess 42 such that it is connected to a depletion layer extending from a pair of side faces 44 of the recess 42, even with the formation of the recess 42, the reduction in the mitigation effect of electric field concentration on the field plate electrode 32 can be suppressed.

[0100] [Effect]

[0101] The nitride semiconductor device 10 according to the first embodiment can achieve the following effects.

[0102] (1-1) The nitride semiconductor device 10 includes: an electron transport layer 16 made of a nitride semiconductor; an electron supply layer 18 formed on the electron transport layer 16 and made of a nitride semiconductor having a band gap larger than that of the electron transport layer 16; a gate layer 22 formed on the electron supply layer 18 and made of a nitride semiconductor containing acceptor-type impurities; a gate electrode 24 formed on the gate layer 22; a passivation layer 26 covering the electron supply layer 18, the gate layer 22 and the gate electrode 24, and having a first opening 26A and a second opening 26B spaced apart in the X direction, the gate layer 22 being located between the first opening 26A and the second opening 26B; a source electrode 28 connected to the electron supply layer 18 via the first opening 26A; a drain electrode 30 connected to the electron supply layer 18 via the second opening 26B; and a field plate electrode 32 formed on the passivation layer 26 and electrically connected to the source electrode 28. The field plate electrode 32 includes a plate extension 34 that extends in the region between the gate layer 22 and the drain electrode 30 when viewed from above, and is opposed to the electron supply layer 18 across the passivation layer 26. An opening 40 is formed in the field plate electrode 32. The opening 40 is formed in the plate extension 34.

[0103] According to this structure, by forming an opening 40 in the plate extension 34, the parasitic capacitance between the field plate electrode 32 and the electron supply layer 18 can be reduced. Therefore, the adverse effects on the switching responsiveness of the nitride semiconductor device 10 can be reduced.

[0104] (1-2) The plate extension 34 has a front end face 34A opposite to the drain electrode 30. The opening 40 is a recess 42 that is recessed from the front end face 34A toward the gate layer 22. The recess 42 extends with the Y direction, which is orthogonal to the X direction when viewed from above, as its width direction and the X direction as its depth direction, and opens toward the drain electrode 30.

[0105] According to this structure, the length of the plate extension 34 can be increased by the front end face 34A, thus mitigating the electric field concentration between the source electrode 28 and the drain electrode 30 caused by the field plate electrode 32. Furthermore, the recess 42 reduces the parasitic capacitance between the field plate electrode 32 and the electron supply layer 18. In this way, it is possible to simultaneously mitigate the electric field concentration between the source electrode 28 and the drain electrode 30 and reduce the parasitic capacitance between the field plate electrode 32 and the electron supply layer 18.

[0106] (1-3) The depth of the recess 42 is more than 1 / 2 the length L in the X direction of the plate extension 34.

[0107] According to this structure, since the recess 42 is formed to be larger in the X direction (depth direction), the effect of reducing the parasitic capacitance between the field plate electrode 32 and the electron supply layer 18 can be improved.

[0108] (1-4) Multiple recesses 42 are arranged at intervals in the Y direction.

[0109] According to this structure, since the number of recesses 42 increases, even if the width of each recess 42 is small, the effect of reducing the parasitic capacitance between the field plate electrode 32 and the electron supply layer 18 can be improved. Furthermore, since the width of the recesses 42 can be reduced, it is easier to form a depletion layer throughout the entire recess 42. Therefore, the effect of suppressing the reduction of the electric field strength of the field plate electrode 32 is improved.

[0110] <Second Implementation Method>

[0111] Reference Figure 7 as well as Figure 8 The second embodiment of the nitride semiconductor device 10 will now be described. In the second embodiment of the nitride semiconductor device 10, the configuration of the field plate electrode 32 differs from that of the first embodiment. Hereinafter, the differences from the first embodiment will be described in detail, and components common to those in the first embodiment will be marked with the same symbols, and their descriptions will be omitted.

[0112] Figure 7 This shows a schematic planar structure of a nitride semiconductor device 10 including a passivation layer 26 and a field electrode 32. Figure 8 Indicates Figure 7The F8-F8 line represents the approximate cross-sectional structure of the nitride semiconductor device 10.

[0113] like Figure 7 As shown, in the second embodiment, an opening 50 is formed on the field electrode 32. At least a portion of the opening 50 is formed on the plate extension 34. In the second embodiment, the opening 50 is formed on the plate extension 34. On the other hand, the opening 50 is not formed on the gate opposing portion 36. A plurality of openings 50 are arranged at intervals in the Y direction. For example, the plurality of openings 50 are arranged at equal intervals.

[0114] Each opening 50 and the opening 40 of the first embodiment (see reference) Figure 5 Unlike the gate electrode 24 side (gate layer 22 side) formed on the front end face 34A of the plate, it is a closed opening formed on the front end face 34A of the plate.

[0115] exist Figure 7 In the example shown, each opening 50 is rectangular in shape with the X direction as its longer side and the Y direction as its shorter side when viewed from above. In one example, the X-direction length LA of the multiple openings 50 is equal to that of each other. In another example, the X-direction length LA of each opening 50 is longer than half the X-direction length L of the plate extension 34.

[0116] The length LB in the Y direction of each opening 50 is set to a size such that the depletion layer extending within each opening 50 is connected when a drain / source voltage is applied. In one example, the lengths LB in the Y direction of the multiple openings 50 are equal to each other. The length LB in the Y direction of each opening 50 is equal to the distance DA between the multiple openings 50. Here, the distance DA can be defined by the distance between two adjacent openings 50 in the Y direction.

[0117] like Figure 8 As shown, the opening 50 is positioned closer to the gate electrode 24 (gate layer 22 side) than the front end face 34A of the board, thus forming a front end portion 52 of the board between the opening 50 and the front end face 34A of the board in the X direction. Figure 7 As shown, the front end 52 of the plate extends along the Y direction.

[0118] Furthermore, the length LA in the X direction of each opening 50 can be arbitrarily changed. In one example, the length LA in the X direction of each opening 50 may be less than half the length L in the X direction of the plate extension 34. In addition, the length LA in the X direction of at least one of the plurality of openings 50 may be different from the length LA in the X direction of the other openings 50.

[0119] [Effect]

[0120] The nitride semiconductor device 10 according to the second embodiment can achieve the following effects.

[0121] (2-1) The plate extension 34 has a plate front end face 34A opposite to the drain electrode 30. The opening 50 is a closed opening formed on the side of the plate front end face 34A closer to the gate electrode 24.

[0122] According to this structure, since the front end face 34A is formed throughout the Y direction of the field plate electrode 32, the length L of the field plate electrode 32 in the X direction is maintained throughout the Y direction of the field plate electrode 32. Therefore, the mitigation effect of electric field concentration on the field plate electrode 32 can be improved.

[0123] (2-2) The length LA of the opening 50 in the X direction is longer than half the length L of the plate extension 34 in the X direction.

[0124] According to this structure, since the opening 50 is formed to be larger in the X direction, the effect of reducing the parasitic capacitance between the field plate electrode 32 and the electron supply layer 18 can be improved.

[0125] (2-3) Multiple openings 50 are arranged at intervals in the Y direction.

[0126] With this structure, the number of openings 50 increases, thus improving the reduction of parasitic capacitance between the field plate electrode 32 and the electron supply layer 18 even if the width (size in the Y direction) of each opening 50 is small. Furthermore, since the width of the openings 50 can be reduced, a depletion layer is easily formed throughout the entire opening 50. This reduces the mitigation effect of electric field concentration caused by the field plate electrode 32.

[0127] <Third Implementation Method>

[0128] Reference Figure 9 as well as Figure 10 The nitride semiconductor device 10 according to the third embodiment will be described below. In the nitride semiconductor device 10 of the third embodiment, the structure of the field plate electrode 32 differs from that of the nitride semiconductor device 10 of the second embodiment. Hereinafter, the differences from the second embodiment will be described in detail, and components common to those in the second embodiment will be marked with the same symbols, and their descriptions will be omitted.

[0129] Figure 9 This shows a schematic planar structure of a nitride semiconductor device 10 including a passivation layer 26 and a field electrode 32. Figure 10 Indicated by Figure 9 The F10-F10 line represents the approximate cross-sectional structure of the nitride semiconductor device 10.

[0130] like Figure 9As shown, in the third embodiment, an opening 60 is formed in the field electrode 32. At least a portion of the opening 60 is formed in the plate extension 34. In the third embodiment, the opening 60 is formed across both the plate extension 34 and the gate opposing portion 36. Figure 9 In this example, the opening 60 is formed across the plate extension 34, the gate opposing portion 36, and the source connection portion 38. That is, the opening 60 is formed in a manner that traverses the gate opposing portion 36. Multiple openings 60 are arranged at intervals in the Y direction. For example, the multiple openings 60 are arranged at equal intervals.

[0131] Each opening 60 and the opening 50 of the second embodiment (see reference) Figure 7 Similarly, each opening 60 is a closed opening located on the front surface 34A of the plate near the gate electrode 24 (gate layer 22 side). Each opening 60, when viewed from above, is rectangular with its longer side in the X direction and its shorter side in the Y direction. The length LC of each opening 60 in the X direction is longer than the length L of the plate extension 34 in the X direction. In one example, the length LC of each opening 60 in the X direction is longer than half the length LF of the field plate electrode 32 in the X direction.

[0132] The Y-direction length LD of each opening 60 is set to a size such that the depletion layer extending within each opening 60 is connected when a drain / source voltage is applied. In one example, the Y-direction lengths LD of the multiple openings 60 are equal to each other. The Y-direction length LD of each opening 60 is equal to the distance DB between the multiple openings 60. Here, the distance DB can be defined by the distance between two adjacent openings 60 in the Y direction.

[0133] like Figure 10 As shown, the opening 60 is positioned closer to the gate electrode 24 (gate layer 22 side) than the front end face 34A of the board, thus forming a front end portion 64 of the board between the opening 60 and the front end face 34A of the board in the X direction. Figure 9 As shown, the front end 64 of the plate extends along the Y direction.

[0134] like Figure 9 as well as Figure 10 As shown, the field plate electrode 32 includes an inner surface 62 forming each opening 60. This inner surface 62 includes a first end surface 62A and a second end surface 62B, which are two end surfaces in the X direction. The first end surface 62A is a side surface forming the front end portion 64 of the plate and is formed in the plate extension portion 34. The second end surface 62B is formed in the source connection portion 38. That is, the second end surface 62B, in plan view, is disposed closer to the gate layer 22 than the source electrode 28. In other words, the second end surface 62B, in plan view, is disposed between the source electrode 28 and the gate layer 22 in the X direction.

[0135] Furthermore, the X-direction positions of the first end face 62A and the second end face 62B can be arbitrarily changed. The X-direction position of the first end face 62A of at least one of the plurality of openings 60 can also differ from the X-direction positions of the first end face 62A of the other openings 60. Similarly, the X-direction position of the second end face 62B of at least one of the plurality of openings 60 can also differ from the X-direction positions of the other openings 60. Consequently, the X-direction length LC of at least one of the plurality of openings 60 can also differ from the X-direction length LC of the other openings 60.

[0136] [Effect]

[0137] The nitride semiconductor device 10 according to the third embodiment can achieve the following effects.

[0138] (3-1) The field plate electrode 32 has a gate opposing portion 36 that is opposed to the gate layer 22 through the passivation layer 26. An opening 60 is formed across both the plate extension portion 34 and the gate opposing portion 36.

[0139] With this structure, the opening 60 is formed spanning both the plate extension 34 and the gate opposing portion 36, thus allowing for a larger opening 60 in the X direction. Therefore, it is possible to improve the reduction of parasitic capacitance between the field plate electrode 32 and the electron supply layer 18.

[0140] (3-2) The opening 60 is a closed opening formed on the front end face 34A of the plate near the gate electrode 24.

[0141] According to this structure, since the front end face 34A is formed throughout the Y direction of the field plate electrode 32, the length L of the field plate electrode 32 in the X direction is maintained throughout the Y direction of the field plate electrode 32. Therefore, the mitigation effect of electric field concentration on the field plate electrode 32 can be improved.

[0142] (3-3) Multiple openings 60 are arranged at intervals in the Y direction.

[0143] With this structure, the number of openings 60 increases, thus improving the reduction of parasitic capacitance between the field plate electrode 32 and the electron supply layer 18 even if the width (size in the Y direction) of each opening 60 is small. Furthermore, since the width of the openings 60 can be reduced, a depletion layer is easily formed throughout the entire opening 60. This reduces the mitigation effect of the electric field concentration caused by the field plate electrode 32.

[0144] (3-4) The opening 60 is formed by extending the plate extension 34, the gate opposing portion 36 and the source connection portion 38.

[0145] According to this structure, the opening 60 is formed over the plate extension 34, the gate opposing portion 36, and the source connection portion 38, thus allowing for a larger opening 60 in the X direction. Therefore, it is possible to improve the effect of reducing the parasitic capacitance between the field plate electrode 32 and the electron supply layer 18.

[0146] <Variation Example>

[0147] The above-described embodiments can be modified as follows. The above-described embodiments and the following variations can be combined with each other as long as they do not create a technical contradiction. Furthermore, in the following variations, the parts common to the above-described embodiments are labeled with the same reference numerals as those in the above-described embodiments, and their descriptions are omitted.

[0148] In the first embodiment, the shape of the recess 42, which serves as the opening 40 of the field plate electrode 32, can be arbitrarily changed. The recess 42 can also be changed to, for example... Figure 11 The recess 42 shown Figure 12 Recess 42 is shown.

[0149] like Figure 11 As shown, the bottom surface 46 of the recess 42 can also be bent. Figure 11 In the example shown, the bottom surface 46 can be formed as a curved concave shape that is recessed toward the gate layer 22 when viewed from above. When viewed from above, the portion of the bottom surface 46 closest to the gate layer 22 is located closer to the drain electrode 30 than the gate layer 22 (see reference). Figure 2 The position of ).

[0150] According to this structure, since no corner portion is formed through the side surface 44 and bottom surface 46 of the recess 42, it becomes curved. Therefore, the depletion layer extending from the curved bottom surface 46 can easily connect with the depletion layer extending from the pair of side surfaces 44. Thus, the electric field concentration generated between the drain electrode 30 and the source electrode 28 can be easily mitigated by the field plate electrode 32.

[0151] like Figure 12 As shown, the pair of side surfaces 44 of the recess 42 can also be formed as cones that approach each other from the front end face 34A of the plate toward the bottom face 46.

[0152] According to this structure, near the bottom surface 46 within the recess 42, the depletion layers of a pair of side surfaces 44 can easily connect. Therefore, the electric field concentration generated between the drain electrode 30 and the source electrode 28 can be easily mitigated by the field plate electrode 32.

[0153] Alternatively, combinations are also possible. Figure 11 The shape of recess 42 is shown and Figure 12The shape of the recess 42 shown. That is, the recess 42 may include a pair of tapered side surfaces 44 that are formed to approach each other from the front end face 34A of the board toward the bottom surface 46, and a bottom surface 46 that is curved toward the gate layer 22.

[0154] • In the first embodiment, the relationship between the width W of the recess 42 and the distance D between the plurality of recesses 42 can be arbitrarily changed.

[0155] In one example, such as Figure 13 As shown, the width W of the recess 42 can also be larger than the distance D between the multiple recesses 42.

[0156] According to this structure, the parasitic capacitance caused by the field plate electrode 32 can be reduced. Therefore, the adverse effects on the switching responsiveness of the nitride semiconductor device 10 can be reduced.

[0157] In another example, such as Figure 14 As shown, the distance D between multiple recesses 42 can also be greater than the width W of the recesses 42.

[0158] According to this structure, the effect of mitigating the electric field concentration of the field plate electrode 32 can be improved.

[0159] Furthermore, in the second and third embodiments as well, the relationship between the lengths LB and LD in the Y direction of the openings 50 and 60 and the distances DA and DB between the plurality of openings 50 and 60 can be arbitrarily changed.

[0160] In one example, the length LB of the opening 50 in the Y direction may be greater than the distance DA between the multiple openings 50. Alternatively, in another example, the length LB of the opening 50 in the Y direction may be smaller than the distance DA between the multiple openings 50.

[0161] In one example, the length LD of the opening 60 in the Y direction may be greater than the distance DB between the multiple openings 60. Alternatively, in another example, the length LD of the opening 60 in the Y direction may be smaller than the distance DB between the multiple openings 60.

[0162] In the first embodiment, the depth H of the recess 42 can be arbitrarily changed. For example, as shown... Figure 15 As shown, the recess 42 can extend from the front end face 34A of the board in the X direction and be longer than the board extension 34. The recess 42 can be formed across both the board extension 34 and the gate opposing portion 36.

[0163] According to this structure, since the depth H of the recess 42 increases, the parasitic capacitance caused by the field plate electrode 32 can be reduced. Therefore, the adverse effects on the switching responsiveness of the nitride semiconductor device 10 can be reduced.

[0164] In the first embodiment, the bottom surfaces 46 of the plurality of recesses 42 are positioned in the same X direction as each other, but this is not a limitation. For example, the X-direction position of at least one of the bottom surfaces 46 of the plurality of recesses 42 may be different from the X-direction positions of the other bottom surfaces 46.

[0165] In the above embodiments, the arrangement, shape, and size of the opening of the field plate electrode 32 can be arbitrarily changed. Hereinafter, several modified examples will be described with reference to the accompanying drawings. Figures 16-23 This indicates the planar structure of the field plate electrode 32.

[0166] [Variation Example 1]

[0167] like Figure 16 As shown, an opening 70 is formed on the field plate electrode 32. The opening 70 is formed on the plate extension 34. On the other hand, the opening 70 is not formed on the gate opposing portion 36. Multiple openings 70 are arranged at intervals in the X direction. Each opening 70, when viewed from above, is rectangular with the X direction as its shorter side and the Y direction as its longer side. Each opening 70 can also be described as a strip extending along the Y direction. Figure 16 In the example shown, three openings 70 are formed at intervals in the X direction in the plate extension 34.

[0168] The length LE in the Y direction of each opening 70 is longer than the length L in the X direction of the plate extension 34. In one example, each opening 70 is formed over the entire area of ​​the gate layer 22 and the drain electrode 30 facing each other in the X direction. Therefore, the length LE in the Y direction of each opening 70 can be greater than or equal to the length LG in the Y direction of the drain electrode 30.

[0169] [Variation Example 2]

[0170] like Figure 17 As shown, an opening 80 is formed in the field plate electrode 32. The opening 80 is disposed in the plate extension 34. On the other hand, the opening 80 is not disposed in the gate opposing portion 36. Multiple openings 80 are arranged at intervals in both the X and Y directions. Figure 17 In the example shown, the plurality of openings 80 are configured such that the columns of the plurality of openings 80 arranged at intervals in the Y direction are arranged in three columns at intervals in the X direction. Furthermore, in the column of openings 80 closest to the front end face 34A and the column of openings 80 closest to the source electrode 28, the positions of the openings 80 in the Y direction are the same. On the other hand, in the column of openings 80 at the center of the X direction among the three columns, the position of the openings 80 in the Y direction is offset from the positions of the openings 80 in the Y direction of the columns of openings 80 closest to the front end face 34A and the columns of openings 80 closest to the source electrode 28.

[0171] [Variation Example 3]

[0172] like Figure 18 As shown, a first opening 90 and a second opening 92 are formed on the field electrode 32. The first opening 90 is disposed on the plate extension 34. Therefore, it can be said that at least a portion of the opening is disposed on the plate extension 34. The second opening 92 is disposed on the gate opposing portion 36. In other words, the second opening 92 is disposed at a position that overlaps with the gate layer 22 when viewed from above. Therefore, in Figure 18 In the example shown, at least a portion of the opening can be positioned to overlap with the gate layer 22 when viewed from above. Furthermore, the opening can be positioned at least within the gate opposing portion 36. Thus, in Figure 18 In the example shown, the opening can be said to be located at both the board extension 34 and the position where it overlaps with the gate layer 22 when viewed from above.

[0173] Multiple first openings 90 are arranged at intervals along the X-direction. Each first opening 90, when viewed from above, is rectangular with the X-direction as its shorter side and the Y-direction as its longer side. Each first opening 90 can also be described as a strip extending along the Y-direction. Figure 18 In the example shown, in the plate extension 34, three first openings 90 are arranged spaced apart from each other in the X direction. Additionally, in... Figure 18 In the example shown, the shape and size of the three first openings 90 are similar to... Figure 16 The three openings 70 shown are identical.

[0174] The second opening 92, when viewed from above, is rectangular in shape with the X direction as the shorter side and the Y direction as the longer side. The second opening 92 can also be described as a strip extending along the Y direction. The second opening 92 is formed over the entire area of ​​the gate layer 22 and the drain electrode 30 opposite each other in the X direction, which overlaps with the gate layer 22 when viewed from above.

[0175] exist Figure 18 In the example shown, the length L1 in the Y direction of the second opening 92 is equal to the length LH in the Y direction of the first opening 90. Therefore, it can be said that the first opening 90 is formed over the entire region of the gate layer 22 and the drain electrode 30 opposite each other in the X direction in the board extension 34. Furthermore, in Figure 18 In the example shown, the length LK in the X direction of the second opening 92 is smaller than the length LJ in the X direction of the first opening 90. Furthermore, the lengths LH and LJ of the first opening 90 and the lengths L1 and LK of the second opening 92 can be arbitrarily changed. In one example, the length LK in the X direction of the second opening 92 may also be larger than the length LJ in the X direction of the first opening 90.

[0176] [Variation Example 4]

[0177] like Figure 19 As shown, a first opening 100 and a second opening 102 are formed on the field electrode 32. The first opening 100 is disposed on the plate extension 34. Therefore, it can be said that at least a portion of the opening is disposed on the plate extension 34. The second opening 102 is disposed on the gate opposing portion 36. In other words, the second opening 102 is disposed at a position that overlaps with the gate layer 22 when viewed from above. Therefore, in Figure 19 In the example shown, at least a portion of the opening can be positioned to overlap with the gate layer 22 when viewed from above. Furthermore, the opening can be positioned at least within the gate opposing portion 36. Thus, in Figure 19 In the example shown, the opening can be said to be located at both the board extension 34 and the position where it overlaps with the gate layer 22 when viewed from above.

[0178] The first opening 100 has multiple openings spaced apart in both the X and Y directions. Figure 19 In the example shown, the plurality of first openings 100 are configured such that the columns of the plurality of first openings 100 arranged at intervals in the Y direction are arranged at intervals in the X direction in three columns. The configuration of the plurality of first openings 100 is similar to... Figure 17 The arrangement of the plurality of openings 80 shown is the same. In addition, the shape and size of each first opening 100 are the same as the shape and size of each opening 80.

[0179] The second opening 102 has multiple openings spaced apart in the Y direction. Figure 19 In the example shown, the shape of each second opening 102 is the same as that of each first opening 100. However, the size of each second opening 102 is smaller than the size of each first opening 100. More specifically, the size of each second opening 102 in the X direction is smaller than the size of each first opening 100 in the X direction. Furthermore, the size of each second opening 102 in the Y direction is smaller than the size of each first opening 100 in the Y direction.

[0180] Furthermore, the shape and size of the first opening 100 and the second opening 102 can be arbitrarily changed. In one example, the shape and size of the first opening 100 can also be the same as the shape and size of the second opening 102.

[0181] [Variation Example 5]

[0182] like Figure 20As shown, an opening 110 is formed in the field electrode 32. The opening 110 is disposed in the gate opposing portion 36. In other words, the opening 110 is disposed at a position overlapping with the gate layer 22 when viewed from above. On the other hand, the opening 110 is not disposed in the plate extension portion 34. Therefore, in Figure 20 In the example shown, it can be said that at least a portion of the opening is positioned to overlap with the gate layer 22 when viewed from above. Furthermore, it can be said that the opening is at least positioned within the gate opposing portion 36.

[0183] The opening 110, when viewed from above, is rectangular in shape with the X direction as its shorter side and the Y direction as its longer side. The opening 110 can also be described as a strip extending along the Y direction. The opening 110 is formed over the entire area of ​​the gate layer 22 and the drain electrode 30 facing each other in the X direction, in the region overlapping with the gate layer 22 when viewed from above. Furthermore, the opening 110 of Modified Example 5 may be added in the first and second embodiments.

[0184] [Variation Example 6]

[0185] like Figure 21 As shown, an opening 120 is formed in the field electrode 32. The opening 120 is disposed in the gate opposing portion 36. In other words, the opening 120 is disposed at a position overlapping with the gate layer 22 when viewed from above. On the other hand, the opening 120 is not disposed in the plate extension portion 34. Therefore, in Figure 21 In the example shown, at least a portion of the opening is positioned to overlap with the gate layer 22 when viewed from above. Furthermore, the opening is at least positioned in the gate-opposing portion 36. Multiple openings 120 are arranged at intervals in the Y direction. Each opening 120 is rectangular in shape with the X direction as its shorter side and the Y direction as its longer side when viewed from above. Additionally, the opening 120 of Modified Example 6 may be added in the first and second embodiments.

[0186] [Variation Example 7]

[0187] like Figure 22 As shown, an opening 130 is formed in the field plate electrode 32. The opening 130 is disposed in the plate extension 34. On the other hand, the opening 130 is not disposed in the gate opposing portion 36. Multiple openings 130 are arranged at intervals in both the X and Y directions. Figure 22 In the example shown, the plurality of openings 130 are configured such that the columns of the plurality of openings 130 arranged at intervals in the Y direction are arranged at intervals in the X direction in three columns. The configuration of the plurality of openings 130 is similar to... Figure 17 The multiple openings 80 shown are configured in the same way.

[0188] Each opening 130 is elliptical in shape when viewed from above. Figure 22In the example shown, each opening 130 is an ellipse with the X-axis as its minor axis and the Y-axis as its major axis when viewed from above. However, the opening 130 is not limited to an elliptical shape when viewed from above; it can also be a circle. Alternatively, the opening 130 can also be polygonal when viewed from above.

[0189] [Variation Example 8]

[0190] like Figure 23 As shown, a first opening 140 and a second opening 142 are formed on the field electrode 32. The first opening 140 is disposed on the plate extension 34. Therefore, it can be said that at least a portion of the opening is disposed on the plate extension 34. The second opening 142 is disposed on the gate opposing portion 36. In other words, the second opening 142 is disposed at a position that overlaps with the gate layer 22 when viewed from above. Therefore, in Figure 23 In the example shown, at least a portion of the opening can be positioned to overlap with the gate layer 22 when viewed from above. Furthermore, the opening can be positioned at least within the gate opposing portion 36. Thus, in Figure 23 In the example shown, the opening can be said to be located at both the board extension 34 and the position where it overlaps with the gate layer 22 when viewed from above.

[0191] The first opening 140 has multiple openings spaced apart in both the X and Y directions. Figure 23 In the example shown, the plurality of first openings 140 are configured such that the columns of the plurality of first openings 140 arranged at intervals in the Y direction are arranged at intervals in the X direction in three columns. The configuration of the plurality of first openings 140 is similar to... Figure 17 The arrangement of the plurality of openings 80 shown is the same. In addition, the shape and size of each first opening 140 are the same as the shape and size of each opening 80.

[0192] The second opening 142 has multiple openings spaced apart in the Y direction. Figure 23 In the example shown, the length LM in the X direction of each second opening 142 is longer than the length LL in the X direction of each first opening 140. The length LP in the Y direction of each second opening 142 is longer than the length LN in the Y direction of each first opening 140. This increases the ratio of the opening area of ​​the second opening 142 to the area of ​​the gate opposing portion 36 when viewed from above. Furthermore, the second opening 142 of Modified Example 8 can be added to both the first and second embodiments.

[0193] In the embodiments described above, the gate opposing portion 36 may also be omitted from the field plate electrode 32. That is, as... Figure 24 As shown, the field plate electrode 32 includes a plate extension 34 and a source connection portion 38. The plate extension 34 and the source connection portion 38 are arranged spaced apart from each other in the X direction. Figure 25 As shown, the board extension 34 is electrically connected to the source connection 38. In one example, the board extension 34 and the source connection 38 are connected by a wiring layer 150, a first via 152, and a second via 154. The wiring layer 150 is arranged in the Z direction at a distance from the board extension 34 and the source connection 38, opposite to the electron supply layer 18. More specifically, the nitride semiconductor device 10 also includes an interlayer insulating layer 156 formed on the passivation layer 26 and covering the source electrode 28, the drain electrode 30, and the field plate electrode 32. The wiring layer 150 is formed on the interlayer insulating layer 156. The first via 152 penetrates the interlayer insulating layer 156 in the Z direction to connect the wiring layer 150 and the board extension 34. The second via 154 penetrates the interlayer insulating layer 156 in the Z direction to connect the wiring layer 150 and the source connection 38.

[0194] • In the above embodiments, the structure of the gate layer 22 can be arbitrarily changed. In one example, such as Figure 26 As shown, the gate layer 22 includes a ridge 22A and extensions 22B extending from both sides of the ridge 22A in opposite directions. The ridge 22A and the extensions 22B form a stepped structure of the gate layer 22.

[0195] The ridge 22A corresponds to the relatively thicker portion of the gate layer 22. The gate electrode 24 contacts the ridge 22A. The ridge 22A extends along... Figure 26 The cross-section of the XZ plane can have a rectangular or trapezoidal shape. The ridge 22A can have a thickness of, for example, 100 nm or more and 200 nm or less. The thickness of the ridge 22A is the distance from the upper surface to the lower surface of the ridge 22A (from the upper surface 22U of the gate layer 22 where the gate electrode 24 is formed to the lower surface 22L of the gate layer 22 that contacts the electron supply layer 18). The thickness of the ridge 22A (gate layer 22) can be determined by taking into account various parameters such as gate breakdown voltage.

[0196] The extension 22B includes a source-side extension 22BS and a drain-side extension 22BD. The source-side extension 22BS extends from the ridge 22A toward the first opening 26A of the passivation layer 26. The drain-side extension 22BD extends from the ridge 22A toward the second opening 26B of the passivation layer 26. The source-side extension 22BS and the drain-side extension 22BD may have the same length or different lengths.

[0197] The source-side extension 22BS may have a thickness of, for example, 5 nm or more and 30 nm or less. The source-side extension 22BS may have a length in the X direction of, for example, 100 nm or more, in the direction from the ridge 22A toward the first opening 26A. The length in the X direction of the source-side extension 22BS may be, for example, 200 nm or more and 300 nm or less. The drain-side extension 22BD may have a thickness of, for example, 5 nm or more and 30 nm or less. The drain-side extension 22BD may have a length in the X direction of, for example, 200 nm or more and 600 nm or less, in the direction from the ridge 22A toward the second opening 26B. In one example, the thickness of the source-side extension 22BS and the thickness of the drain-side extension 22BD are equal to each other.

[0198] Gate layer 22 has an upper surface 22U and a lower surface 22L. The lower surface 22L is the surface of gate layer 22 opposite to the upper surface 18U of electron supply layer 18, and the upper surface 22U is the surface of gate layer 22 located on the opposite side of lower surface 22L. The upper surface 22U of gate layer 22 with a stepped structure refers to the upper surface of ridge 22A. The lower surface 22L of gate layer 22 with a stepped structure refers to the surface including the lower surface of ridge 22A, the lower surface of source-side extension 22BS, and the lower surface of drain-side extension 22BD.

[0199] Figure 27 Schematic representation of the relationship in the Y direction with Figure 26 A cross-sectional structure showing the nitride semiconductor device 10 cut along the XZ plane at different locations.

[0200] like Figure 27 As shown, in the field electrode 32, the recess 42, which serves as the opening 40, is disposed near the front end surface 34A of the gate layer 22 (see reference). Figure 26 That is, the bottom surface 46 of the recess 42 is located at a position relative to the front end surface 34A of the drain-side extension 22BD of the gate layer 22.

[0201] One or more of the various examples described in this specification may be combined to the extent that they are not technically contradictory.

[0202] In this specification, "at least one of A and B" should be understood to mean "only A, or only B, or both A and B".

[0203] The terms “first,” “second,” “third,” etc., used in this disclosure are used only to distinguish objects, not to order them.

[0204] As used in this disclosure, the term "~above" includes both the meaning of "~above" and "above," unless the context clearly indicates "~above." Therefore, the expression "structure A is formed on structure B" means that in one embodiment structure A can contact structure B and be directly disposed on structure B, but in other embodiments structure A can be disposed above structure B without contacting structure B. That is, the term "~above" does not exclude structures where other structures are formed between structure A and structure B.

[0205] The Z-direction used in this disclosure does not necessarily need to be vertical, nor does it need to be completely consistent with the vertical direction. Therefore, the various structures of this disclosure are not limited to the "up" and "down" of the Z-direction as described in this specification being vertical. For example, the X-direction can also be vertical, or the Y-direction can also be vertical.

[0206] <Postscript>

[0207] The following describes the technical concepts that can be grasped from this disclosure. Furthermore, for the purpose of aiding understanding without limitation, the corresponding constituent elements in the embodiments are indicated by reference numerals for the constituent elements described in the appendices. The reference numerals are shown as examples to aid understanding, and the constituent elements described in each appendix should not be limited to those indicated by the reference numerals.

[0208] [Postscript 1]

[0209] A nitride semiconductor device 10, comprising:

[0210] Electron transport layer 16 is made of nitride semiconductor;

[0211] An electron supply layer 18 is formed on the electron transport layer 16 and is made of a nitride semiconductor having a larger band gap than the electron transport layer 16.

[0212] A gate layer 22 is formed on the electron supply layer 18 and is made of a nitride semiconductor containing acceptor-type impurities;

[0213] Gate electrode 24 is formed on the gate layer 22;

[0214] A passivation layer 26 covers the electron supply layer 18, the gate layer 22 and the gate electrode 24. The passivation layer 26 has a first opening 26A and a second opening 26B spaced apart in a first direction (X direction). The gate layer 22 is located between the first opening 26A and the second opening 26B.

[0215] The source electrode 28 is connected to the electron supply layer 18 via the first opening 26A;

[0216] Drain electrode 30, which is connected to the electron supply layer 18 via the second opening 26B; and

[0217] The field plate electrode 32 is formed on the passivation layer 26 and electrically connected to the source electrode 28.

[0218] The field plate electrode 32 includes a plate extension 34, which, when viewed from above, extends in the region between the gate layer 22 and the drain electrode 30 and faces the electron supply layer 18 across the passivation layer 26.

[0219] An opening 40 is formed in the field plate electrode 32, and the opening 40 is formed in at least one of the plate extension 34 and the position that overlaps with the gate layer 22 when viewed from above.

[0220] [Postscript 2]

[0221] According to the nitride semiconductor device described in Appendix 1, wherein,

[0222] At least a portion of the opening 40 is formed in the plate extension 34.

[0223] [Postscript 3]

[0224] According to the nitride semiconductor device described in Appendix 2, wherein,

[0225] The plate extension 34 has a front end face 34A opposite to the drain electrode 30.

[0226] The opening 40 is a recess 42 that is recessed from the front end face 34A of the plate toward the gate layer 22.

[0227] When viewed from above, the recess 42 extends with a width in a second direction (Y direction) orthogonal to the first direction (X direction) and a depth in the first direction (X direction), and opens toward the drain electrode 30.

[0228] [Postscript 4]

[0229] According to the nitride semiconductor device described in Appendix 3, wherein,

[0230] The depth H of the recess 42 is more than half the length L of the plate extension 34 in the first direction (X direction).

[0231] [Postscript 5]

[0232] According to the nitride semiconductor device described in Appendix 4, wherein,

[0233] The field plate electrode 32 has a gate opposing portion 36 that is opposed to the gate layer 22 through the passivation layer 26.

[0234] The recess 42 extends from the front end face 34A of the plate in the first direction (X direction) and is longer than the plate extension 34, and is formed across both the plate extension 34 and the gate opposing portion 36.

[0235] [Postscript 6]

[0236] The nitride semiconductor device according to any one of Appendices 3 to 5, wherein...

[0237] The recesses 42 are arranged in a plurality of spaced-apart configurations in the second direction (Y direction).

[0238] [Postscript 7]

[0239] According to the nitride semiconductor device described in Appendix 6, wherein,

[0240] The distance D between the plurality of recesses 42 is greater than the width W of the recesses 42.

[0241] [Postscript 8]

[0242] According to the nitride semiconductor device described in Appendix 6, wherein,

[0243] The width W of the recess 42 is greater than the distance D between the plurality of recesses 42.

[0244] [Postscript 9]

[0245] According to the nitride semiconductor device described in Appendix 3, wherein...

[0246] The bottom surface 46 of the recess 42 is curved.

[0247] [Postscript 10]

[0248] According to the nitride semiconductor device described in Appendix 2, wherein,

[0249] The plate extension 34 has a front end face 34A opposite to the drain electrode 30.

[0250] The opening 50 is a closed opening formed on the side of the front end face 34A of the plate closer to the gate electrode 24.

[0251] [Postscript 11]

[0252] According to the nitride semiconductor device described in Appendix 10, wherein,

[0253] When viewed from above, the opening 50 is rectangular with the first direction (X direction) as its long side and the second direction (Y direction) orthogonal to the first direction (X direction) as its short side.

[0254] [Postscript 12]

[0255] According to the nitride semiconductor device described in Appendix 11, wherein,

[0256] The length LA of the opening 50 in the first direction (X direction) is longer than half the length L of the plate extension 34 in the first direction (X direction).

[0257] [Postscript 13]

[0258] According to the nitride semiconductor device described in Appendix 10, wherein,

[0259] When viewed from above, the opening 70 is rectangular with the first direction (X direction) as the short side and the second direction (Y direction) orthogonal to the first direction (X direction) as the long side.

[0260] [Postscript 14]

[0261] The nitride semiconductor device according to any one of Appendices 10 to 12, wherein,

[0262] The field plate electrode 32 has a gate opposing portion 36 that is opposed to the gate layer 22 through the passivation layer 26.

[0263] The opening 60 is formed across both the plate extension 34 and the gate opposing portion 36.

[0264] [Postscript 15]

[0265] According to the nitride semiconductor device described in Appendix 1, wherein,

[0266] At least a portion of the opening 60 is formed at a position that overlaps with the gate layer 22 when viewed from above.

[0267] [Postscript 16]

[0268] According to the nitride semiconductor device described in Appendix 15, wherein,

[0269] The field plate electrode 32 has a gate opposing portion 36 that is opposed to the gate layer 22 through the passivation layer 26.

[0270] The opening 110 is formed at least in the gate opposing portion 36.

[0271] [Postscript 17]

[0272] According to the nitride semiconductor device described in Appendix 15 or 16, wherein,

[0273] The gate layer 22 and the drain electrode 30 extend along a second direction (Y direction) orthogonal to the first direction (X direction) when viewed from above.

[0274] The opening 110 is formed over the entire area of ​​the gate layer 22 and the drain electrode 30 in the first direction (X direction), which overlap with the gate layer 22 when viewed from above.

[0275] [Postscript 18]

[0276] According to the nitride semiconductor device described in Appendix 1 or 2, wherein,

[0277] The opening 130 is circular or elliptical.

[0278] [Postscript 19]

[0279] The nitride semiconductor device according to any one of Appendices 3 to 9, wherein...

[0280] The gate layer 22 includes:

[0281] Ridge 22A, which is in contact with the electron supply layer 18;

[0282] The source-side extension 22BS is in contact with the electron supply layer 18 and extends from the ridge 22A toward the source electrode 28 in the first direction (X direction), and is thinner than the ridge 22A.

[0283] The drain-side extension 22BD is in contact with the electron supply layer 18 and extends from the ridge 22A toward the drain electrode 30 in the first direction (X direction), and is thinner than the ridge 22A.

[0284] [Postscript 20]

[0285] The nitride semiconductor device described in Appendix 19, wherein,

[0286] The bottom surface 46 of the recess 42 is located in the first direction (X direction) closer to the drain electrode 30 than the drain-side extension 22BD.

[0287] The above description is merely illustrative. Those skilled in the art will recognize that many other combinations and substitutions are possible beyond those listed for the purpose of illustrating the technology of this disclosure. This disclosure is intended to include all substitutions, modifications, and alterations within the scope of this disclosure, including the claims.

[0288] Symbol Explanation

[0289] 10—Nitride semiconductor device; 10A—Unit transistor; 12—Semiconductor substrate; 14—Buffer layer; 16—Electron transport layer; 18—Electron supply layer; 18U—Upper surface; 20—Two-dimensional electron gas (2DEG); 22—Gate layer; 22A—Ridge; 22B—Extension; 22BD—Drain-side extension; 22BS—Source-side extension; 22U—Upper surface; 22L—Lower surface; 22X—Side surface; 24—Gate electrode; 26—Passivation layer; 26A—First opening; 26B—Second opening; 28 —Source electrode; 30—Drain electrode; 32—Field plate electrode; 34—Plate extension; 34A—Plate front end face; 36—Gate opposite portion; 38—Source connection portion; 40—Opening; 42—Recess; 44—Side side; 46—Bottom surface; 50—Opening; 52—Plate front end; 60—Opening; 62—Inner side; 62A—First end face; 62B—Second end face; 64—Plate front end; 70—Opening; 80—Opening; 90—First opening; 92—Second opening; 100—First opening; 102— Second opening; 110—Opening; 120—Opening; 130—Opening; 140—First opening; 142—Second opening; 150—Wiring layer; 152—First through-hole; 154—Second through-hole; 156—Interlayer insulation layer; L—Length of the board extension in the X direction; H—Depth of the recess; W—Width of the recess; D—Distance between recesses; DA, DB—Distance between openings; LA—Length of the opening in the X direction; LB—Length of the opening in the Y direction; LC—Length of the opening in the X direction; LD — Length of the opening in the Y direction; LF — Length of the field plate electrode in the X direction; LE — Length of the opening in the Y direction; LG — Length of the drain electrode in the Y direction; LH — Length of the first opening in the Y direction; LI — Length of the second opening in the Y direction; LJ — Length of the first opening in the X direction; LK — Length of the second opening in the X direction; LL — Length of the first opening in the X direction; LM — Length of the second opening in the X direction; LN — Length of the first opening in the Y direction; LP — Length of the second opening in the Y direction.

Claims

1. A nitride semiconductor device, characterized in that, have: The electron transport layer is composed of nitride semiconductors; An electron supply layer is formed on the electron transport layer and is made of a nitride semiconductor having a larger band gap than the electron transport layer. A gate layer is formed on the electron supply layer and is made of a nitride semiconductor containing acceptor-type impurities; A gate electrode is formed on the gate layer; A passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and having a first opening and a second opening spaced apart in a first direction, the gate layer being located between the first opening and the second opening; The source electrode is connected to the electron supply layer via the first opening; The drain electrode is connected to the electron supply layer via the second opening; as well as A field plate electrode is formed on the passivation layer and electrically connected to the source electrode. The field plate electrode includes a plate extension that, when viewed from above, extends in the region between the gate layer and the drain electrode, and faces the electron supply layer across the passivation layer. An opening is formed in the field plate electrode, the opening being formed in at least one of the plate extension and a position that overlaps with the gate layer when viewed from above.

2. The nitride semiconductor device according to claim 1, characterized in that, At least a portion of the opening is formed in the plate extension.

3. The nitride semiconductor device according to claim 2, characterized in that, The plate extension has a front end face opposite to the drain electrode. The opening is a recess that is recessed from the front end face of the plate toward the gate layer. When viewed from above, the recess extends with a width in a second direction orthogonal to the first direction and a depth in the first direction, and opens toward the drain electrode.

4. The nitride semiconductor device according to claim 3, characterized in that, The depth of the recess is greater than 1 / 2 the length of the plate extension in the first direction.

5. The nitride semiconductor device according to claim 4, characterized in that, The field plate electrode has a gate opposing portion that is separated from the gate layer by the passivation layer. The recess extends longer than the plate extension from the front end face of the plate in the first direction and is formed across both the plate extension and the gate opposing portion.

6. The nitride semiconductor device according to any one of claims 3 to 5, characterized in that, The recesses are arranged in a plurality of spaced-apart configurations in the second direction.

7. The nitride semiconductor device according to claim 6, characterized in that, The distance between the plurality of recesses is greater than the width of the recesses.

8. The nitride semiconductor device according to claim 6, characterized in that, The width of the recess is greater than the distance between the plurality of recesses.

9. The nitride semiconductor device according to claim 3, characterized in that, The bottom surface of the recess is curved.

10. The nitride semiconductor device according to claim 2, characterized in that, The plate extension has a front end face opposite to the drain electrode. The opening is a closed opening formed on the side of the gate electrode closer to the front end face of the plate.

11. The nitride semiconductor device according to claim 10, characterized in that, When viewed from above, the opening is rectangular with the first direction as its long side and the second direction, which is orthogonal to the first direction, as its short side.

12. The nitride semiconductor device according to claim 11, characterized in that, The length of the opening in the first direction is longer than half the length of the plate extension in the first direction.

13. The nitride semiconductor device according to claim 10, characterized in that, When viewed from above, the opening is rectangular with the first direction as its short side and the second direction, which is orthogonal to the first direction, as its long side.

14. The nitride semiconductor device according to any one of claims 10 to 12, characterized in that, The field plate electrode has a gate opposing portion that is separated from the gate layer by the passivation layer. The opening is formed across both the plate extension and the gate opposing portion.

15. The nitride semiconductor device according to claim 1, characterized in that, At least a portion of the opening is formed at a position that overlaps with the gate layer when viewed from above.

16. The nitride semiconductor device according to claim 15, characterized in that, The field plate electrode has a gate opposing portion that is separated from the gate layer by the passivation layer. The opening is formed at least in the gate opposite portion.

17. The nitride semiconductor device according to claim 15 or 16, characterized in that, The gate layer and the drain electrode extend in a second direction orthogonal to the first direction when viewed from above. The opening is formed over the entire area of ​​the gate layer and the drain electrode, which are opposite each other in the first direction, in the region that overlaps with the gate layer when viewed from above.

18. The nitride semiconductor device according to claim 1 or 2, characterized in that, The opening is circular or elliptical.

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