Deposition mask

Abstract

A deposition mask is provided. The deposition mask includes a substrate and a cell pattern disposed in each of a plurality of cell openings in the substrate. The unit pattern is formed of an inorganic film and includes a mask film pattern having a plurality of openings. The dummy pattern surrounds the mask film pattern, and a width of the dummy pattern is irregular. The deposition apparatus includes a deposition mask.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0063176, filed on May 14, 2024, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to a mask and a deposition apparatus (or deposition device) including the mask. Background Technology

[0003] Wearable devices that focus at a distance close to the user's eyes have been developed in the form of glasses or helmets. For example, wearable devices can include head-mounted display (HMD) devices or augmented reality (AR) glasses. Wearable devices provide users with AR or virtual reality (VR) visuals.

[0004] Wearable devices, such as HMD devices or AR glasses, require a display specification of at least 2000 PPI (pixels per inch) to allow users to use them for extended periods without experiencing dizziness. For this purpose, silicon-based organic light-emitting diode (OLEDoS) technology (high-resolution, small organic light-emitting display devices) is emerging. OLEDoS involves setting organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) semiconductors are positioned. Summary of the Invention

[0005] The embodiment provides a mask and a deposition apparatus (or device) including the mask, the mask being used as a deposition mask for manufacturing a high-resolution organic light-emitting display device, wherein reliability is improved by increasing pixel position accuracy (PPA).

[0006] The embodiments also provide a mask that can reduce shadow defects and the accumulation of deposited material on the mask, and a deposition apparatus (or device) including the mask.

[0007] However, the embodiments are not limited to those described herein. The above and other embodiments will become clear to those skilled in the art from the detailed description provided below.

[0008] According to an embodiment, the deposition mask may include a substrate and a cell pattern, the cell pattern being disposed in each of a plurality of cell openings in the substrate, the cell pattern being formed of an inorganic film. The cell pattern may include: a mask film pattern including a plurality of openings; and a dummy pattern surrounding the mask film pattern, wherein the width of the dummy pattern is irregular.

[0009] In an embodiment, the plurality of unit openings may include: at least one first-type unit opening adjacent to the central portion of the substrate, comprising a first unit pattern; and a plurality of second-type unit openings disposed around the periphery of the first-type unit opening, comprising a second unit pattern. The width of the dummy pattern included in the first unit pattern may be uniform, and the width of the dummy pattern included in the second unit pattern may be irregular.

[0010] In an embodiment, the first unit pattern may include: a first dummy pattern disposed on one side of the mask film pattern and having a first width; and a second dummy pattern disposed on the other side of the mask film pattern and having a first width.

[0011] In an embodiment, the second unit pattern may include: a first dummy pattern disposed on one side of the mask film pattern and having a first width; and a second dummy pattern disposed on the other side of the mask film pattern and having a second width, the second width being greater than the first width. The second dummy pattern may be closer to the center portion of the substrate than the first dummy pattern.

[0012] In an embodiment, the plurality of second-type unit openings may include: a first unit opening including a first dummy pattern and a second dummy pattern, spaced apart from the center portion of the substrate by a first distance; and a second unit opening including a third dummy pattern and a fourth dummy pattern, spaced apart from the center portion of the substrate by a second distance, the second distance being smaller than the first distance. The width of each of the first to fourth dummy patterns may be different from each other.

[0013] In an embodiment, the first dummy pattern may have a first width, the second dummy pattern may have a second width greater than the first width, the third dummy pattern may have a third width, and the fourth dummy pattern may have a fourth width greater than the third width.

[0014] In an embodiment, the first width may be different from the third width, and the second width may be different from the fourth width.

[0015] In an embodiment, the inorganic membrane may include: a first inorganic membrane comprising silicon oxide (SiO2). x ); and a second inorganic film disposed on the first inorganic film, comprising silicon nitride (SiN); x ).

[0016] In the embodiments, the inorganic film may comprise silicon (Si) or silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO)x At least one of the following.

[0017] In some embodiments, the substrate may comprise silicon (Si).

[0018] According to an embodiment, the deposition apparatus (or device) may include a deposition source and a mask disposed between a first substrate and the deposition source. The mask may include a second substrate and a cell pattern, the cell pattern being disposed in each of a plurality of cell openings in the second substrate and formed of an inorganic film. The cell pattern may include: a mask film pattern including a plurality of openings; and a dummy pattern surrounding the mask film pattern, wherein the width of the dummy pattern is irregular.

[0019] In an embodiment, the plurality of unit openings may include: at least one first-type unit opening adjacent to the central portion of the second substrate, comprising a first unit pattern; and a plurality of second-type unit openings disposed around the periphery of the first-type unit opening, comprising a second unit pattern. The width of the dummy pattern included in the first unit pattern may be uniform, and the width of the dummy pattern included in the second unit pattern may be irregular.

[0020] In an embodiment, the first unit pattern may include: a first dummy pattern disposed on one side of the mask film pattern and having a first width; and a second dummy pattern disposed on the other side of the mask film pattern and also having a first width.

[0021] In an embodiment, the second unit pattern may include: a first dummy pattern disposed on one side of the mask film pattern and having a first width; and a second dummy pattern disposed on the other side of the mask film pattern and having a second width, the second width being greater than the first width. The second dummy pattern may be closer to the center portion of the second substrate than the first dummy pattern.

[0022] In an embodiment, the plurality of second-type unit openings may include: a first unit opening including a first dummy pattern and a second dummy pattern, spaced apart from the center portion of the second substrate by a first distance; and a second unit opening including a third dummy pattern and a fourth dummy pattern, spaced apart from the center portion of the second substrate by a second distance, the second distance being smaller than the first distance. The width of each of the first to fourth dummy patterns may be different from each other.

[0023] In an embodiment, the first dummy pattern may have a first width, the second dummy pattern may have a second width greater than the first width, the third dummy pattern may have a third width, and the fourth dummy pattern may have a fourth width greater than the third width.

[0024] In an embodiment, the first width may be different from the third width, and the second width may be different from the fourth width.

[0025] In an embodiment, the inorganic membrane may include: a first inorganic membrane comprising silicon oxide (SiO2). x ); and a second inorganic film disposed on the first inorganic film, comprising silicon nitride (SiN); x ).

[0026] In the embodiments, the inorganic film may comprise silicon (Si) or silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following.

[0027] In an embodiment, the second substrate may comprise silicon (Si).

[0028] According to an embodiment, reliability can be improved by increasing pixel position accuracy (PPA).

[0029] According to the embodiments, shadow defects and the accumulation of deposited material on the mask can also be reduced. Attached Figure Description

[0030] The above and other aspects, features and advantages of the embodiments will become clearer from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is an exploded schematic perspective view showing a display device according to an embodiment; Figure 2 This is a schematic block diagram illustrating a display device according to an embodiment; Figure 3 This is a schematic equivalent circuit diagram of the first sub-pixel according to an embodiment; Figure 4 This is a schematic layout diagram showing an example of a display panel according to an embodiment; Figure 5 and Figure 6 It is shown Figure 4 A schematic layout diagram of an embodiment of the display area; Figure 7 It shows along Figure 5 A schematic cross-sectional view of an example display panel, taken by line I1-I1'; Figure 8 This is a schematic perspective view showing a head-mounted display according to an embodiment; Figure 9 It is shown Figure 8 An exploded schematic perspective view of an example of a head-mounted display; Figure 10This is a schematic perspective view showing a head-mounted display according to an embodiment; Figure 11 This is a schematic perspective view of a mask according to an embodiment; Figure 12 This is a schematic plan view of the mask according to an embodiment; Figures 13 to 15 This is a schematic process cross-sectional view illustrating a method for manufacturing a mask according to an embodiment; Figure 16 This is a schematic diagram illustrating the shadow defects that occur during a deposition process using a mask; Figures 17 to 18 It is a schematic construction diagram based on the mask of the comparative example; Figures 19 to 20 It is a schematic structural diagram of a mask according to an embodiment; and Figure 21 This is a schematic structural diagram illustrating a deposition apparatus (or device) according to an embodiment. Detailed Implementation

[0031] The disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The various embodiments are not necessarily exclusive, nor are they intended to limit the disclosure. For example, a particular shape, construction, and characteristic of one embodiment may be used or implemented in another embodiment. In the drawings, the size, thickness, scale, and dimensions of elements may be exaggerated for ease of description and for clarity. The same reference numerals and / or reference numerals always refer to the same elements.

[0032] Some parts that are not relevant to the description may be omitted in order to describe the disclosed embodiments.

[0033] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0034] When an element (such as a layer, region, or portion) is referred to as being "on," "connected to," or "bonded to" another element or layer, it may be directly on, directly connected to, or directly bonded to the other element or layer, or an intermediary element or intermediary layer may be present. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, an intermediary element or intermediary layer may not be present. The terms "connection" or "bonding" can refer to physical, electrical, and / or fluid connections, with or without an intermediary element, including cases where elements are "electrically connected" or "electrically bonded."

[0035] The phrase "in a plan view" indicates an object viewed from above, and the phrase "in a schematic sectional view" indicates a schematic section of an object that has been vertically cut, viewed from the side. Therefore, the phrase "in a plan view" as used here can indicate an object viewed from above in a third direction. The phrase "in a schematic sectional view" indicates a section of an object that has been vertically cut, viewed from the side, in a first or second direction. The third direction can also be referred to as the "thickness direction."

[0036] The terms "overlapping" or "coinciding" refer to a first object being positioned above, below, to the side of, or in any other positional relationship with a second object. The term "overlapping" can also include constructions such as stacking, overlapping, facing, extending over, covering, or partially covering, and any other suitable relationship that will be understood by those skilled in the art. As will be understood by those skilled in the art, the term "not overlapping" can refer to a construction where objects are "separated," "offset," "shifted," or in other equivalent spatial arrangements. The terms "facing" and "oriented" refer to a first object being directly or indirectly opposite a second object. Even when a third object is positioned between the first and second objects, the first and second objects can still be considered to be indirectly facing each other.

[0037] For ease of description, the spatial relative terms “below,” “under,” “lower,” “above,” or “upper,” etc., may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device shown in the drawings is flipped, the device positioned “below” or “under” another device may be placed “above” another device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatial relative terms may be interpreted differently depending on the orientation.

[0038] When the terms “comprising,” “including,” “having,” “owning,” and / or variations thereof are used in this specification, the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof may be specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0039] It will be understood that although the terms “first,” “second,” or “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or for ease of description and explanation. For example, without departing from the scope of disclosure, a “first element” may be referred to as a “second element” or a “third element,” and similarly, a “second element” or a “third element” may be referred to as a “first element” or a “second element.”

[0040] As used herein, the terms “about” or “approximately” include the stated value and mean, taking into account the measurement in question and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system), within an acceptable deviation of the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within about ±30%, ±20%, ±10%, ±5% of the stated value.

[0041] For purposes of its meaning and interpretation, the term “and / or” is intended to include any combination of the terms “and” and “or”. For example, “A and / or B” can be understood to mean “A, B or A and B”. The terms “and” and “or” can be used in the sense of conjunction or disjunction and can be understood as equivalent to “and / or”.

[0042] For the purposes of its meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one of the groups of…”. For example, “at least one of A and B” can be understood as “A, B or A and B”.

[0043] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which they pertain. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context (background) of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined in the description.

[0044] Figure 1 This is an exploded schematic perspective view showing a display device according to an embodiment. Figure 2 This is a schematic block diagram illustrating a display device according to an embodiment.

[0045] Reference Figure 1 and Figure 2 The display device 10 according to the embodiment can be a device for displaying moving or still images. The display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 according to the embodiment can be applied as a display unit for televisions, laptop computers, monitors, billboards, or Internet of Things (IoT) terminals. In another embodiment, the display device 10 according to the embodiment can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for implementing virtual and augmented reality.

[0046] The display device 10 according to the embodiment may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing controller 400, and a power supply circuit 500.

[0047] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2, the second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or rounded with a selected curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0048] like Figure 2 As shown, the display panel 100 may include a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0049] The display area (DAA) can include multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0050] Multiple pixels (PX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Scan lines (SL) and emission control lines (EL) can extend on the first direction DR1 and be arranged on the second direction DR2. Data lines (DL) can extend on the second direction DR2 and be arranged on the first direction DR1.

[0051] Multiple scan lines SL may include a write scan line GWL, a control scan line GCL, and a bias scan line GBL. Emit control lines EL may include a first emit control line EL1 and a second emit control line EL2.

[0052] Multiple pixels PX can include sub-pixels SP1, SP2, and SP3. Sub-pixels SP1, SP2, and SP3 can include, for example: Figure 3 The multiple pixel transistors shown can be formed using semiconductor processes and disposed on a semiconductor substrate SSUB (see [reference]). Figure 7 For example, the pixel transistors of sub-pixels SP1, SP2, and SP3 can be formed from complementary metal-oxide-semiconductor (CMOS).

[0053] Each of sub-pixels SP1, SP2, and SP3 can be connected to any of the write scan lines GWL, any of the control scan lines GCL, any of the bias scan lines GBL, any of the first emission control lines EL1, any of the second emission control lines EL2, and any of the data lines DL. Each of sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0054] The non-display area NDA may include a scan driver 610, a transmit driver 620, and a data driver 700.

[0055] The scan driver 610 may include multiple scan transistors, and the emitter driver 620 may include multiple light-emitting transistors. The scan transistors and light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor diagram]). Figure 7 For example, scanning transistors and light-emitting transistors can be formed using CMOS. Although Figure 2 A scan driver 610 is shown on the left side of the display area DAA and a transmit driver 620 is shown on the right side of the display area DAA, but this disclosure is not limited thereto. For example, the scan driver 610 and the transmit driver 620 may be located on both the left and right sides of the display area DAA.

[0056] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing controller 400. The write scan signal output unit 611 may generate write scan signals based on the scan timing control signal SCS from the timing controller 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals based on the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0057] The transmit driver 620 may include a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 may receive transmit timing control signals ECS from the timing controller 400. The first transmit control driver 621 may generate a first transmit control signal based on the transmit timing control signals ECS and output them sequentially to a first transmit control line EL1. The second transmit control driver 622 may generate a second transmit control signal based on the transmit timing control signals ECS and output them sequentially to a second transmit control line EL2.

[0058] The data driver 700 may include multiple data transistors, which can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to SSUB]). Figure 7 For example, data transistors can be formed using CMOS.

[0059] The data driver 700 can receive digital video data DATA and data timing control signal DCS from the timing controller 400. The data driver 700 can convert the digital video data DATA into analog data voltage according to the data timing control signal DCS and output the analog data voltage to the data line DL. Sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal from the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0060] The heat dissipation layer 200 can be stacked on the display panel 100 in a third-direction DR3, where DR3 is the thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on the surface of the display panel 100 (e.g., on the rear surface of the display panel 100). The heat dissipation layer 200 can be used to dissipate heat generated by the display panel 100. The heat dissipation layer 200 can include a metallic or non-metallic layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity.

[0061] Circuit board 300 can be electrically connected to the first pad (also called "soldering pad") portion of display panel 100 PDA1 (see [link to circuit board 300]) using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board or flexible film made of flexible material. Although circuit board 300 in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. The ends of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The ends of the circuit board 300 can be connected to the first pad portion PDA1 of the display panel 100 using conductive adhesive members (see...). Figure 4 The first pad PD1 (see) Figure 4 The ends of the ) are opposite each other.

[0062] The timing controller 400 can receive digital video data DATA and timing signals from an external source. In response to the timing signals, the timing controller 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS to control the display panel 100. The timing controller 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing controller 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0063] The power supply circuit 500 can generate multiple panel driving voltages based on the external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 3 The first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT are described. In addition, the power supply circuit 500 can also generate a reference voltage VREF.

[0064] Each of the timing controller 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to the surface of the circuit board 300. Scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS from the timing controller 400 can be supplied to the display panel 100 via the circuit board 300. A first drive voltage VSS, a second drive voltage VDD, and a third drive voltage VINT from the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0065] In another embodiment, similar to scan driver 610, transmit driver 620, and data driver 700, each of timing controller 400 and power supply circuit 500 may be disposed in the non-display area NDA of display panel 100. Timing controller 400 may include multiple timing transistors, and power supply circuit 500 may include multiple power transistors. The timing transistors and power transistors may be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 7 On the data driver 700. For example, the timing transistors and power transistors can be formed by CMOS. Each of the timing controller 400 and the power supply circuit 500 can be arranged in the data driver 700 and the first pad PDA1 (see...). Figure 4 )between.

[0066] Figure 3 This is a schematic equivalent circuit diagram of the first sub-pixel according to an embodiment.

[0067] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. The first sub-pixel SP1 can also be connected to a first drive voltage line VSL, which is applied with a first drive voltage VSS corresponding to a low potential voltage; a second drive voltage line VDL, which is applied with a second drive voltage VDD corresponding to a high potential voltage; and a third drive voltage line VIL, which is applied with a third drive voltage VINT corresponding to an initialization voltage. The first drive voltage VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. The first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT.

[0068] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0069] The light-emitting element LE can emit light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element (such as a micro light-emitting diode) including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode.

[0070] The first transistor T1 may be a drive transistor that controls the drain-source current (hereinafter referred to as the "drive current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 may include a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0071] The second transistor T2 can be disposed between the electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by the write scan signal of the write scan line GWL, connecting the electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the electrode of the first capacitor CP1.

[0072] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 can be turned on by a control scan signal controlling the scan line GCL, connecting the first node N1 to the second node N2. For this reason, since the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 may include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0073] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 can be turned on by a first emitter control signal from the first emitter control line EL1, connecting the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0074] A fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 can be turned on by a bias scan signal from the bias scan line GBL, connecting the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT from the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0075] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 can be turned on by a second emitter control signal from the second emitter control line EL2, connecting the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, a second drive voltage VDD from the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0076] A first capacitor CP1 may be formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0077] The second capacitor CP2 can be formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 may include one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0078] The first node N1 can be the junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 can be the junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 can be the junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0079] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but the disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. In another embodiment, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and the remaining transistors can be N-type MOSFETs.

[0080] although Figure 3 The diagram shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2, but the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0081] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be repeated in this disclosure.

[0082] Figure 4 This is a schematic layout diagram showing an example of a display panel according to an embodiment.

[0083] Reference Figure 4 The display area DAA of the display panel 100 according to the embodiment includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to the embodiment may include a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad PDA1, and a second pad PDA2.

[0084] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in a first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. The scan driver 610 can be disposed on the left side of the display area DAA, and the transmit driver 620 can be disposed on the right side of the display area DAA. However, this disclosure is not limited thereto, and the scan driver 610 and the transmit driver 620 can be disposed on both the first and second sides of the display area DAA.

[0085] The first pad portion PDA1 may include a plurality of first pads PD1 that are connected to the circuit board 300 by a conductive adhesive member. The first pad portion PDA1 may be disposed on the third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2.

[0086] The first pad PDA1 can be disposed on the outside of the data driver 700 on the second direction DR2. For example, the first pad PDA1 can be disposed closer to the edge of the display panel 100 than the data driver 700.

[0087] The second pad PDA2 may include multiple second pads PD2, which serve as inspection pads for testing whether the display panel 100 is operating correctly. The second pads PD2 may be connected to a fixture or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0088] The first distribution circuit 710 can distribute the data voltage applied through the first pad PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad PDA1 to P (P is a positive integer of 2 or greater) data lines DL, reducing the number of first pads PD1. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0089] The second distribution circuit 720 can distribute the signal applied through the second pad PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad PDA2 and the second distribution circuit 720 can check the operation of each pixel PX in the display area DAA. The second distribution circuit 720 can be disposed on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0090] Figure 5 and Figure 6 It is shown Figure 4 A schematic layout diagram of an embodiment of the display area.

[0091] Reference Figure 5 and Figure 6 Each of the pixels PX includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0092] Each of the first launch area EA1, the second launch area EA2, and the third launch area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in the plan view.

[0093] The maximum length of the third transmission region EA3 in the first direction DR1 can be less than the maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1. The maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1 can be substantially the same.

[0094] The maximum length of the third transmission region EA3 in the second direction DR2 can be greater than the maximum length of the first transmission region EA1 in the second direction DR2 and the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2.

[0095] like Figure 5 and Figure 6As shown, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a hexagonal shape formed by six straight lines in the plan view, but the disclosure is not limited thereto. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal shapes, circular shapes, elliptical shapes, or irregular shapes other than hexagons in the plan view.

[0096] like Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the second direction DR2. The first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. The second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0097] In another embodiment, such as Figure 6 As shown, the first transmission region EA1 and the second transmission region EA2 can be adjacent to each other in the first direction DR1, but the second transmission region EA2 and the third transmission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first transmission region EA1 and the third transmission region EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 can be perpendicular to the first diagonal direction DD1.

[0098] The first emission region EA1 can emit a first light, the second emission region EA2 can emit a second light, and the third emission region EA3 can emit a third light. The first light can be light in the blue band, the second light can be light in the green band, and the third light can be light in the red band. For example, the blue band can have a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green band can have a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red band can have a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0099] although Figure 5 and Figure 6 The diagram depicts each of a plurality of pixels PX comprising three emission regions EA1, EA2, and EA3, but the disclosure is not limited thereto. For example, each of the plurality of pixels PX may include four emission regions.

[0100] The layout of the emission region in a pixel PX is not limited to Figure 5 and Figure 6The layout shown is illustrated. For example, the emission region in pixel PX can be configured as a stripe structure with the emission region arranged in the first direction DR1, or as a pentile with the emission region arranged in a diamond shape. ® Structures or emission regions with a hexagonal shape in a plan view, such as Figure 6 The hexagonal structure arranged as shown in the figure.

[0101] Figure 7 It shows along Figure 5 A schematic cross-sectional view of an example display panel taken by line I1-I1'.

[0102] Reference Figure 7 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), an encapsulation layer (TFE), an organic film (APL), a cover layer (CVL), and a polarizing plate (POL).

[0103] The semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the pixel transistors (PTRs). The pixel transistors (PTRs) may correspond to a reference. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0104] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. These well regions WA can be doped with a second type of impurity, different from the first type of impurity. For example, if the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. In another embodiment, if the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0105] Each of the well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0106] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE, also covering the lower insulating film (BINS).

[0107] Each of the source region SA and drain region DA can be doped with type I impurities. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third-direction DR3. The channel region CH can be stacked with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0108] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating film BINS, the first low-concentration impurity region LDD1 can have a lower impurity concentration than the source region SA. Due to the lower insulating film BINS, the second low-concentration impurity region LDD2 can have a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA can be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTR can be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may be caused by short channels.

[0109] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes are formed, but the disclosure is not limited to this.

[0110] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2). x Inorganic membranes are formed, but the disclosure is not limited to this.

[0111] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating both the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (INS2). The contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them.

[0112] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the contact terminals (CTEs). The top surface of each of the contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x Inorganic membranes are formed, but the disclosure is not limited to this.

[0113] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. Thin-film transistors can be disposed on either a glass substrate or a polymer resin substrate. The glass substrate can be a rigid, non-bending substrate, while the polymer resin substrate can be a flexible substrate capable of bending or flexing.

[0114] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. The backplane (EBP) of the light-emitting element may include multiple insulating films INS1 to INS9 disposed between the semiconductor backplane (SBP) and the display element layer (EML).

[0115] The first conductive layer ML1 to the eighth conductive layer ML8 can be used to connect the contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuitry for the first sub-pixel SP1 is shown. For example, although the first transistors T1 to the sixth transistor T6 are only formed in the semiconductor backplane SBP, the connection between the first transistors T1 to the sixth transistor T6 and the connection between the first capacitor CP1 and the second capacitor CP2 are achieved through the first conductive layer ML1 to the eighth conductive layer ML8. The connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE can also be achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0116] A first insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 and connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating film INS1 and may connect to the first via VA1.

[0117] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and connect to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be disposed on the second insulating film INS2 and can connect to the second via VA2.

[0118] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can penetrate the third insulating film INS3 and connect to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be disposed on the third insulating film INS3 and can connect to the third via VA3.

[0119] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 and connect to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 and can connect to the fourth via VA4.

[0120] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 and connect to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 and can connect to the fifth via VA5.

[0121] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 and connect to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 and can connect to the sixth via VA6.

[0122] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 and connect to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 and can connect to the seventh via VA7.

[0123] An eighth insulating film INS8 can be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can penetrate the eighth insulating film INS8 and connect to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 can be disposed on the eighth insulating film INS8 and can connect to the eighth via VA8.

[0124] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising two or more of these. The first insulating films INS1 to INS8 can be made of substantially the same material. The first insulating films INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes are formed, but the disclosure is not limited to this.

[0125] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately 1360 Å. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 1440 Å. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately 1150 Å.

[0126] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately 6000 Å.

[0127] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes are formed, but the disclosure is not limited to this.

[0128] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising two or more of these. The thickness of the ninth via VA9 can be approximately 16500 Å.

[0129] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The EML may include a reflective electrode layer (RL), a tenth insulating film (INS10) and an eleventh insulating film (INS11), a tenth via (VA10), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), and a pixel defining film (PDL). In an embodiment, the light-emitting element (LE) may be composed of the first electrode (AND), the light-emitting stack (IL), and the second electrode (CAT).

[0130] A reflective electrode layer RL can be disposed on the ninth insulating film INS9. The reflective electrode layer RL may include at least one reflective electrode, such as RL1, RL2, RL3, and RL4. For example, as... Figure 7 As shown, the reflective electrode layer RL may include a first reflective electrode to a fourth reflective electrode RL1, RL2, RL3 and RL4.

[0131] Each of the first reflective electrodes RL1 can be disposed on the ninth insulating film INS9 and can be connected to the ninth via VA9. The first reflective electrodes RL1 can be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy comprising two or more of them. For example, the first reflective electrodes RL1 may comprise titanium nitride (TiN).

[0132] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy comprising two or more of them. For example, the second reflective electrode RL2 may comprise aluminum (Al).

[0133] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy comprising two or more of them. For example, the third reflective electrode RL3 may comprise titanium nitride (TiN).

[0134] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising two or more of these. For example, the fourth reflective electrode RL4 may comprise titanium (Ti).

[0135] Since the second reflective electrode RL2 is the electrode that primarily reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately 100 Å, and the thickness of the second reflective electrode RL2 can be approximately 850 Å.

[0136] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9. The tenth insulating film INS10 can be disposed between adjacent reflective electrode layers RL along the horizontal direction. The tenth insulating film INS10 can be made of silicon oxide (SiO2). x Inorganic membranes are formed, but the disclosure is not limited to this.

[0137] The eleventh insulating film INS11 can be disposed on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be made of silicon oxide (SiO2). x An inorganic film is formed, but the disclosure is not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 can be used as optical auxiliary layers, through which light reflected by the reflective electrode layer RL from the light emitted from the light-emitting element LE passes.

[0138] To match the resonant distance of the light emitted from the light-emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the eleventh insulating film INS11 may not be disposed below the first electrode AND. For example, the first electrode AND of the first sub-pixel SP1 may be disposed directly on the reflective electrode layer RL. The eleventh insulating film INS11 may be disposed below the first electrode AND of the second sub-pixel SP2. The tenth insulating film INS10 and the eleventh insulating film INS11 may be disposed below the first electrode AND of the third sub-pixel SP3.

[0139] In summary, the distance between the first electrode AND and the reflective electrode layer RL can vary among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. To adjust the distance from the reflective electrode layer RL to the first electrode AND based on the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh insulating film INS11 can be different in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. The disclosure is not limited to the above examples.

[0140] Each of the tenth vias VA10 can penetrate the eleventh insulating film INS11 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and can be connected to the exposed fourth reflective electrode RL4. The tenth via VA10 can be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising two or more of these. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3, but can be greater than the thickness of the tenth via VA10 in the first sub-pixel SP1.

[0141] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising two or more of these. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0142] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edges of the first electrode AND of each of the light-emitting elements (LEs). The PDL can be used to delineate a first emission region EA1, a second emission region EA2, and a third emission region EA3.

[0143] The first emission region EA1 can be defined as the region in which a first electrode AND, a light-emitting stack IL (e.g., IL1), and a second electrode CAT are sequentially stacked in a first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which a first electrode AND, a light-emitting stack IL (e.g., IL2), and a second electrode CAT are sequentially stacked in a second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which a first electrode AND, a light-emitting stack IL (e.g., IL3), and a second electrode CAT are sequentially stacked in a third sub-pixel SP3 to emit light.

[0144] The pixel-defining film (PDL) may include first pixel-defining films to third pixel-defining films PDL1, PDL2, and PDL3. The first pixel-defining film PDL1 may be disposed at the edge of the first electrode AND of each of the light-emitting elements (LEs). The second pixel-defining film PDL2 may be disposed on the first pixel-defining film PDL1, and the third pixel-defining film PDL3 may be disposed on the second pixel-defining film PDL2. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may be made of silicon oxide (SiO2). x The inorganic film is formed, but the disclosure is not limited thereto. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may each have a thickness of about 500 Å.

[0145] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 are formed as a single pixel defining film, the height of the single pixel defining film can be increased, making it possible for the first encapsulating inorganic film TFE1 to be cut due to step coverage. Step coverage can refer to the ratio of the degree to which the film is coated on the inclined portion to the degree to which the film is coated on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0146] Therefore, in order to reduce or prevent the first encapsulated inorganic film TFE1 from being cut due to step coverage, the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can have a cross-sectional structure with stepped portions. For example, the width of the first pixel-defining film PDL1 can be greater than the width of the second pixel-defining film PDL2 and the width of the third pixel-defining film PDL3, and the width of the second pixel-defining film PDL2 can be greater than the width of the third pixel-defining film PDL3. The width of the first pixel-defining film PDL1 can refer to the horizontal length of the first pixel-defining film PDL1 defined in the first direction DR1 and the second direction DR2.

[0147] The light-emitting stack IL can include multiple intermediate layers. The light-emitting stack IL can include a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, each emitting different light. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be disconnected between adjacent sub-pixels.

[0148] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting first light, and a first electron transport layer are sequentially stacked. The first stacked layer IL1 may be disposed on the first electrode AND and the pixel defining film PDL in the first emission region EA1 of the first sub-pixel SP1.

[0149] The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting second light, and a second electron transport layer are sequentially stacked. The second stacked layer IL2 may be disposed on the first electrode AND and the pixel defining film PDL in the second emission region EA2 of the second sub-pixel SP2.

[0150] The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting third light, and a third electron transport layer are sequentially stacked. The third stacked layer IL3 may be disposed on the first electrode AND and the pixel defining film PDL in the third emission region EA3 of the third sub-pixel SP3.

[0151] The second electrode CAT can be disposed on the light-emitting stack IL and the pixel-defining film PDL. The second electrode CAT can be formed of a transparent conductive material (TCO) that can transmit light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency in each of the first to third sub-pixels SP1, SP2, and SP3 can be improved due to the microcavity effect.

[0152] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film (such as TFE1 and TFE2) to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0153] The first encapsulating inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is selected. x ) membrane, silicon oxynitride (SiO) x N y ) film and silicon dioxide (SiO) x A multilayer of one or more inorganic films stacked alternately. The first encapsulating inorganic film TFE1 can be formed using a chemical vapor deposition (CVD) process.

[0154] The second encapsulating inorganic film TFE2 can be disposed on the first encapsulating inorganic film TFE1. The second encapsulating inorganic film TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO x The second encapsulation inorganic film TFE2 can be formed using atomic layer deposition (ALD) technology. The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0155] Organic film APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the cover layer CVL. Organic film APL can be formed from materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0156] The CVL (converterless glass layer) can be deposited on the organic membrane APL. The CVL can be formed from glass or polymer resin.

[0157] The polarizer POL can be disposed on the surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but the disclosure is not limited thereto.

[0158] Figure 8 This is a schematic perspective view showing a head-mounted display according to an embodiment. Figure 9 It is shown Figure 8 An exploded schematic perspective view of an example of a head-mounted display.

[0159] Reference Figure 8 and Figure 9The head-mounted display 1000 according to the embodiment may include a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0160] The first display device 10_1 can provide an image to the user's left eye, and the second display device 10_2 can provide an image to the user's right eye. Because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 and Figure 2 The display devices 10 described are basically the same, so the descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0161] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0162] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 can be used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0163] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert image sources received from the outside into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0164] The control circuit board 1600 can transmit digital video data DATA, optimized for the user's left eye and corresponding to the left-eye image, to the first display device 10_1, and can transmit digital video data DATA, optimized for the user's right eye and corresponding to the right-eye image, to the second display device 10_2. In another embodiment, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0165] The display device housing 1100 can be used to house a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 positioned for the user's left eye and a second eyepiece 1220 positioned for the user's right eye. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are shown to be configured separately, but the disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may also be combined into one.

[0166] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image from the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image from the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0167] The headband 1300 can be used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned above the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display 1000 can be configured as follows: Figure 10 The eyeglasses frame shown is not the headband 1300.

[0168] The head-mounted display 1000 may also include a battery for power supply, an external memory slot for accommodating external memory, an external connection port for receiving image sources, and a wireless communication module. The external connection port may include a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0169] Figure 10 This is a schematic perspective view showing a head-mounted display according to an embodiment.

[0170] Reference Figure 10According to an embodiment, the head-mounted display 1000_1 can be an eyeglass-type display device, wherein the display device housing 1200_1 is implemented in a lightweight and compact form. The head-mounted display 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path changing component 1070, and a display device housing 1200_1.

[0171] The display device housing 1200_1 can accommodate and protect the display device 10_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 10_3 with the real image seen through the right eye lens 1020.

[0172] Figure 10 The display device housing 1200_1 is shown positioned at the right end of the support frame 1030, but the disclosure is not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and the image displayed on the display device 10_3 may be provided to the user's left eye. In another embodiment, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, and the user may view the image displayed on the display device 10_3 through both the left and right eyes.

[0173] Figure 11 This is a schematic perspective view of a mask according to an embodiment. Figure 12 This is a schematic plan view of the mask according to an embodiment. Figure 11 A schematic perspective view of a cell mask UM, which is separate from multiple cell masks, is shown. Figure 11 and Figure 12 The mask MK shown can be used in deposition reference. Figure 7 The process of at least a portion of the described light-emitting stack IL. For example, the light-emitting stack IL can emit different colors in each of the sub-pixels SP1, SP2, and SP3.

[0174] Reference Figure 11 and Figure 12 According to an embodiment, the mask MK can be a shadow mask in which the mask film MM is disposed on the silicon substrate 1700. The mask MK can also be referred to as a "silicon mask".

[0175] According to an embodiment, the mask MK may include a silicon substrate 1700 (or "second substrate"), and a mask film MM may be disposed on the silicon substrate 1700. The mask film MM may be disposed in cell regions 1710 arranged in a matrix, and each cell region 1710 may be surrounded by a mask rip region 1721. The mask rip region 1721 may have a portion of the silicon substrate 1700 disposed therein, and may be used to support the mask film MM.

[0176] The mask film MM can form part of the cell mask UM set in each of the cell regions 1710.

[0177] The silicon substrate 1700 may include cell regions 1710 and mask frame regions 1720 excluding the cell regions 1710. The mask frame region 1720 may include mask edge regions 1721 surrounding each cell region 1710 and an outer frame region 1722 disposed at the outermost edge of the silicon substrate 1700. A mask frame MF may be disposed within the mask frame region 1720, and the mask frame MF may include mask edges surrounding the cell regions 1710.

[0178] The mask edge region 1721 can be divided into multiple unit regions 1710. For example, the unit regions 1710 can be arranged in a matrix, and the mask edges provided in the mask edge region 1721 can surround the outer edge of the mask film MM provided in each unit region 1710.

[0179] Cell openings (COPs) and cell masks (UMs) for masking at least a portion of the cell openings (COPs) can be disposed in each of the cell regions (1710) of the silicon substrate (1700).

[0180] Multiple cell openings (COPs) can penetrate the mask frame MF along the thickness direction of the mask MK (e.g., third-direction DR3). These cell openings (COPs) can be formed by etching a portion of the silicon substrate 1700 from the back side.

[0181] Each unit mask UM may include a mask membrane MM, and the mask membrane MM may include a mask opening.

[0182] The mask openings in the mask film MM can be referred to as "holes" or "mask holes". The mask openings can penetrate the unit mask UM along the thickness direction of the mask MK (e.g., third-direction DR3).

[0183] A cell mask UM can be used in the deposition process of display panel 100. In the disclosure, the term "cell mask UM" may also be referred to as "mask cell" UM.

[0184] Figures 13 to 15This is a schematic cross-sectional view illustrating a method for manufacturing a mask according to an embodiment. For example, Figure 15 It could be a schematic cross-sectional view of a portion of the mask MK being cut off. Figures 13 to 15 The process of manufacturing the mask MK can be shown sequentially.

[0185] In the following text, reference will be made to Figures 13 to 15 This describes a method for manufacturing a mask MK according to an embodiment.

[0186] Reference Figure 13 It can provide a substrate 1800 (e.g., Figure 12 (1700 in the example). The substrate 1800 may contain silicon (Si). The substrate 1800 may also be referred to as a "host substrate" or a "film substrate", but is not limited thereto.

[0187] When a substrate 1800 is provided, inorganic films 1910 and 1920 can be deposited on the substrate 1800. Inorganic films 1910 and 1920 can be deposited across the entire surface of the substrate 1800. For example, inorganic films 1910 and 1920 can be deposited on the front, side, and rear surfaces of the substrate 1800.

[0188] According to embodiments, inorganic membranes 1910 and 1920 may comprise a single membrane. For example, the inorganic membrane may comprise a first inorganic membrane 1910, and the first inorganic membrane 1910 may contain materials selected from silicon (Si) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following materials.

[0189] According to an embodiment, inorganic films 1910 and 1920 may include multiple films. For example, the inorganic films may include a first inorganic film 1910 and a second inorganic film 1920 disposed on the first inorganic film 1910. The first inorganic film 1910 may contain silicon oxide (SiO2). x The second inorganic film 1920 may contain silicon nitride (SiN). x However, the material of each of the first inorganic film 1910 and the second inorganic film 1920 is not limited thereto. For example, each of the first inorganic film 1910 and the second inorganic film 1920 may contain silicon (Si), silicon nitride (SiN) selected from silicon (Si), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following materials.

[0190] In the following, an embodiment in which a first inorganic membrane 1910 and a second inorganic membrane 1920 are deposited on a substrate 1800 will be described.

[0191] Reference Figure 14 The second inorganic membrane 1920 is patterned to form a second inorganic membrane pattern 1921 including multiple openings OP1 (see Figure 15 For example, as referenced Figure 12 As described, multiple unit regions 1710 are defined in the substrate 1800 (see...) Figure 12 The portions of the second inorganic film 1920 corresponding to the plurality of unit regions 1710 of the substrate 1800 are patterned, resulting in the formation of a plurality of second inorganic film patterns 1921. The second inorganic film patterns 1921 can become part of the mask film MM after the mask manufacturing process is completed.

[0192] The process of patterning the second inorganic film 1920 may include the following steps as part of a dry etching process for the second inorganic film 1920. A photoresist pattern may be formed on the second inorganic film 1920. Subsequently, the portion of the second inorganic film 1920 located in the cell region 1710 may be etched using the photoresist pattern as a mask. Thus, the second inorganic film 1920 superimposed with the photoresist pattern may be retained and become the second inorganic film pattern 1921, while the etched portion using the photoresist pattern as a mask may become the opening OP1 of the mask film MM.

[0193] Reference Figure 15 The second inorganic film 1920, the substrate 1800, and the first inorganic film 1910 are etched from the underside of the substrate 1800 to form a cell opening COP, exposing the second inorganic film pattern 1921. The process of forming the cell opening COP may include etching the silicon (Si)-containing substrate 1800 and the silicon oxide (SiO)-containing substrate 1800. x The first inorganic film 1910 was patterned using a wet etching process.

[0194] Figure 16 This is a schematic concept drawing illustrating the shadow defects that occur during a deposition process using a mask.

[0195] Reference Figure 16 During the deposition process using the mask MK, the deposition source DS can be prepared as a surface facing the mask MK (e.g., the lower surface of the mask MK), while the deposition substrate 2420 (e.g., a first substrate or...) is deposited. Figures 1 to 10The display panel 100 shown is aligned to face the other surface of the mask MK (e.g., the upper surface of the mask MK).

[0196] When the deposition substrate 2420 and the mask MK are aligned, the deposition material contained in the deposition source DS evaporates, and the evaporated deposition material passes through the cell openings COP of the mask MK and is deposited onto the deposition substrate 2420. At this time, the deposition incident angle K1 of each cell opening COP from the deposition source DS to the mask MK can vary. For example, the deposition incident angle K1 can be larger towards the center of the mask MK and smaller towards the outer edge of the mask MK.

[0197] Cell openings COP located on the outer edge of mask MK can have relatively small deposition incident angles K1, which increases the shadow area due to the mask edge region 1721. For example, in cell regions located near the outer edge of mask MK (such as...) Figure 16 In region 2001, shading defects or color mixing defects may increase.

[0198] Figures 17 to 18 It is a schematic construction diagram based on the mask of the comparative example. For example, Figure 17 A schematic plan view and a schematic cross-sectional view of the cell pattern 2100 set in the cell opening COP of the mask MK according to the comparative example are shown. Figure 18 It shows the setting Figure 17 A schematic cross-sectional view of the mask MK of the cell pattern 2100 in the cell opening COP shown.

[0199] Reference Figure 17 and Figure 18 According to the comparative example, the mask MK includes a unit pattern 2100 disposed in each of the unit openings COP and formed by an inorganic film. The inorganic film forming the unit pattern 2100 may correspond to the reference. Figures 13 to 15 The inorganic membranes described in 1910 and 1920.

[0200] Unit pattern 2100 includes mask film pattern (or film pattern) 2110 and dummy pattern 2120. Mask film pattern 2110 includes multiple openings OP1 (see...). Figure 15 A dummy pattern 2120 surrounds a mask pattern 2110. The mask pattern 2110 may include a reference. Figures 13 to 15 The mask MM is described. A dummy pattern 2120 is disposed on the outer edge of the mask pattern 2110. For example, the dummy pattern 2120 is disposed at the boundary of the cell opening COP and adjacent to the mask edge region 1721 of the mask MK. The dummy pattern 2120 can be used to relieve stress or tension applied to the mask pattern 2110.

[0201] In the mask MK according to the comparative example, when viewed in a plan view, the width of the dummy pattern 2120 surrounding the mask film pattern 2110 is uniform. For example, when viewed in a plan view, the dummy pattern 2120 is uniformly positioned along each of the following directions of the mask film pattern 2110: a first side direction (e.g., left direction), a second side direction opposite to the first side direction (e.g., right direction), a third side direction perpendicular to the first side direction (e.g., up direction), and a fourth side direction opposite to the third side direction (e.g., down direction).

[0202] According to the comparative example, the mask MK includes multiple cell openings (COPs), and the width of the dummy pattern 2120 set in each of the cell openings (COPs) is all the same. For example, as Figure 18 As shown, the mask MK includes a first unit opening COP1 and a second unit opening COP2 adjacent to the first unit opening COP1. The first unit opening COP1 is located at the center of the mask MK (e.g., Figure 15 The second unit opening COP2 is spaced apart from the center portion of the base 1800 in the mask MK by a first distance. The second unit opening COP2 is separated from the center portion of the mask MK by, for example, Figure 15 The central portion of the base 1800 is separated by a second distance, which is smaller than the first distance.

[0203] According to the comparative example, a dummy pattern 2120 is disposed around the outer edge of the mask pattern 2110 in the first unit opening COP1, and the dummy pattern 2120 includes a first dummy pattern 2121 (e.g., Dummy1) disposed on one side (e.g., the left side) of the mask pattern 2110 and a second dummy pattern 2122 (e.g., Dummy2) disposed on the opposite side (e.g., the right side) of the mask pattern 2110.

[0204] According to the comparative example, the width of the first dummy pattern 2121 and the width of the second dummy pattern 2122 in the first unit opening COP1 are the same.

[0205] Similarly, in the second unit opening COP2, the dummy pattern 2120 is configured to surround the outer edge of the mask pattern 2110, and the dummy pattern 2120 includes a third dummy pattern 2123 (e.g., Dummy3) disposed on one side of the mask pattern 2110 and a fourth dummy pattern 2124 (e.g., Dummy4) disposed on the opposite side of the mask pattern 2110.

[0206] In the comparative example, the widths of the third dummy pattern 2123 and the fourth dummy pattern 2124 in the second unit opening COP2 are also the same.

[0207] Based on the comparative example, from the sedimentary source DS (see...) Figure 16The deposition incident angle 2202 from the deposition source DS to the first unit opening COP1 is smaller than the deposition incident angle 2201 from the deposition source DS to the second unit opening COP2. The deposition incident angles 2202 and 2201 relative to the first unit opening COP1 and the second unit opening COP2 are different from each other. Therefore, the shadow area generated in the first unit opening COP1 is larger than the shadow area generated in the second unit opening COP2. According to the comparative example, although the deposition incident angles 2202 and 2201 relative to the first unit opening COP1 and the second unit opening COP2 are different from each other, the width of each of the dummy patterns 2121 and 2122 set in the first unit opening COP1 and the width of each of the dummy patterns 2123 and 2124 set in the second unit opening COP2 are the same. In such a comparative example, due to the uniform width of the dummy pattern 2120, shadow defects or color mixing defects may increase towards the outer edge of the mask MK.

[0208] In the following, a mask MK according to an embodiment for reducing shading defects or color mixing defects of a mask MK will be described compared with a mask MK of a comparative example.

[0209] Figures 19 to 20 This is a schematic construction diagram of a mask according to an embodiment. For example, Figure 19 A schematic plan view and a schematic cross-sectional view of a cell pattern 2100 disposed in a cell opening COP of a mask MK according to an embodiment are shown. Figure 20 It shows the setting Figure 19 A schematic cross-sectional view of the element pattern 2100 in the element opening COP shown.

[0210] According to an embodiment, the mask MK may include a cell pattern 2100 disposed in each of a plurality of cell openings COP and formed of an inorganic film. The inorganic film forming the cell pattern 2100 may correspond to a reference. Figures 13 to 15 The inorganic membranes described are 1910 and 1920. For example, the inorganic membrane may contain materials selected from silicon (Si) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following materials.

[0211] Unit pattern 2100 may include mask pattern 2110 and dummy pattern 2120, wherein mask pattern 2110 includes a plurality of openings OP1 (see Figure 15A dummy pattern 2120 surrounds a mask pattern 2110. The mask pattern 2110 may include a reference. Figures 13 to 15 The mask MM is described. A dummy pattern 2120 may be disposed on the outer edge of the mask pattern 2110. For example, the dummy pattern 2120 may be disposed at the boundary of the cell opening COP and adjacent to the mask edge region 1721 of the mask MK. Such a dummy pattern 2120 may be used to relieve stress or tension applied to the mask pattern 2110.

[0212] In the mask MK according to the embodiment, in a plan view, the width of the dummy pattern 2120 surrounding the mask film pattern 2110 may be non-uniform (or irregular). For example, when viewed in a plan view, the dummy pattern 2120 may be disposed on each of the following directions of the mask film pattern 2110: a first lateral direction (e.g., left direction), a second lateral direction opposite to the first lateral direction (e.g., right direction), a third lateral direction perpendicular to the first lateral direction (e.g., up direction), and a fourth lateral direction opposite to the third lateral direction (e.g., down direction), and its width is non-uniform (or irregular).

[0213] According to an embodiment, multiple cell openings COP may include a substrate 1800 (see embodiment 1800). Figure 15 The central portion of the first unit pattern 2100a includes at least one first-type unit opening COPa and a plurality of second-type unit openings COPb, including a second unit pattern 2100b, disposed around the periphery of the first-type unit opening COPa. The width of the dummy pattern 2120 included in the first unit pattern 2100a is uniform, while the width of the dummy pattern 2120 included in the second unit pattern 2100b is non-uniform (or irregular). For example, in Figure 19 In the figure, reference numeral 2301 shows the alignment of the dummy pattern 2120 in the comparative example, and such dummy pattern 2120 can be designed to be offset toward the center portion of the substrate 1800 (i.e., the center portion of the mask MK) as shown by arrow 2302.

[0214] The first type of cell opening COPa may include a dummy pattern 2120 with a uniform width because the first type of cell opening COPa is located near the center portion of the substrate 1800. Since the first type of cell opening COPa is close to the center portion of the substrate 1800, the deposition incident angle is approximately 90 degrees, and therefore, no shading defects occur. Therefore, even when the first type of cell opening COPa includes a dummy pattern 2120 with a uniform width, the possibility of shading defects is low. According to an embodiment, the first cell pattern 2100a of the first type of cell opening COPa may include a first dummy pattern 2121 with a first width disposed on one side of the mask pattern 2110 and a second dummy pattern 2122 with a first width disposed on the opposite side of the mask pattern 2110.

[0215] On the other hand, the second type of cell opening COPb may include dummy patterns 2121 and 2122 with uneven (or irregular) widths because the second type of cell opening COPb is far from the center portion of the substrate 1800, and the deposition incident angle is less than 90 degrees. Therefore, since the second type of cell opening COPb has a higher probability of shading defects, the width of each of the dummy patterns 2121 and 2122 is adjusted to be uneven (or irregular). According to an embodiment, the second type of cell opening COPb may include a first dummy pattern 2121 with a first width disposed on one side of the mask film pattern 2110 and a second dummy pattern 2122 with a second width disposed on the other side of the mask film pattern 2110, the second width being smaller than the first width. The second dummy pattern 2122 may be configured to be farther from the center portion of the substrate 1800 than the first dummy pattern 2121.

[0216] Reference Figure 20 Multiple second-type unit openings COPb may include a first unit opening COP1 and a second unit opening COP2.

[0217] The first unit opening COP1 may include a first dummy pattern 2121 and a second dummy pattern 2122. The first unit opening COP1 and the substrate 1800 (see...) Figure 15 The central part of the ) is separated by the first distance.

[0218] The second unit opening COP2 may include a third dummy pattern 2123 and a fourth dummy pattern 2124, and the second unit opening COP2 is connected to the substrate 1800 (see...). Figure 15 The central portions of the first distance are separated by a second distance, which is smaller than the first distance.

[0219] According to an embodiment, each of the first to fourth dummy patterns 2121, 2122, 2123, and 2124 has a different width. For example, the first dummy pattern 2121 has a first width, the second dummy pattern 2122 has a second width greater than the first width, the third dummy pattern 2123 has a third width, and the fourth dummy pattern 2124 has a fourth width greater than the third width. The first width and the third width are different, and the second width and the fourth width are also different from each other.

[0220] Because of the design requirements of different deposition incident angles 2201 and 2202 for the first unit opening COP1 and the second unit opening COP2, the widths of each of the dummy patterns (i.e., the first dummy pattern 2121 and the second dummy pattern 2122) provided in the first unit opening COP1 and the dummy patterns (i.e., the third dummy pattern 2123 and the fourth dummy pattern 2124) provided in the second unit opening COP2 are different. In the mask MK according to the embodiment, by allowing the dummy patterns provided in the first unit opening COP1 and the dummy patterns provided in the second unit opening COP2 to have different widths, shading defects can be reduced.

[0221] Figure 21 This is a schematic structural diagram showing a deposition apparatus (or deposition device) according to an embodiment.

[0222] Reference Figure 21 The deposition apparatus (or deposition device) according to the embodiment may include a chamber 2410, a deposition source DS disposed inside the chamber 2410, a mask MK disposed inside the chamber 2410 between a first substrate 2420 and the deposition source DS, and a mask support 2440 disposed between the deposition source DS and the mask MK to support at least a portion of the mask MK.

[0223] According to an embodiment, the mask MK may include a second substrate 1700 (see embodiment MK). Figure 12 The second substrate 1700 includes multiple unit regions 1710 (see ) and mask film MM. Figure 12 ) and mask frame region 1720 other than unit region 1710 (see Figure 12 The mask MM is set in each cell region 1710.

[0224] Figure 21 The first substrate 2420 shown can correspond to the reference. Figures 1 to 10 The described display panel 100. Therefore, using reference... Figures 1 to 10 The description of the display panel 100 replaces the description of the first substrate 2420.

[0225] Figure 21The mask MK shown can represent a second substrate and can include a reference. Figures 12 to 20 The silicon substrate described is 1700 or 1800. (Refer to...) Figures 12 to 20 The description of silicon substrate 1700 or substrate 1800 replaces the description of the second substrate.

[0226] The mask support 2440 can be used to support and secure the mask MK. For example, the mask support 2440 may include an electrostatic chuck. According to an embodiment, the mask support 2440 may include a first support region 2441 supporting the mask edge region 1721 and a second support region 2442 supporting the outer frame region 1722. In another embodiment, the first support region 2441 may be omitted from the mask support 2440, and the mask edge region 1721 may not be supported.

[0227] Figure 21 The reference numeral 2430 shown in the figures may indicate a fixing member 2430 for fixing the first base 2420. The fixing member 2430 may include, for example, an electrostatic chuck.

[0228] Embodiments have been disclosed herein, and although terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with the embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the disclosure set forth in the claims.

Claims

1. A deposition mask, the deposition mask comprising: Base; as well as The unit pattern, disposed in each of the plurality of unit openings in the substrate, is formed of an inorganic film. The unit pattern includes: a mask pattern having multiple openings; and a dummy pattern surrounding the mask pattern, wherein the width of the dummy pattern is irregular.

2. The deposition mask according to claim 1, wherein, The plurality of unit openings includes: at least one first-type unit opening adjacent to the central portion of the substrate, comprising a first unit pattern; and a plurality of second-type unit openings disposed around the periphery of the first-type unit opening, comprising a second unit pattern, and The width of the dummy pattern included in the first unit pattern is uniform, while the width of the dummy pattern included in the second unit pattern is irregular.

3. The deposition mask according to claim 2, wherein, The first unit pattern includes: a first dummy pattern disposed on one side of the mask film pattern and having a first width; and a second dummy pattern disposed on the other side of the mask film pattern and having the first width.

4. The deposition mask according to claim 2, wherein, The second unit pattern includes: a first dummy pattern disposed on one side of the mask film pattern and having a first width; and a second dummy pattern disposed on the other side of the mask film pattern and having a second width, the second width being greater than the first width, and The second dummy pattern is closer to the center portion of the substrate than the first dummy pattern.

5. The deposition mask according to claim 2, wherein, The plurality of second-type unit openings include: a first unit opening including a first dummy pattern and a second dummy pattern, spaced apart from the central portion of the substrate by a first distance; and a second unit opening including a third dummy pattern and a fourth dummy pattern, spaced apart from the central portion of the substrate by a second distance, the second distance being smaller than the first distance, and The widths of each of the first dummy pattern, the second dummy pattern, the third dummy pattern, and the fourth dummy pattern are different from each other.

6. The deposition mask according to claim 5, wherein, The first dummy pattern has a first width. The second dummy pattern has a second width, which is greater than the first width. The third dummy pattern has a third width, and The fourth dummy pattern has a fourth width, which is greater than the third width.

7. The deposition mask according to claim 6, wherein, The first width is different from the third width, and the second width is different from the fourth width.

8. The deposition mask according to claim 1, wherein, The inorganic membrane comprises: The first inorganic film comprises silicon oxide; and A second inorganic membrane, disposed on the first inorganic membrane, comprises silicon nitride.

9. The deposition mask according to claim 1, wherein, The inorganic film includes at least one of silicon, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, amorphous silicon, and aluminum oxide.

10. The deposition mask according to claim 1, wherein, The substrate includes silicon.

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