Deposition mask

Abstract

A deposition mask includes: a mask substrate including a central region and an edge region; a plurality of cell patterns disposed on the mask substrate and including a cell pattern disposed in the edge region and a cell pattern disposed in the central region; and a mask frame disposed on the mask substrate and surrounding the plurality of unit patterns, the number of unit patterns per unit area of the edge region among the unit patterns provided in the edge region is greater than the number of unit patterns per unit area of the center region among the unit patterns provided in the center region.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0037522 filed on March 19, 2024, as well as all the benefits accruing therefrom, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The present disclosure relates to a deposition mask. BACKGROUND

[0004] A wearable device in the form of glasses or a helmet is being developed, and focusing is formed at a position close to a user's eyes. For example, the wearable device can be a head-mounted display ("HMD") device or augmented reality ("AR") glasses. Such a wearable device provides a user with an AR picture or a virtual reality ("VR") picture.

[0005] In a wearable device such as an HMD device and AR glasses, a display specification of at least 2000 pixels per inch (PPI) is required to allow a user to use it for a long time without dizziness. For this purpose, silicon on organic light emitting diode ("OLEDoS") technology, which is a technology for a high-resolution small organic light emitting element display device, is emerging. OLEDoS is a technology for disposing an organic light emitting diode ("OLED") on a semiconductor wafer substrate on which a complementary metal oxide semiconductor ("CMOS") is disposed. SUMMARY

[0006] The features of the present disclosure provide a silicon deposition mask that can manufacture a high-resolution display panel.

[0007] The features of the present disclosure provide a deposition mask that improves the adhesion between a high-resolution display panel and a deposition mask by solving the problem of warping of a mask inorganic layer included in a mask frame.

[0008] It should be noted that the features of the present disclosure are not limited to the above-mentioned features, and other features of the present disclosure will be apparent to those skilled in the art from the following description.

[0009] The details of embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description.

[0010] In an embodiment of the disclosure, a deposition mask includes: a mask substrate including a center region and an edge region; a plurality of unit patterns disposed on the mask substrate and including unit patterns disposed in the edge region and unit patterns disposed in the center region; and a mask frame disposed on the mask substrate and surrounding the plurality of unit patterns, wherein a number of unit patterns per unit area of each of the edge regions among the unit patterns disposed in the edge region is greater than a number of unit patterns per unit area of each of the center regions among the unit patterns disposed in the center region.

[0011] In an embodiment, the unit patterns in the edge region can be spaced apart from each other at a first distance, and the unit patterns in the center region are spaced apart from each other at a second distance, wherein the first distance is different from the second distance.

[0012] In an embodiment, the second distance can be greater than the first distance.

[0013] In an embodiment, the mask substrate can further include an intermediate region disposed between the edge region and the center region, wherein the plurality of unit patterns further includes unit patterns disposed in the intermediate region, the unit patterns in the intermediate region are spaced apart from each other at a third distance, and the first distance, the second distance, and the third distance are different from each other.

[0014] In an embodiment, the third distance can be less than the second distance.

[0015] In an embodiment, the third distance can be greater than the first distance.

[0016] In an embodiment, the first distance can be equal to the third distance.

[0017] In an embodiment, the center region can include a center point of the mask substrate, and wherein the edge region includes an edge of the mask substrate.

[0018] In an embodiment, a shape of the center region can be defined as a circular shape having a first radius from the center point of the mask substrate, and the first radius is in a range of 10% to 40% of a radius of the mask substrate.

[0019] In an embodiment, the mask substrate can be a silicon substrate, and the mask substrate has a circular shape in a plan view.

[0020] In an embodiment, the unit patterns can be spaced apart from each other at a random distance on the mask substrate.

[0021] In an embodiment, the mask frame can include a mask inorganic layer disposed on the mask base, and the mask inorganic layer can include an inorganic insulating material.

[0022] In an embodiment, a pixel opening can be defined in a unit pattern of the plurality of unit patterns, and the unit pattern can include a mask shield surrounding the pixel opening.

[0023] In an embodiment, the mask shield can include the same material as that of the mask inorganic layer.

[0024] In an embodiment, the pixel opening can be a via hole, and an ultra-high resolution pixel can be formed through the pixel opening.

[0025] In an embodiment, the mask shield can completely surround the pixel opening in a plan view, and the mask frame can surround all of the mask shield in a plan view.

[0026] In an embodiment of the disclosure, a deposition mask includes a mask base including a center region, an edge region, and an intermediate region disposed between the center region and the edge region, a plurality of unit patterns disposed on the mask base, and a mask frame disposed on the mask base and surrounding the plurality of unit patterns, wherein the plurality of unit patterns do not overlap the center region, and the plurality of unit patterns are disposed in the edge region and the intermediate region.

[0027] In an embodiment, the unit patterns in the edge region can be spaced apart from each other at a first distance, and the unit patterns in the intermediate region are spaced apart from each other at a second distance, wherein the first distance is different from the second distance.

[0028] In an embodiment, the unit patterns disposed in the edge region and the intermediate region can all be spaced apart from each other at a first distance.

[0029] In an embodiment, the unit patterns can be spaced apart from each other at random distances.

[0030] In an embodiment of the disclosure, unit patterns are arranged more in an edge region of a mask base of a deposition mask than in a center region of the mask base, thereby preventing warping of a mask inorganic layer included in a mask frame. Accordingly, the deposition mask in an embodiment of the disclosure can enhance adhesion between a high resolution display panel and the deposition mask.

[0031] It should be noted that the effects of the disclosure are not limited to the effects described above, and other effects of the disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0032] The above and other advantages and features of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings.

[0033] Figure 1 is a perspective view illustrating an embodiment of a head-mounted electronic device according to the present disclosure.

[0034] Figure 2 is an exploded perspective view illustrating an embodiment of a head-mounted electronic device of Figure 1 .

[0035] Figure 3 is a perspective view illustrating an embodiment of a head-mounted electronic device according to the present disclosure.

[0036] Figure 4 is an exploded perspective view illustrating an embodiment of a display device according to the present disclosure.

[0037] Figure 5 is a cross-sectional view illustrating an embodiment of a portion of a display panel according to the present disclosure.

[0038] Figure 6 is a plan view of an embodiment of a mask according to the present disclosure.

[0039] Figure 7 is an enlarged plan view of area A of Figure 6 .

[0040] Figure 8 is a cross-sectional view taken along line X1-X1' of Figure 7 .

[0041] Figure 9 is a plan view illustrating an embodiment of a layout of areas included in a mask substrate according to the present disclosure.

[0042] Figure 10 is a plan view illustrating a plurality of unit patterns arranged on a mask substrate of Figure 9 .

[0043] Figures 11 to 13 is a plan view illustrating a plurality of unit patterns arranged on a mask substrate of Figure 9 according to different embodiments. DETAILED DESCRIPTION

[0044] Embodiments of the present disclosure will now be described below more fully with reference to the accompanying drawings in which various embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

[0045] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element or intervening elements can be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0046] It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "a first component," "a first region," "a first layer," or "a first section" discussed below could be termed a second element, a second component, a second region, a second layer, or a second section without departing from the teachings herein.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Thus, for example, reference to "a component" includes a plurality of components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0048] Furthermore, spatially relative terms, such as "lower" or "bottom" and "upper" or "top", can be used herein for ease of description to describe one element's or portion's relationship to another element(s) or portion(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The term "lower" can thereby encompass both an orientation of lower and upper. Likewise, the term "above" or "above" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0049] "about" or "approximately" as used herein include the recited value and mean within an acceptable range of deviation for the specified value as determined by one of ordinary skill in the art. For example, a term such as "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, or ± 5% of the recited value.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected by one of ordinary skill in the art. Thus, embodiments described herein are not to be construed as limited to the precise shapes as illustrated but are to include deviations in shapes that result from manufacturing. For example, a region illustrated or described as flat can often have rough and / or nonlinear features. Moreover, the illustrated corners can typically be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

[0052] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0053] Figure 1is a perspective view illustrating an embodiment of a head-mounted electronic device according to the disclosure. Figure 2 is an exploded perspective view illustrating an embodiment of a head-mounted electronic device of Figure 1 .

[0054] Referring to Figure 1 and Figure 2 , the head-mounted electronic device 1 in the embodiment includes a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a headband harness 140, a first display device 10_1, a second display device 10_2, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170, and a connector.

[0055] The first display device 10_1 provides an image to the left eye of a user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described with reference to Figure 4 and Figure 5 . Accordingly, the description of the first display device 10_1 and the second display device 10_2 will be replaced with the description of the display device 10 with reference to Figure 4 and Figure 5 .

[0056] The first optical member 151 can be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 can be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 can include at least one convex lens.

[0057] The intermediate frame 160 can be disposed between the first display device 10_1 and the control circuit board 170, and can be disposed between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 serves to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0058] The control circuit board 170 can be disposed between the intermediate frame 160 and the display device housing 110. The control circuit board 170 can be connected to the first display device 10_1 and the second display device 10_2 through the connector. The control circuit board 170 can convert an image source input from the outside into digital video data, and can transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0059] The control circuit board 170 can transmit digital video data associated with a left-eye image optimized for the left eye of the user to the first display device 10_1 and can transmit digital video data associated with a right-eye image optimized for the right eye of the user to the second display device 10_2. In an alternative embodiment, the control circuit board 170 can transmit the same digital video data to the first display device 10_1 and the second display device 10_2.

[0060] The display device housing 110 accommodates the first display device 10_1, the second display device 10_2, the intermediate frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 is provided to cover an open face of the display device housing (also referred to as a housing) 110. The housing cover 120 can include a first eyepiece 131 on which the left eye of the user is placed and a second eyepiece 132 on which the right eye of the user is placed. Although the first eyepiece 131 and the second eyepiece 132 are separately provided in the example shown in FIGS. 1A and 1B, the present disclosure is not limited thereto. The first eyepiece 131 and the second eyepiece 132 can be combined into a single element. Figure 1 and Figure 2 In the example shown in FIGS. 1A and 1B, the first eyepiece 131 and the second eyepiece 132 are separately provided, but the present disclosure is not limited thereto. The first eyepiece 131 and the second eyepiece 132 can be combined into a single element.

[0061] The first eyepiece 131 can be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 can be aligned with the second display device 10_2 and the second optical member 152. Accordingly, the user can see a virtual image of an image in the first display device 10_1 amplified by the first optical member 151 through the first eyepiece 131, and a virtual image of an image in the second display device 10_2 amplified by the second optical member 152 through the second eyepiece 132.

[0062] The headband 140 fixes the housing 110 to the head of the user so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 overlap the left eye and the right eye of the user, respectively. By implementing a relatively light and small display device housing 110, the head-mounted electronic device 1 can include a spectacle frame as shown in FIG. 2B instead of the headband 140. Figure 3

[0063] In addition, the head-mounted electronic device 1 can further include a battery for supplying power, an external memory slot for inserting an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port can be a universal serial bus (“USB”) terminal, a display port, or a high-definition multimedia interface (“HDMI”) terminal. The wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0064] Figure 3 ​​is a perspective view illustrating an embodiment of a head-mounted electronic device according to the disclosure.

[0065] Referring to Figure 3 , the head-mounted electronic device 1_1 in the embodiment can be a glasses-type display device having a relatively light and small display device housing 120_1. The head-mounted electronic device 1_1 in the embodiment can include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, temple arms 341 and 342, an optical member 320, an optical path conversion member 330, and the display device housing 120_1.

[0066] Figure 3 The display device 10_3 shown in FIG. 1A is substantially the same as the display device 10 described with reference to Figure 4 and Figure 5 . Therefore, the description with reference to Figure 4 and Figure 5 will be substituted for the description of the display device 10_3.

[0067] The display device housing 120_1 can include the display device 10_3, the optical member 320, and the optical path conversion member 330. An image displayed in the display device 10_3 can be magnified by the optical member 320, and the optical path of the image is converted by the optical path conversion member 330 to be provided to the right eye of the user through the right eye lens 312. Accordingly, the user can see an augmented reality image with the right eye, which combines a virtual image displayed in the display device 10_3 and a real world image observed through the right eye lens 312.

[0068] Although in the example shown in Figure 3 , the display device housing 120_1 is disposed at the right end of the support frame 350, the disclosure is not limited thereto. In an embodiment, for example, the display device housing 120_1 can be disposed at the left end of the support frame 350. In this case, an image displayed in the display device 10_3 can be provided to the left eye of the user. In an alternative embodiment, the display device housing 120_1 can be disposed at both the left and right ends of the support frame 350, respectively. In this case, the user can view an image displayed in the display device 10_3 through both the left and right eyes.

[0069] Figure 4 is an exploded perspective view illustrating an embodiment of a display device according to the disclosure.

[0070] Referring to Figure 4The display device 10 in the embodiments displays moving or still images. The display device 10 in the embodiments can be employed by portable electronic devices such as mobile phones, smartphones, tablet PCs (“PCs”), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (“PMPs”), navigation devices, and ultra-mobile PCs (“UMPCs”). For example, in embodiments, the display device 10 can be used as a display unit for a television, laptop computer, monitor, electronic billboard, or Internet of Things (“IoT”) device. In alternative embodiments, the display device 10 can be applied to a smartwatch, a watch phone, or a head-mounted display (“HMD”) for realizing virtual and augmented reality.

[0071] According to an embodiment, the display device 10 includes a display panel 410, a heat dissipation layer 420, a circuit board 430, a driver circuit 440, and a power supply circuit 450.

[0072] The display panel 410 may have a shape similar to a quadrilateral shape (e.g., a rectangle) in a plan view. In an embodiment, the display panel 410 may have a shape similar to a rectangle having a shorter side in a first direction (X-axis direction) and a longer side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). In the display panel 410, for example, each of the angles where the shorter side in the first direction (X-axis direction) meets the longer side in the second direction (Y-axis direction) may be rounded with a predetermined curvature or may be a right angle. The shape of the display panel 410 in a plan view is not limited to a quadrilateral shape (e.g., a rectangle), but may be formed in a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. In a plan view, the shape of the display device 10 may follow the shape of the display panel 410, but this disclosure is not limited thereto.

[0073] The display panel 410 includes a display area for displaying images and a non-display area for not displaying images.

[0074] The display area comprises multiple pixels, and each of these pixels includes multiple sub-pixels SP1, SP2, and SP3 (see reference). Figure 5 Subpixels SP1, SP2, and SP3 comprise multiple pixel transistors. These pixel transistors are formed via semiconductor processes and can be disposed on a semiconductor substrate SSUB (see reference). Figure 5 In an embodiment, for example, the pixel transistor may be implemented as a complementary metal-oxide-semiconductor (“CMOS”) transistor.

[0075] The heat dissipation layer 420 can overlap the display panel 410 in a third direction (Z-axis direction) that is a thickness direction of the display panel 410. The heat dissipation layer 420 can be disposed on one surface of the display panel 410 (e.g., on a rear surface of the display panel 410). The heat dissipation layer 420 functions to release heat generated in the display panel 410. The heat dissipation layer 420 can include a metal layer (such as graphite, silver (Ag), copper (Cu), and aluminum (Al)) having a relatively high thermal conductivity.

[0076] The circuit board 430 can be electrically connected to the plurality of pads in the pad area of the display panel 410 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 can be a flexible printed circuit board including or consisting of a flexible material or a flexible film. Although the circuit board 430 is unfolded in Figure 4 The circuit board 430 can be bent. When the circuit board 430 is bent, one end of the circuit board 430 can be disposed on the rear surface of the display panel 410. The one end of the circuit board 430 can be opposite to the opposite end of the circuit board 430 that is connected to the pads in the pad area of the display panel 410 using the conductive adhesive member.

[0077] The driver circuit 440 can receive digital video data and a timing signal from the outside. The driver circuit 440 can generate a scan timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 in response to the timing signal.

[0078] The power supply circuit 450 can generate a plurality of panel driving voltages in response to a supply voltage from the outside.

[0079] Each of the driver circuit 440 and the power supply circuit 450 can be implemented as an integrated circuit ("IC") and attached to a surface of the circuit board 430.

[0080] Figure 5 is a cross-sectional view illustrating an embodiment of a portion of a display panel according to the present disclosure. For example, Figure 5 a cross-sectional structure of a portion of a display area including a plurality of sub-pixels is illustrated.

[0081] Referring to Figure 5 , the display panel 410 includes a semiconductor backplane (or semiconductor backsheet) SBP, an emission material backplane (or emission material backsheet) EBP, an emission material layer EML, a packaging layer TFE, an optical layer OPL, and a cover layer CVL.

[0082] The semiconductor substrate SBP includes a semiconductor substrate SSUB containing multiple pixel transistors PTR, multiple semiconductor insulating films covering the multiple pixel transistors PTR, and multiple contact terminals CTE electrically connected to the multiple pixel transistors PTR respectively.

[0083] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a type I impurity. Multiple well regions WA can be disposed on the upper surface of the semiconductor substrate SSUB. The well regions WA can be doped with a type II impurity. The type II impurity can be different from the type I impurity. In an embodiment, for example, when the type I impurity is a p-type impurity, the type II impurity can be an n-type impurity. In an alternative embodiment, when the type I impurity is an n-type impurity, the type II impurity can be a p-type impurity.

[0084] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate (such as polyimide). In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0085] Each of the well regions WA includes a source region SA associated with the source electrode of the pixel transistor PTR, a drain region DA associated with the drain electrode of the pixel transistor PTR, and a channel region CH located between the source region SA and the drain region DA.

[0086] Each of the source region SA and drain region DA may be doped with type I impurities. The gate electrode GE of the pixel transistor PTR may overlap with the well region WA in the third direction (Z-axis direction). The channel region CH may overlap with the gate electrode GE in the third direction (Z-axis direction). The source region SA may be located on one side of the gate electrode GE, and the drain region DA may be located on the opposite side of the gate electrode GE.

[0087] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may include an inorganic film such as silicon carbide (SiCN) or silicon oxide (SiO2). x Inorganic films of this type or made of silicon carbide (SiCN) or silicon oxide (SiO) x It is composed of inorganic membranes, but is not limited to them.

[0088] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may include silicon oxide (SiO2). x Inorganic films of this type or made of silicon dioxide (SiO2) x The composition is an inorganic membrane, but this disclosure is not limited thereto.

[0089] Multiple contact terminals CTEs can be formed on the second semiconductor insulating film SINS2. Each of the multiple contact terminals CTEs can be connected to one of the gate electrode GE, source region SA, and drain region DA of each of the pixel transistors PTRs through holes penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The contact terminals CTEs can include one or an alloy containing at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or can be composed of one or an alloy containing at least one of these, or can be composed of one or an alloy containing at least one of these.

[0090] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the contact terminals (CTEs). The top surface of each of the contact terminals (CTEs) may not be covered by the third semiconductor insulating film (SINS3) and can be exposed. The third semiconductor insulating film (SINS3) may include silicon oxide (SiO2). x Inorganic films of this type or made of silicon dioxide (SiO2) x The composition is an inorganic membrane, but this disclosure is not limited thereto.

[0091] The emissive substrate EBP includes first metal layers ML1 to eighth metal layers ML8, reflective metal layers RL1 to RL4, multiple vias VA1 to VA10, and a step layer STPL. In addition, the emissive substrate EBP also includes multiple dielectric films INS1 to INS10.

[0092] The first metal layers ML1 to the eighth metal layers ML8 are used to implement the circuitry of the sub-pixel SP by connecting multiple contact terminals CTE exposed from the semiconductor substrate SBP.

[0093] A first dielectric film INS1 may be disposed on a semiconductor substrate SBP. Each of the first vias VA1 may penetrate the first dielectric film INS1 and may be connected to a contact terminal CTE exposed from the semiconductor substrate SBP. Each of the first metal layers ML1 may be disposed on the first dielectric film (also referred to as the first intermediate insulating film) INS1 and may be connected to the first via VA1.

[0094] A second dielectric film INS2 can be provided on the first dielectric film INS1 and the first metal layer ML1. Each of the second vias VA2 can penetrate the second dielectric film INS2 to connect to the exposed first metal layer ML1. Each of the second metal layer ML2 can be provided on the second intermediate insulating film INS2 and can connect to the second via VA2.

[0095] A third dielectric film INS3 can be provided on the second dielectric film INS2 and the second metal layer ML2. Each of the third vias VA3 can penetrate the third dielectric film INS3 to connect to the exposed second metal layer ML2. Each of the third metal layer ML3 can be provided on the third intermediate insulating film INS3 and can connect to the third via VA3.

[0096] A fourth dielectric film INS4 can be provided on the third dielectric film INS3 and the third metal layer ML3. Each of the fourth vias VA2 can penetrate the fourth dielectric film INS4 to connect to the exposed third metal layer ML3. Each of the fourth metal layer ML4 can be provided on the fourth intermediate insulating film INS4 and can connect to the fourth via VA4.

[0097] A fifth dielectric film INS5 can be provided on the fourth dielectric film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 can penetrate the fifth dielectric film INS5 to connect to the exposed fourth metal layer ML4. Each of the fifth metal layer ML5 can be provided on the fifth dielectric film INS5 and can connect to the fifth via VA5.

[0098] A sixth dielectric film INS6 can be provided on the fifth dielectric film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 can penetrate the sixth dielectric film INS6 to connect to the exposed fifth metal layer ML5. Each of the sixth metal layer ML6 can be provided on the sixth intermediate insulating film INS6 and can connect to the sixth via VA6.

[0099] A seventh dielectric film INS7 can be provided on the sixth dielectric film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 can penetrate the seventh dielectric film INS7 to connect to the exposed sixth metal layer ML6. Each of the seventh metal layer ML7 can be provided on the seventh intermediate insulating film INS7 and can connect to the seventh via VA7.

[0100] An eighth dielectric film INS8 can be provided on the seventh dielectric film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 can penetrate the eighth dielectric film INS8 to connect to the exposed seventh metal layer ML7. Each of the eighth metal layer ML8 can be provided on the eighth intermediate insulating film INS8 and can connect to the eighth via VA8.

[0101] The first metal layers ML1 to ML8 and the first vias VA1 to VA8 may comprise or be composed of substantially the same material as each other. The first metal layers ML1 to ML8 and the first vias VA1 to VA8 may comprise one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising at least one of these, or may be composed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising at least one of these, or an alloy comprising at least one of these. The first vias VA1 to VA8 may comprise or be composed of substantially the same material as each other. The first dielectric film INS1 to INS8 may comprise silicon oxide (SiO2). x Inorganic films of this type or made of silicon dioxide (SiO2) x The embodiments in this specification are composed of inorganic membranes, but are not limited to this.

[0102] The thicknesses of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thicknesses of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can be greater than the thickness of the first metal layer ML1. The thicknesses of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 can all be substantially equal.

[0103] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 can be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 can be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 can be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 can be substantially equal to the thickness of the eighth metal layer ML8.

[0104] A ninth dielectric film INS9 can be disposed on the eighth dielectric film INS8 and the eighth metal layer ML8. The ninth dielectric film INS9 can include a silicon oxide (SiO x ) based inorganic film or consist of a silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited thereto.

[0105] Each of the ninth vias VA9 can penetrate the ninth dielectric film INS9 to connect to the exposed eighth metal layer ML8. The ninth via VA9 can include, consist of, or consist essentially of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including or consisting of at least one of these.

[0106] A first reflective metal layer (also referred to as a first reflective electrode) RL1 can be disposed on the ninth dielectric film INS9 and can be connected to the ninth via VA9. The first reflective electrode RL1 can include, consist of, or consist essentially of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including or consisting of at least one of these.

[0107] The second reflective electrode RL2 can be disposed on the first reflective electrode RL1. The second reflective electrode RL2 can include one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including or consisting of at least one of these, or can consist of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including or consisting of at least one of these. In an embodiment, for example, the second reflective electrode RL2 can be titanium nitride (TiN).

[0108] In the first sub-pixel SP1, a step layer STPL can be disposed on the second reflective electrode RL2. The step layer STPL can not be disposed in each of the second sub-pixel SP2 and the third sub-pixel SP3. A thickness of the step layer STPL can be determined based on a wavelength of light of the first color and a distance from the first emission layer (an emission material layer EML corresponding to the first sub-pixel SP1) to the fourth reflective electrode RL4, so that light of the first color emitted from the first emission layer (an emission material layer EML corresponding to the first sub-pixel SP1) is advantageously reflected. The step layer STPL can include or consist of a silicon carbon nitride (SiCN) or silicon oxide (SiO x ) inorganic film, but is not limited thereto. x

[0109] In the first sub-pixel SP1, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2 and the step layer STPL. In the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. The third reflective electrode RL3 can include one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including or consisting of at least one of these, or can consist of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including or consisting of at least one of these.

[0110] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 can be eliminated (or omitted).

[0111] ​The fourth reflective electrode RL4 can be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 can reflect light from the first emission layer (an emission material layer EML corresponding to the first sub-pixel SP1), the second emission layer (an emission material layer EML corresponding to the second sub-pixel SP2), and the third emission layer (an emission material layer EML corresponding to the third sub-pixel SP3). The fourth reflective electrode RL4 can include a metal having a relatively high reflectance to facilitate light reflection. The fourth reflective electrode RL4 can consist of, but is not limited to, aluminum (Al), a stack of aluminum and titanium (Ti / Al / Ti), a stack of aluminum and indium tin oxide ("ITO") (ITO / Al / ITO), silver (Ag), palladium (Pd), and copper (Cu) alloy ("APC alloy"), and a stack of APC alloy and ITO (ITO / APC / ITO).

[0112] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9 and the fourth reflective electrode RL4. The tenth insulating film INS10 can include or consist of a silicon oxide (SiO x ) based inorganic film, but the present disclosure is not limited thereto. x

[0113] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 to connect to the exposed fourth reflective electrode RL4. The tenth via VA10 can include, consist of, or consist essentially of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including or consisting of at least one of these. Due to the step layer STPL, the thickness of the tenth via VA10 in the first sub-pixel SP1 can be less than the thickness of the tenth via VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0114] The emission material layer EML can be disposed on an emission material bottom plate EBP. The emission material layer EML can include a plurality of light emitting elements LE each including a first electrode AND, an intermediate layer IL, and a second electrode CAT, and a pixel definition layer PDL.

[0115] ​The first electrode AND can be disposed on the tenth dielectric film INS10 and connected to the tenth via VA10. The first electrode AND can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND can include one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing at least one of these or composed of at least one of these, or it can be composed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing at least one of these or composed of at least one of these. In an embodiment, for example, the first electrode AND can be titanium nitride (TiN).

[0116] The pixel definition layer (PDL) can be partially disposed on the first electrode AND. The PDL can be disposed on the edge of the first electrode AND. The PDL is used to divide the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0117] The first emission region EA1 can be defined as the area in the first sub-pixel SP1 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are stacked on top of each other to emit light. The second emission region EA2 can be defined as the area in the second sub-pixel SP2 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are stacked on top of each other to emit light. The third emission region EA3 can be defined as the area in the third sub-pixel SP3 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are stacked on top of each other to emit light.

[0118] The pixel definition layer (PDL) may include a first pixel definition film (PDL1), a second pixel definition film (PDL2), and a third pixel definition film (PDL3). The first pixel definition film (PDL1) may be disposed on the edge of the first electrode AND, the second pixel definition film (PDL2) may be disposed on the first pixel definition film (PDL1), and the third pixel definition film (PDL3) may be disposed on the second pixel definition film (PDL2). The first pixel definition film (PDL1), the second pixel definition film (PDL2), and the third pixel definition film (PDL3) may include silicon oxide (SiO2). x Inorganic films of this type or made of silicon dioxide (SiO2) x The composition is an inorganic membrane, but this disclosure is not limited thereto.

[0119] The intermediate layer IL can include a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3.

[0120] The intermediate layer IL can have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 that emit different light. In an embodiment, for example, the intermediate layer IL can include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a second color, and a third intermediate layer IL3 that emits light of a third color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 can be sequentially stacked with each other.

[0121] The first intermediate layer IL1 can have a structure in which a first hole transport layer, a first organic emission layer that emits light of a first color, and a first electron transport layer are sequentially stacked with each other. The second intermediate layer IL2 can have a structure in which a second hole transport layer, a second organic emission layer that emits light of a second color, and a second electron transport layer are sequentially stacked with each other. The third intermediate layer IL3 can have a structure in which a third hole transport layer, a third organic emission layer that emits light of a third color, and a third electron transport layer are sequentially stacked with each other.

[0122] The plurality of intermediate layers IL disposed adjacent to each other in the first direction (X-axis direction (see Figure 1 In the display panel 410 in an embodiment, it is possible to prevent a leakage current between adjacent sub-pixels SP1, SP2, and SP3 and to prevent color cross-talk by breaking the intermediate layers IL of the adjacent sub-pixels SP1, SP2, and SP3. Color cross-talk refers to, for example, a phenomenon in which a red sub-pixel adjacent to a blue sub-pixel is unintentionally turned on when the blue sub-pixel emits blue light. Since color cross-talk occurs due to a leakage current, color cross-talk can occur when a blue sub-pixel and a red sub-pixel adjacent to each other have a relatively large difference in voltage for driving the sub-pixels. In an embodiment, for example, while a driving current is supplied to a light emitting element LE of a blue sub-pixel in order to turn on the blue sub-pixel, a part of the driving current can be transmitted to a red sub-pixel as a leakage current through at least some of the conductive layers in the intermediate layers IL. When the leakage current is generated, the red sub-pixel can be unintentionally turned on when the blue sub-pixel is turned on.

[0123] The number of intermediate layers IL1, IL2, and IL3 that emit different light is not limited to Figure 5The intermediate layer IL can include two intermediate layers in an embodiment. In this case, for example, one of the two intermediate layers is substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers can include a second hole transport layer, a second organic emission layer, a third organic emission layer, and a second electron transport layer. In this case, a charge generation layer can be disposed between the two intermediate layers to supply electrons to one intermediate layer and to supply charges to the other intermediate layer.

[0124] Although Figure 5 The first, second, and third intermediate layers IL1, IL2, and IL3 are all disposed in the first, second, and third emission areas EA1, EA2, and EA3 in the embodiment of FIG. 1, the present disclosure is not limited thereto. In an embodiment, for example, the first intermediate layer IL1 can be disposed in the first emission area EA1 without being disposed in the second and third emission areas EA2 and EA3. Also, the second intermediate layer IL2 can be disposed in the second emission area EA2 without being disposed in the first and third emission areas EA1 and EA3. Also, the third intermediate layer IL3 can be disposed in the third emission area EA3 without being disposed in the first and second emission areas EA1 and EA2. In this case, the first, second, and third color filters CF1, CF2, and CF3 of the optical layer OPL can be eliminated (or omitted).

[0125] The second electrode CAT can be disposed on the third intermediate layer IL3. The second electrode CAT can be disposed on the third intermediate layer IL3. The second electrode CAT can include or consist of a transparent conductive material (“TCP”) (such as ITO and indium zinc oxide (“IZO”)) that can transmit light, or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), and an alloy of magnesium (Mg) and silver (Ag)). When the second electrode CAT includes or consists of a semi-transmissive conductive material, light extraction efficiency can be improved by a microcavity in each of the first, second, and third sub-pixels SP1, SP2, and SP3.

[0126] An encapsulation layer TFE can be disposed on the emission material layer EML. The encapsulation layer TFE can include one or more inorganic encapsulation films TFE1 and TFE3 to prevent oxygen or moisture from permeating into the emission material layer EML. In addition, the encapsulation layer TFE can include at least one organic encapsulation film TFE2 to protect the emission material layer EML from particles such as dust. In an embodiment, for example, the encapsulation layer TFE can include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

[0127] The first inorganic encapsulation film TFE1 can be disposed on the second electrode CAT, the organic encapsulation film TFE2 can be disposed on the first inorganic encapsulation film TFE1, and the second inorganic encapsulation film TFE3 can be disposed on the organic encapsulation film TFE2. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 can be composed of a multi-layer in which one or more inorganic layers of a silicon nitride layer (SiN x ), a silicon oxynitride layer (SiO x N y ), a silicon oxide layer (SiO x ), a titanium oxide layer (TiO x ), and an aluminum oxide layer (AlO x ) are alternately stacked with each other. The organic encapsulation film TFE2 can be a single body. In an alternative embodiment, the organic encapsulation film TFE2 can be an organic film including, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like.

[0128] An adhesive layer ADL can adhere the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive member. In addition, the adhesive layer ADL can be a transparent adhesive member including, for example, an optically clear adhesive or an optically clear resin.

[0129] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a fill layer FIL. The plurality of color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed on the adhesive layer ADL.

[0130] The first color filter CF1 can overlap the first emission area EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, i.e., light in a blue wavelength range. The blue wavelength range can be approximately 370 nanometers (nm) to approximately 460 nm. Accordingly, the first color filter CF1 can transmit light of the first color among light emitted from the first emission area EA1.

[0131] The second color filter CF2 can overlap the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, i.e., light in a green wavelength range. The green wavelength range can be approximately 480 nm to approximately 560 nm. Accordingly, the second color filter CF2 can transmit light of the second color among light emitted from the second emission area EA2.

[0132] The third color filter CF3 can overlap the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color, i.e., light in a red wavelength range. The red wavelength range can be approximately 600 nm to approximately 750 nm. Accordingly, the third color filter CF3 can transmit light of the third color among light emitted from the third emission area EA3.

[0133] The lens LNS can be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the lenses LNS can have a structure for increasing a ratio of light guided to a front side of the display device 10 (see Figure 4 ). Each of the lenses LNS can have a cross-sectional shape that is convex upward.

[0134] The fill layer FIL can be disposed on the plurality of lenses LNS. The fill layer FIL can have a predetermined refractive index so that light travels in the third direction (Z-axis direction) at an interface between the plurality of lenses LNS and the fill layer FIL. In addition, the fill layer FIL can be a planarization layer. The fill layer FIL can be an organic film including, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

[0135] The cover layer CVL can be disposed on the fill layer FIL. The cover layer CVL can be a glass substrate or include a polymer resin. When the cover layer CVL is a glass substrate, the cover layer CVL can be attached to the fill layer FIL. In this case, the fill layer FIL can adhere the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL can serve as an encapsulation substrate. When the cover layer CVL includes a polymer resin, the cover layer CVL can be directly applied on the fill layer FIL.

[0136] Figure 6 is a plan view of an embodiment of a mask according to the present disclosure. Figure 7 is an enlarged plan view of the area A of Figure 6 . Figure 6 The mask in the embodiment shown in Figure 5 may be used in a process of depositing at least a portion of the intermediate layer IL of the display panel 410 described above with reference to

[0137] Referring to Figure 6 andFigure 7 In the embodiments, the mask MK1 may be a mask for manufacturing an ultra-high resolution display. In the embodiments, for example, the mask MK1 may be a mask for manufacturing a display included in an extended reality device (“XR device”) (such as a virtual reality device (“VR device”), an augmented reality device (“AR device”), and a mixed reality device (“MR device”)).

[0138] The mask MK1 in the embodiment can be used to perform subpixelation on a silicon wafer rather than on a relatively large substrate used in existing displays. Figure 5 The deposition process of subpixels SP1, SP2, and SP3 in the image. For a display included in an extended reality device, the screen is directly in front of the user's eyes, and therefore the display can have a relatively small screen rather than a relatively large screen. Furthermore, because the display is positioned close to the user's eyes, an ultra-high resolution may be required. In embodiments, for example, the desired resolution of the display included in the extended reality device may be approximately 1000 pixels per inch (PPI) or higher, and preferably, an ultra-high resolution of approximately 2000 PPI or higher. Therefore, the deposition mask MK1 in the embodiments can be a mask used to manufacture such an ultra-high resolution display.

[0139] According to embodiments of this disclosure, the mask MK1 may include a plurality of unit patterns CP and a mask frame MF.

[0140] In this embodiment, the mask frame MF can be configured as a whole surrounding multiple unit patterns CP in a planar view. The mask frame MF can support the mask MK1. The structures included in the mask frame MF will be described in detail later.

[0141] According to embodiments of this disclosure, multiple unit patterns CP can be formed, and the unit patterns CP can be spaced apart from each other. According to embodiments of this disclosure, the unit patterns CP can be... Figure 5 The multiple sub-pixels SP shown overlap. In the figures, the unit pattern CP is shown in a quadrilateral shape (e.g., a rectangular shape), but the unit pattern CP is not limited to this. In some embodiments, the unit pattern CP can be formed in various shapes (such as rhombuses, pentagons, circles, and hexagons).

[0142] like Figure 7 As shown, the unit pattern CP may include a masking element MS, and a pixel opening SOP may be defined within the unit pattern CP. The masking element MS may surround the pixel opening SOP in a planar view, and a mask frame MF may surround the masking element MS in a planar view. The pixel opening SOP may be defined such that the pixel opening SOP is... Figure 5 The intermediate layer IL of multiple sub-pixels SP shown is overlapped.

[0143] Figure 8 is a cross-sectional view taken along a line X1-X1' of Figure 7

[0144] Referring to Figure 8 A plurality of mask frames MF can be spaced apart from each other in a first direction (X-axis direction), and the plurality of mask frames MF spaced apart from each other can define a mask opening COP. The mask frame MF can include a mask substrate MSUB and a mask inorganic layer MIO.

[0145] The mask substrate MSUB can include a silicon wafer. Since the silicon wafer can allow a finer, more accurate process by utilizing technology developed in a semiconductor process, compared to a relatively large area substrate, the silicon wafer can be used as a substrate for a super high resolution display. The mask MK1 in the embodiment can use the silicon wafer in the same manner to form a pixel on the silicon wafer of such a super high resolution display.

[0146] The shape of the mask substrate MSUB in the embodiment can conform to the silicon wafer of the super high resolution display. For example, in the embodiment, the mask substrate MSUB can have the same size or shape as the silicon wafer of the super high resolution display. However, it should be understood that the present disclosure is not limited thereto. The mask substrate MSUB can include a relatively large area substrate. For example, in the embodiment, the mask substrate MSUB can include a material such as glass, quartz, and a polymer resin. When the mask substrate MSUB includes a relatively large area substrate, the mask substrate MSUB can be formed in a quadrilateral shape (for example, a rectangular shape) as well as a circular shape.

[0147] According to an embodiment of the present disclosure, the mask inorganic layer MIO can be disposed on and can contact an upper surface s1 of the mask substrate MSUB. The mask inorganic layer MIO can include the same material as that of the mask shield MS, which will be described later. The mask shield MS and the mask inorganic layer MIO can be integrally formed during a manufacturing process, and then formed into the illustrated shape via a subsequent etching process.

[0148] The mask inorganic layer MIO can include an inorganic insulating material. In the embodiment, for example, the mask inorganic layer MIO can include one of silicon nitride, silicon oxide, and silicon oxynitride.

[0149] According to an embodiment, the cell pattern CP can be disposed to overlap the mask opening COP. The plurality of cell patterns CP can be created by etching a portion of the mask substrate MSUB from a lower surface s2 of the mask substrate MSUB.

[0150] ​According to an embodiment of the disclosure, the unit pattern CP can include a plurality of mask shields MS. The plurality of adjacent mask shields MS can define a pixel opening SOP. The plurality of pixel openings SOP can penetrate the mask frame MF along a thickness direction (e.g., a third direction (Z-axis direction)) of the mask MK1. The pixel opening SOP can also be referred to as a hole, a via, or a mask hole. The plurality of pixel openings SOP can be created by etching a portion of the mask substrate MSUB from a lower surface s2 of the mask substrate MSUB.

[0151] When a deposition material is evaporated from a deposition source inside a deposition apparatus, the mask shield MS can function as a blocking unit that masks a substrate (e.g., a display panel 410 (see Figure 4 and Figure 5 ) or a backplane substrate) that is subjected to deposition. Accordingly, the deposition material generated from the deposition source can be deposited on a surface of the substrate (e.g., the display panel 410 or the backplane substrate) that is subjected to deposition through the pixel opening SOP.

[0152] Figure 9 is a plan view illustrating an embodiment of a layout of a region included in a mask substrate according to the disclosure.

[0153] Referring to Figure 9 , the mask substrate MSUB in an embodiment can include a center region C, an edge region E, and an intermediate region M.

[0154] The center region C of the mask substrate MSUB can include a center point of the mask substrate MSUB and a peripheral region disposed close to the center point. The shape of the center region C of the mask substrate MSUB can be defined as a circular shape having a first radius r1 from the center point. In an embodiment, for example, the first radius r1 can be in a range of 10% to 40% of a radius R of the mask substrate MSUB. However, it should be understood that the disclosure is not limited thereto.

[0155] The shape of the intermediate region M of the mask substrate MSUB can be defined as an annular shape obtained by excluding the center region C in a circular shape having a second radius r2 from the center point. In other words, the intermediate region M can surround a boundary of the center region C. In an embodiment, for example, the second radius r2 can be in a range of 30% to 70% of the radius R of the mask substrate MSUB. However, it should be understood that the disclosure is not limited thereto.

[0156] The edge region E of the mask substrate MSUB can include an edge of the mask substrate MSUB and a peripheral region disposed close to the edge. In other words, the shape of the edge region E can be defined as an annular shape obtained by excluding the center region C and the intermediate region M in a circular shape having a radius R of the mask substrate MSUB from the center point. In other words, the edge region E can surround a boundary of the intermediate region M.

[0157] According to embodiments of the present disclosure, the mask substrate MSUB can have different degrees of warping for different regions in the plan view. This can be because the mask inorganic layer MIO included in the mask frame MF has a tensile stress or a compressive stress.

[0158] In embodiments, for example, when the mask inorganic layer MIO is deposited on the entire surface of the mask substrate MSUB in the plan view, the degree of warping of the mask inorganic layer MIO on the edge region E of the mask substrate MSUB can be less than the degree of warping of the mask inorganic layer MIO on the center region C of the mask substrate MSUB. In other words, the degree of warping of the mask inorganic layer MIO can decrease from the center point of the mask substrate MSUB toward the edge.

[0159] In embodiments, for example, when the unit pattern CP is formed at a place where the mask inorganic layer MIO has a relatively high degree of warping, the adhesion between the unit pattern CP of the mask MK1 and the display panel 410 shown in FIGS. 11A and 11B can decrease, resulting in a deposition failure. Figure 4 and Figure 5 In embodiments, for example, when the unit pattern CP is formed at a place where the mask inorganic layer MIO has a relatively high degree of warping, the adhesion between the unit pattern CP of the mask MK1 and the display panel 410 shown in FIGS. 11A and 11B can decrease, resulting in a deposition failure.

[0160] Therefore, in the mask MK1 in embodiments, the plurality of unit patterns CP can be arranged differently depending on the degree of warping in different regions of the mask substrate MSUB.

[0161] Figure 10 is a plan view showing a plurality of unit patterns arranged on the mask substrate of Figure 9

[0162] Referring to Figure 10 In embodiments of the present disclosure, the number of unit patterns CP provided in the edge region E can be greater than the number of unit patterns CP provided in the center region C. In other words, the number of unit patterns CP per unit area in the edge region E can be greater than the number of unit patterns CP per unit area in the center region C.

[0163] In addition, the number of unit patterns CP provided in the intermediate region M can be greater than the number of unit patterns CP provided in the center region C. In other words, the number of unit patterns CP per unit area in the edge region E can be greater than the number of unit patterns CP per unit area in the center region C.

[0164] In addition, the number of unit patterns CP provided in the edge region E can be greater than the number of unit patterns CP provided in the intermediate region M. It should be noted that in some implementations, the number of unit patterns CP provided in the edge region E can be equal to the number of unit patterns CP provided in the intermediate region M. ​

[0165] That is, in the mask MK1 in the embodiment of the disclosure, the number of the unit patterns CP provided in the center region C can be less than the number of the unit patterns CP provided in the edge region E and the middle region M.

[0166] In some embodiments, the plurality of unit patterns CP can be spaced apart from each other at a first distance D1 in the edge region E. Herein, the unit patterns CP provided across the edge region E and the middle region M can be regarded as provided in the edge region E. Accordingly, the unit patterns CP provided across the edge region E and the middle region M can be spaced apart from the unit patterns CP provided only in the edge region E at the first distance D1.

[0167] In some embodiments, the plurality of unit patterns CP provided in the center region C can be spaced apart from each other at a second distance D2. Herein, the unit patterns CP provided across the center region C and the middle region M can be regarded as provided in the center region C. According to embodiments, the plurality of unit patterns CP provided in the middle region M can be spaced apart from each other at a third distance D3.

[0168] In some embodiments, the first distance D1, the second distance D2, and the third distance D3 can include values different from each other. Specifically, in the embodiment of the disclosure, the first distance D1 can be less than the second distance D2. That is, the plurality of unit patterns CP provided in the edge region E can be spaced apart from each other at a smaller distance than the plurality of unit patterns CP provided in the center region C. In other words, the plurality of unit patterns CP provided in the edge region E can be arranged more closely than the plurality of unit patterns CP provided in the center region C.

[0169] Further, the first distance D1 can be less than the third distance D3. That is, the plurality of unit patterns CP provided in the edge region E can be spaced apart from each other at a smaller distance than the plurality of unit patterns CP provided in the middle region M. In other words, the plurality of unit patterns CP provided in the edge region E can be arranged more closely than the plurality of unit patterns CP provided in the middle region M and the center region C.

[0170] Further, the third distance D3 can be less than the second distance D2. That is, the unit patterns CP provided in the middle region M can be spaced apart from each other at a smaller distance than the unit patterns CP provided in the center region C. In other words, the plurality of unit patterns CP provided in the middle region M can be arranged more closely than the plurality of unit patterns CP provided in the center region C.

[0171] As described above, in the mask MK1 in the embodiment, the unit patterns CP are provided more in the edge region E where the degree of warping is lowest than in the center region C where the degree of warping is highest, so that the adhesion between the mask MK1 and the display panel 410 can be enhanced without warping of the mask MK1.

[0172] Figures 11 to 13 is a plan view showing a plurality of unit patterns provided on a mask substrate according to different embodiments. Figure 9

[0173] Figure 11 The mask MK3 in the embodiment is similar to the mask MK1 of Figure 10 in that the unit patterns CP provided in the center region C are spaced apart from each other by the second distance D2.

[0174] However, in the mask MK3 in the embodiment, the plurality of unit patterns CP provided in the edge region E can be spaced apart from each other by the first distance DO, and the plurality of unit patterns CP provided in the middle region M can also be spaced apart from each other by the first distance DO. In other words, the mask MK3 according to the present embodiment is different from the mask MK1 in that the plurality of unit patterns CP can be spaced apart from each other by the same distance in the edge region E as well as in the middle region M.

[0175] In some embodiments, the second distance D2 can be greater than the first distance DO. That is, the unit patterns CP provided in the edge region E and the middle region M can be spaced apart from each other by a smaller distance than the unit patterns CP provided in the center region C. In other words, the unit patterns CP provided in the edge region E and the middle region M can be arranged more closely than the unit patterns CP provided in the center region C. Redundant descriptions will be omitted.

[0176] In the mask MK3 in the embodiment, the unit patterns CP are provided more in the edge region E and the middle region M where the degree of warping is lower than in the center region C where the degree of warping is higher, so that the adhesion between the mask MK3 and the display panel 410 can be enhanced without warping of the mask MK3.

[0177] Figure 12 The mask MK5 in the embodiment is similar to the mask MK1 of Figure 10 in that the unit patterns CP provided in the edge region E are spaced apart from each other by the first distance D1.

[0178] However, in the mask MK5 according to the embodiment, no unit patterns CP can be provided in the center region C. The following description will focus on the difference between the mask MK1 and the mask MK5.

[0179] ​In the mask MK5 according to the embodiment, the unit patterns CP disposed in the edge area E can be spaced apart from each other at the first distance D1, and the unit patterns CP disposed in the middle area M can be spaced apart from each other at the third distance D3.

[0180] In some embodiments, the first distance D1 can be equal to or different from the third distance D3.

[0181] In the embodiment, for example, when the first distance D1 is different from the third distance D3, the first distance D1 can be smaller than the third distance D3. That is, the plurality of unit patterns CP disposed in the edge area E can be spaced apart from each other at a smaller distance than the plurality of unit patterns CP disposed in the middle area M. In other words, the plurality of unit patterns CP disposed in the edge area E can be arranged more densely than the plurality of unit patterns CP disposed in the middle area M.

[0182] In the embodiment, for example, when the first distance D1 is equal to the third distance D3, the mask MK5 in the embodiment can include the plurality of unit patterns CP spaced apart from each other at the same distance.

[0183] In the mask MK5 in the embodiment, the unit patterns CP are disposed in the middle area M and the edge area E where the degree of warping is low, and are not disposed in the center area C where the degree of warping is high, so that the adhesion between the mask MK5 and the display panel 410 can be enhanced without warping of the mask MK5.

[0184] Referring to Figure 13 The plurality of unit patterns CP included in the mask MK7 in the embodiment can be spaced apart from each other at a random distance Drdm. In other words, the plurality of unit patterns CP included in the mask MK7 in the embodiment can be irregularly arranged at different distances. As used herein, the expression "irregularly" can have the same meaning as "randomly".

[0185] According to the embodiment of the disclosure, the unit patterns CP can be arranged more densely in the edge area E than in the center area C. That is, the number of unit patterns CP per unit area in the edge area E and the middle area M can be greater than the number of unit patterns CP per unit area in the center area C.

[0186] According to the present embodiment, the unit patterns CP disposed in the edge area E can be spaced apart from each other at different distances. Further, according to the present embodiment, the plurality of unit patterns CP disposed in the middle area M can also be spaced apart from each other at different distances. Further, in the embodiment of the disclosure, the plurality of unit patterns CP disposed in the center area C can be spaced apart from each other at different distances.

[0187] It should be noted that in some embodiments, the plurality of cell patterns CP can not be disposed in the center region C. When the cell patterns CP are not disposed in the center region C, the plurality of cell patterns CP can be densely formed in the edge region E and the middle region M, and the plurality of cell patterns CP in the edge region E and the middle region M can be irregularly arranged.

[0188] In the mask MK7 in the embodiment, more cell patterns CP are disposed in the edge region E where the degree of warping is low than in the center region C where the degree of warping is high, so that the adhesion between the mask MK7 and the display panel 410 can be enhanced without warping of the mask MK7.

[0189] Embodiments of the present disclosure should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the inventive concept of the present utility to those skilled in the art.

[0190] While the present utility has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit or scope of the present utility as defined by the appended claims.

Claims

1. A deposition mask, characterized in that, The deposition mask comprises: a mask base comprising a center region and an edge region; a plurality of unit patterns disposed on the mask base, the plurality of unit patterns comprising: unit patterns disposed in the edge region; and unit patterns disposed in the center region; and a mask frame disposed on the mask base and surrounding the plurality of unit patterns, wherein a number of unit patterns per unit area of each of the edge regions among the unit patterns disposed in the edge region is greater than a number of unit patterns per unit area of each of the center regions among the unit patterns disposed in the center region.

2. The deposition mask of claim 1, wherein, The unit patterns in the edge region are spaced apart from each other by a first distance, and the unit patterns in the center region are spaced apart from each other by a second distance, wherein the first distance is different from the second distance.

3. The deposition mask of claim 2, wherein, The second distance is greater than the first distance.

4. The deposition mask of claim 3, wherein, The mask base further comprises an intermediate region disposed between the edge region and the center region, wherein the plurality of unit patterns further comprises unit patterns disposed in the intermediate region, and the unit patterns in the intermediate region are spaced apart from each other by a third distance, and wherein the first distance, the second distance, and the third distance are different from each other.

5. The deposition mask of claim 4, wherein, The third distance is less than the second distance, wherein the third distance is greater than the first distance.

6. The deposition mask of claim 4, wherein, The first distance is equal to the third distance.

7. The deposition mask of claim 1, wherein, The center region comprises a center point of the mask base, and wherein the edge region comprises an edge of the mask base, wherein a shape of the center region is defined as a circular shape having a first radius from the center point of the mask base, and wherein the first radius is in a range of 10% to 40% of a radius of the mask base.

8. The deposition mask of claim 1, wherein, The mask base is a silicon substrate, and wherein the mask base has a circular shape in a plan view.

9. A deposition mask, characterized by, The deposition mask comprises: a mask base comprising a center region, an edge region, and an intermediate region disposed between the center region and the edge region; a plurality of unit patterns disposed on the mask base; and a mask frame disposed on the mask base and surrounding the plurality of unit patterns, wherein the plurality of unit patterns does not overlap with the center region, and the plurality of unit patterns is disposed in the edge region and the intermediate region.

10. The deposition mask of claim 9, wherein, The unit patterns in the edge region are spaced apart from each other by a first distance, and the unit patterns in the intermediate region are spaced apart from each other by a second distance, wherein the first distance is different from the second distance.

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