System and method for measuring and demodulating synchronous vectors of power distribution network

Abstract

The invention discloses a system and a method for measuring and demodulating synchronous vectors of a power distribution network, and belongs to the technical field of automation of power systems. The system comprises an FPGA module used for carrying out data signal acquisition on a power distribution network and carrying out preprocessing on the acquired data signal to obtain three-phase voltage and current phasor data; and the DSP module is used for receiving the three-phase voltage and current phasor data obtained by the FPGA module and quantizing the electric energy quality of the power distribution network according to the three-phase voltage and current phasor data. According to the method, the measurement precision, the synchronization performance, the real-time performance, the functionality, the integration and the like are remarkably improved, the technical problems faced by the power distribution network PMU are well solved, and the expected invention purpose is achieved.

Description

Technical Field

[0001] This invention relates to the field of power system automation technology, and more specifically, to a system and method for synchronization vector measurement and demodulation in distribution networks. Background Technology

[0002] With the development of smart grids, distribution automation, as a key technology for realizing smart distribution, has received increasing attention. Distribution automation requires comprehensive, real-time, and high-precision monitoring of the distribution network to support its optimized scheduling and intelligent control. Synchronous phasor measurement units (PMUs), with their advantages of high sampling rate, high precision, and unified time scale, have become important measurement devices in distribution automation.

[0003] However, traditional power distribution units (PMUs) are primarily designed for high-voltage and ultra-high-voltage transmission networks and are difficult to apply directly to distribution networks. Compared to transmission networks, distribution networks have the following characteristics:

[0004] (1) The voltage level is relatively low, usually 10kV and below, which puts forward higher requirements for signal conditioning and electromagnetic compatibility of measuring equipment;

[0005] (2) The access points are scattered, the line structure is complex, and there are many nodes. Multi-point synchronous measurement is required, which poses a challenge to the synchronization accuracy and communication capability of the equipment.

[0006] (3) The loads are mostly nonlinear and unbalanced, with high harmonic content and prominent power quality problems, requiring the PMU to have complete power quality analysis functions.

[0007] In summary, existing distribution network PMU designs still have the following shortcomings:

[0008] (1) The hardware architecture is unreasonable, making it difficult to balance real-time performance and flexibility;

[0009] (2) The clock synchronization accuracy is not high and is greatly affected by the communication environment;

[0010] (3) The phasor demodulation algorithm is simple and difficult to adapt to the three-phase imbalance characteristics of the distribution network;

[0011] (4) The power quality analysis function is lacking and cannot fully assess the operating status of the distribution network. Summary of the Invention

[0012] To address the above problems, this invention proposes a system for synchronization vector measurement and demodulation in distribution networks, comprising:

[0013] The FPGA module is used to acquire data signals from the power distribution network and preprocess the acquired data signals to obtain three-phase voltage and current phasor data.

[0014] The DSP module is used to receive three-phase voltage and current phasor data obtained from the FPGA module, and quantify the power quality of the distribution network based on the three-phase voltage and current phasor data.

[0015] Optional FPGA modules include:

[0016] Analog input unit, A / D conversion unit, digital filtering unit, clock synchronization unit, and phasor demodulation unit;

[0017] The analog input unit includes: a signal conditioning circuit for isolating, amplifying, and anti-interference processing the voltage and current signals of the power distribution network;

[0018] The A / D conversion unit is used to synchronously sample analog signals;

[0019] The digital filtering unit is used to suppress high-frequency interference and noise in voltage and current signals;

[0020] The clock synchronization unit is used to synchronize the local clock with the GPS clock through adaptive phase-locked loop technology;

[0021] The phasor demodulation unit is used to sample the data signal and perform real-time calculations using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data.

[0022] Optional DSP modules include:

[0023] Interface unit, harmonic analysis unit, power quality assessment unit, and communication unit;

[0024] The data interface unit is used for high-speed data exchange with the FPGA module and to receive the three-phase voltage and current phasor data from the FPGA module.

[0025] The harmonic analysis unit is used to calculate the harmonic content of the distribution network based on the three-phase voltage and current phasor data using the FFT algorithm.

[0026] The power quality assessment unit is used to determine the power supply quality of the distribution network based on the three-phase imbalance quantification index and the content of each harmonic.

[0027] The communication unit uses a standard communication protocol to communicate and transmit data with the power distribution automation master station.

[0028] Optionally, the phasor demodulation unit has a built-in three-phase synchronous phasor demodulation algorithm. Based on the three-phase synchronous phasor demodulation algorithm, the data signal is sampled and calculated in real time using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data, including:

[0029] The data signal is converted into orthogonal α-β two-phase components using Clarke transform, and then into synchronously rotating dq two-phase components using Park transform. The amplitude and phase angle of the dq two-phase components are extracted using the principle of quadrature demodulation. Based on the amplitude and phase angle, the synchronous phasors of the three-phase voltage and current are determined.

[0030] Optionally, the FFT algorithm incorporates window functions and interpolation mechanisms to calculate the amplitude ratio of each harmonic and the fundamental frequency.

[0031] Furthermore, this invention also proposes a method for synchronization vector measurement and demodulation in distribution networks, comprising:

[0032] Data signal acquisition for the power distribution network;

[0033] The collected data signals are preprocessed to obtain three-phase voltage and current phasor data;

[0034] The system receives three-phase voltage and current phasor data from the FPGA module and quantifies the power quality of the distribution network based on this data.

[0035] Optionally, based on the three-phase synchronous phasor demodulation algorithm, the data signal is sampled and calculated in real time using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data, including:

[0036] The data signal is converted into orthogonal α-β two-phase components using Clarke transform, and then into synchronously rotating dq two-phase components using Park transform. The amplitude and phase angle of the dq two-phase components are extracted using the principle of quadrature demodulation. Based on the amplitude and phase angle, the synchronous phasors of the three-phase voltage and current are determined.

[0037] Optionally, a window function and interpolation mechanism can be introduced into the FFT algorithm to calculate the amplitude ratio of each harmonic and the fundamental wave of the distribution network based on the three-phase voltage and current phasor data.

[0038] Based on the harmonics of the distribution network.

[0039] In another aspect, the present invention also provides a computing device, comprising: one or more processors;

[0040] A processor is used to execute one or more programs;

[0041] When the one or more programs are executed by the one or more processors, the method described above is implemented.

[0042] In another aspect, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements the method described above.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] This invention provides a system for synchronization vector measurement and demodulation in distribution networks, comprising: an FPGA module for acquiring data signals from the distribution network and preprocessing the acquired data signals to obtain three-phase voltage and current phasor data; and a DSP module for receiving the three-phase voltage and current phasor data obtained from the FPGA module and quantifying the power quality of the distribution network based on the three-phase voltage and current phasor data. This invention significantly improves measurement accuracy, synchronization performance, real-time performance, functionality, and integration, effectively solving the technical challenges faced by distribution network PMUs and achieving the intended purpose of the invention. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the system structure of the present invention;

[0046] Figure 2 This is a flowchart of the FPGA clock synchronization process of the system of the present invention;

[0047] Figure 3 This is a block diagram of the phasor demodulation algorithm of the system of the present invention. Detailed Implementation

[0048] Exemplary embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.

[0049] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.

[0050] Example 1:

[0051] This invention proposes a system for synchronization vector measurement and demodulation in distribution networks, such as... Figure 1 As shown, it includes:

[0052] The FPGA module is used to acquire data signals from the power distribution network and preprocess the acquired data signals to obtain three-phase voltage and current phasor data.

[0053] The DSP module is used to receive three-phase voltage and current phasor data obtained from the FPGA module, and quantify the power quality of the distribution network based on the three-phase voltage and current phasor data.

[0054] The FPGA module includes:

[0055] Analog input unit, A / D conversion unit, digital filtering unit, clock synchronization unit, and phasor demodulation unit;

[0056] The analog input unit includes: a signal conditioning circuit for isolating, amplifying, and anti-interference processing the voltage and current signals of the power distribution network;

[0057] The A / D conversion unit is used to synchronously sample analog signals;

[0058] The digital filtering unit is used to suppress high-frequency interference and noise in voltage and current signals;

[0059] The clock synchronization unit is used to synchronize the local clock with the GPS clock through adaptive phase-locked loop technology;

[0060] The phasor demodulation unit is used to sample the data signal and perform real-time calculations using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data.

[0061] The DSP module includes:

[0062] Interface unit, harmonic analysis unit, power quality assessment unit, and communication unit;

[0063] The data interface unit is used for high-speed data exchange with the FPGA module and to receive the three-phase voltage and current phasor data from the FPGA module.

[0064] The harmonic analysis unit is used to calculate the harmonic content of the distribution network based on the three-phase voltage and current phasor data using the FFT algorithm.

[0065] The power quality assessment unit is used to determine the power supply quality of the distribution network based on the three-phase imbalance quantification index and the content of each harmonic.

[0066] The communication unit uses a standard communication protocol to communicate and transmit data with the power distribution automation master station.

[0067] The phasor demodulation unit incorporates a three-phase synchronous phasor demodulation algorithm. Based on this algorithm, it samples the data signal and performs real-time calculations using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data, including:

[0068] The data signal is converted into orthogonal α-β two-phase components using Clarke transform, and then into synchronously rotating dq two-phase components using Park transform. The amplitude and phase angle of the dq two-phase components are extracted using the principle of quadrature demodulation. Based on the amplitude and phase angle, the synchronous phasors of the three-phase voltage and current are determined.

[0069] The FFT algorithm incorporates window functions and interpolation mechanisms to calculate the amplitude ratio of each harmonic and the fundamental frequency.

[0070] The system of this invention mainly includes the following aspects:

[0071] PMU hardware architecture design based on FPGA+DSP:

[0072] This invention employs a dual-core architecture of FPGA and DSP, leveraging the strengths of both by rationally dividing system tasks. The FPGA handles front-end processing tasks such as data acquisition, clock synchronization, and phasor demodulation, ensuring high real-time performance through its parallel processing capabilities. The DSP handles back-end computational tasks such as harmonic analysis and power quality assessment, enhancing system flexibility and scalability through its powerful computing capabilities and abundant software resources.

[0073] The FPGA module mainly includes an analog input unit, an A / D conversion unit, a digital filtering unit, a clock synchronization unit, and a phasor demodulation unit. The analog input unit employs a high-precision signal conditioning circuit to achieve isolated amplification and anti-interference processing of voltage and current signals; the A / D conversion unit uses a high-speed, high-precision ADC chip to achieve synchronous sampling of analog signals; the digital filtering unit uses an FIR filter to suppress high-frequency interference and noise in the signal; the clock synchronization unit uses phase-locked loop technology to achieve nanosecond-level synchronization between the local clock and the GPS clock; and the phasor demodulation unit uses an orthogonal demodulation algorithm to achieve real-time calculation of three-phase voltage and current phasors.

[0074] The DSP module mainly includes a data interface unit, a harmonic analysis unit, a power quality assessment unit, and a communication unit. The data interface unit exchanges data with the FPGA at high speed, receiving phasor data calculated by the FPGA; the harmonic analysis unit uses an improved FFT algorithm to calculate the content of each harmonic; the power quality assessment unit uses a three-phase imbalance metric to assess the power supply quality of the distribution network; and the communication unit uses a standard communication protocol to achieve data uploading and command issuance with the distribution automation master station.

[0075] This includes the collaboration, interfaces, data flow, and division of labor between hardware and software, detailing the responsibilities of hardware and software, the data transmission mechanisms between them, and how to ensure the real-time performance and flexibility of the system.

[0076] An overview of hardware and software architecture, including:

[0077] This invention employs an FPGA+DSP dual-core architecture, leveraging the advantages of both hardware and software through rational task allocation:

[0078] The FPGA module is responsible for real-time hardware tasks, including signal acquisition, preprocessing, clock synchronization, and phasor demodulation.

[0079] The DSP module is responsible for high-level computing tasks, including harmonic analysis, power quality assessment, and communication with the host computer or distribution automation master station.

[0080] The division of responsibilities between hardware and software includes:

[0081] (1) Responsibilities of the FPGA module:

[0082] Analog Input Unit: Receives voltage and current signals from the power distribution network, processes the signals through isolation and amplification circuits to make them suitable for subsequent digital processing. The hardware and signal conditioning circuitry of this unit provide the raw signal data input to the software.

[0083] A / D conversion unit: Converts analog signals into digital signals using a high-speed, high-precision ADC (such as TI's ADS8568), providing input for subsequent digital processing.

[0084] Digital filtering unit: Digital filtering is implemented in the FPGA to suppress high-frequency interference and noise, providing a clean signal for subsequent data processing.

[0085] Clock synchronization unit: By integrating a GPS receiver module and phase-locked loop technology, the local clock is synchronized with the GPS clock, providing a unified time standard for the entire system. The FPGA transmits the synchronization clock to the subsequent phasor demodulation unit.

[0086] Phasor demodulation unit: Performs phasor demodulation on the acquired signal, and uses Clarke and Park transforms to convert the signal into synchronous α-β and dq components, generating synchronous phasors for three-phase voltage and current.

[0087] (2) Responsibilities of the DSP module:

[0088] Interface Unit: Receives three-phase voltage and current phasor data from the FPGA module and exchanges data via a high-speed serial interface (such as SPI or UART). This module is responsible for receiving and buffering the data stream before passing it to subsequent analysis units.

[0089] Harmonic Analysis Unit: This unit performs harmonic analysis on three-phase voltage and current signals based on the FFT algorithm, calculating each harmonic and its amplitude. To improve accuracy, window functions and interpolation mechanisms can be used in the FFT algorithm.

[0090] Power Quality Assessment Unit: Based on calculated harmonic data and quantitative indicators of three-phase imbalance, this unit assesses the power quality of the distribution network. It provides feedback on the grid's operating status to aid system decision-making.

[0091] Communication Unit: This unit exchanges data with the host computer or power distribution automation master station via standard protocols (such as IEC61850, DNP3, etc.) to achieve data transmission and remote control. The communication unit ensures that the system can upload evaluation results to the central control system in real time.

[0092] Data flow between hardware and software includes:

[0093] (1) Data acquisition and preprocessing:

[0094] The signal is first processed by the analog input unit, and after A / D conversion, it enters the digital filtering unit to remove interference noise. Then, the data is transmitted to the phasor demodulation unit through the FPGA's internal data bus.

[0095] The FPGA performs real-time calculations in the phasor demodulation unit to generate phasor data of the three-phase voltage and current, and transmits these data to the DSP module through a high-speed serial interface (such as SPI).

[0096] (2) Data processing and evaluation:

[0097] The DSP module receives data transmitted from the FPGA and first buffers the data through the interface unit.

[0098] Next, the harmonic analysis unit performs FFT processing on the received phasor data to calculate the amplitude and frequency of each harmonic.

[0099] The power quality assessment unit evaluates power quality based on harmonic data and uses quantitative indicators of three-phase imbalance to output a power quality report.

[0100] (3) Real-time data transmission and feedback:

[0101] The processed data is transmitted to the power distribution automation master station or host computer via the DSP's communication unit using standard communication protocols.

[0102] The master station makes corresponding adjustments or monitoring based on the transmitted data to ensure optimized scheduling and intelligent control of the power distribution network.

[0103] Hardware and software collaborative working mechanisms include:

[0104] Timing Synchronization: The clock synchronization unit in the FPGA module achieves high-precision clock synchronization through adaptive phase-locked loop technology. The FPGA and DSP share a synchronization clock, ensuring time alignment between them and making the timing relationships during data acquisition, processing, and analysis accurate and error-free.

[0105] Data processing sequence: The FPGA module prioritizes real-time data acquisition and preprocessing to ensure real-time system response. The DSP module handles more complex computational tasks; the FPGA sends data to the DSP, which then uses its powerful computing capabilities to perform detailed power quality analysis.

[0106] Task scheduling and allocation: The FPGA handles low-latency hardware processing tasks, minimizing latency in data acquisition and phasor demodulation. The DSP focuses on lower-frequency but computationally complex tasks, such as harmonic analysis and power quality assessment. The two collaborate efficiently via a high-speed data bus.

[0107] Interfaces and extensibility, including:

[0108] Standard interfaces: Hardware interfaces adopt standardized designs (such as SPI and UART) to facilitate system expansion and integration. Interfaces between different modules can be configured according to actual needs, supporting modular assembly and customized development.

[0109] Communication Protocols: The system communicates with external automation platforms using standard protocols (such as IEC61850, DNP3, etc.), ensuring seamless integration with existing power distribution automation systems. These standard protocols provide capabilities for data exchange, remote monitoring, and equipment management.

[0110] Clock synchronization design using adaptive phase-locked loop technology:

[0111] To achieve high-precision clock synchronization, this invention integrates a GPS receiver module into the FPGA and uses phase-locked loop (PLL) technology to synchronize the local clock with the GPS clock at the nanosecond level. The synchronization process is divided into two stages: coarse synchronization and fine synchronization. Figure 2 As shown, the synchronization process includes: coarse synchronization using the GPS 1PPS signal as a reference, achieving local clock cycle alignment through a digital delay-locked loop (DDLL); and fine synchronization using the GPS IRIG-B modulated signal as a reference, achieving local clock phase alignment through an analog-to-digital converter (ADC) and a digital phase-locked loop (DPLL). The PLL employs an adaptive filtering algorithm, which automatically adjusts the loop parameters according to the quality of the GPS signal, improving synchronization accuracy and robustness.

[0112] To adapt to the dynamic changes in frequency and phase of the distribution network, this invention also employs adaptive digital phase-locked loop (PLL) technology for real-time signal tracking. This technology dynamically adjusts the output of the digitally controlled oscillator (CNC) through frequency feedback and phase compensation, ensuring synchronization with the frequency and phase of the input signal. Compared to traditional PLLs, this technology offers higher dynamic response speed and tracking accuracy, effectively overcoming problems such as frequency fluctuations and phase oscillations in the distribution network.

[0113] Clock synchronization is one of the key technologies of this invention, especially crucial for multi-point synchronous measurement tasks in power distribution networks. To ensure consistent time accuracy across all measurement points, an adaptive phase-locked loop (PLL) technique is employed to achieve high-precision clock synchronization.

[0114] To overcome the synchronization distortion problem that traditional PLLs may experience under poor signal conditions, an adaptive algorithm is introduced to dynamically adjust the filters and loop parameters in the phase-locked loop. The adaptive algorithm optimizes synchronization performance by estimating the quality of the input signal (e.g., signal noise, phase fluctuations) online and automatically adjusting the PLL's gain and bandwidth based on these estimates. The design process of the adaptive phase-locked loop consists of two main stages: coarse synchronization and fine synchronization.

[0115] 1. Coarse synchronization stage, including:

[0116] The goal of the coarse synchronization phase is to roughly align the local clock cycle with the reference clock cycle to ensure that the system can enter a synchronized state.

[0117] GPS signal: In this design, the GPS system provides a high-precision clock signal as a reference clock. The GPS signal is used as a periodic reference input via a 1PPS (1 Pulse Per Second) signal.

[0118] Digital Delay-Locked Loop (DDLL): DDLL technology is used to achieve coarse synchronization. The DDLL adjusts the local clock period to align with the 1PPS signal period of the GPS by measuring the delay between the input signal and the local clock.

[0119] The precise synchronization phase includes:

[0120] The goal of the fine synchronization phase is to precisely align the phases of the local clock and the reference clock to ensure clock synchronization accuracy at the nanosecond level.

[0121] IRIG-B signal: The IRIG-B modulated signal of the GPS signal is used as a reference signal for fine synchronization. The IRIG-B signal carries more accurate time information, which can be used to further correct the phase of the local clock.

[0122] Digital Phase-Locked Loop (DPLL): In the fine synchronization stage, the phase alignment of the local clock is achieved through DPLL technology. DPLL digitizes the clock information of the IRIG-B signal, calculates the phase difference between the local clock and the GPS signal, and adjusts the local clock phase in real time to achieve synchronization.

[0123] Hardware implementation schemes include:

[0124] (1) FPGA implementation:

[0125] The main hardware implementation of local clock synchronization relies on FPGA (such as the Xilinx Kintex-7 series) chips. The FPGA is used not only for real-time data processing and signal acquisition, but also for implementing phase-locked loops (PLLs) and adaptive algorithms. Through the parallel processing capabilities of the FPGA, clock synchronization, phasor demodulation, and signal processing can be performed simultaneously.

[0126] Clock synchronization unit: The core algorithm for implementing adaptive phase-locked loops in FPGAs, achieving clock synchronization through digital delay-locked loops (DDLLs) and digital phase-locked loops (DPLLs). Utilizing the parallel processing capabilities of FPGAs, clock correction and synchronization can be performed in an extremely short time.

[0127] Synchronization accuracy control: FPGA is also used to control the accuracy of clock synchronization. It adjusts the gain and bandwidth of the synchronization loop in real time through adaptive algorithms to ensure synchronization accuracy under different environments.

[0128] DSP Implementation:

[0129] The DSP module is used for further analysis and data processing of synchronization signals, playing a crucial role, particularly in signal demodulation and power quality assessment. Its specific functions include:

[0130] Process the synchronization data acquired from the FPGA and evaluate the synchronization accuracy.

[0131] The synchronization status is reported back to the control center, and the synchronization parameters are adjusted as necessary.

[0132] Improved three-phase synchronous phasor demodulation algorithm:

[0133] To address the characteristics of three-phase four-wire wiring in power distribution networks, this invention proposes an improved three-phase synchronous demodulation algorithm. For example... Figure 3As shown, the algorithm first uses Clarke transform to convert the three-phase voltage and current signals into orthogonal α-β two-phase components, eliminating the coupling between the three-phase signals; then it uses Park transform to convert the α-β two-phase components into synchronously rotating dq two-phase components, realizing phasor decoupling and reference frame alignment; finally, it uses the orthogonal demodulation principle to extract the amplitude and phase angle of the dq two-phase components to obtain the synchronous phasors of the three-phase voltage and current.

[0134] Compared with traditional single-phase demodulation algorithms, this algorithm fully utilizes the parallel processing capabilities of FPGAs to achieve simultaneous demodulation of three-phase signals, improving the efficiency and accuracy of phasor measurement. Simultaneously, the algorithm introduces a phase compensation mechanism, which can flexibly adjust the phase reference of the phasors according to the actual wiring configuration of the distribution network, adapting to the diverse needs of the distribution network.

[0135] DSP-based power quality assessment scheme for distribution networks:

[0136] To comprehensively assess the power quality level of distribution networks, this invention implements algorithms for harmonic analysis and unbalance calculation in a DSP. The harmonic analysis employs an improved FFT algorithm, incorporating window functions and interpolation to enhance the accuracy and frequency resolution of harmonic measurements. By calculating the amplitude ratio of each harmonic to the fundamental frequency, the harmonic pollution level of the distribution network can be accurately quantified.

[0137] The unbalance calculation takes into account the three-phase asymmetry of the distribution network and adopts internationally accepted quantitative indicators of unbalance such as the negative-sequence / positive-sequence voltage ratio and the negative-sequence / positive-sequence current ratio, reflecting the unbalanced operating state of the distribution network from both voltage and current dimensions. Simultaneously, indicators such as zero-sequence voltage and zero-sequence current are also introduced to assess the grounding fault and common-mode interference levels of the distribution network.

[0138] The DSP receives phasor data calculated by the FPGA in real time through the data interface unit, and flexibly configures parameters such as harmonic order, frequency resolution, and unbalance threshold according to the requirements of the evaluation algorithm. This realizes the parameterization and programming of the power quality evaluation function, and improves the flexibility and adaptability of the system.

[0139] Integration interface design for engineering applications:

[0140] To facilitate engineering applications and promotion, this invention provides a complete integration interface and supporting software. The various functional modules of the PMU are connected via standard digital interfaces (such as SPI, UART, etc.), supporting plug-and-play and flexible combinations. The PMU communicates with the distribution automation master station using standard communication protocols (such as IEC61850, DNP3, etc.) to achieve bidirectional data transmission and remote equipment management. Simultaneously, upper-level configuration software has been developed, providing human-computer interaction functions such as parameter setting, data display, and fault diagnosis, facilitating user operation and maintenance.

[0141] In summary, the distribution network synchronization vector measurement and demodulation method proposed in this invention features innovative designs in multiple aspects, including hardware architecture, clock synchronization, phasor demodulation, power quality assessment, and engineering applications, forming a complete technical solution. This solution fully considers the characteristics and needs of the distribution network, possessing advantages such as high precision, strong real-time performance, and easy integration. It provides advanced and reliable measurement methods for distribution automation and plays a crucial supporting role in the construction of smart distribution networks.

[0142] The distribution network synchronization vector measurement and demodulation method proposed in this invention has the following significant advantages and beneficial effects compared with the prior art:

[0143] Improved the measurement accuracy and reliability of PMUs in the distribution network:

[0144] By employing high-precision analog signal conditioning circuits, high-speed, high-resolution ADC chips, and high-order digital filtering algorithms, the measurement accuracy of the PMU is effectively improved, and the influence of external interference and internal noise is suppressed. The introduction of adaptive digital phase-locked loop technology enables real-time tracking of the distribution network frequency and phase, overcoming the impact of distribution network parameter fluctuations and ensuring the dynamic performance of phasor measurements. Furthermore, the use of an improved three-phase synchronous demodulation algorithm achieves high-precision calculation of three-phase voltage and current phasors, meeting the measurement accuracy requirements of distribution automation.

[0145] Comprehensive testing shows that the measurement accuracy of this invention is better than 0.1%, the frequency tracking error is less than 0.01Hz, and the phase tracking error is less than 0.1°, which is significantly better than the traditional distribution network PMU.

[0146] Improved the synchronous measurement accuracy of PMUs in the distribution network:

[0147] By integrating a GPS receiver module into the FPGA and utilizing adaptive phase-locked loop (PLL) technology, nanosecond-level clock synchronization was achieved, significantly improving the synchronization measurement accuracy of the PMU. In the coarse synchronization stage, the 1PPS signal from GPS was used to achieve period alignment of the local clock, with a synchronization accuracy better than 1μs. In the fine synchronization stage, the IRIG-B modulation signal from GPS was used to achieve phase alignment of the local clock, with a synchronization accuracy better than 100ns. This high-precision clock synchronization ensures a unified timescale for measurement data from different PMUs, providing a high-quality data source for applications such as fault location and state estimation in distribution networks.

[0148] Field tests show that the synchronization accuracy of this invention is far superior to that of traditional network synchronization methods.

[0149] Improved the real-time processing capability of the distribution network PMU:

[0150] By adopting a dual-core architecture of FPGA+DSP, system tasks are rationally divided, fully leveraging the processing advantages of both. The parallel processing capabilities of the FPGA enable high-speed data acquisition and real-time preprocessing, effectively reducing the computational burden on the DSP. The software flexibility of the DSP enables complex calculations such as harmonic analysis and power quality assessment, improving the system's scalability. The collaborative operation of the dual cores significantly enhances the real-time processing capabilities of the PMU, meeting the high-speed response requirements of distribution automation.

[0151] Performance tests show that the processing latency of this invention is less than one power frequency cycle (20ms), and the data refresh rate can reach 4000 frames / second, which fully meets the requirements of real-time control of power distribution networks.

[0152] Improved the assessment level of power quality in the distribution network:

[0153] By implementing harmonic analysis and unbalance calculation in a DSP, several internationally recognized power quality assessment indicators are introduced, enabling a comprehensive evaluation of power quality in distribution networks. Harmonic analysis employs an improved FFT algorithm, enhancing the accuracy and resolution of harmonic measurements. Unbalance calculation considers the three-phase asymmetry characteristics of the distribution network, using multiple quantitative indicators to comprehensively reflect the unbalance level. This comprehensive power quality analysis function provides a basis for reactive power optimization and harmonic mitigation in distribution networks, contributing to improved power supply quality.

[0154] Improved the integrated application level of PMU in the distribution network:

[0155] By adopting a modular design and standardized interfaces, the PMU's integration and application capabilities have been improved. Internally, standard digital interfaces enable plug-and-play functionality and flexible combination of functional modules; externally, standard communication protocols ensure seamless integration with distribution automation systems. This integrated design not only enhances the PMU's maintainability and scalability but also facilitates mass production and widespread application. Simultaneously, the accompanying host computer software provides a user-friendly interface, simplifying on-site commissioning and maintenance.

[0156] In summary, the distribution network synchronization vector measurement and demodulation method proposed in this invention significantly improves measurement accuracy, synchronization performance, real-time performance, functionality, and integration. It effectively solves the technical challenges faced by distribution network PMUs and achieves the intended purpose of the invention. This invention has significant practical value and application value for promoting technological advancements in distribution automation and the development of smart grids, and deserves widespread promotion in the distribution field.

[0157] In this invention:

[0158] Analog input unit:

[0159] It employs high-precision voltage / current sensors with measurement ranges of 0–15kV and 0–600A, respectively.

[0160] The sensor output signal is processed by conditioning circuits such as isolation amplification and low-pass filtering.

[0161] The analog signal is sampled by the A / D conversion circuit of the FPGA.

[0162] FPGA processing unit:

[0163] It uses Xilinx Kintex-7 series FPGA chips, which have abundant logic resources and DSP modules;

[0164] The A / D conversion circuit uses TI's ADS8568, with a sampling rate of 5MHz and a resolution of 16 bits.

[0165] The clock synchronization circuit integrates Maxim's MAX2769 GPS receiver and achieves nanosecond-level synchronization through a phase-locked loop.

[0166] The phasor demodulation algorithm is implemented in parallel within the FPGA and supports three-phase four-wire connection.

[0167] DSP processing unit:

[0168] It uses TI's TMS320C6678 multi-core DSP chip with a maximum clock speed of 1.25GHz;

[0169] Data interaction with the FPGA is achieved via the high-speed serial interface SPI.

[0170] The harmonic analysis algorithm uses an improved Goertzel algorithm and supports the measurement of harmonics from the 2nd to the 50th order.

[0171] Imbalance metrics include the negative-sequence / positive-sequence voltage ratio and the negative-sequence / positive-sequence current ratio.

[0172] Communication unit:

[0173] It adopts an industrial Ethernet interface and supports IEC61850-9-2 and IEEEC37.118.2 protocols;

[0174] The communication unit and the DSP use a UART interface to achieve bidirectional transmission of configuration information and data;

[0175] It provides 6 digital inputs and 4 digital outputs for local control of the PMU.

[0176] The PMU device in this embodiment was deployed and tested in a 10kV distribution network, achieving good application results.

[0177] Voltage / current measurement error is better than 0.2%, meeting the 0.2S standard;

[0178] The frequency measurement error is better than 0.001Hz, and the phase measurement error is better than 0.01°.

[0179] The harmonic measurement range reaches 50th order, and the total harmonic distortion (THD) complies with the IEC61000-4-7 standard.

[0180] The average communication latency with the master station is less than 20ms, which meets the real-time control requirements of power distribution automation.

[0181] This embodiment fully utilizes the hardware and software resources of FPGA and DSP, and achieves high-precision, full-function, and highly real-time synchronous phasor measurement of the power distribution network by rationally dividing system tasks. The modular design and standardized interfaces greatly improve the system's integration and scalability, facilitating its widespread application in power distribution automation systems.

[0182] It should be noted that this embodiment is merely a preferred application example of the present invention and does not limit the scope of protection of the present invention. Those skilled in the art can make appropriate adjustments to the hardware configuration, access method, measurement range, etc. of the PMU according to actual application needs, and such adjustments should be considered to fall within the scope of protection of the present invention.

[0183] In summary, the high-precision synchronous phasor measurement device provided in this embodiment effectively meets the needs of power distribution automation development and plays a significant role in improving the intelligence level of the power distribution network. With the continuous promotion and application of this invention patent, it will undoubtedly provide more reliable, efficient, and flexible measurement methods and data support for the construction of smart power distribution networks.

[0184] Example 2:

[0185] This invention also proposes a method for synchronization vector measurement and demodulation in distribution networks, comprising:

[0186] Step 1: Acquire data signals for the power distribution network;

[0187] Step 2: Preprocess the collected data signals to obtain three-phase voltage and current phasor data;

[0188] Step 3: Receive the three-phase voltage and current phasor data obtained from the FPGA module, and quantify the power quality of the distribution network based on the three-phase voltage and current phasor data.

[0189] Specifically, based on the three-phase synchronous phasor demodulation algorithm, the data signal is sampled and calculated in real time using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data, including:

[0190] The data signal is converted into orthogonal α-β two-phase components using Clarke transform, and then into synchronously rotating dq two-phase components using Park transform. The amplitude and phase angle of the dq two-phase components are extracted using the principle of quadrature demodulation. Based on the amplitude and phase angle, the synchronous phasors of the three-phase voltage and current are determined.

[0191] In this process, a window function and interpolation mechanism are introduced into the FFT algorithm to calculate the amplitude ratio of each harmonic and the fundamental wave of the distribution network based on the three-phase voltage and current phasor data.

[0192] Based on the harmonics of the distribution network.

[0193] This invention significantly improves measurement accuracy, synchronization performance, real-time performance, functionality, and integration, effectively solving the technical challenges faced by distribution network PMUs and achieving the intended purpose of the invention.

[0194] Example 3:

[0195] Based on the same inventive concept, this invention also provides a computer device, which includes a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions in the computer storage medium to implement corresponding method flows or corresponding functions, thereby implementing the steps of the methods in the above embodiments.

[0196] Example 4:

[0197] Based on the same inventive concept, this invention also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and extended storage media supported by the computer device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for loading and execution by a processor. These instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk storage device. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the steps of the method in the above embodiments.

[0198] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0199] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0200] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0201] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0202] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0203] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A system for synchronization vector measurement and demodulation in a distribution network, characterized in that, include: The FPGA module is used to acquire data signals from the power distribution network and preprocess the acquired data signals to obtain three-phase voltage and current phasor data. The DSP module is used to receive three-phase voltage and current phasor data obtained from the FPGA module, and quantify the power quality of the distribution network based on the three-phase voltage and current phasor data.

2. The system according to claim 1, characterized in that, The FPGA module includes: Analog input unit, A / D conversion unit, digital filtering unit, clock synchronization unit, and phasor demodulation unit; The analog input unit includes: a signal conditioning circuit for isolating, amplifying, and anti-interference processing the voltage and current signals of the power distribution network; The A / D conversion unit is used to synchronously sample analog signals; The digital filtering unit is used to suppress high-frequency interference and noise in voltage and current signals; The clock synchronization unit is used to synchronize the local clock with the GPS clock through adaptive phase-locked loop technology; The phasor demodulation unit is used to sample the data signal and perform real-time calculations using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data.

3. The system according to claim 1, characterized in that, The DSP module includes: Interface unit, harmonic analysis unit, power quality assessment unit, and communication unit; The data interface unit is used for high-speed data exchange with the FPGA module and to receive the three-phase voltage and current phasor data from the FPGA module. The harmonic analysis unit is used to calculate the harmonic content of the distribution network based on the three-phase voltage and current phasor data using the FFT algorithm. The power quality assessment unit is used to determine the power supply quality of the distribution network based on the three-phase imbalance quantification index and the content of each harmonic. The communication unit uses a standard communication protocol to communicate and transmit data with the power distribution automation master station.

4. The system according to claim 2, characterized in that, The phasor demodulation unit has a built-in three-phase synchronous phasor demodulation algorithm. Based on this algorithm, the data signal is sampled and real-time calculations are performed using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data, including: The data signal is converted into orthogonal α-β two-phase components using Clarke transform, and then into synchronously rotating dq two-phase components using Park transform. The amplitude and phase angle of the dq two-phase components are extracted using the principle of quadrature demodulation. Based on the amplitude and phase angle, the synchronous phasors of the three-phase voltage and current are determined.

5. The system according to claim 3, characterized in that, The FFT algorithm introduces a window function and interpolation mechanism to calculate the amplitude ratio of each harmonic and the fundamental frequency.

6. A method for synchronization vector measurement and demodulation in a distribution network, characterized in that, include: Data signal acquisition for the power distribution network; The collected data signals are preprocessed to obtain three-phase voltage and current phasor data; The system receives three-phase voltage and current phasor data from the FPGA module and quantifies the power quality of the distribution network based on this data.

7. The method according to claim 6, characterized in that, Based on the aforementioned three-phase synchronous phasor demodulation algorithm, the data signal is sampled and calculated in real time using an orthogonal modulation algorithm to obtain three-phase voltage and current phasor data, including: The data signal is converted into orthogonal α-β two-phase components using Clarke transform, and then into synchronously rotating dq two-phase components using Park transform. The amplitude and phase angle of the dq two-phase components are extracted using the principle of quadrature demodulation. Based on the amplitude and phase angle, the synchronous phasors of the three-phase voltage and current are determined.

8. The method according to claim 6, characterized in that, A window function and interpolation mechanism are introduced into the FFT algorithm to calculate the amplitude ratio of each harmonic and the fundamental wave of the distribution network based on the three-phase voltage and current phasor data. Based on the harmonics of the distribution network.

9. A computer device, characterized in that, include: One or more processors; A processor is used to execute one or more programs; When the one or more programs are executed by the one or more processors, the method described in any one of claims 6-8 is implemented.

10. A computer-readable storage medium, characterized in that, It contains a computer program, which, when executed, implements the method as described in any one of claims 6-8.

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