Intelligent flow detection method and system based on FPGA (Field Programmable Gate Array) integrated edge power equipment

Abstract

The invention discloses an intelligent flow detection method and system based on FPGA integrated edge power equipment, and relates to the technical field of intelligent monitoring of a power system, and the method comprises the steps: training a neural network model; deploying the trained neural network model in FPGA equipment, and optimizing storage and operation environments; the FPGA device loaded with the model is integrated to an edge node of the power device, real-time power flow data are collected and processed, and localized anomaly detection and state recognition are carried out on the power flow data. According to the method, the extraction and expression of the potential feature mode in the power data are realized, and an algorithm basis of the intelligent recognition capability of the system is laid; efficient execution of the neural network model on resource-constrained hardware is realized, and the real-time performance and stability of the reasoning process in an edge scene are ensured; in-situ reasoning and state discrimination are completed, and localized intelligent identification and anomaly detection of the operation state of the power system are realized.

Description

Technical Field

[0001] This invention relates to the field of intelligent monitoring technology for power systems, specifically to a method and system for intelligent flow detection based on FPGA-integrated edge power equipment. Background Technology

[0002] In the evolution of modern power systems, with the continuous expansion of transmission and distribution networks and the continuous improvement of their intelligence level, system monitoring and anomaly detection technologies based on real-time data have increasingly become key means to ensure the safe and stable operation of the power grid. Especially in edge power scenarios such as substations, distribution terminals, and distributed generation access nodes, real-time monitoring of flow changes and identification of abnormal states have become crucial foundations for precise operation and maintenance. Traditional power monitoring systems mostly adopt a centralized architecture, that is, data is transmitted back to a remote central server through edge sensing devices for unified analysis and processing. However, this structure relies on the quality of communication links and the support of central computing power, and suffers from problems such as information transmission delays, bandwidth bottlenecks, and integrity risks during data transmission, making it difficult to meet the business requirements of high real-time performance and high-precision anomaly identification. Against this backdrop, edge computing architecture has gradually been introduced into the field of power monitoring, aiming to decentralize some decision-making capabilities to the forefront of data acquisition and achieve a "sensing as processing" response mechanism. Simultaneously, with the widespread application of artificial intelligence technology, especially deep neural networks, in time-series data modeling, feature learning, and anomaly identification, intelligent algorithms have demonstrated superior generalization ability and discrimination accuracy in power flow detection compared to traditional rule-based threshold methods. However, since neural network models typically have a high parameter scale and computational complexity, how to achieve efficient operation on resource-constrained edge devices has become the main technical obstacle to the in-depth development of this direction.

[0003] While some research and products have attempted to apply FPGAs to tasks such as image recognition and condition monitoring in industrial scenarios, significant challenges remain in the power sector, particularly in real-time power flow analysis. Existing solutions largely lack deep adaptation to the characteristics of power operations, failing to provide an end-to-end optimization path from model training, operator transformation, hardware mapping to edge integration. In the FPGA deployment phase, existing technologies often employ general caching and resource scheduling strategies, making it difficult to fully exploit the optimization potential of FPGA on-chip resources for specific neural network structures. Edge integration is too coarse-grained, often treating FPGAs as peripheral computing units rather than embedding them into actual power equipment for in-situ acquisition and synchronous processing of flow data, resulting in extended data access chains and increased response latency. Regarding the processing mechanism of inference results, existing methods mostly remain at the classification output level, lacking differential modeling and state mapping logic for feature response dimensions, limiting the system's application capabilities in multi-state anomaly scenarios. Summary of the Invention

[0004] In view of the above-mentioned problems, the present invention is proposed.

[0005] Therefore, the technical problem solved by this invention is that existing power flow detection technologies using centralized processing methods suffer from problems such as high response latency, strong dependence on communication links, and untimely data processing, making it difficult to meet the real-time and localized processing requirements in edge scenarios, and how to achieve efficient deployment and inference execution of neural network models in edge nodes.

[0006] To address the aforementioned technical problems, this invention provides the following technical solution: a method for intelligent flow detection of edge power equipment based on FPGA, comprising training a neural network model; deploying the trained neural network model in an FPGA device and optimizing the storage and operating environment; integrating the FPGA device with the loaded model into the edge node of the power equipment, collecting and processing real-time power flow data, and performing localized anomaly detection and status identification on the power flow data.

[0007] As a preferred embodiment of the intelligent flow detection method for FPGA-integrated edge power equipment described in this invention, the training of the neural network model includes training the neural network model in a general computing environment, quantizing and compiling the neural network model, and rewriting the operators used in the neural network model algorithm during the training process.

[0008] As a preferred embodiment of the intelligent flow detection method for FPGA-integrated edge power equipment described in this invention, the quantization includes: performing numerical format conversion processing on floating-point parameters in the neural network model, and performing format conversion and operator-level reconstruction on activation functions, normalization operations, and parameter update logic.

[0009] As a preferred embodiment of the intelligent flow detection method for FPGA-integrated edge power equipment described in this invention, the compilation includes: converting operators in the neural network model into a form that can run on the FPGA device; replacing and reconstructing incompatible operational logic in the neural network model based on the FPGA operator execution structure; generating an intermediate expression form according to the FPGA computing architecture; and generating a model inference code file adapted to the FPGA device based on the compilation toolchain.

[0010] As a preferred embodiment of the intelligent flow detection method based on FPGA integrated edge power equipment described in this invention, the optimized storage and operating environment includes: configuring the on-chip storage structure of the FPGA device, constructing a memory mapping structure for neural network model inference, loading library function resources that support the execution of neural network model inference, registering the operator execution logic used by the model, and controlling the entire process of starting, executing and stopping the neural network model in the FPGA device through runtime environment configuration parameters.

[0011] As a preferred embodiment of the intelligent flow detection method for FPGA-integrated edge power equipment described in this invention, the step of integrating the FPGA device with the loaded model into the edge node of the power equipment includes reserving a communication interface and installation space in the power data acquisition device, establishing a data communication connection between the FPGA device and the edge node of the power equipment through a standard communication bus, and collecting power flow data of the power equipment.

[0012] As a preferred embodiment of the intelligent flow detection method for FPGA-integrated edge power equipment described in this invention, the localized anomaly detection and state identification of power flow data includes: performing unified data format conversion and numerical normalization processing on the power flow data of the power equipment; inputting the processed power flow data into the FPGA device as input data; performing inference analysis; obtaining the feature response value corresponding to the input dimension in the inference analysis result; performing numerical extraction operation on the feature response value; comparing the extraction result with the corresponding preset threshold; generating an anomaly identifier when the feature response value exceeds the preset threshold range; combining and matching the comparison results of the feature response values; and determining the operating state category of the power flow data according to the preset state mapping rules.

[0013] Another objective of this invention is to provide a flow intelligent detection system based on FPGA-integrated edge power equipment. This system solves the problems of complex model deployment processes and unstable system inference response in current edge intelligent analysis technologies by decoupling and separating the processes of model training, model deployment, and edge inference.

[0014] As a preferred embodiment of the intelligent flow detection system based on FPGA-integrated edge power equipment described in this invention, it includes: a model training module, an FPGA deployment and optimization module, and an edge inference and detection module; the model training module is used to construct and train the neural network model required for power flow detection; the FPGA deployment and optimization module is used to deploy the trained model to the FPGA device and configure the operating environment; the edge inference and detection module is used to collect power flow data and perform inference on the FPGA to realize anomaly detection and status recognition.

[0015] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement a method for intelligent flow detection based on FPGA-integrated edge power devices.

[0016] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a flow intelligent detection method based on FPGA-integrated edge power equipment.

[0017] The beneficial effects of this invention are as follows: The intelligent flow detection method for FPGA-integrated edge power equipment provided by this invention constructs a deep model foundation suitable for power flow anomaly identification by training a neural network model, realizing the extraction and expression of potential feature patterns in power data, and laying the algorithmic foundation for the system's intelligent identification capability; the trained model is deployed in an FPGA device, and the storage and operating environment are optimized, realizing the efficient execution of the neural network model on resource-constrained hardware, ensuring the real-time performance and stability of the inference process in edge scenarios; the FPGA device with the loaded model is integrated into the edge node of the power equipment to collect and process real-time flow data, complete in-situ inference and state discrimination, realize localized intelligent identification and anomaly detection of the power system's operating status, and significantly improve the system's response speed and autonomy. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The flowchart is an overall flowchart of the intelligent flow detection method based on FPGA integrated edge power equipment provided in Embodiment 1 of the present invention. Detailed Implementation

[0020] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0021] Example 1, referring to Figure 1 As one embodiment of the present invention, a method for intelligent flow detection based on FPGA-integrated edge power equipment is provided, comprising:

[0022] S1: Train the neural network model.

[0023] Furthermore, training a neural network model includes training the neural network model in a general computing environment, quantizing and compiling the neural network model, and rewriting the operators used by the neural network model algorithm during the training process.

[0024] It should be noted that in a general computing environment, a training dataset is constructed based on historical power flow data, and a model framework is built using convolutional neural networks, recurrent neural networks, or lightweight Transformer structures. The neural network model is trained using a Python deep learning framework, employing loss functions such as cross-entropy or mean squared error. The network weights are iteratively updated using the backpropagation algorithm. After training, the model parameters are saved as an intermediate file format, and further model quantization is performed to convert the original floating-point parameters to fixed-point or low-bit integer formats to reduce resource overhead during subsequent deployment on the FPGA platform. A compilation toolchain is used to fuse the model structure and quantized weights, generating an FPGA-executable intermediate model file format. During compilation, the operator operations contained in the original neural network are converted into a set of operators that can be mapped to the FPGA structure. If non-standard operators not supported by the FPGA hardware DPU exist, they are functionally equivalently replaced and rewritten using basic mathematical operation statements through operator-level reconstruction to ensure the complete runnability of the neural network model on the FPGA platform.

[0025] It should also be noted that by executing the structure definition and training process of the neural network model in a general computing environment, the neural network model was able to deeply express and learn the characteristics of power flow data, and an adaptable model parameter system was established, laying a data-driven logical foundation for subsequent deployment. The model structure and quantization weights were integrated through the compilation toolchain to generate an intermediate model format that can be loaded by FPGA, realizing the logical mapping from the high-level abstract model to the low-level hardware expression.

[0026] Furthermore, quantization includes performing numerical format conversion on floating-point parameters in the neural network model, and performing format conversion and operator-level reconstruction on activation functions, normalization operations, and parameter update logic.

[0027] It should be noted that the 32-bit floating-point weight parameters are converted into 8-bit or lower fixed-point integer representations, and a corresponding scaling factor table is established for numerical restoration calculations during inference. For activation functions in the model, such as ReLU, Sigmoid, or Tanh, function value mapping is performed using lookup tables or piecewise linear approximation. For substructures involving normalization operations such as batch normalization and layer normalization, their mean, variance, and other statistical parameters are extracted and embedded into the weight parameters of the previous layer to form an equivalent calculation path to avoid the floating-point normalization calculation overhead during FPGA runtime. For the model errors introduced by the above quantization conversion, the inference accuracy and stability of the quantized model are improved by retraining and adjusting the weights and outputs during the quantization training stage. The quantized model parameters and structural information are encapsulated into an intermediate representation file that can be recognized by the FPGA for subsequent compilation toolchain to perform low-level operator mapping and resource scheduling.

[0028] It should also be noted that by introducing a quantization mechanism for the floating-point parameters of the neural network, the 32-bit floating-point weights are converted into fixed-point integer expressions with a width of 8 bits or less, and a scaling factor table is constructed simultaneously to ensure that numerical restoration can be performed during the inference stage. Without significantly sacrificing the expressive power of the model, the model storage space is effectively compressed and the computational complexity is reduced, thereby improving the running efficiency and load adaptability on the FPGA platform.

[0029] Furthermore, the compilation process includes converting operators in the neural network model into a form that can run on FPGA devices, replacing and reconstructing incompatible computational logic in the neural network model based on the FPGA operator execution structure, generating intermediate representations according to the FPGA computing architecture, and generating model inference code files adapted to FPGA devices based on the compilation toolchain.

[0030] It should be noted that the quantized neural network model is input into the FPGA compilation toolchain, and the computational operators in the neural network model are mapped, transformed, and reconstructed according to the computational structure and operator resource requirements of the FPGA hardware. For common deep learning framework operators used in neural network models, such as convolution (Conv2D), pooling (MaxPool), normalization (BatchNorm), and activation functions (ReLU), standard mapping is performed using the DPU library or compatible operator library provided by the FPGA platform. For non-standard operators not directly supported by the FPGA platform, such as custom activation functions with conditional judgments and dynamic dimension transformation operations, equivalent substitution expressions are manually implemented based on the basic computational logic and numerical computation process, and then encapsulated as custom operator nodes. According to the computational path, storage resources, and data scheduling mechanism in the FPGA architecture, the above operator nodes are converted into intermediate representation formats (such as xmodel, bitstream, etc.) for loading by the FPGA runtime environment. During this compilation process, the input and output tensor structures, number of channels, parameter storage structures, etc. of the operators are standardized in format and resources are allocated to ensure that the model as a whole has executability and high-performance scheduling capabilities on the FPGA. Deployable model inference code files are output, and binding configuration with FPGA firmware is completed.

[0031] It should also be noted that after the operator structure is reconstructed, in conjunction with the configurable resource mapping mechanism and data scheduling path in the FPGA platform, the structural expression is encapsulated in intermediate formats such as bitstream or xmodel, and uniformly output as a loading file adapted to the firmware. This not only bridges the execution gap between the model structure and the hardware computing power structure, but also achieves joint deployment and synchronous inference scheduling of multiple types of operators through standardized operations on input / output forms and parameter storage formats, effectively improving the stability and parallelism of the overall model during FPGA operation.

[0032] S2: Deploy the trained neural network model on an FPGA device to optimize the storage and operating environment.

[0033] Furthermore, optimizing the storage and runtime environment includes configuring the on-chip storage structure of the FPGA device, constructing a memory mapping structure for neural network model inference, loading library function resources that support the execution of neural network model inference, registering the operator execution logic used by the model, and controlling the entire process of starting, executing, and stopping the neural network model in the FPGA device through runtime environment configuration parameters.

[0034] It should be noted that the quantized and compiled neural network model is loaded onto the FPGA device. By configuring its on-chip Block RAM (BRAM) and UltraRAM (URAM) storage resources, memory mapping structures such as input data buffers, weight mapping regions, and intermediate output buffers required for neural network model inference are constructed. FPGA runtime function library resources supporting model execution are loaded and called, such as low-level hardware functions for basic operations like activation functions, matrix multiplication, and weighted summation. Key operator logic structures used by the model are registered in the FPGA platform, a correspondence table of operator hardware execution units is established, and the data flow scheduling order is specified. During runtime, operation parameters such as interrupt control, model entry functions, and stop signal judgment conditions are further configured to form a self-starting, self-executing, and self-stopping control flow. In the above process, by setting control register values, calling soft-core control logic, and configuring DMA (Direct Memory Access) read / write channels, precise control is implemented throughout the entire process of loading, running, and unloading the model in the FPGA device, ensuring efficient and stable operation of the neural network model in an edge environment.

[0035] It should also be noted that by loading and calling runtime function resource libraries that support underlying basic computational logic such as activation functions, matrix operations, and weighted summation, and in conjunction with the key operator logic structures already registered in the model, an instruction-level mapping table is established between the model logic layer and the FPGA physical execution unit. This allows the model inference process to be dynamically managed by the scheduler and executed on demand, improving the structural flexibility of the operation. This mechanism solves the problems of poor adaptability and low controllability between model execution units and operator computing resources in existing FPGA deployment schemes.

[0036] S3: Integrates the FPGA device with the loaded model into the edge node of the power equipment, collects and processes real-time power flow data, and performs localized anomaly detection and status identification on the power flow data.

[0037] Furthermore, integrating the FPGA device with the loaded model into the edge node of the power equipment includes reserving communication interfaces and installation space in the power data acquisition device, establishing a data communication connection between the FPGA device and the edge node of the power equipment through a standard communication bus, and collecting power flow data of the power equipment.

[0038] It should be noted that standard bus pins and unused physical installation areas are reserved in the selected power equipment for communication interface connections. The FPGA board pre-loaded with the neural network model is embedded into the installation area via bolts, guide rails, or clips, and connects to a standard bus, such as RS-485, CAN, SPI, or Ethernet, through communication pins to establish a data communication channel. After the communication channel is established, the FPGA device receives real-time data streams from the power data acquisition device. Data types include instantaneous voltage, current, active power, reactive power, frequency, and other power flow information. While continuously receiving data, the neural network model loaded in the FPGA device performs calculations according to a set cycle, identifying abnormal power characteristics in data changes, such as sudden changes, exceeding limits, and abnormal periodic fluctuations. It also performs real-time analysis of the flow status, outputting identification results such as fault risk, operating status level, or fluctuation trend. To achieve stable operation, the edge nodes are pre-set with power outage protection and abnormal reset mechanisms to ensure that the model execution process remains uninterrupted or can be quickly restarted even in the event of voltage fluctuations or network interruptions in the field operating environment. The identification results can be fed back to the upper control platform through the reverse communication channel of the FPGA device, or they can be recorded, archived, or retrieved locally by the edge node.

[0039] It should also be noted that by directly integrating the FPGA device loaded with the neural network model into the edge node of the power equipment, power flow data can be intelligently analyzed and anomaly detected locally. This avoids the traditional data upload and feedback process that relies on a central server, significantly reducing network communication latency and data transmission bandwidth burden, and enhancing the autonomous operation capability of the power system in a distributed environment. The neural network model loaded inside the FPGA can process high-frequency updated data such as instantaneous voltage, current, and active power in real time, and identify abnormal events (such as sudden changes, exceeding limits, and abnormal fluctuations), outputting fault risk levels and trend warning results. It provides intelligent discrimination capabilities that differ from traditional threshold-based alarm logic, enhancing predictability and fault tolerance.

[0040] Furthermore, localized anomaly detection and status identification of power flow data includes performing unified data format conversion and numerical normalization on the power flow data of power equipment, inputting the processed power flow data into the FPGA device for inference analysis, obtaining the feature response values ​​corresponding to the input dimensions in the inference analysis results, performing numerical extraction operations on the feature response values, comparing the extraction results with the corresponding preset thresholds, generating an anomaly identifier when the feature response value exceeds the preset threshold range, combining and matching the comparison results of the feature response values, and determining the operating status category of the power flow data according to preset status mapping rules.

[0041] It should be noted that a unified data format conversion and numerical normalization process is performed on the power flow data of the power equipment. Preferably, a 32-bit fixed-point format is used to convert the sampled instantaneous voltage, current, power, and other power flow data into a standardized input sequence, and the processed power flow data is input into the FPGA device for inference analysis. During the inference analysis, based on the pre-built neural network model structure, the power flow data is subjected to matrix mapping and feature extraction operations within the FPGA to obtain the feature response values ​​corresponding to the input dimensions in the inference analysis results. Feature response values ​​include, but are not limited to, frequency fluctuation factors, voltage fluctuation factors, current mutation factors, and active power difference factors. Numerical extraction operations are performed on the feature response values, and the extraction results are compared with the corresponding preset thresholds. A preferred scheme for the preset thresholds is as follows: the preset threshold for the voltage mutation response factor is preferably set to ±7% (corresponding to the upper limit of the rated voltage fluctuation), which can effectively identify the voltage deviation of the equipment exceeding the normal fluctuation range; the preset threshold for the current mutation response factor is preferably set to ±10%, which is based on the fluctuation tolerance of the rated operating current of the equipment, taking into account both sensitivity and false alarm rate; the power difference factor is also considered. The preset threshold of the response factor is preferably set to ±12%, which can accurately reflect load changes or local short-term nonlinear characteristics. The preset threshold of the frequency response factor is preferably set to ±0.2Hz. Compared with the standard power frequency of 50Hz, the preset threshold of the frequency response factor takes into account both disturbance suppression and anomaly detection capabilities. When the characteristic response value exceeds the preset threshold range, an anomaly label is automatically generated, and the comparison result of the characteristic response value is combined and matched with historical label data. Based on the preset state mapping rules, the operating state category of the power flow data is determined, including steady-state operation, abnormal disturbance, critical overload, sudden jump and other state classifications.

[0042] It should also be noted that, in terms of implementation path, for the first time, the power flow data collected by power equipment is converted to a unified format and normalized before being transmitted as standardized input data to the FPGA device. Within the FPGA device, feature vector extraction, neural network model inference, and preset threshold comparison are completed, forming an integrated edge-end deployment structure for the data processing chain. Compared to the traditional method of transmitting power data to a central server for centralized processing, this invention enables rapid identification of abnormal data and generation of status feedback at edge nodes, effectively reducing transmission load, identification latency, and false alarm rate, and improving robustness and practicality under complex operating conditions.

[0043] Example 2, an embodiment of the present invention, provides a flow intelligent detection system based on FPGA-integrated edge power equipment, including a model training module, an FPGA deployment and optimization module, and an edge inference and detection module.

[0044] Among them, the model training module is used to build and train the neural network model required for power flow detection.

[0045] The FPGA deployment and optimization module is used to deploy the trained model to the FPGA device and configure the runtime environment.

[0046] The edge inference and detection module is used to collect power flow data and perform inference on the FPGA to realize anomaly detection and status recognition.

Claims

1. A method for intelligent flow detection based on FPGA-integrated edge power equipment, characterized in that, include: Train the neural network model; The trained neural network model is deployed on an FPGA device, optimizing the storage and runtime environment; The FPGA device with the loaded model is integrated into the edge node of the power equipment to collect and process real-time power flow data, and to perform localized anomaly detection and status identification on the power flow data.

2. The intelligent flow detection method based on FPGA-integrated edge power equipment as described in claim 1, characterized in that: The training of the neural network model includes training the neural network model in a general computing environment, quantizing and compiling the neural network model, and rewriting the operators used by the neural network model algorithm during the training process.

3. The intelligent flow detection method for FPGA-integrated edge power equipment as described in claim 2, characterized in that: The quantization includes performing numerical format conversion on floating-point parameters in the neural network model, and performing format conversion and operator-level reconstruction on activation functions, normalization operations, and parameter update logic.

4. The intelligent flow detection method for FPGA-integrated edge power equipment as described in claim 3, characterized in that: The compilation includes converting operators in the neural network model into a form that can run on an FPGA device, replacing and reconstructing incompatible computational logic in the neural network model based on the FPGA operator execution structure, generating an intermediate representation form according to the FPGA computing architecture, and generating model inference code files adapted to the FPGA device based on the compilation toolchain.

5. The intelligent flow detection method for FPGA-integrated edge power equipment as described in claim 4, characterized in that: The optimized storage and runtime environment includes configuring the on-chip storage structure of the FPGA device, constructing a memory mapping structure for neural network model inference, loading library function resources that support the execution of neural network model inference, registering the operator execution logic used by the model, and controlling the entire process of starting, executing, and stopping the neural network model in the FPGA device through runtime environment configuration parameters.

6. The intelligent flow detection method for FPGA-integrated edge power equipment as described in claim 5, characterized in that: The process of integrating the FPGA device with the loaded model into the edge node of the power equipment includes reserving a communication interface and installation space in the power data acquisition device, establishing a data communication connection between the FPGA device and the edge node of the power equipment through a standard communication bus, and acquiring power flow data of the power equipment.

7. The intelligent flow detection method for FPGA-integrated edge power equipment as described in claim 6, characterized in that: The localized anomaly detection and status identification of power flow data includes: performing unified data format conversion and numerical normalization processing on the power flow data of power equipment; inputting the processed power flow data into the FPGA device as input data for inference analysis; obtaining the feature response value corresponding to the input dimension in the inference analysis result; performing numerical extraction operation on the feature response value; comparing the extraction result with the corresponding preset threshold; generating an anomaly identifier when the feature response value exceeds the preset threshold range; combining and matching the comparison results of the feature response values; and determining the operating status category of the power flow data according to the preset status mapping rules.

8. A flow intelligent detection system based on FPGA-integrated edge power equipment, employing the flow intelligent detection method based on FPGA-integrated edge power equipment as described in any one of claims 1 to 7, characterized in that: It includes a model training module, an FPGA deployment and optimization module, and an edge inference and detection module; The model training module is used to build and train the neural network model required for power flow detection; The FPGA deployment and optimization module is used to deploy the trained model to the FPGA device and configure the runtime environment; The edge reasoning and detection module is used to collect power flow data and perform reasoning on the FPGA to achieve anomaly detection and status recognition.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the flow intelligent detection method for FPGA-based integrated edge power devices as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the intelligent flow detection method for FPGA-integrated edge power equipment as described in any one of claims 1 to 7.

Images