Semiconductor device thermal resistance extraction method

Abstract

The invention relates to the technical field of semiconductor device thermal management, and discloses a semiconductor device thermal resistance extraction method, aiming at a multilayer packaging semiconductor device, transient thermal response is acquired by applying unit power excitation, and an integral structure function and a differential structure function are constructed; identifying junction-shell thermal resistance demarcation points based on structure function curve features, and extracting equivalent thermal resistance of each material layer; and verifying the conservation relationship between the sum of the equivalent thermal resistances and the junction-shell thermal resistance or the total thermal resistance of the device, and then performing error correction according to the deviation degree. According to the method for extracting the thermal resistance of the semiconductor device, the thermal resistance of each material layer and an interface in a multi-layer packaging structure is accurately extracted, the identification precision of a micro thermal resistance section is improved, the process is standardized, the universality is high, and key support is provided for packaging optimization and thermal design improvement of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device thermal management technology, specifically a method for extracting the thermal resistance of semiconductor devices. Background Technology

[0002] The heat generated during the operation of semiconductor devices leads to an increase in junction temperature, which in turn causes performance degradation, decreased reliability, and shortened lifespan. Thermal resistance is a core indicator for measuring the heat dissipation capability of a device. In multilayer packaging structures, the differences in thermal properties of different material layers such as epitaxial layers, buffer layers, and substrate layers determine the overall thermal resistance distribution. Therefore, accurately extracting the thermal resistance of each layer is of critical engineering significance for improving the thermal management level of devices.

[0003] Current semiconductor device thermal resistance extraction technologies are mainly divided into three categories:

[0004] 1. Interface separation method based on structure function analysis: The transient thermal response curve of the device is collected by a thermal resistance testing system. Based on industry standards, integral and differential structure functions are constructed (the horizontal axis of the integral structure function is the cumulative thermal resistance and the vertical axis is the heat capacity; the differential structure function is its derivative form, and the vertical axis reflects the rate of change of heat capacity under unit thermal resistance). The material layering is identified by the abrupt change in the slope of the integral structure function or the local peak of the differential structure function, and then key parameters such as junction-shell thermal resistance are extracted.

[0005] 2. A method based on the combination of infrared thermal imaging and simulation modeling: The surface temperature distribution of the device is obtained by infrared thermal imaging, and a three-dimensional thermal model is established by combining it with finite element thermal simulation tools. Parameters such as thermal conductivity, layer thickness, and interface thermal resistance are repeatedly adjusted to fit the simulated temperature with the measured data, and the internal thermal resistance is extracted in reverse.

[0006] 3. A method based on multi-physics simulation and spatial coupling calibration: For complex chips such as multi-gate finger GaNHEMT, a two-dimensional TCAD electrothermal model, three-dimensional finite element thermal simulation and infrared temperature measurement data are combined, and the model parameters are corrected through iterative error control to achieve static thermal resistance extraction.

[0007] However, for the aforementioned existing technologies, interface separation methods based on structure function analysis rely on abrupt changes in the slope of the integral structure function or local peaks in the differential structure function to identify layering. However, in actual devices, materials with continuous thermal properties (such as multilayer ceramics and composite interfaces) make the integral structure function curve smooth without significant inflection points, leading to extraction failure. Methods based on infrared thermal imaging and simulation modeling rely on manual experience for modeling, requiring repeated adjustments of multiple parameters and lacking standardized procedures. Infrared thermal imaging can only capture surface temperature and cannot reflect internal thermal gradients, resulting in low accuracy in internal thermal resistance extraction. Furthermore, it relies on external equipment, making operation cumbersome, costly, and unsuitable for batch extraction. Methods based on multi-physics simulation and spatial coupling calibration require constructing multi-dimensional models and iteratively verifying errors, consuming significant computational resources and having long cycles. Error fitting conditions (such as error thresholds) are subjectively set and easily affected by boundary conditions. For specific chip designs, the models and processes are difficult to extend to other devices, lacking versatility.

[0008] Therefore, existing technologies are insufficient in terms of adaptability to complex packaging, accuracy of identifying minute thermal resistances, and process standardization, and there is an urgent need for a more accurate technology for extracting thermal resistances of semiconductor devices. Summary of the Invention

[0009] The purpose of this application is to provide a method for extracting the thermal resistance of semiconductor devices to solve the technical problems mentioned in the background art.

[0010] To achieve the above objectives, this application discloses the following technical solution: a method for extracting the thermal resistance of a semiconductor device, the method comprising the following steps:

[0011] Step 1: Perform temperature-sensitive parameter calibration and K-coefficient calibration on the semiconductor device to obtain the K-coefficient that can convert the voltage-time curve into a temperature-time curve;

[0012] Step 2: Based on the transient dual-interface method, construct high interface thermal resistance environment and low interface thermal resistance environment for the same device in the thermal resistance test system, and collect the voltage change curves of the device during the cooling process under the two environments.

[0013] Step 3: Based on the K coefficient, the voltage change curve is converted into a junction temperature curve, and the electrical interference during the switching of heating current is corrected. Then, by extrapolating the linear characteristics of the temperature change and the square root of time at the instant the heating current is switched to the test current, the initial junction temperature of the device at the moment the heating current is disconnected is obtained.

[0014] Step 4: Calculate the transient thermal impedance curve based on the device heating power, and according to the industry standard for thermal resistance testing of semiconductor devices, perform recursive integration and differentiation on the transient thermal impedance curve using the RC network modeling method to obtain the integral structure function and differential structure function under each environment. The horizontal axis of the integral structure function is the cumulative thermal resistance and the vertical axis is the heat capacity, and the horizontal axis of the differential structure function is the cumulative thermal resistance and the vertical axis is the rate of change of heat capacity per unit thermal resistance.

[0015] Step 5: Compare the integral structure function under high interface thermal resistance with the integral structure function under low interface thermal resistance, or compare the differential structure function under high interface thermal resistance with the differential structure function under low interface thermal resistance. Extract the thermal resistance position where the two curves gradually change from the initial overlapping state to the separation state as the junction-shell thermal resistance boundary point to identify the junction-shell thermal resistance.

[0016] Step 6: Based on the differential structure function under any environment, identify the peak sequence through the feature recognition algorithm, perform logarithmic coordinate transformation on the thermal resistance axis to amplify the characteristics of small thermal resistance segments inside the device, and extract the equivalent thermal resistance of each material layer through the thermal resistance difference between adjacent peaks.

[0017] Step 7: Cross-validate the equivalent thermal resistance layer by layer using the theoretical thermal resistance model, and at the same time verify the conservation relationship between the sum of all equivalent thermal resistances and the junction-shell thermal resistance or the total thermal resistance of the device, thus completing the multilayer thermal resistance extraction.

[0018] Preferably, the step of constructing the low interface thermal resistance environment includes: uniformly applying a thermally conductive medium to the bottom of the device, wherein the thermally conductive medium is used to fill the gap between the bottom of the device and the cold stage;

[0019] The steps for constructing the high interface thermal resistance environment include: placing the bottom of the device in direct contact with the cold stage.

[0020] Preferably, the thermal resistance testing system is a T3Ster thermal resistance testing system.

[0021] Preferably, in step 2, the prerequisites for acquiring the voltage change curve during the cooling process include:

[0022] The device is continuously heated to a thermally stable state according to the set heating parameters;

[0023] Once the device temperature stabilizes and stops changing, disconnect the heating current and switch to the test current, then start collecting the voltage change curve of the cooling process.

[0024] Preferably, the K coefficient calibration includes a deviation judgment step, which includes:

[0025] The K coefficient of each semiconductor device in the same batch is tested separately, and the standard deviation of the K coefficient of the batch is calculated. The standard deviation is compared with a preset deviation threshold. If the standard deviation is less than the preset deviation threshold, the overall deviation of the K coefficient of the batch is determined to meet the requirements, and the average value of the K coefficient of all devices in the batch is taken as the K coefficient of each device in the batch. Otherwise, the temperature-sensitive parameter calibration and K coefficient calibration are performed separately for each semiconductor device in the batch.

[0026] Preferably, the expression for the heating power of the device is:

[0027] P = I H ×V DS

[0028] Among them, I H For heating current, V DS This represents the measured drain-source voltage value of the device in its thermal steady state. When the device is heated to its thermal steady state, all heating power is converted into heat dissipation. At this time, the formula for calculating the transient thermal impedance curve is:

[0029]

[0030] Among them, Z th (t) represents the real-time value of the transient thermal impedance at time t after the switch, T j (t) represents the real-time junction temperature of the device at time t, where T is the junction temperature of the device. j0 The initial junction temperature obtained by extrapolation is ΔP. D The heat dissipation during the device heating process is ΔP. D =P.

[0031] Preferably, the method of cross-validating the equivalent thermal resistance layer by layer through the theoretical thermal resistance model includes:

[0032] The theoretical thermal resistance of the i-th layer is calculated using the following formula:

[0033]

[0034] Where, d i Let λ be the actual thickness of the i-th layer of material. i Let A be the thermal conductivity of the i-th layer material at the test ambient temperature. i Let be the thermally conductive cross-sectional area of ​​the i-th layer material perpendicular to the heat flow direction;

[0035] By comparing the equivalent thermal resistance of each material layer with its corresponding theoretical thermal resistance layer by layer, the error of a single layer and the overall average error are calculated. The formula is as follows:

[0036]

[0037] If both the single-layer error and the overall average error are within a reasonable range, the thermal resistance mapping is determined to meet the physical reliability. If the error exceeds the reasonable range, steps 2 to 6 are repeated to correct the heating current stability and the thermal conductive medium coating state before extracting the equivalent thermal resistance again.

[0038] Preferably, the method of identifying peak sequences using a feature recognition algorithm, performing logarithmic coordinate transformation on the thermal resistance axis to amplify the characteristics of minute thermal resistance segments inside the device, and extracting the equivalent thermal resistance of each material layer through the thermal resistance difference between adjacent peaks includes:

[0039] The first derivative zero-crossing method or the local extremum method are selected as the feature recognition algorithm;

[0040] Define the micro thermal resistance section inside the chip. The micro thermal resistance section inside the device refers to the thermal resistance range corresponding to the internal structure of the device where the thermal resistance value is less than a preset micro thermal resistance threshold.

[0041] Logarithmic coordinate transformation is performed on the thermal resistance axis of the differential structure function to amplify the waveform characteristics of the small thermal resistance segment inside the device; after the logarithmic coordinate transformation, the peak characteristic deviation of the differential structure function in this segment is reduced to within a preset deviation threshold.

[0042] Based on the magnified peak features, the peak sequence on the differential structure function is identified by the feature recognition algorithm, and the coordinate difference between two adjacent peaks on the thermal resistance axis is calculated as the equivalent thermal resistance of the corresponding material layer.

[0043] Preferably, the verification of the conservation relationship between the sum of all equivalent thermal resistances and the junction-case thermal resistance or the total thermal resistance of the device includes:

[0044] Step 71 - Obtain the junction-to-shell thermal resistance, the total thermal resistance of the device read from the coordinates of the endpoints of the curves corresponding to the integral structure function and the differential structure function, the equivalent thermal resistance of each material layer, and the total number of peaks identified on the differential structure function, wherein the total thermal resistance of the device is the total thermal resistance of the device from the junction region to the external environment.

[0045] Step 72 - Using material layer number i as the calculation dimension, sum the equivalent thermal resistances of each material layer to obtain the total equivalent thermal resistance. The calculation formula is as follows:

[0046]

[0047] Where i is the material layer number, Let be the equivalent thermal resistance of the i-th layer material, and n be the total number of peaks identified on the differential structure function;

[0048] Step 73 - Verify the equation using the formulas for the following two scenarios. If either scenario is satisfied, the conservation relationship is determined to be valid:

[0049] Scenario 1: Conservation verification of the sum of equivalent thermal resistances and junction-shell thermal resistance, the formula is:

[0050]

[0051] Among them, R JC Junction-shell thermal resistance;

[0052] Scenario 2: Conservation verification of the sum of equivalent thermal resistances and the total thermal resistance of the device, the formula is:

[0053]

[0054] Among them, R total This represents the total thermal resistance of the device.

[0055] Preferably, the verification of the conservation relationship between the sum of all equivalent thermal resistances and the junction-case thermal resistance or the total thermal resistance of the device further includes:

[0056] Step 74 - Calculate the degree of deviation, using the following formula:

[0057] For scenario one, the degree of deviation is calculated using the following formula:

[0058]

[0059] For scenario two, the degree of deviation is calculated using the following formula:

[0060]

[0061] Step 75 - Compare the calculated deviation with the preset verification threshold. If the deviation is less than the preset verification threshold, the total thermal resistance conservation verification is deemed to be qualified. If the deviation is not less than the preset verification threshold, proceed to the error correction process.

[0062] The error correction process mentioned above includes any one of the following:

[0063] Return to step 5, re-compare the structure function curves of the same type under high interface thermal resistance environment and low interface thermal resistance environment, adjust the criteria for judging the curve separation point to correct the boundary point of junction-shell thermal resistance, and re-execute steps 71 to 75.

[0064] Return to step 6, optimize the parameters of the feature recognition algorithm, re-extract the equivalent thermal resistance of each material layer, and re-execute steps 71 to 75.

[0065] Beneficial effects: The semiconductor device thermal resistance extraction method of this application constructs a one-to-one correspondence between the peak sequence in the differential structure function curve and the structural level, so that the identification of regional thermal resistance no longer depends on obvious curve slope changes, thereby improving the ability to distinguish complex structures, improving the applicability of structure function analysis under the condition of insignificant slope changes, and breaking through the limitation of traditional methods on inflection point abrupt changes. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 A flowchart illustrating the method for extracting the thermal resistance of a semiconductor device provided in an embodiment of this application;

[0068] Figure 2 This is a schematic diagram of the RC network model structure constructed for an embodiment of this application. Detailed Implementation

[0069] The technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0070] In this document, the term "comprising" is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] This embodiment discloses, as follows: Figure 1 The method for extracting the thermal resistance of a semiconductor device, as shown, includes the following steps:

[0072] Step 1: Perform temperature-sensitive parameter calibration and K-coefficient calibration on the semiconductor device to obtain the K-coefficient that can convert the voltage-time curve into a temperature-time curve; the temperature-sensitive parameter is selected from any one of the gate on-state voltage drop, drain-source on-state voltage drop, or gate resistance;

[0073] Step 2: Based on the transient dual-interface method, construct high interface thermal resistance environment and low interface thermal resistance environment for the same device in the thermal resistance test system, and collect the voltage change curves of the device during the cooling process under the two environments.

[0074] Step 3: Based on the K coefficient, the voltage change curve is converted into a junction temperature curve, and the electrical interference during the switching of heating current is corrected. Then, by extrapolating the linear characteristics of the temperature change and the square root of time at the instant the heating current is switched to the test current, the initial junction temperature of the device at the moment the heating current is disconnected is obtained.

[0075] Step 4: Calculate the transient thermal impedance curve based on the device heating power, and according to the industry standard for semiconductor device thermal resistance testing, perform recursive integration and differentiation on the transient thermal impedance curve using an RC network modeling method. The RC network model used in this embodiment is as follows: Figure 2 As shown in the figure (Gallium nitride (GaN) is a high-performance wide bandgap semiconductor material; the buffer layer is used to alleviate lattice mismatch or thermal expansion coefficient differences between the substrate and the upper functional layer (such as the gallium nitride layer) in the device structure, and optimize the epitaxial growth quality; the transition layer undertakes the structural or compositional transition function from the buffer layer to other layers (such as the substrate layer), ensuring the continuity of device structure and performance; the substrate (such as Sapphire, with a chemical composition of aluminum oxide) serves as the substrate material for semiconductor devices (such as GaN-based devices), possessing good thermal stability and mechanical properties); the integral structure function and differential structure function are obtained under each environment, where the horizontal axis of the integral structure function is the cumulative thermal resistance and the vertical axis is the thermal capacity, and the horizontal axis of the differential structure function is the cumulative thermal resistance and the vertical axis is the rate of change of thermal capacity per unit thermal resistance;

[0076] Step 5: Compare the integral structure function under high interface thermal resistance with the integral structure function under low interface thermal resistance, or compare the differential structure function under high interface thermal resistance with the differential structure function under low interface thermal resistance. Extract the thermal resistance position where the two curves gradually change from the initial overlapping state to the separation state as the junction-shell thermal resistance boundary point to identify the junction-shell thermal resistance.

[0077] Step 6: Based on the differential structure function under any environment, identify the peak sequence through the feature recognition algorithm, perform logarithmic coordinate transformation on the thermal resistance axis to amplify the characteristics of small thermal resistance segments inside the device, and extract the equivalent thermal resistance of each material layer through the thermal resistance difference between adjacent peaks.

[0078] Step 7: Cross-validate the equivalent thermal resistance layer by layer using the theoretical thermal resistance model, and at the same time verify the conservation relationship between the sum of all equivalent thermal resistances and the junction-shell thermal resistance or the total thermal resistance of the device, thus completing the multilayer thermal resistance extraction.

[0079] In this embodiment, electrical interference exists at the moment the heating current is disconnected (switched to the test current) (such as voltage fluctuations caused by current switching and transient responses of parasitic inductance and capacitance), making it impossible to directly acquire accurate junction temperature data at that moment. However, according to the physical laws of transient heat conduction: in the extremely short time immediately after heating stops (usually tens to hundreds of microseconds), the internal heat conduction of the device is in a "non-steady-state initial stage," at which time the junction temperature change (ΔT = T) is relatively small. j (t)-T j 0) and the square root of time ( The relationship between the time t (where t is the time after switching) and the transient thermal response of a semi-infinite medium is strictly linear, a typical characteristic of such transient thermal responses. The specific extrapolation steps are as follows:

[0080] Data preprocessing: First, using the K coefficient calibrated in step 1, the collected cooling process voltage change curve is converted into a junction temperature curve (T). j (t)-t); then, through filtering algorithms (such as moving average filtering, wavelet denoising) the electrical interference at the moment of current switching is corrected to obtain smooth junction temperature data;

[0081] Linear segment extraction: Extract junction temperature data within a very short time after the heating current switch, for example, t∈[10μs,200μs] (the specific range needs to be adjusted according to the device type to ensure that it is in the linear heat conduction stage), and extract the junction temperature value (T) within this segment. j (t) and the square root of the corresponding time Two sets of data.

[0082] Linear fitting and extrapolation: for the truncated The data was fitted using linear regression to obtain the equation of the fitted line: (where k is the slope and b is the intercept); extrapolate the fitted line to t = 0 (i.e., the instant the heating current is turned off), at this time... Substituting into the equation, we get T j (0) = b, which is the initial junction temperature (T) of the device at the moment the heating current is disconnected. j 0).

[0083] In this embodiment, the steps for constructing the low interface thermal resistance environment include: uniformly applying a thermally conductive medium (such as thermally conductive silicone grease) to the bottom of the device. The thermally conductive medium is used to fill the gap between the bottom of the device and the cold stage, reducing the obstruction of heat transfer by air in the gap, thereby reducing the interface thermal resistance between the device and the cold stage and improving the thermal contact efficiency.

[0084] The steps for constructing the high interface thermal resistance environment include: directly contacting the bottom of the device with the cold stage to form a high interface thermal resistance environment without a thermally conductive medium.

[0085] Feasible option is to use the T3Ster thermal resistance testing system, which can automatically switch between heating current and test current, and can also collect and store voltage change curves of the device during the cooling process under two different environments in real time.

[0086] In this embodiment, the prerequisites for collecting the voltage change curve during the cooling process in step 2 include:

[0087] The device is continuously heated to a thermally stable state according to the set heating parameters;

[0088] Once the device temperature stabilizes and stops changing, disconnect the heating current and switch to the test current, then start collecting the voltage change curve of the cooling process.

[0089] In this embodiment, the K-coefficient calibration includes a deviation judgment step, which includes:

[0090] The K-coefficient of each semiconductor device in the same batch is tested separately, and the standard deviation of the K-coefficient of the batch is calculated. The standard deviation is compared with a preset deviation threshold. If the standard deviation is less than the preset deviation threshold, the overall deviation of the K-coefficient of the batch is determined to meet the requirements, and the average value of the K-coefficient of all devices in the batch is taken as the K-coefficient of each device in the batch. Otherwise, the temperature-sensitive parameter calibration and K-coefficient calibration of each semiconductor device in the batch are performed separately to ensure that the accuracy of the K-coefficient of a single device meets the requirements of subsequent testing.

[0091] In this embodiment, the expression for the heating power of the device is:

[0092] P = I H ×V DS

[0093] Among them, I H For heating current, V DS This represents the measured drain-source voltage value of the device in its thermal steady state. When the device is heated to its thermal steady state, all heating power is converted into heat dissipation. At this time, the formula for calculating the transient thermal impedance curve is:

[0094]

[0095] Among them, Z th (t) represents the real-time value of the transient thermal impedance at time t after the switch, T j (t) represents the real-time junction temperature of the device at time t, where T is the junction temperature of the device. j0 The initial junction temperature obtained by extrapolation is ΔP. D The heat dissipation during the device heating process is ΔP. D =P.

[0096] Furthermore, the aforementioned step-by-step cross-validation of the equivalent thermal resistance using a theoretical thermal resistance model includes:

[0097] The theoretical thermal resistance of the i-th layer is calculated using the following formula:

[0098]

[0099] Where, d i Let λ be the actual thickness of the i-th layer of material. i Let A be the thermal conductivity of the i-th layer material at the test ambient temperature. i Let be the thermally conductive cross-sectional area of ​​the i-th layer material perpendicular to the heat flow direction;

[0100] By comparing the equivalent thermal resistance of each material layer with its corresponding theoretical thermal resistance layer by layer, the error of a single layer and the overall average error are calculated. The formula is as follows:

[0101]

[0102] If both the single-layer error and the overall average error are within a reasonable range, the thermal resistance mapping is deemed to meet physical reliability. If the error exceeds the reasonable range, steps 2 to 6 are repeated to correct the heating current stability and the thermally conductive medium coating state before extracting the equivalent thermal resistance again. The reasonable range refers to the numerical limit between the single-layer error and the overall average error. Its setting needs to be combined with the three core factors of industry precision requirements for semiconductor device thermal resistance testing, theoretical model error sources, and experimental system errors. Essentially, it is a threshold standard for judging whether the extracted equivalent thermal resistance conforms to physical laws. It is feasible to set the reasonable range of single-layer error based on the following: (1) theoretical thermal resistance calculation error: material thermal conductivity measurement error (±3%~5%), thickness measurement error (±2%~3%); (2) experimental system error: heating current stability (±1%~2%), temperature acquisition accuracy (±0.5%~1%). The corresponding industry typical reasonable range is ≤5%~10%. The basis for setting the reasonable range of the overall average error includes: the single-layer error of multi-material layers has positive and negative cancellation effects, and it needs to reflect the overall extraction accuracy, so the range is more stringent than the single-layer error. The corresponding industry typical reasonable range is ≤3% to 8%. Secondly, in practical applications, the reasonable range can be flexibly adjusted. The adjustment principles include: (1) Adjustment according to device type: power devices (such as IGBT, GaNHEMT) have a more complex packaging structure (including multi-layer solder and heat dissipation substrate), and the theoretical thermal resistance calculation error is larger. The reasonable range can be relaxed to "single-layer error ≤10%, overall average error ≤8%"; discrete small devices (such as diodes) have a simple structure, and the reasonable range needs to be tightened to "single-layer error ≤5%, overall average error ≤3%"; (2) Adjustment according to test standards: if the JEDEC JESD51 series thermal resistance test standards are followed, the reasonable range needs to match the "measurement uncertainty requirements" in the standard (usually requiring total uncertainty ≤10%), so the single-layer error needs to be ≤8% to reserve other error margins. Furthermore, if the error exceeds a reasonable range, it indicates that the equivalent thermal resistance extraction result does not conform to the physical theory (e.g., unstable heating current leads to distortion of the junction temperature curve, uneven coating of the thermally conductive medium leads to thermal contact error). The experimental conditions need to be corrected step by step and the extraction needs to be repeated to ensure the reliability of the final thermal resistance data.

[0103] Secondly, the method of identifying peak sequences using feature recognition algorithms, performing logarithmic coordinate transformation on the thermal resistance axis to amplify the characteristics of minute thermal resistance segments within the device, and extracting the equivalent thermal resistance of each material layer through the thermal resistance difference between adjacent peaks includes:

[0104] The first derivative zero-crossing method or the local extremum method are selected as the feature recognition algorithm;

[0105] Define the micro thermal resistance section inside the chip. The micro thermal resistance section inside the device refers to the thermal resistance range corresponding to the internal structure of the device where the thermal resistance value is less than a preset micro thermal resistance threshold.

[0106] A logarithmic coordinate transformation is performed on the thermal resistance axis of the differential structure function to amplify the waveform characteristics of the small thermal resistance segment inside the device. After the logarithmic coordinate transformation, the peak characteristic deviation of the differential structure function within this segment is reduced to within a preset deviation threshold, wherein the formula for calculating the peak characteristic deviation is:

[0107]

[0108] Based on the amplified peak features, the peak sequence on the differential structure function is identified by the feature recognition algorithm, and the coordinate difference between two adjacent peaks on the thermal resistance axis is calculated as the equivalent thermal resistance of the corresponding material layer, thereby improving the peak recognition resolution of the chip epitaxial layer, buffer layer and substrate layer.

[0109] In addition, the verification of the conservation relationship between the sum of all equivalent thermal resistances and the junction-case thermal resistance or the total thermal resistance of the device includes:

[0110] Step 71 - Obtain the junction-to-shell thermal resistance, the total thermal resistance of the device read from the coordinates of the endpoints of the curves corresponding to the integral structure function and the differential structure function, the equivalent thermal resistance of each material layer, and the total number of peaks identified on the differential structure function, wherein the total thermal resistance of the device is the total thermal resistance of the device from the junction region to the external environment.

[0111] Step 72 - Using material layer number i as the calculation dimension, sum the equivalent thermal resistances of each material layer to obtain the total equivalent thermal resistance. The calculation formula is as follows:

[0112]

[0113] Where i is the material layer number, Let be the equivalent thermal resistance of the i-th layer material, and n be the total number of peaks identified on the differential structure function;

[0114] Step 73 - Verify the equation using the formulas for the following two scenarios. If either scenario is satisfied, the conservation relationship is determined to be valid:

[0115] Scenario 1: Conservation verification of the sum of equivalent thermal resistances and junction-shell thermal resistance, the formula is:

[0116]

[0117] Among them, R JC Junction-shell thermal resistance;

[0118] Scenario 2: Conservation verification of the sum of equivalent thermal resistances and the total thermal resistance of the device, the formula is:

[0119]

[0120] Among them, R total This represents the total thermal resistance of the device.

[0121] It is feasible that the verification of the conservation relationship between the sum of all equivalent thermal resistances and the junction-case thermal resistance or the total thermal resistance of the device also includes:

[0122] Step 74 - Calculate the degree of deviation, using the following formula:

[0123] For scenario one, the degree of deviation is calculated using the following formula:

[0124]

[0125] For scenario two, the degree of deviation is calculated using the following formula:

[0126]

[0127] Step 75 - Compare the calculated deviation with the preset verification threshold. If the deviation is less than the preset verification threshold, the total thermal resistance conservation verification is deemed to be qualified. If the deviation is not less than the preset verification threshold, proceed to the error correction process.

[0128] The error correction process mentioned above includes any one of the following:

[0129] Return to step 5, re-compare the structure function curves of the same type under high interface thermal resistance environment and low interface thermal resistance environment, adjust the criteria for judging the curve separation point to correct the boundary point of junction-shell thermal resistance, and re-execute steps 71 to 75.

[0130] Return to step 6, optimize the parameters of the feature recognition algorithm, re-extract the equivalent thermal resistance of each material layer, and re-execute steps 71 to 75.

[0131] In summary, the semiconductor device thermal resistance extraction method of this embodiment, through the technical logic of structure function feature identification, equivalent thermal resistance extraction, total thermal resistance conservation verification, and deviation-driven error correction, accurately captures the thermal resistance contribution patterns of each material layer and interface in a multilayer package structure based on the complementary characteristics of integral structure functions and differential structure functions. Its core principle lies in utilizing the high sensitivity of differential structure functions to local thermal conductivity changes, overcoming the limitations of traditional methods that rely on abrupt slope changes in integral structure functions to identify layering. Combined with the verification and error correction mechanism of the total thermal resistance conservation relationship, it ensures the accuracy and consistency of thermal resistance extraction. Ultimately, it achieves accurate and standardized extraction of thermal resistance for multilayer complex packaged semiconductor devices, effectively solving the shortcomings of existing technologies in identifying small thermal resistance segments, adaptability to complex structures, and process universality. This provides key technical support for semiconductor device package structure optimization, thermal failure early warning, and thermal design improvement.

[0132] In the embodiments provided in this application, it should be understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, code, or any suitable combination thereof. For hardware implementation, the processor may be implemented in one or more of the following: application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic units designed to implement the functions described herein, or combinations thereof. For software implementation, some or all of the processes of the embodiments may be performed by a computer program instructing the associated hardware. During implementation, the program may be stored in a computer-readable storage medium or transmitted as one or more instructions or code on a computer-readable storage medium. Computer-readable storage media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of a computer program from one place to another. Storage media may be any available medium accessible to a computer. Computer-readable storage media may include, but are not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code having the form of instructions or data structures and accessible to a computer.

[0133] Finally, it should be noted that the above description is only a preferred embodiment of this application and is not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for extracting the thermal resistance of a semiconductor device, characterized in that, The method includes the following steps: Step 1: Perform temperature-sensitive parameter calibration and K-coefficient calibration on the semiconductor device to obtain the K-coefficient that can convert the voltage-time curve into a temperature-time curve; Step 2: Based on the transient dual-interface method, construct high interface thermal resistance environment and low interface thermal resistance environment for the same device in the thermal resistance test system, and collect the voltage change curves of the device during the cooling process under the two environments. Step 3: Based on the K coefficient, the voltage change curve is converted into a junction temperature curve, and the electrical interference during the switching of heating current is corrected. Then, by extrapolating the linear characteristics of the temperature change and the square root of time at the instant the heating current is switched to the test current, the initial junction temperature of the device at the moment the heating current is disconnected is obtained. Step 4: Calculate the transient thermal impedance curve based on the device heating power, and according to the industry standard for thermal resistance testing of semiconductor devices, perform recursive integration and differentiation on the transient thermal impedance curve using the RC network modeling method to obtain the integral structure function and differential structure function under each environment. The horizontal axis of the integral structure function is the cumulative thermal resistance and the vertical axis is the heat capacity, and the horizontal axis of the differential structure function is the cumulative thermal resistance and the vertical axis is the rate of change of heat capacity per unit thermal resistance. Step 5: Compare the integral structure function under high interface thermal resistance with the integral structure function under low interface thermal resistance, or compare the differential structure function under high interface thermal resistance with the differential structure function under low interface thermal resistance. Extract the thermal resistance position where the two curves gradually change from the initial overlapping state to the separation state as the junction-shell thermal resistance boundary point to identify the junction-shell thermal resistance. Step 6: Based on the differential structure function under any environment, identify the peak sequence through the feature recognition algorithm, perform logarithmic coordinate transformation on the thermal resistance axis to amplify the characteristics of small thermal resistance segments inside the device, and extract the equivalent thermal resistance of each material layer through the thermal resistance difference between adjacent peaks. Step 7: Cross-validate the equivalent thermal resistance layer by layer using the theoretical thermal resistance model, and at the same time verify the conservation relationship between the sum of all equivalent thermal resistances and the junction-shell thermal resistance or the total thermal resistance of the device, thus completing the multilayer thermal resistance extraction.

2. The method for extracting the thermal resistance of semiconductor devices according to claim 1, characterized in that, The steps for constructing the low interface thermal resistance environment include: uniformly applying a thermally conductive medium to the bottom of the device, wherein the thermally conductive medium is used to fill the gap between the bottom of the device and the cold stage; The steps for constructing the high interface thermal resistance environment include: placing the bottom of the device in direct contact with the cold stage.

3. The method for extracting the thermal resistance of semiconductor devices according to claim 1, characterized in that, The thermal resistance testing system is the T3Ster thermal resistance testing system.

4. The method for extracting the thermal resistance of a semiconductor device according to claim 1 or 3, characterized in that, In step 2, the prerequisites for collecting the voltage change curve during the cooling process include: The device is continuously heated to a thermally stable state according to the set heating parameters; Once the device temperature stabilizes and stops changing, disconnect the heating current and switch to the test current, then start collecting the voltage change curve of the cooling process.

5. The method for extracting the thermal resistance of semiconductor devices according to claim 1, characterized in that, The K-coefficient calibration includes a deviation judgment step, which includes: The K coefficient of each semiconductor device in the same batch is tested separately, and the standard deviation of the K coefficient of the batch is calculated. The standard deviation is compared with a preset deviation threshold. If the standard deviation is less than the preset deviation threshold, the overall deviation of the K coefficient of the batch is determined to meet the requirements, and the average value of the K coefficient of all devices in the batch is taken as the K coefficient of each device in the batch. Otherwise, the temperature-sensitive parameter calibration and K coefficient calibration are performed separately for each semiconductor device in the batch.

6. The method for extracting the thermal resistance of a semiconductor device according to claim 1, characterized in that, The expression for the heating power of the device is: P=I H ×V DS Among them, I H For heating current, V DS This represents the measured drain-source voltage value of the device in its thermal steady state. When the device is heated to its thermal steady state, all heating power is converted into heat dissipation. At this time, the formula for calculating the transient thermal impedance curve is: Among them, Z th (t) represents the real-time value of the transient thermal impedance at time t after the switch, T j (t) represents the real-time junction temperature of the device at time t, where T is the junction temperature of the device. j0 The initial junction temperature obtained by extrapolation is ΔP. D The heat dissipation during the device heating process is ΔP. D =P.

7. The method for extracting the thermal resistance of a semiconductor device according to claim 1 or 6, characterized in that, The aforementioned method of cross-validating equivalent thermal resistance layer by layer using a theoretical thermal resistance model includes: The theoretical thermal resistance of the i-th layer is calculated using the following formula: Where, d i Let λ be the actual thickness of the i-th layer of material. i Let A be the thermal conductivity of the i-th layer material at the test ambient temperature. i Let be the thermally conductive cross-sectional area of ​​the i-th layer material perpendicular to the heat flow direction; By comparing the equivalent thermal resistance of each material layer with its corresponding theoretical thermal resistance layer by layer, the error of a single layer and the overall average error are calculated. The formula is as follows: If both the single-layer error and the overall average error are within a reasonable range, the thermal resistance mapping is determined to meet the physical reliability. If the error exceeds the reasonable range, steps 2 to 6 are repeated to correct the heating current stability and the thermal conductive medium coating state before extracting the equivalent thermal resistance again.

8. The method for extracting the thermal resistance of a semiconductor device according to claim 1 or 6, characterized in that, The method described above involves identifying peak sequences using a feature recognition algorithm, performing a logarithmic coordinate transformation on the thermal resistance axis to amplify the characteristics of minute thermal resistance segments within the device, and extracting the equivalent thermal resistance of each material layer through the thermal resistance difference between adjacent peaks. The first derivative zero-crossing method or the local extremum method are selected as the feature recognition algorithm; Define the micro thermal resistance section inside the chip. The micro thermal resistance section inside the device refers to the thermal resistance range corresponding to the internal structure of the device where the thermal resistance value is less than a preset micro thermal resistance threshold. Logarithmic coordinate transformation is performed on the thermal resistance axis of the differential structure function to amplify the waveform characteristics of the small thermal resistance segment inside the device; after the logarithmic coordinate transformation, the peak characteristic deviation of the differential structure function in this segment is reduced to within a preset deviation threshold. Based on the magnified peak features, the peak sequence on the differential structure function is identified by the feature recognition algorithm, and the coordinate difference between two adjacent peaks on the thermal resistance axis is calculated as the equivalent thermal resistance of the corresponding material layer.

9. The method for extracting the thermal resistance of a semiconductor device according to claim 1, characterized in that, The aforementioned verification of the conservation relationship between the sum of all equivalent thermal resistances and the junction-case thermal resistance or the total thermal resistance of the device includes: Step 71 - Obtain the junction-to-shell thermal resistance, the total thermal resistance of the device read from the coordinates of the endpoints of the curves corresponding to the integral structure function and the differential structure function, the equivalent thermal resistance of each material layer, and the total number of peaks identified on the differential structure function, wherein the total thermal resistance of the device is the total thermal resistance of the device from the junction region to the external environment. Step 72 - Using material layer number i as the calculation dimension, sum the equivalent thermal resistances of each material layer to obtain the total equivalent thermal resistance. The calculation formula is as follows: Where i is the material layer number, Let be the equivalent thermal resistance of the i-th layer material, and n be the total number of peaks identified on the differential structure function; Step 73 - Verify the equation using the formulas for the following two scenarios. If either scenario is satisfied, the conservation relationship is determined to be valid: Scenario 1: Conservation verification of the sum of equivalent thermal resistances and junction-shell thermal resistance, the formula is: Among them, R JC Junction-shell thermal resistance; Scenario 2: Conservation verification of the sum of equivalent thermal resistances and the total thermal resistance of the device, the formula is: Among them, R total This represents the total thermal resistance of the device.

10. The method for extracting the thermal resistance of a semiconductor device according to claim 9, characterized in that, The verification of the conservation relationship between the sum of all equivalent thermal resistances and the junction-case thermal resistance or the total thermal resistance of the device also includes: Step 74 - Calculate the degree of deviation, using the following formula: For scenario one, the degree of deviation is calculated using the following formula: For scenario two, the degree of deviation is calculated using the following formula: Step 75 - Compare the calculated deviation with the preset verification threshold. If the deviation is less than the preset verification threshold, the total thermal resistance conservation verification is deemed to be qualified. If the deviation is not less than the preset verification threshold, proceed to the error correction process. The error correction process mentioned above includes any one of the following: Return to step 5, re-compare the structure function curves of the same type under high interface thermal resistance environment and low interface thermal resistance environment, adjust the criteria for judging the curve separation point to correct the boundary point of junction-shell thermal resistance, and re-execute steps 71 to 75. Return to step 6, optimize the parameters of the feature recognition algorithm, re-extract the equivalent thermal resistance of each material layer, and re-execute steps 71 to 75.

Images