Driving voltage generation circuit, detection circuit thereof and power management system

Abstract

The invention discloses a driving voltage generation circuit, a detection circuit thereof and a power management system. The driving voltage generation circuit comprises a voltage generation module, an error amplification module and an output power tube, the voltage generation module is used for receiving a constant current source to generate a first reference voltage and a second reference voltage; the error amplification module adopts a transconductance amplifier, a first input end of the transconductance amplifier receives the first reference voltage, and a second input end of the transconductance amplifier receives power level output voltage feedback output by an output end of the transconductance amplifier; the grid electrode of the output power tube is controlled by the power stage output voltage, the source electrode of the output power tube is grounded, the drain electrode of the output power tube outputs driving voltage, and the second input end of the transconductance amplifier is connected to the drain electrode of the output power tube to receive a feedback signal of the driving voltage. According to the technical scheme, the defect that the output voltage drops seriously when a traditional structure drives large load current is overcome, and it is ensured that the driving voltage has high precision and high driving capacity under the static and dynamic load conditions.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a driving voltage generation circuit, a detection circuit, and a power management system for PLDMOS. Background Technology

[0002] When designing and manufacturing switching power management systems using CMOS technology, the high-voltage withstand capability of the devices is a critical consideration. Laterally diffused metal-oxide-semiconductor (LDMOS) devices manufactured using this technology typically have drains capable of withstanding high voltages, but their gate withstand capability is limited. For N-type LDMOS (NLDMOS), its drive circuit can be directly powered by a low-voltage supply; however, for P-type LDMOS (PLDMOS), a drive voltage (VDRV) with a fixed value lower than the supply voltage (VCCP) (e.g., VCCP-1.8V) is required. This drive voltage serves as the reference ground (virtual ground) for the PLDMOS drive circuit, and its stability directly affects the overall system performance.

[0003] The drive voltage must meet several stringent requirements, including good dynamic and static load capacity, high output voltage accuracy, and maintaining logical determinism during voltage build-up to prevent the PLDMOS from entering an uncertain state or failing to turn off. Therefore, appropriate detection circuitry is necessary to monitor its stability and build-up process.

[0004] The existing technical solution generates a reference voltage by applying a constant current source across a fixed resistor, and then uses a PMOS drive to follow the reference voltage to obtain the reference ground of the drive circuit. However, this method has obvious limitations: the output voltage is prone to deviation when driving a large load; it is sensitive to changes in the process corner and has poor adaptability; and its response performance is insufficient under dynamic load conditions, affecting the stability and reliability of the system. Summary of the Invention

[0005] The main objective of this invention is to provide a driving voltage generation circuit, its detection circuit, and a power management system, which aim to provide a stable and accurate driving voltage for PLDMOS.

[0006] To achieve the above objectives, the present invention provides a driving voltage generation circuit, comprising: a voltage generation module, an error amplification module, and an output power transistor; the voltage generation module is used to receive a constant current source to generate a first reference voltage and a second reference voltage; the error amplification module employs a transconductance amplifier, its first input terminal receiving the first reference voltage, and its second input terminal receiving feedback of the output voltage of the power stage output from its output terminal; the gate of the output power transistor is controlled by the output voltage of the power stage, its source is grounded, and its drain outputs a driving voltage; the second input terminal of the transconductance amplifier is connected to the drain of the output power transistor to receive the feedback signal of the driving voltage.

[0007] Preferably, the voltage generation module includes a first constant current source and a first resistor and a second resistor connected in series. One end of the first resistor is connected to the power supply voltage, and the other end is connected to one end of the second resistor. The other end of the second resistor is connected to the first constant current source through a first N-type LDMOS field-effect transistor. The first reference voltage is obtained from the connection point of the first resistor and the second resistor. The source of the first N-type LDMOS field-effect transistor is connected to the first constant current source, the drain is connected to the other end of the second resistor, and the gate is connected to an enable signal to control its on / off state.

[0008] Preferably, the driving voltage generating circuit further includes a clamping voltage generating circuit, which includes a second constant current source, a third constant current source, and a first current mirror structure. The second constant current source is used to provide a bias voltage to the first current mirror structure, and the first current mirror structure generates at least one clamping voltage to protect subsequent circuits by connecting to the third constant current source.

[0009] Preferably, a control module is further connected between the output terminal of the transconductance amplifier and the output power transistor to control the output voltage of the power stage, including: a second N-type LDMOS field-effect transistor, a third N-type LDMOS field-effect transistor, a fourth N-type LDMOS field-effect transistor and a ninth P-type LDMOS field-effect transistor; The source and drain of the second N-type LDMOS field-effect transistor, the third N-type LDMOS field-effect transistor, and the fourth N-type LDMOS field-effect transistor are connected in series. The drain of the second N-type LDMOS field-effect transistor is connected to the power supply voltage, and the source of the fourth N-type LDMOS field-effect transistor is grounded. The gate of the second N-type LDMOS field-effect transistor is connected to the output terminal of the transconductance amplifier to receive the output of the transconductance amplifier, and is mirrored to the output power transistor through the fourth N-type LDMOS field-effect transistor. The gate of the fourth N-type LDMOS field-effect transistor is connected to the gate of the output power transistor and the drain of the fourth N-type LDMOS field-effect transistor. The source of the ninth P-type LDMOS field-effect transistor is connected to the gate of the second N-type LDMOS field-effect transistor, the drain is grounded, and the gate receives a clamping voltage to protect the second N-type LDMOS field-effect transistor. The gate of the third N-type LDMOS field-effect transistor receives a clamping voltage to protect the fourth N-type LDMOS field-effect transistor and the output power transistor.

[0010] Preferably, the tail current of the transconductance amplifier is provided by a third constant current source through a second current mirror structure.

[0011] The present invention also provides a detection circuit for detecting the driving voltage as described above, comprising: A comparator, operating in a first power supply domain, is used to compare the drive voltage with a second reference voltage; A power domain conversion module is used to convert the output signal of the comparator from a first power domain to a second power domain. An output shaping circuit is used to shape the signal after power domain conversion and output a detection signal.

[0012] Preferably, the comparator is a transconductance amplifier, whose differential input pair converts the input differential signal into current.

[0013] Preferably, the output shaping circuit includes a Schmitt trigger and a buffer.

[0014] The present invention also provides a power management system, including the drive voltage generation circuit and the detection circuit as described above.

[0015] The technical solution of this invention utilizes a closed-loop negative feedback control mechanism including a transconductance amplifier to compare the difference between the generated driving voltage and the reference voltage in real time and dynamically adjust its output, thereby achieving precise adjustment of the driving voltage. This active adjustment method overcomes the defect of traditional structures where the output voltage drops severely when driving large load currents, ensuring that the driving voltage has high accuracy and strong driving capability under both static and dynamic load conditions. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the driving voltage generation circuit and its detection circuit in the power management system of the present invention. Figure 2 This is a schematic diagram of the driving voltage generation circuit according to an embodiment of the present invention.

[0017] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0019] The invention will be further described below with reference to the accompanying drawings.

[0020] This invention provides a driving voltage generation circuit, such as... Figure 1 As shown, it can provide a stable and accurate drive voltage for P-type LDMOS and effectively detect the state of this voltage to avoid system logic errors.

[0021] In this embodiment of the invention, the driving voltage generation circuit includes: a voltage generation module, an error amplification module, and an output power transistor; the voltage generation module is used to receive a constant current source to generate a first reference voltage VREF1 and a second reference voltage VREF2; the error amplification module uses a transconductance amplifier OTA, whose first input terminal receives the first reference voltage VREF1, and whose second input terminal receives the output voltage feedback of the power stage output from its output terminal; the gate of the output power transistor NLD5 is controlled by the output voltage of the power stage, its source is grounded, and its drain outputs the driving voltage VDRV; the second input terminal of the transconductance amplifier OTA is connected to the drain of the output power transistor NLD5 to receive the feedback signal of the driving voltage VDRV.

[0022] This invention controls the output power transistor NLD5 through the output of the transconductance amplifier OTA, thereby controlling the drive stage current and the drive voltage VDRV. Simultaneously, the drive voltage VDRV is fed back to the input stage of the transconductance amplifier OTA, enhancing the precise control of VDRV. Unlike conventional LDOs, this drive voltage VDRV uses the power supply voltage minus a reference voltage as a reference, generating a drive voltage VDRV numerically equal to the power supply voltage minus the reference voltage. The power supply voltage is used as the positive terminal, and this drive voltage VDRV is used as the negative terminal to supply power to the PLDMOS power load.

[0023] In this embodiment of the invention, the driving voltage VDRV generation circuit further includes an off-chip capacitor connected between the driving voltage VDRV output node and the power supply voltage, for stabilizing the output voltage and compensating for loop stability.

[0024] like Figure 1As shown, in a specific embodiment of the present invention, the voltage generation module includes a first constant current source IBN1 and a first resistor R1 and a second resistor R2 connected in series. One end of the first resistor R1 is connected to the power supply voltage, and the other end is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the first constant current source IBN1 through a first N-type LDMOS field-effect transistor NLD1. The first reference voltage is obtained from the connection point of the first resistor R1 and the second resistor R2. The source of the first N-type LDMOS field-effect transistor NLD1 is connected to the first constant current source IBN1, the drain is connected to the other end of the second resistor R2, and the gate is connected to a first enable signal ENB to control its on / off state. In other embodiments, the voltage generation module can also use any reference voltage generation module in the prior art. Specifically, the first enable signal ENB operates in the VCCA-1.8V and ground voltage domain.

[0025] The first constant current source IBN1 generates a first reference voltage VREF1 via a first resistor R1 and a second resistor R2, which is typically set to 1.8V. At the same time, this structure also generates a second reference voltage VREF2 for subsequent detection circuits.

[0026] The key biases in the circuit of this invention are all generated using a current mirror structure, which has better matching characteristics than a simple resistor-constant current source structure. Meanwhile, the closed-loop feedback system itself has a certain degree of suppression effect on slow changes in internal device parameters. Therefore, the circuit's sensitivity to different process angles, voltages, and temperatures (PVTs) is significantly reduced, improving chip yield and reliability.

[0027] like Figure 1 As shown, in this embodiment of the invention, the driving voltage VDRV generation circuit further includes a clamping voltage generation circuit. The clamping voltage generation circuit includes a second constant current source IBN2, a third constant current source IBN3, and a first current mirror structure. The second constant current source IBN2 is used to provide a bias voltage to the first current mirror structure. The first current mirror structure generates at least one clamping voltage by connecting to the third constant current source IBN3 to protect subsequent circuits.

[0028] In a specific embodiment, the clamping voltage generation circuit includes a first P-type LDMOS field-effect transistor PLD1, a second P-type LDMOS field-effect transistor PLD2, a third P-type LDMOS field-effect transistor PLD3, a fourth P-type LDMOS field-effect transistor PLD4, a fifth P-type LDMOS field-effect transistor PLD5, a sixth P-type LDMOS field-effect transistor PLD6, a sixth N-type LDMOS field-effect transistor NLD6, and a seventh N-type LDMOS field-effect transistor NLD7; wherein, the third P-type LDMOS field-effect transistor PLD3, the fourth P-type LDMOS field-effect transistor PLD4, the fifth P-type LDMOS field-effect transistor PLD5, and the sixth P-type LDMOS field-effect transistor PLD6 constitute a first current mirror structure; The source of the sixth N-type LDMOS field-effect transistor NLD6 is connected to the second constant current source IBN2, the drain is connected to the drain of the second P-type LDMOS field-effect transistor PLD2, and the gate is connected to the first enable signal ENB to control its on / off state. The source of the first P-type LDMOS field-effect transistor PLD1 is connected to the power supply voltage, and the drain is connected to the source of the second P-type LDMOS field-effect transistor PLD2. The gates of the first P-type LDMOS field-effect transistor PLD1 and the second P-type LDMOS field-effect transistor PLD2 are interconnected and connected to the drain of the second P-type LDMOS field-effect transistor PLD2 to provide bias voltage for the subsequent current mirror structure. The source of the seventh N-type LDMOS field-effect transistor NLD7 is connected to the third constant current source IBN3, the drain is connected to the drain of the fourth P-type LDMOS field-effect transistor PLD4, and the gate is connected to the first enable signal ENB to control its on / off state. The source of the third P-type LDMOS field-effect transistor PLD3 is connected to the power supply voltage, and the drain is connected to the source of the fourth P-type LDMOS field-effect transistor PLD4. The gate of the third P-type LDMOS field-effect transistor PLD3 is connected to the drain of the fourth P-type LDMOS field-effect transistor PLD4. The gate of the fourth P-type LDMOS field-effect transistor PLD4 is connected to the gate and drain of the second P-type LDMOS field-effect transistor PLD2 to receive the bias voltage.

[0029] In the first current mirror structure, the gate of the third P-type LDMOS field-effect transistor PLD3 is interconnected with the gate of the fifth P-type LDMOS field-effect transistor PLD5 and connected to the drain of the fourth P-type LDMOS field-effect transistor PLD4; the gate of the fourth P-type LDMOS field-effect transistor PLD4 is interconnected with the gate of the sixth P-type LDMOS field-effect transistor PLD6 and connected to the gate of the first P-type LDMOS field-effect transistor PLD1 and the second P-type LDMOS field-effect transistor PLD2; the sources of the third P-type LDMOS field-effect transistor PLD3 and the fifth P-type LDMOS field-effect transistor PLD5 are connected to the power supply voltage; the drain of the fifth P-type LDMOS field-effect transistor PLD5 is connected to the source of the sixth P-type LDMOS field-effect transistor PLD6; the drain of the sixth P-type LDMOS field-effect transistor PLD6 is connected to the clamping voltage output terminal to provide at least one clamping voltage for subsequent circuits.

[0030] Specifically, the clamping voltage output terminal includes a first NMOS transistor NM1, a second NMOS transistor NM2, and a third NMOS transistor NM3 connected in series. The drain of the first NMOS transistor NM1 is connected to the drain of a sixth P-type LDMOS field-effect transistor PLD6, its gate is connected to its drain and outputs a first clamping voltage NG_HCLAMP1, and its source is connected to the drain of the second NMOS transistor NM2. The gate of the second NMOS transistor NM2 is connected to its drain and outputs a second clamping voltage NG_HCLAMP2, and its source is connected to the drain of the third NMOS transistor NM3. The drain of the third NMOS transistor NM3 is connected to its gate, and its source is grounded. In other embodiments, the clamping voltage output terminal may also include four NMOS transistors connected in the same manner as described above to provide three clamping voltages to subsequent circuits. Similarly, in other embodiments, those skilled in the art can design specific circuits according to specific needs to meet the requirements for protecting subsequent circuits.

[0031] In this embodiment of the invention, a control module is also connected between the output terminal of the transconductance amplifier OTA and the output power transistor NLD5 to control the drive stage current and the output voltage of the power stage, including: a second N-type LDMOS field-effect transistor NLD2, a third N-type LDMOS field-effect transistor NLD3, a fourth N-type LDMOS field-effect transistor NLD4 and a ninth P-type LDMOS field-effect transistor PLD9. In this configuration, the source and drain of the second N-type LDMOS field-effect transistor NLD2, the third N-type LDMOS field-effect transistor NLD3, and the fourth N-type LDMOS field-effect transistor NLD4 are connected in series. The drain of the second N-type LDMOS field-effect transistor NLD2 is connected to the power supply voltage, and the source of the fourth N-type LDMOS field-effect transistor NLD4 is grounded. The gate of the second N-type LDMOS field-effect transistor NLD2 is connected to the output terminal of the transconductance amplifier OTA to receive the output of the transconductance amplifier OTA, and is mirrored to the output power transistor NLD5 through the fourth N-type LDMOS field-effect transistor NLD4. The gate of the fourth N-type LDMOS field-effect transistor NLD4 is connected to the gate of the output power transistor NLD5 and the drain of the fourth N-type LDMOS field-effect transistor NLD4. The gate of the third N-type LDMOS field-effect transistor NLD3 receives a clamping voltage to protect the fourth N-type LDMOS field-effect transistor NLD4 and the output power transistor NLD5. Specifically, the gate of the third N-type LDMOS field-effect transistor NLD3 is connected to the gate of the first NMOS transistor NM1 to receive the first clamping voltage NG_HCLAMP1.

[0032] The source of the ninth P-type LDMOS field-effect transistor PLD9 is connected to the gate of the second N-type LDMOS field-effect transistor NLD2, the drain is grounded, and the gate receives a clamping voltage to protect the second N-type LDMOS field-effect transistor NLD2. Specifically, the gate of the ninth P-type LDMOS field-effect transistor PLD9 is connected to the gate of the second NMOS transistor NM2 to receive the second clamping voltage NG_HCLAMP2.

[0033] In this embodiment of the invention, the tail current of the transconductance amplifier OTA is provided by the third constant current source IBN3 through the second current mirror structure. Specifically, the second current mirror structure includes a third P-type LDMOS field-effect transistor PLD3, a fourth P-type LDMOS field-effect transistor PLD4, a seventh P-type LDMOS field-effect transistor PLD7, and an eighth P-type LDMOS field-effect transistor PLD8, wherein the drain of the eighth P-type LDMOS field-effect transistor PLD8 is connected to the tail current input terminal of the transconductance amplifier OTA, providing the tail current for the transconductance amplifier OTA.

[0034] Specifically, in the second current mirror structure, the source of the seventh P-type LDMOS field-effect transistor PLD7 is connected to the power supply voltage, and the drain is connected to the source of the eighth P-type LDMOS field-effect transistor PLD8; the gate of the seventh P-type LDMOS field-effect transistor PLD7 is connected to the gate of the third P-type LDMOS field-effect transistor PLD3, and the gate of the eighth P-type LDMOS field-effect transistor PLD8 is connected to the gate of the fourth P-type LDMOS field-effect transistor PLD4.

[0035] In a specific embodiment of the present invention, such as Figure 2As shown, the transconductance amplifier OTA includes an input pair of transistors: a 10th P-type LDMOS field-effect transistor PLD10 and an 11th P-type LDMOS field-effect transistor PLD11. The gate of the 10th P-type LDMOS field-effect transistor PLD10 serves as the output terminal of the transconductance amplifier OTA, used to output the output voltage of the power stage and feed it back to the drain of the 11th P-type LDMOS field-effect transistor PLD11 (the second input terminal of the transconductance amplifier OTA). The sources of the 10th P-type LDMOS field-effect transistor PLD10 and the 11th P-type LDMOS field-effect transistor PLD11 are connected to the drain of the 8th P-type LDMOS field-effect transistor PLD8 in the second current mirror structure to receive the tail current. The gate of the 11th P-type LDMOS field-effect transistor PLD11 is connected to the voltage generation module to receive the first reference voltage VREF1. Specifically, a compensation capacitor Ccomp is also connected between the gate of the 10th P-type LDMOS field-effect transistor PLD10 and the drain of the 11th P-type LDMOS field-effect transistor PLD11.

[0036] The transconductance amplifier OTA also includes the twelfth P-type LDMOS field-effect transistor PLD12, the thirteenth P-type LDMOS field-effect transistor PLD13, the fourteenth P-type LDMOS field-effect transistor PLD14 and the fifteenth P-type LDMOS field-effect transistor PLD15, the eighth N-type LDMOS field-effect transistor NLD8, the ninth N-type LDMOS field-effect transistor NLD9, the fourth NMOS transistor NM4, the tenth N-type LDMOS field-effect transistor NLD10, the fifth NMOS transistor NM5, the eleventh N-type LDMOS field-effect transistor NLD11, the sixth NMOS transistor NM6, the twelfth N-type LDMOS field-effect transistor NLD12 and the seventh NMOS transistor NM7; Among them, the sources of the twelfth P-type LDMOS field-effect transistor PLD12 and the fourteenth P-type LDMOS field-effect transistor PLD14 are connected to the power supply voltage, their gates are connected to each other and receive the second enable signal ENA to control the on / off state; the drain of the twelfth P-type LDMOS field-effect transistor PLD12 is connected to the source of the thirteenth P-type LDMOS field-effect transistor PLD13, the drain of the thirteenth P-type LDMOS field-effect transistor PLD13 is connected to the gate of the twelfth P-type LDMOS field-effect transistor PLD12 and the drain of the eighth N-type LDMOS field-effect transistor NLD8; the source of the fifteenth P-type LDMOS field-effect transistor PLD15 is connected to the drain of the fourteenth P-type LDMOS field-effect transistor PLD14, its gate is connected to the gate of the thirteenth P-type LDMOS field-effect transistor PLD13 and the gate of the eighth P-type LDMOS field-effect transistor PLD8, and its drain is connected to the drain of the twelfth N-type LDMOS field-effect transistor NLD12; The source and drain of the eighth N-type LDMOS field-effect transistor NLD8, the ninth N-type LDMOS field-effect transistor NLD9, and the fourth NMOS transistor NM4 are connected in series; the gate of the eighth N-type LDMOS field-effect transistor NLD8 is connected to the clamping voltage generation circuit to receive the first clamping voltage NG_HCLAMP1, the gate of the ninth N-type LDMOS field-effect transistor NLD9 is connected to the gate of the fourth NMOS transistor NM4 and receives the first enable signal ENB; the source of the fourth NMOS transistor NM4 is grounded; The source and drain of the tenth N-type LDMOS field-effect transistor NLD10 and the fifth NMOS transistor NM5 are connected in series, and their gates are connected to each other and receive the first enable signal ENB. They are also connected to the drain of the tenth N-type LDMOS field-effect transistor NLD10. The drain of the tenth N-type LDMOS field-effect transistor NLD10 is connected to the drain of the eleventh P-type LDMOS field-effect transistor PLD11, and the source of the fifth NMOS transistor NM5 is grounded. The source and drain of the eleventh N-type LDMOS field-effect transistor NLD11 and the sixth NMOS transistor NM6 are connected in series, and their gates are connected to each other and receive the first enable signal ENB. They are also connected to the drain of the eleventh N-type LDMOS field-effect transistor NLD11. The drain of the eleventh N-type LDMOS field-effect transistor NLD11 is connected to the drain of the tenth P-type LDMOS field-effect transistor PLD10. The source of the sixth NMOS transistor NM6 is grounded. The source and drain of the twelfth N-type LDMOS field-effect transistor NLD12 and the seventh NMOS transistor NM7 are connected in series, and their gates are connected to each other and receive the first enable signal ENB; the drain of the twelfth N-type LDMOS field-effect transistor NLD12 is connected to the drain of the fifteenth P-type LDMOS field-effect transistor PLD15, and the source of the seventh NMOS transistor NM7 is grounded.

[0037] Specifically, the second enable signal ENA operates in the VCCA and Vcca-1.8V voltage domains.

[0038] In other embodiments, the error amplification module may also use amplifiers with other structures in the prior art.

[0039] In this embodiment of the invention, the driving voltage VDRV generation circuit further includes a filtering and discharging module, comprising an external capacitor C1 and a third resistor R3 connected between the driving voltage VDRV output node and the power supply voltage; and a fourth resistor R4, one end of which receives a second enable signal ENA and the other end of which is connected to the driving voltage VDRV output node. The external capacitor C1 is used to stabilize the output driving voltage VDRV and compensate for the stability of the loop.

[0040] The technical solution of this invention provides a complete solution for the efficient and reliable use of high-voltage PLDMOS in standard CMOS processes by generating the "virtual ground" drive voltage VDRV (VDRV = VCCP - VREF) required by the power supply voltage for PLDMOS, and is equipped with a complete generation, regulation and monitoring mechanism. It provides an accurate drive voltage VDRV with strong driving capability.

[0041] like Figure 1 As shown, this embodiment of the invention also provides a detection circuit for detecting the driving voltage VDRV as described above, comprising: a comparator operating in a first power domain (VCCA_5V / GND) for comparing the driving voltage VDRV with a second reference voltage VREF2; a power domain conversion module for converting the output signal of the comparator from the first power domain to the second power domain (VCCA_5V / VDRV); and an output shaping circuit for shaping the signal after power domain conversion and outputting a detection signal VDRV_OK.

[0042] In some embodiments, the comparator is a transconductance amplifier whose differential input pair converts the input differential signal into current.

[0043] like Figure 1 As shown, in this embodiment of the invention, the comparator includes a differential pair transistor, a twentieth P-type LDMOS field-effect transistor PLD20 and a twenty-first P-type LDMOS field-effect transistor PLD21, a first deep N-well N-transistor DNW_NM1, a second deep N-well N-transistor DNW_NM2, a sixteenth P-type LDMOS field-effect transistor PLD16, a seventeenth P-type LDMOS field-effect transistor PLD17, an eighteenth P-type LDMOS field-effect transistor PLD18, a nineteenth P-type LDMOS field-effect transistor PLD19, a twenty-second P-type LDMOS field-effect transistor PLD22, a twenty-third P-type LDMOS field-effect transistor PLD23, a thirteenth N-type LDMOS field-effect transistor NLD13, a fourteenth N-type LDMOS field-effect transistor NLD14, a fifteenth N-type LDMOS field-effect transistor NLD15, a sixteenth N-type LDMOS field-effect transistor NLD16, a seventeenth N-type LDMOS field-effect transistor NLD17, and an eighteenth N-type LDMOS field-effect transistor NLD18; Among them, the gate of the 20th P-type LDMOS field-effect transistor PLD20 receives the driving voltage VDRV, and the gate of the 21st P-type LDMOS field-effect transistor PLD21 receives the second reference voltage VREF2. The sources of both are connected to the drain of the 22nd P-type LDMOS field-effect transistor PLD22, and the drains are grounded through the 14th N-type LDMOS field-effect transistor NLD14 and the 15th N-type LDMOS field-effect transistor NLD15, respectively. The comparator also includes a first deep N-well transistor DNW_NM1 and a second deep N-well transistor DNW_NM2 for receiving the drive voltage VDRV. The gates of the two transistors are connected to each other, and their sources are connected to the drive voltage VDRV generation circuit to receive the drive voltage VDRV. The drain and gate of the first deep N-well transistor DNW_NM1 are connected to each other and to the drain of the eighteenth P-type LDMOS field-effect transistor PLD18. The drain of the second deep N-well transistor DNW_NM2 is connected to the drain of the seventeenth P-type LDMOS field-effect transistor PLD17, and outputs a detection signal to the subsequent output shaping circuit. The source of the thirteenth N-type LDMOS field-effect transistor NLD13 is grounded, and its drain is connected to the drain of the nineteenth P-type LDMOS field-effect transistor PLD19. Its gate is connected to the gate of the fourteenth N-type LDMOS field-effect transistor NLD14 and receives the first enable signal ENB. The source of the fourteenth N-type LDMOS field-effect transistor NLD14 is grounded, and its drain is connected to its gate and the drain of the twentieth P-type LDMOS field-effect transistor PLD20. The source of the fifteenth N-type LDMOS field-effect transistor NLD15 is grounded, and its drain is connected to its gate and the drain of the twentyth P-type LDMOS field-effect transistor PLD21. The fifteenth N-type LDMOS field-effect transistor... The gate of transistor NLD15 is connected to the gate of the sixteenth N-type LDMOS field-effect transistor NLD16 and receives the first enable signal ENB; the source of the sixteenth N-type LDMOS field-effect transistor NLD16 and the seventeenth N-type LDMOS field-effect transistor NLD17 is grounded and the drain is connected to the drain of the sixteenth P-type LDMOS field-effect transistor PLD16; the source of the eighteenth N-type LDMOS field-effect transistor NLD18 is grounded, the drain is connected to the gate and connected to the drain of the twenty-third P-type LDMOS field-effect transistor PLD23, and the gate is connected to the gate of the seventeenth N-type LDMOS field-effect transistor NLD17 and receives the first enable signal ENB; The sources of the sixteenth P-type LDMOS field-effect transistor PLD16 and the seventeenth P-type LDMOS field-effect transistor PLD17 are connected to the power supply voltage, their gates are connected to each other and receive the second enable signal ENA, and are also connected to the drain of the sixteenth P-type LDMOS field-effect transistor PLD16. The drain of the eighteenth P-type LDMOS field-effect transistor PLD18 and the source of the nineteenth P-type LDMOS field-effect transistor PLD19 are connected to the power supply voltage, their gates are connected to each other and receive the second enable signal ENA, and are also connected to the drain of the nineteenth P-type LDMOS field-effect transistor PLD19. The source of the twenty-second P-type LDMOS field-effect transistor PLD22 and the twenty-third P-type LDMOS field-effect transistor PLD23 are connected to the power supply voltage, and the gate is connected to the drive voltage VDRV in the current mirror structure of the circuit.

[0044] In this embodiment of the invention, the output shaping circuit includes a Schmitt trigger (SMT) and a buffer (BUF).

[0045] The key to the detection circuit in this embodiment of the invention lies in its power domain conversion (from VCCA_5V / GND domain to VCCA_5V / VDRV domain) after completing the current mirroring, followed by differential-to-single-ended signal conversion. The comparator's output signal, shaped by a Schmitt trigger, is output as the detection signal VDRV_OK by the buffer BUF. When the drive voltage VDRV is not effectively established, the detection signal VDRV_OK outputs an invalid level (e.g., a high level) to shield the subsequent drive logic, forcibly shutting down the drive circuit, ensuring system reliability, and preventing leakage caused by erroneous turn-on of the PLDMOS during operation.

[0046] This invention also provides a power management system, including a drive voltage VDRV generation circuit as described in the above embodiments and a detection circuit as described in the above embodiments.

[0047] It should be understood that the above are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A driving voltage generating circuit, characterized in that, include: Voltage generation module, error amplification module, and output power transistor; The voltage generation module is used to receive a constant current source to generate a first reference voltage and a second reference voltage. The error amplification module employs a transconductance amplifier, with its first input terminal receiving the first reference voltage and its second input terminal receiving the output voltage feedback from the power stage output from its output terminal. The gate of the output power transistor is controlled by the output voltage of the power stage. Its source is grounded and its drain outputs a drive voltage. The second input terminal of the transconductance amplifier is connected to the drain of the output power transistor to receive the feedback signal of the drive voltage.

2. The driving voltage generating circuit according to claim 1, characterized in that, The voltage generation module includes a first constant current source and a first resistor and a second resistor connected in series. One end of the first resistor is connected to the power supply voltage, and the other end is connected to one end of the second resistor. The other end of the second resistor is connected to the first constant current source through a first N-type LDMOS field-effect transistor. The first reference voltage is obtained from the connection point of the first resistor and the second resistor. The source of the first N-type LDMOS field-effect transistor is connected to the first constant current source, the drain is connected to the other end of the second resistor, and the gate is connected to an enable signal to control its on / off state.

3. The driving voltage generating circuit according to claim 1 or 2, characterized in that, The driving voltage generation circuit further includes a clamping voltage generation circuit, which includes a second constant current source, a third constant current source, and a first current mirror structure. The second constant current source is used to provide a bias voltage to the first current mirror structure, and the first current mirror structure generates at least one clamping voltage to protect subsequent circuits by connecting to the third constant current source.

4. The driving voltage generating circuit according to claim 3, characterized in that, A control module is also connected between the output terminal of the transconductance amplifier and the output power transistor to control the output voltage of the power stage, including: a second N-type LDMOS field-effect transistor, a third N-type LDMOS field-effect transistor, a fourth N-type LDMOS field-effect transistor and a ninth P-type LDMOS field-effect transistor; The source and drain of the second N-type LDMOS field-effect transistor, the third N-type LDMOS field-effect transistor, and the fourth N-type LDMOS field-effect transistor are connected in series. The drain of the second N-type LDMOS field-effect transistor is connected to the power supply voltage, and the source of the fourth N-type LDMOS field-effect transistor is grounded. The gate of the second N-type LDMOS field-effect transistor is connected to the output terminal of the transconductance amplifier to receive the output of the transconductance amplifier, and is mirrored to the output power transistor through the fourth N-type LDMOS field-effect transistor. The gate of the fourth N-type LDMOS field-effect transistor is connected to the gate of the output power transistor and the drain of the fourth N-type LDMOS field-effect transistor. The source of the ninth P-type LDMOS field-effect transistor is connected to the gate of the second N-type LDMOS field-effect transistor, the drain is grounded, and the gate receives a clamping voltage to protect the second N-type LDMOS field-effect transistor. The gate of the third N-type LDMOS field-effect transistor receives a clamping voltage to protect the fourth N-type LDMOS field-effect transistor and the output power transistor.

5. The driving voltage generating circuit according to claim 1, characterized in that, The tail current of the transconductance amplifier is provided by a third constant current source through a second current mirror structure.

6. A detection circuit for detecting the driving voltage as described in any one of claims 1-5, characterized in that, include: A comparator, operating in a first power supply domain, is used to compare the drive voltage with a second reference voltage; A power domain conversion module is used to convert the output signal of the comparator from a first power domain to a second power domain. An output shaping circuit is used to shape the signal after power domain conversion and output a detection signal.

7. The detection circuit according to claim 6, characterized in that, The comparator is a transconductance amplifier, whose differential input pair converts the input differential signal into current.

8. The detection circuit according to claim 6 or 7, characterized in that, The output shaping circuit includes a Schmitt trigger and a buffer.

9. A power management system, characterized in that, It includes the driving voltage generating circuit as described in any one of claims 1-5 and the detection circuit as described in any one of claims 6-8.

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