Storage device and electronic device including the same

Abstract

The invention provides a storage device and an electronic device including the same. The memory device includes a substrate including a first surface extending in a first direction and a second direction intersecting each other; an electronic component disposed on the first surface of the substrate; a connector connected to the host device; a bracket on which the substrate is mounted; and a guide frame disposed in the bracket to support the substrate and having a slot formed to extend to a first length in a first direction, in which the bracket moves along the slot by the first length when loss of power supplied from the host device occurs.

Description

Technical Field

[0001] This disclosure relates to a storage device that can operate stably even in the event of power loss, an electronic device including the storage device, and a method of operating the electronic device. Background Technology

[0002] With increasing data consumption and growing demands for data security, improving the data processing capabilities or performance of server devices is becoming a crucial issue. Furthermore, as the capacity and performance of the functional modules or blocks that constitute server devices and perform data storage or processing increase, the power consumption of each functional module or block also increases.

[0003] Therefore, when power problems such as power loss occur in functional modules or blocks during the operation of a server device, measures are needed to protect data from the impact of power loss. Summary of the Invention

[0004] Generally, in some aspects, this disclosure relates to storage devices that can operate stably even when power is lost, electronic devices that can operate stably even when power is lost, and methods of operating electronic devices that can operate stably even when power is lost.

[0005] According to some implementations, this disclosure relates to a storage device comprising: a substrate including a first surface extending in a first direction and a second direction intersecting each other; electronic components disposed on the first surface of the substrate; a connector connected to a host device; a bracket on which the substrate is mounted; and a guide frame disposed in the bracket to support the substrate and having a slot formed to extend along the first direction to a first length, wherein the bracket moves along the slot by the first length when a loss of power supplied from the host device occurs.

[0006] According to some implementations, this disclosure relates to an electronic device comprising: a storage device; and a host device connected to the storage device, wherein the host device includes a power supply unit that provides main power to the storage device, a baseboard management controller (BMC) module that provides a data refresh command to the storage device when a main power loss occurs, and a power loss protection (PLP) module that provides a detection signal to the BMC module by detecting a main power loss and provides auxiliary power when a main power loss occurs, the storage device including a baseboard, volatile memory and non-volatile memory disposed on the baseboard, a connector disposed at one end of the baseboard and connected to the host device, a bracket on which the baseboard is mounted, and a guide frame having a slot formed to extend to a first length, wherein when a main power loss occurs, the bracket moves along the slot by the first length.

[0007] According to some implementations, this disclosure relates to an electronic device comprising: a storage device; a host device including a power supply unit that provides main power to the storage device; and a latching unit connected to the host device via a switch, wherein the host device includes a BMC module and a PLP module, wherein when the latching unit and the host device are separated, the BMC module provides a data refresh command to the storage device, and the PLP module monitors the power status of the power supply unit and provides auxiliary power to the storage device, the storage device including a substrate, volatile memory and non-volatile memory disposed on the substrate, a connector disposed at one end of the substrate and connected to the host device, a bracket for mounting the substrate thereon, and a guide frame having a slot formed to extend to a first length, wherein when the latching unit and the host device are separated, the bracket moves along the slot by the first length.

[0008] According to some implementations, this disclosure relates to a method of operating an electronic device, the electronic device including a host device, a storage device having a bracket pin and a slot formed corresponding to each other, and a latching unit connected to the host device via a switch. The method includes: detecting an open state of the switch using the host device; providing a data refresh command to the storage device using the host device; and receiving the bracket pin in the slot and moving it along the slot by a first length. Attached Figure Description

[0009] The example implementation will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1 It is a block diagram of an example electronic device based on some implementation methods.

[0011] Figure 2 and Figure 3 It is a perspective view of an example of a storage device based on some implementation methods.

[0012] Figure 4 It depends on some implementation methods. Figure 3 A schematic diagram of an example of a bootstrapping framework.

[0013] Figure 5 It depends on some implementation methods. Figure 4 An enlarged view of an example of a part of the bootstrapping framework.

[0014] Figure 6 and Figure 7 It depends on some implementation methods. Figure 3 A floor plan of the storage device.

[0015] Figure 8 It depends on some implementation methods. Figure 7 A side view of the storage device.

[0016] Figure 9This is a flowchart illustrating an example of how an electronic device operates according to some implementation methods.

[0017] Figures 10 to 13 It is an intermediate diagram used to illustrate the operation of an electronic device according to some implementation methods.

[0018] Figures 14 to 19 It is a block diagram of an example electronic device based on some implementation methods.

[0019] Figure 20 This illustrates an example of a data center with application storage devices implemented in some ways. Detailed Implementation

[0020] The following section will describe an example implementation with reference to the accompanying drawings.

[0021] Figure 1 This is a block diagram illustrating examples of electronic devices based on some implementation methods. Figure 1 In this embodiment, electronic device 10 may include host device 1000 and storage device 2000. Furthermore, storage device 2000 may include storage controller 2100 and non-volatile memory (NVM) 2200. Additionally, in some implementations, host device 1000 may include host controller 1001 and host memory 1002. Host memory 1002 may be used as a buffer for temporarily storing data to be transferred to or received from storage device 2000.

[0022] Storage device 2000 may include a storage medium for storing data according to a request from host device 1000. For example, storage device 2000 may include at least one of a solid-state drive (SSD), embedded memory, and removable external memory. When storage device 2000 is an SSD, it may be a device conforming to the Non-Volatile Memory Faster (NVMe) standard. When storage device 2000 is embedded memory or external memory, it may be a device including the Universal Flash Memory (UFS) standard or the Embedded Multimedia Card (eMMC) standard. Each of host device 1000 and storage device 2000 may generate and transmit data packets according to the adopted standard protocol.

[0023] When the non-volatile memory 2200 of the storage device 2000 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. In some implementations, the storage device 2000 may include various other types of non-volatile memory. For example, the storage device 2000 may include magnetic random access memory (MRAM), spin-torque MRAM, conductive bridged random access memory (CBRAM), ferroelectric random access memory (FeRAM), phase-change random access memory (PRAM), resistive random access memory (RRAM), and various other types of memory.

[0024] In some implementations, the host controller 1001 and the host memory 1002 can be implemented as separate semiconductor chips. In other implementations, the host controller 1001 and the host memory 1002 can be integrated into the same semiconductor chip. For example, the host controller 1001 can be any of a plurality of modules included in an application processor, which can be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 1002 can be embedded memory included in the application processor, or it can be non-volatile memory or a memory module disposed externally to the application processor.

[0025] The host controller 1001 can manage operations that store data in the buffer area (e.g., write the data) in the non-volatile memory 2200 or store data in the non-volatile memory 2200 (e.g., read the data) in the buffer area.

[0026] The storage controller 2100 may include a host interface 2110, a memory interface 2120, and a central processing unit (CPU) 2130. Additionally, the storage controller 2100 may also include a flash translation layer (FTL) 2140, a packet manager 2150, a buffer memory 2160, an error correction code (ECC) engine 2170, and an Advanced Encryption Standard (AES) engine 2180.

[0027] The storage controller 2100 may also include working memory to which an FTL 2140 is loaded. Data write and read operations to the non-volatile memory 2200 can be controlled by executing the FTL 2140 using the CPU 2130.

[0028] The host interface 2110 can send data packets to and receive data packets from the host device 1000. Data packets sent from the host device 1000 to the host interface 2110 may include commands or data to be written to the non-volatile memory 2200, and data packets sent from the host interface 2110 to the host device 1000 may include responses to commands or data read from the non-volatile memory 2200.

[0029] The memory interface 2120 can send data to be written to the non-volatile memory 2200, or can receive data read from the non-volatile memory 2200. The memory interface 2120 can be implemented to conform to standard protocols such as Toggle or ONFI.

[0030] The FTL 2140 can perform various functions, such as address mapping, wear leveling, and garbage collection. Address mapping is the process of translating logical addresses received from the host into physical addresses used to actually store data in the non-volatile memory 2200. Wear leveling is a technique used to prevent excessive degradation of specific blocks by ensuring that blocks in the non-volatile memory 2200 are used evenly. For example, wear leveling can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection is a technique used to ensure available capacity in the non-volatile memory 2200 by copying valid data from blocks to new blocks and then erasing existing blocks.

[0031] The packet manager 2150 can generate data packets according to the protocol of the interface agreed upon with the host device 1000, or it can parse various information from data packets received from the host device 1000. Furthermore, the buffer memory 2160 can temporarily store data to be written to or read from the non-volatile memory 2200. The buffer memory 2160 can be a component included in the storage controller 2100, or it can be located outside the storage controller 2100.

[0032] The ECC engine 2170 can perform error detection and correction functions on data read from the non-volatile memory 2200. More specifically, the ECC engine 2170 can generate parity bits for the write data to be written to the non-volatile memory 2200, and the generated parity bits can be stored in the non-volatile memory 2200 along with the write data. When reading data from the non-volatile memory 2200, the ECC engine 2170 can use the read data and the parity bits to correct errors in the read data and can output the error-corrected read data.

[0033] The AES engine 2180 can perform at least one of encryption and decryption operations on the data input to the storage controller 2100 using a symmetric key algorithm.

[0034] Figure 2 and Figure 3 This is a perspective view of an example of a storage device 2000 based on some implementation methods. Figure 4 It depends on some implementation methods. Figure 3 A schematic diagram of an example of the bootstrap framework 500. Figure 5 It depends on some implementation methods. Figure 4 An enlarged image of a portion of the Bootstrap 500 example. Figure 6 and Figure 7 It depends on some implementation methods. Figure 3 Floor plan of storage device 2000. Figure 8 It depends on some implementation methods. Figure 7 Side view of the storage device 2000.

[0035] exist Figure 2 and Figure 3 In this device, storage device 2000 may include a substrate 100, a lower housing 200, electronic components CHP, a connector 300, a bracket 400, a guide frame 500, and a latching unit 600. Storage device 2000 may be substantially shaped like a cuboid. The appearance of storage device 2000 may follow standardized or arbitrary shape factors. The dimensions of the cuboid-shaped storage device 2000 can also be varied according to various standards.

[0036] The substrate 100 may include one or more insulating layers and wiring layers. The substrate 100 may include, for example, a printed circuit board. The substrate 100 may include a first surface 100_1 and a second surface 100_2 opposite to each other. The first surface 100_1 and the second surface 100_2 may extend in a first direction X and a second direction Y that intersect each other. The first surface 100_1 and the second surface 100_2 may be opposite to each other in a third direction Z that perpendicularly intersects each of the first direction X and the second direction Y. The first surface 100_1 and the second surface 100_2 of the substrate 100 may refer to an upper surface and a lower surface, respectively.

[0037] The substrate 100 may include one or more fastening holes 110H. The fastening holes 110H may penetrate the substrate 100 in a third direction Z. Each fastening hole 110H may provide space for fastening members (such as screws or bolts) to be inserted therein, but this disclosure is not limited thereto.

[0038] The fastening hole 110H can be provided at the corner of the substrate 100. However, this disclosure is not limited thereto, and the fastening hole 110H can also be omitted from some corners or can be further installed in areas other than corners (e.g., the central portion, the area adjacent to the side).

[0039] The lower housing 200 can be disposed below the substrate 100 and can cover the lower part of the substrate 100. The lower housing 200 may include a space therein capable of accommodating the substrate 100 and the electronic component CHP.

[0040] For example, the lower housing 200 may include a material with high thermal conductivity to dissipate heat generated from the electronic component CHP to the outside, but this disclosure is not limited thereto.

[0041] In some implementations, the storage device 2000 may not include an upper housing covering the upper part of the substrate 100.

[0042] The electronic component CHP can be disposed on the first surface 100_1 and / or the second surface 100_2 of the substrate 100. The electronic component CHP can be manufactured in the form of a chip separate from the substrate 100 and then mounted on the substrate 100.

[0043] Electronic components (CHPs) can include semiconductor components. For example, semiconductor components can include non-volatile memory (such as NAND flash memory), volatile memory (such as dynamic random access memory (DRAM)), and a memory controller that controls the memory. In some implementations, such as Figure 1 The storage controller 2100, host interface 2110, memory interface 2120, CPU 2130, and buffer memory 2160 shown can be manufactured and mounted on the substrate 100 in the form of electronic components CHP. In some implementations, the electronic components CHP may also include capacitor elements. Each electronic component CHP can be connected to wiring on the substrate 100 to perform electrical operation. The electronic components CHP can be spaced apart from each other. Horizontal gaps can be defined in each space between the electronic components CHP. The horizontal gaps can be filled with air or the like.

[0044] Connector 300 may be disposed at one end of substrate 100. Connector 300 may be connected to substrate 100. Connector 300 may be provided as a separate component from substrate 100 and attached to substrate 100. However, in some implementations, connector 300 may also be integral with substrate 100. When connector 300 is integral with substrate 100, it may be provided in a protruding region of substrate 100, in which a portion of substrate 100 protrudes outward.

[0045] Connector 300 may include a plurality of connection terminals EL. The connection terminals EL may be spaced apart from each other along a second direction Y. Each connection terminal EL of connector 300 may be connected to host device 1000 (see...). Figure 1 The corresponding connection part of ).

[0046] Each connection terminal EL of connector 300 can be connected to the wiring of substrate 100. When connector 300 is integral with substrate 100, the connection terminals EL of connector 300 can be formed on the same layer using the same material as the wiring of substrate 100. The connection terminals EL can be at least partially exposed to the outside without being covered by an insulating layer.

[0047] The substrate 100 can be mounted on the bracket 400. The bracket 400 may include a first pin 411P and a second pin 412P protruding in the first direction X, and a third pin 413P and a fourth pin 414P protruding in the second direction Y.

[0048] The first pin 411P and the second pin 412P may extend in the first direction X and may be spaced apart from each other in the second direction Y. The third pin 413P and the fourth pin 414P may extend in the second direction Y and may be spaced apart from each other in the second direction Y.

[0049] The first pin 411P, the second pin 412P, the third pin 413P, and the fourth pin 414P can be connected to the boot frame 500 described below.

[0050] A guide frame 500 may be disposed in a bracket 400 and may support a substrate 100. At least one slot 510S and at least one frame hole 510H may be formed in the guide frame 500. The frame hole 510H may correspond to each fastening hole 110H and provide space for fastening members (such as screws or bolts) to be inserted therein, but this disclosure is not limited thereto.

[0051] The guide frame 500 may include a first member 510 and a second member 520, which are parallel to each other in a first direction X and face each other in a second direction Y. When the substrate 100 is supported, the first member 510 and the second member 520 may be spaced apart from each other so that they face each other in the second direction Y.

[0052] One end 510_E1 and the other end 510_E2 of the first member 510 may protrude toward the interior of the substrate 100 in the second direction Y. One end 520_E1 and the other end 520_E2 of the second member 520 may protrude toward the interior of the substrate 100 in the second direction Y.

[0053] The first member 510 and the second member 520 can support the substrate 100. One side of the substrate 100 can be supported by the first member 510, and the other side of the substrate 100 opposite to the first side can be supported by the second member 520. A first groove 510A can be formed in the first member 510, and a second groove 520A can be formed in the second member 520. The one side and the other side of the substrate 100 can be inserted into the first groove 510A of the first member 510 and the second groove 520A of the second member 520, respectively, and thus can be stably supported.

[0054] One end 510_E1 and the other end 510_E2 of the first component 510, and one end 520_E1 and the other end 520_E2 of the second component 520, can respectively cover the corners of the substrate 100. However, in some implementations, the first component 510 and the second component 520 may not completely cover the substrate 100. For example, the first component 510 and the second component 520 may expose the portions of the substrate 100 on which the electronic components CHP and the connector 300 are formed.

[0055] The slot 510S may be formed in at least one of the first member 510 and the second member 520. The slot 510S may extend along the first direction X to a first length D1.

[0056] For example, Figure 5 A slot 510S formed in a portion of the first member 510 is shown. The slot 510S can be shaped like a hole that completely penetrates the first member 510. However, in some implementations, the slot 510S can also be shaped like a recess that partially, rather than completely, penetrates the first member 510. The aforementioned length of the slot 510S is merely an example, and this disclosure is not limited to the length shown in the figures. For example, as will be described later, the length of the slot 510S can be appropriately varied within the first member 510 to ensure data refresh time. For example, the length of the slot 510S can be equal to or less than the length of the first member 510 in the first direction X.

[0057] Figure 6 This shows the occurrence of the first main power MPWR1 (see...) Figure 14 Storage device 2000 before loss (e.g., before the bracket 400 is moved). Figure 7 and Figure 8 This shows that when bracket 400 is powered by the first main power MPWR1 (see...) Figure 14 Storage device 2000 when it is lost and moved.

[0058] exist Figure 7 and Figure 8 In the middle, when the first main power MPWR1 occurs (see Figure 14When the bracket 400 is lost, it can move a first length D1 along the slot 510S in the first direction X. The third pin 413P of the bracket 400 can be accommodated in the slot 510S to enable the bracket 400 to move. The distance the bracket 400 moves can be equal to the first length D1 of the slot 510S.

[0059] The latching unit 600 can be connected to the main unit 1000 via a switch (see...). Figure 14 When latching unit 600 and main unit 1000 (see...) Figure 14 When connected, the latch unit 600 can enter the latch closed state. When the latch unit 600 and the main unit 1000 (see...) Figure 14 When separated, it can enter the latch open state. The latch open state can refer to the switch being in the off state.

[0060] For example, the latching unit 600 can be detachably provided in the lower housing 200. (Will use) Figures 9 to 13 The latch unit 600 is described in more detail.

[0061] Figure 9 This is a flowchart illustrating an example of how an electronic device operates according to some implementation methods. Figures 10 to 13 It is an intermediate diagram used to illustrate the operation of an electronic device according to some implementation methods.

[0062] Figure 10 The latching unit 600 and the main unit 1000 are shown (see...) Figure 14 In this case, the latch unit 600 is electrically connected to the main unit 1000 (see switch 1000) to enter the latch-off state. Figure 14 The connector 300 has a solder pad (not shown) at one end. The connector 300 can be connected to the host device 1000 (see...). Figure 14 The other end of 1000_1.

[0063] Figure 11 The latching unit 600 and the main unit 1000 are shown (see...) Figure 14 The latch unit 600 is separated from the main unit 1000 to enter the latch open state. In this case, the latch unit 600 can be switched on and off by a switch located in the main unit 1000 (see...). Figure 14 The pads at one end of the circuit are electrically decoupled.

[0064] exist Figure 9 and Figure 11 In, for example, it may be in host device 1000 (see Figure 14 A problem occurs in some of the components of the storage device 2000, resulting in a sudden loss of power supply. In this situation, the latching unit 600 and the host device 1000 (see...) Figure 14It can be separated to enter the latch open state and the switch open state (operation S100).

[0065] Next, host device 1000 (see Figure 14 It can detect the switch being open (operation S200). Main unit 1000 (see...) Figure 14 The switch-off state can be detected by the wires electrically connected to connector 300. More specifically, the board management controller (BMC) module 1120, which will be described later (see...) Figure 14 The switch can be detected as open by using a wire.

[0066] Next, in Figure 9 and Figure 12 In the middle, the main unit 1000 (see Figure 14 ) can be sent to storage device 2000 (see Figure 3 ) provides the data refresh command FCMD (see Figure 15 (Operation S300). Therefore, the bracket 400 can move along the slot 510S (see...) Figure 8 Move the first length D1 (see) Figure 7 More specifically, the third pin (which may also be referred to as the bracket pin) 413P (see...) Figure 8 ) can be along the slot 510S (see Figure 8 Move the first length D1 (see) Figure 7 ).

[0067] The bracket 400 can be configured to receive electrical signals (such as the data refresh command FCMD, see...) Figure 15 The electronic component CHP is transmitted to the storage device 2000.

[0068] Therefore, the data refresh time can be increased corresponding to the first length D1 (see...) Figure 7 The time (operation S400).

[0069] Next, in Figure 9 and Figure 13 In the middle, along the slot 510S in bracket 400 (see Figure 8 Move the first length D1 (see) Figure 7 After that, data refresh can be completed (operation S500). More specifically, at the third pin 413P (see... Figure 8 ) along slot 510S (see Figure 8 Move the first length D1 (see) Figure 7 After that, data refresh can be completed. Connector 300 can connect to host device 1000 (see...) Figure 14 The other end 1000_1 is separated.

[0070] When the bracket 400 is aligned with the slot 510S as described above (see...) Figure 8 When moving, the data refresh time can be delayed by a time corresponding to the distance moved. For example, the data refresh time can be, but is not limited to, about 100 ms or more. According to some implementations, by delaying the data refresh time via a slot 510S formed in the storage device 2000, it is possible to minimize the potential for data refresh issues between the latch unit 600 and the host device 1000 (see...). Figure 14 Data loss that occurs during separation.

[0071] Figure 14 and Figure 15 This is a block diagram of an example of an electronic device 10A based on some implementation methods. For reference, Figure 14 This shows the main power supply situation. Figure 15 This illustrates a situation where auxiliary power is supplied due to the loss of main power.

[0072] exist Figure 14 and Figure 15 In this device, electronic device 10A may include host device 1000 and storage module (circuit) 1400. Host device 1000 may include motherboard 1100, power loss protection (PLP) module (circuit) 1200 and backplane 1300.

[0073] The motherboard 1100 may include a power supply unit 1110, a first CPU 1111, a second CPU 1112, first memory (MEM) 1121 to fourth memory (MEM) 1124, and a BMC module (circuit) 1120. The power supply unit 1110, the first CPU 1111, the second CPU 1112, the first memory 1121 to fourth memory 1124, and the BMC module 1120 may be mounted on the motherboard 1100.

[0074] exist Figure 14 In this configuration, the power supply unit 1110 can receive power from an external device and supply a first main power MPWR1 to the storage module 1400 via the motherboard 1100. The first CPU 1111, the second CPU 1112, the first memory 1121 to the fourth memory 1124, and the BMC module 1120, all mounted on the motherboard 1100, can operate based on the first main power MPWR1.

[0075] The first memory 1121 and the second memory 1122 can be electrically connected to the first CPU 1111. The third memory 1123 and the fourth memory 1124 can be electrically connected to the second CPU 1112.

[0076] The first CPU 1111 and the second CPU 1112 can be configured to run an operating system and various applications. For example, the first CPU 1111 and the second CPU 1112 may include various accelerators (or accelerated processors) configured to perform unique operations, such as graphics processing units (GPUs), digital signal processors (DSPs), image signal processors (ISPs), and neural processing units (NPUs), but this disclosure is not limited thereto.

[0077] The first CPU 1111 can use the first memory 1121 and the second memory 1122 as its working memory. The second CPU 1112 can use the third memory 1123 and the fourth memory 1124 as its working memory. For example, the first memory 1121 to the fourth memory 1124 can be DRAM and can have a dual in-line memory module (DIMM) form factor. However, this disclosure is not limited thereto, and the first memory 1121 to the fourth memory 1124 can also include non-volatile memory, such as flash memory, PRAM, RRAM, MRAM, etc.

[0078] The first CPU 1111 and the second CPU 1112 can control components disposed on the motherboard 1100. For example, the first CPU 1111 and the second CPU 1112 can control components disposed on the motherboard 1100 based on the Peripheral Component Interconnect High Speed ​​(PCIe), but this disclosure is not limited thereto.

[0079] BMC module 1120 can control the supply of the first main power MPWR1 received from power supply unit 1110 to the first CPU 1111, the second CPU 1112, and the first memory 1121 to the fourth memory 1124.

[0080] PLP module 1200 may include a first energy module (circuit) 1210 and a second energy module (circuit) 1220. The first energy module 1210 may include a first controller 1211 and a first capacitor 1212. The second energy module 1220 may include a second controller 1221 and a second capacitor 1222. Each of the first controller 1211 and the second controller 1221 may monitor the power status of the power supply unit 1110.

[0081] As will be described below, when the first main power MPWR1 is lost, the first capacitor 1212 and the first controller 1211 can supply first auxiliary power to the storage module 1400, and the second capacitor 1222 and the second controller 1221 can supply second auxiliary power to the storage module 1400.

[0082] The power supply unit 1110 can charge the first capacitor 1212 and the second capacitor 1222 by supplying energy to the first capacitor 1212 and the second capacitor 1222. For example, each of the first capacitor 1212 and the second capacitor 1222 can be, but is not limited to, an aluminum (Al) capacitor.

[0083] For example, the first energy module 1210 and the second energy module 1220 can be disposed on a printed circuit board. The first energy module 1210 can be mounted on the printed circuit board via a first PLP module connector (CNT1) 1213. The second energy module 1220 can be mounted on the printed circuit board via a second PLP module connector (CNT2) 1223.

[0084] Despite Figure 14 and Figure 15 Two energy modules are shown in the figure, but the number of energy modules is not limited to the number shown in the figure.

[0085] The backplane 1300 can transmit the first main power MPWR1 supplied from the power supply unit 1110 to the storage module 1400.

[0086] A backplane 1300 may be disposed between the host device 1000 and the storage module 1400 to connect the host device 1000 and the storage module 1400. The backplane 1300 may be configured to allow the host device 1000 and the storage module 1400 to exchange data via various communication protocols.

[0087] The backplane 1300 may include a switch module 1310 and a multiplexer (MUX) 1320.

[0088] For example, the switching module 1310 can selectively supply power to at least one of the storage devices 2000a to 2000n of the storage module 1400. The switching module 1310 can supply power to the storage devices 2000a to 2000n that require power supply according to the switching operation.

[0089] The backplane 1300 may include storage device connectors corresponding to and respectively connected to the storage devices 2000a to 2000n.

[0090] Storage module 1400 may refer to a collection of storage devices 2000a to 2000n. Each of the storage devices 2000a to 2000n may be associated with... Figure 3 The storage device 2000 corresponds to the component. Each of the storage devices 2000a to 2000n may include non-volatile memory, volatile memory, and memory controller. Here, the non-volatile memory, volatile memory, and memory controller may be components included in... Figure 3The electronic components in CHP.

[0091] exist Figure 15 In this module, PLP module 1200 can monitor the power status of power supply unit 1110. PLP module 1200 can detect the first main power MPWR1 (see... Figure 14 The first controller 1211 can monitor the power status of the power supply unit 1110 and detect the first main power MPWR1 (see [link to relevant documentation]). Figure 14 The system detects the power disconnection state and outputs a detection signal DS.

[0092] PLP module 1200 can provide the output detection signal DS to BMC module 1120. For example, first controller 1211 can provide the output detection signal DS to BMC module 1120.

[0093] The first controller 1211 can monitor the electrical state of the first capacitor 1212 and control the charging and / or discharging of the first capacitor 1212, so that the first auxiliary power APWR is supplied to the storage devices 2000a to 2000n. The first controller 1211 and the first capacitor 1212 can send and receive the first monitoring signal MS.

[0094] The second controller 1221 can monitor the electrical state of the second capacitor 1222 and control the charging and / or discharging of the second capacitor 1222, so that the second auxiliary power is supplied to the storage devices 2000a to 2000n. The second controller 1221 and the second capacitor 1222 can send and receive a second monitoring signal (not shown).

[0095] The exemplary description of the operation of the first controller 1211 and the first capacitor 1212 can be similarly applied to the operation of the second controller 1221 and the second capacitor 1222.

[0096] When the first main power MPWR1 occurs (see...) Figure 14 When the data is lost, the BMC module 1120 can provide a data refresh command FCMD to the storage module 1400 through the MUX 1320. For example, the BMC module 1120 can receive the detection signal DS output from the first controller 1211 and provide the data refresh command FCMD to the storage module 1400.

[0097] When the first main power MPWR1 occurs (see...) Figure 14 When the first auxiliary power APWR and the second auxiliary power are lost, the backplane 1300 can transmit the aforementioned first auxiliary power APWR and second auxiliary power to the storage devices 2000a to 2000n via the MUX 1320.

[0098] The switching module 1310 can supply energy to the storage module 1400 using either the first capacitor 1212 or the second capacitor 1222. For example, if either the first capacitor 1212 or the second capacitor 1222 fails to operate properly due to a problem, the switching module 1310 can supply energy to the storage module 1400 from a normal capacitor according to a switching operation.

[0099] BMC module 1120 can send data to and receive data from storage devices 2000a to 2000n based on out-of-band communication. BMC module 1120 and storage devices 2000a to 2000n can be configured to support out-of-band communication.

[0100] Through this process, even if the main power is lost, the energy of the charged capacitor can be used to supply auxiliary power to the storage module 1400. When the main power is lost, the BMC module 1120 can retain the data in the volatile memory or refresh the data to the non-volatile memory.

[0101] Figure 16 This is a block diagram of an example electronic device 10B based on some implementation methods. For ease of description, the following description will focus on its use. Figures 1 to 15 The differences described.

[0102] exist Figure 16 In the electronic device 10B, the backplane 1300 may include a first energy module 1210 and a second energy module 1220. That is, the PLP module formed by the first energy module 1210 and the second energy module 1220 is included in the backplane 1300.

[0103] The backplane 1300 may include a first energy module 1210 and a second energy module 1220 that monitor the power status of the power supply unit 1110 and output a detection signal DS.

[0104] In this case, the first energy module 1210 and the second energy module 1220 may not be provided as separate modules from the backplane 1300, but may be included in the backplane 1300.

[0105] Despite Figure 16 Two energy modules are shown in the figure, but the number of energy modules is not limited to the number shown in the figure.

[0106] Figure 17 This is a block diagram of an example of an electronic device 10C based on some implementation methods. For ease of description, the following description will focus on its use. Figures 1 to 16 The differences described.

[0107] exist Figure 17In the electronic device 10C, the controller of the energy module can be located outside the energy module.

[0108] The first energy module 1210 may include a first capacitor 1212, and the first controller 1211 may be located outside the first energy module 1210. The first controller 1211 may be directly mounted on the backplane 1300.

[0109] The second energy module 1220 may include a second capacitor 1222, and the second controller 1221 may be located outside the second energy module 1220. The second controller 1221 may be directly mounted on the backplane 1300.

[0110] Figure 18 This is a block diagram of an example of an electronic device 10D based on some implementation methods. For ease of description, the following description will focus on its use. Figures 1 to 17 The differences described.

[0111] exist Figure 18 In the electronic device 10D, the BMC module 1120 and the storage devices 2000a to 2000n can be directly connected via signal line 1500 without going through backplane 1300.

[0112] BMC module 1120 can provide data refresh command FCMD to storage devices 2000a to 2000n via signal line 1500, which is directly connected to storage devices 2000a to 2000n.

[0113] Figure 19 This is a block diagram of an example electronic device 10E based on some implementation methods. For ease of description, the following description will focus on its use. Figures 1 to 18 The differences described.

[0114] exist Figure 19 In the electronic device 10E, the host device 1000 may further include a battery module (circuit) 1130 that supplies a second main power MPWR2 to storage devices 2000a to 2000n. The battery module 1130 may be mounted on the motherboard 1100. The battery module 1130 may be provided as a separate component from the power supply unit 1110. For example, the battery module 1130 may be configured to supply the second main power MPWR2 when the first main power MPWR1 is not normally supplied from the power supply unit 1110.

[0115] Figure 20 This illustrates a data center 3000 with application storage devices implemented in several ways. Figure 20In this context, data center 3000 is a facility that collects various types of data and provides services, and may also be referred to as a data storage center. Data center 3000 can be a system for operating search engines and databases, and can be a computing system used in companies such as banks or government agencies. Data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m can be selected in various ways depending on the implementation. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m can differ from each other.

[0116] Application server 3100 may include at least one of processor 3110 and memory 3120, and storage server 3200 may include at least one of processor 3210 and memory 3220. For example, in storage server 3200, processor 3210 may control the overall operation of storage server 3200 and may access memory 3220 to execute commands and / or data loaded into memory 3220. Memory 3220 may be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVDIMM). Depending on some implementations, the number of processors 3210 and the number of memories 3220 included in storage server 3200 can be selected in various ways.

[0117] In some implementations, processor 3210 and memory 3220 may provide a processor-memory pair. In some implementations, the number of processors 3210 and the number of memories 3220 may differ from each other. Processor 3210 may include a single-core processor or a multi-core processor. The above description of storage server 3200 can be similarly applied to application server 3100. Storage device 3150 of application server 3100 may be optional. In some implementations, application server 3100 may include storage device 3150. In some implementations, application server 3100 may not include storage device 3150. Storage server 3200 may include at least one storage device 3250. Depending on the implementation, the number of storage devices 3250 included in storage server 3200 may be selected in various ways.

[0118] The aforementioned storage component can be installed on or removed from the storage server 3200, which serves as the host, in the form of a storage device 3250.

[0119] Application servers 3100 to 3100n and storage servers 3200 to 3200m can communicate with each other via network 3300. Network 3300 can be implemented using Fibre Channel (FC) or Ethernet. Here, FC can be a medium for relatively high-speed data transmission and can utilize optical switches that provide high performance / high availability. Depending on the access method of network 3300, storage servers 3200 to 3200m can be provided as file storage, block storage, or object storage.

[0120] In some implementations, network 3300 can be a storage-specific network, such as a storage area network (SAN). For example, the SAN can be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN can be an IP-SAN implemented using a TCP / IP network and according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In some implementations, network 3300 can be a general-purpose network such as a TCP / IP network. For example, network 3300 can be implemented according to protocols such as Ethernet FC (FCoE), Network Attached Storage (NAS), or Fibre Channel NVMe (NVMe-oF).

[0121] The following description will focus on application server 3100 and storage server 3200. The description of application server 3100 can also be applied to other application servers 3100n, and the description of storage server 3200 can also be applied to other storage servers 3200m.

[0122] Application server 3100 can store data requested by users or clients in one of storage servers 3200 to 3200m via network 3300. Furthermore, application server 3100 can obtain data requested by users or clients from one of storage servers 3200 to 3200m via network 3300. For example, application server 3100 can be implemented as a web server or a database management system (DBMS).

[0123] Application server 3100 can access memory 3120n or storage device 3150n included in another application server 3100n via network 3300, or access memory 3220 to 3220m or storage device 3250 to 3250m included in storage servers 3200 to 3200m via network 3300. Therefore, application server 3100 can perform various operations on data stored in application servers 3100 to 3100n and / or storage servers 3200 to 3200m. For example, application server 3100 can execute commands for transferring or copying data between application servers 3100 to 3100n and / or storage servers 3200 to 3200m. In this configuration, data can be transferred from storage devices 3220 to 3220m of storage servers 3200 to 3200m or directly from storage devices 3250 to 3250m of storage servers 3200 to 3200m to storage devices 3120 to 3120n of application servers 3100 to 3100n. Data transmitted over network 3300 may be encrypted for security or privacy purposes.

[0124] For example, in storage server 3200, interface 3254 can provide physical connectivity between processor 3210 and controller (CTRL) 3251, and between network interface controller (NIC) 3240 and controller 3251. For example, interface 3254 can be implemented as a Direct Attached Storage (DAS) interface that directly connects storage device 3250 to a dedicated cable. Furthermore, interface 3254 can be implemented as various interfaces such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCIexpress (PCIe), NVM express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded MMC (eMMC), Universal Flash Memory (UFS), Embedded UFS (eUFS), and Compact Flash Memory (CF) card interfaces.

[0125] Storage server 3200 may further include switch 3230 and NIC 3240. Switch 3230 can selectively connect processor 3210 and storage device 3250 or selectively connect NIC 3240 and storage device 3250 under the control of processor 3210. Application server 3100 may further include switch 3130 and NIC 3140. Switch 3130 can selectively connect processor 3110 and storage device 3150 or selectively connect NIC 3140 and storage device 3150 under the control of processor 3110.

[0126] In some implementations, NIC 3240 may include a network interface card, network adapter, etc. NIC 3240 can connect to network 3300 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 3240 may include internal memory, DSP, host bus interface, etc., and can connect to processor 3210 and / or switch 3230 via the host bus interface. The host bus interface can be implemented as one of the above examples of interface 3254. In some implementations, NIC 3240 can be integrated with at least one of processor 3210, switch 3230, and storage device 3250.

[0127] In storage servers 3200 to 3200m or application servers 3100 to 3100n, the processor can program or read data by sending commands to storage devices 3150 to 3150n or 3250 to 3250m or memory 3120 to 3120n or 3220 to 3220m. Here, data can be error-corrected via an ECC engine. The data can be processed via Data Bus Inversion (DBI) or Data Masking (DM) and may include Cyclic Redundancy Check (CRC) information. The data can be encrypted for security or privacy.

[0128] Storage devices 3150 to 3150n or 3250 to 3250m can send control signals and command / address signals to NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. Therefore, data can be read from NAND flash memory devices 3252 to 3252m. In this case, the read enable (RE) signal can be used as a data output control signal input and can be used to output data to the DQ bus. The RE signal can be used to generate a data strobe (DQS). Command and address signals can be latched into the page buffer based on the rising or falling edge of the write enable (WE) signal.

[0129] Controller 3251 can control the overall operation of storage device 3250. In some implementations, controller 3251 may include static random access memory (SRAM). Controller 3251 can write data to NAND flash memory device 3252 in response to a write command, or can read data from NAND flash memory device 3252 in response to a read command. For example, write and / or read commands may be provided from processor 3210 in storage server 3200, processor 3210m in another storage server 3200m, or processor 3110 or 3110n in application server 3100 or 3100n. DRAM 3253 can temporarily store (buffer) data to be written to or read from NAND flash memory device 3252. In addition, DRAM 3253 can store metadata. Here, metadata is user data or data generated by controller 3251 to manage NAND flash memory device 3252. Storage device 3250 may include a security element (SE) for security or privacy.

[0130] Although this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of any claims that may be claimed, their equivalents, or the claims described later. Certain features described in this disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from that combination, which may be for sub-combinations or variations thereof.

[0131] This application claims the benefits of Korean Patent Application No. 10-2024-0062510 filed with the Korean Intellectual Property Office on May 13, 2024, and Korean Patent Application No. 10-2024-0123636 filed with the Korean Intellectual Property Office on September 11, 2024, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A storage device, comprising: The substrate includes a first surface extending in a first direction and a second direction that intersect each other; Electronic components are disposed on the first surface of the substrate; Connector, used to connect to the host device; The base plate is mounted on the bracket; as well as A guide frame, disposed in the bracket, is configured to support the substrate and has a slot extending along the first direction to a first length. In the event of a loss of power from the host device, the bracket is configured to move along the slot by the first length.

2. The storage device according to claim 1, The guide frame includes a first member and a second member that are parallel to each other in the first direction and face each other in the second direction, and The slot is formed in at least one of the first member and the second member.

3. The storage device of claim 2, wherein the slot penetrates the first member.

4. The storage device of claim 2, wherein the slot partially passes through the first member.

5. The storage device according to claim 2, wherein the length of the slot is equal to or less than the length of the first member in the first direction.

6. The storage device according to claim 2, A first groove is formed in the first member, and one side of the substrate is configured to be inserted into the first groove. The second groove is formed in the second member, and the other side of the substrate is configured to be inserted into the second groove.

7. The storage device according to claim 1, The bracket includes a first pin and a second pin extending in the first direction. The bracket further includes a third pin and a fourth pin extending in the second direction, and in, When the loss of power occurs, the third pin is configured to move the first length along the slot.

8. The storage device of claim 7, wherein the first pin, the second pin, the third pin, and the fourth pin are coupled to the guide frame.

9. The storage device of claim 1, wherein the electronic element comprises volatile memory and non-volatile memory.

10. The storage device of claim 1, wherein the connector is disposed at one end of the substrate and includes a plurality of connection terminals connected to the host device.

11. The storage device of claim 1, further comprising a latching unit connected to the host device. in, When the latch unit and the main unit are separated, the bracket is configured to move along the slot by the first length.

12. An electronic device, comprising: Storage device; and The host device is connected to the storage device. The host device includes: A power supply unit is configured to supply main power to the storage device; A baseboard management controller (BMC) circuit is configured to provide a data refresh command to the storage device in the event of a loss of main power; and A power loss protection (PLP) circuit is configured to provide a detection signal to the BMC circuit by detecting the loss of the main power and to supply auxiliary power when the loss of the main power occurs. The storage device includes: substrate; Volatile memory and non-volatile memory are disposed on the substrate; A connector, disposed at one end of the substrate and configured to connect to the host device; and A bracket and a guide frame, wherein the substrate is mounted on the bracket, and the guide frame has a slot formed extending to a first length. When the loss of main power occurs, the bracket is configured to move the first length along the slot.

13. The electronic device according to claim 12, wherein, When the loss of main power occurs, the BMC circuit is configured to refresh the data in the volatile memory to the non-volatile memory.

14. The electronic device according to claim 12, The substrates extend in a first direction and a second direction that intersect each other. The bracket includes a first pin and a second pin extending in the first direction, and the bracket further includes a third pin and a fourth pin extending in the second direction. in, When the loss of main power occurs, the third pin is configured to be received in the slot and move the first length.

15. The electronic device according to claim 12, The PLP circuit includes: The first energy circuit includes a first capacitor and a first controller that supply first auxiliary power to the storage device; and The second energy circuit includes a second capacitor and a second controller that supply second auxiliary power to the storage device. The first controller is configured to monitor the electrical state of the first capacitor and control the first capacitor to supply the first auxiliary power to the storage device. The second controller is configured to monitor the power status of the second capacitor and control the second capacitor to supply the second auxiliary power to the storage device.

16. The electronic device of claim 15, wherein each of the first capacitor and the second capacitor is an aluminum capacitor.

17. The electronic device of claim 15, wherein the host device further includes a backplane configured to transmit the first auxiliary power and the second auxiliary power to the storage device in the event of the loss of the main power.

18. An electronic device comprising: Storage device; The host device includes a power supply unit configured to supply main power to the storage device; as well as The latching unit is connected to the main unit via a switch. The host device includes: A baseboard management controller (BMC) circuit is configured to provide a data refresh command to the storage device when the latch unit and the host device are separated; and A power loss protection (PLP) circuit is configured to monitor the power status of the power supply unit and supply auxiliary power to the storage device, and The storage device includes: substrate; Volatile memory and non-volatile memory are disposed on the substrate; A connector is disposed at one end of the substrate and connected to the host device; The bracket, on which the substrate is mounted; and The guide frame has a slot formed extending to a first length. When the latching unit and the main unit are separated, the bracket moves along the slot by the first length.

19. The electronic device according to claim 18, wherein, When the latch unit and the host device are separated, the data refresh time increases by a time corresponding to the first length.

20. The electronic device of claim 18, wherein the host device further includes a backplane configured to transmit the auxiliary power to the storage device.

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