A high-efficiency memory repair system and method based on pooled memory

Abstract

The application provides a high-efficiency memory repair system and method based on a pooling memory, which comprises a memory test module for detecting UCE error addresses of a memory bank with cacheline as a granularity; a management module for converting memory error addresses into memory page addresses, and issuing repair commands for the memory page addresses; an address routing module for replacing and adding the memory page addresses into a routing table by using a routing lookup table algorithm to complete address repair, and for performing corresponding address conversion and routing to a port where the memory bank or the out-of-band storage module is located according to a repair state of a host memory address accessed; and an out-of-band storage module for repairing damaged memory with memory page as a granularity. The application achieves the effects of improving memory utilization efficiency and compatibility, and enhancing a memory RAS system by using the out-of-band storage module and the high-efficiency memory repair system with dynamically configurable memory page as a granularity.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a high-efficiency memory repair system and method based on pooled memory. BACKGROUND

[0002] The three key elements in the core architecture of data center are computing, storage and network. Among them, memory as a volatile storage unit, its performance and reliability directly affect the operation efficiency and service capability of the whole data center. With the continuous development of AI and other technologies, a large amount of temporary data generated by computing requires a large amount of memory, so there is often a shortage of memory resources in the computing node; at the same time, some business edge nodes will appear the situation of memory surplus and insufficient memory utilization. From the timeline, due to the diversity and burstiness of the services carried by the data center, the memory resource usage of different nodes is highly unbalanced, and the state of short-term burst resource shortage and long-term idle resource coexists. Therefore, in order to make full use of the expensive memory resources of the data center, memory pooling technology has become an important trend of the development of data center.

[0003] Memory pooling technology can allocate and dynamically supply memory on demand at the system level to achieve on-demand flexible scheduling of resources. However, on the one hand, the data center has high requirements for data security and service stability, and the current RAS (Reliability, Availability and Serviceability) guarantee mechanism in the pooled memory environment, especially the memory repair means, is not perfect. On the other hand, in order to guarantee the high quality and stability of the service, the data center needs to replace the memory and other high sensitive devices regularly, usually the period is 3-5 years, but the memory base of the data center is large, which leads to a large waste of resources and greatly increases the operation cost of cloud vendors.

[0004] The main memory repair solutions in the market at present include: post package repair technology (PPR: Post Package Repair), adaptive double DRAM device correction (ADDDC: Adaptive Double DRAM Device Correction), memory rank sparing (MRS: Memory Rank Sparing), memory page retire (MPR: Memory Page Retire), memory patrol scrub technology (MPS: Memory Patrol Scrub) and the like. Among them, the PPR, ADDDC and MRS technologies are based on the physical structure units (such as ROW, BANK or RANK) of the memory stick (DIMM) to replace the uncorrectable memory error (UCE: Uncorrectable Memory Error), and the implementation of these solutions needs to backup the corresponding physical units in advance, although it can guarantee the data security to a certain extent, but there is a serious problem of resource waste. At the same time, its implementability is seriously dependent on the product process of the DIMM manufacturer, and in the actual application, it will also be affected by the number of UCE errors, repair time and the like, and cannot meet the RAS system requirements of the memory. The MPR and MPS technologies are only error memory alarm and shielding mechanisms, and cannot really repair the memory.

[0005] In summary, the existing reliability management scheme of the pooled memory still has the following defects: first, the resource waste is serious, whether it is a repair scheme based on redundant backup or a preventive device replacement strategy, the demand for memory redundancy resources is large, which greatly reduces the effective utilization rate of memory resources; second, the technical conservatism, the existing scheme is limited to the memory physical structure and storage material; third, the architecture limitation, the granularity and flexibility of the existing repair means are insufficient, and it is difficult to adapt to the fine and dynamic resource management requirements in the pooled environment. Therefore, it is urgent to design a memory repair system and method which can be applied to memory pooling, improve the utilization efficiency of memory and the compatibility to the operating system, enhance the function of the memory RAS system to improve the reliability, availability and service life of the memory system. SUMMARY

[0006] In order to solve the problems existing in the prior art, the purpose of the present application is to provide an efficient memory repair system and method based on pooled memory, which can improve the utilization efficiency of memory and the compatibility to the operating system, enhance the function of the memory RAS system to improve the reliability, availability and service life of the memory system.

[0007] The present application achieves the above-mentioned purposes through the following technical solutions:

[0008] A high-efficiency memory repair system based on pooled memory, comprising a memory test module, a management module, an address routing module, and an out-of-band storage module, the memory test module detects error addresses of memory banks in cacheline granularity, and reports the detected UCE error addresses to the management module.

[0009] The management module is configured to convert the UCE error addresses into memory page addresses, query repair states of the memory page addresses, generate repair commands for the memory page addresses according to the repair states, and deliver the repair commands to the address routing module.

[0010] The address routing module adds the memory page addresses into a routing table by using a routing table lookup algorithm according to the repair commands to complete address repair, and performs corresponding address conversion and routing according to repair states of accessed host memory addresses and routes the host memory addresses to ports where the memory banks or the out-of-band storage module are located.

[0011] The out-of-band storage module is an out-of-band memory pool independent of a system memory pool, and is configured to repair damaged memory in memory page granularity.

[0012] The high-efficiency memory repair system based on pooled memory provided by the application has the memory test module integrated in a DDR controller in a memory system, and the detection range of the memory test module is limited to the memory banks on one or more memory channels governed by the DDR controller, and the UCE error addresses detected by the memory test module are addresses of the memory channels corresponding to the memory banks having UCE errors.

[0013] The high-efficiency memory repair system based on pooled memory provided by the application has the memory test module report UCE error information detected by the memory test module to the management module, and the UCE error information includes: a slot, a memory die, a memory controller, a channel, a slot, a physical array, a sub-physical array, a logical array group, a logical array and a row address and a column address, a device identifier, a memory particle identifier, and a transmission number.

[0014] The high-efficiency memory repair system based on pooled memory provided by the application has the address routing module, and the repair state judgment process of the host memory address includes:

[0015] The host sends a memory access address and performs routing table entry calculation.

[0016] The routing table entry is accessed and the repair state of the host memory address is judged by using the routing table entry calculation result.

[0017] If the host memory address is a normal accessible memory address, its repair state is unrepaired.

[0018] If the host memory address is a repaired memory page address, its repair state is repaired.

[0019] According to the high-efficiency memory repair system based on the pooled memory provided by the application, the routing table item is an address conversion and address routing combined table item, the calculation mode adopts hash calculation, the host memory address is calculated by a hash function to generate a routing table index, and the corresponding table item in the routing table is accessed according to the index.

[0020] According to the high-efficiency memory repair system based on the pooled memory provided by the application, the address routing module acquires the host memory address, if it is judged that the address is in an unrepaired state, the address is converted into a readable and writable DDR control channel address and routed to the port where the memory bank is located, if it is judged that the address is in a repaired state, the address is converted into the address of the out-of-band storage module and routed to the port where the out-of-band storage module is located.

[0021] According to the high-efficiency memory repair system based on the pooled memory provided by the application, the management module generates a memory repair log, the memory repair log is used to query the repair state of the memory page address and the RAS log information of the memory repair system, and the memory repair log includes a UCE error address, a repaired memory page address, a repaired out-of-band storage module address, repair result information and abnormal reason information.

[0022] According to the high-efficiency memory repair system based on the pooled memory provided by the application, the out-of-band storage module has an address code independent of the system memory pool, the address code is managed by the management module, and the address size is determined in the granularity of a memory page at system initialization.

[0023] The address routing module routes the memory access command of the damaged and repaired address to the out-of-band storage module according to the routing table item, and the out-of-band storage module performs memory reading or writing operation according to the memory access command.

[0024] According to the high-efficiency memory repair system based on the pooled memory provided by the application, the memory page of the out-of-band storage space of the out-of-band storage module is defined as the memory page, and the page size of the memory page can be dynamically configured according to the memory damage condition, and the value is:

[0025]

[0026] Wherein, n is a non-negative integer.

[0027] The dynamic configuration range of the page size is:

[0028]

[0029] Among them, The maximum capacity of the out-of-band storage space.

[0030] An efficient memory repair method based on a pooling memory, applied to the efficient memory repair system based on the pooling memory, comprising:

[0031] S1: The memory test module detects the error address in cacheline granularity for the memory bank managed by it, and reports the detected UCE error address.

[0032] S2: After the management module receives the UCE error address, it is converted into the memory page address belonging to it, and it is queried whether the memory page address has been repaired, if not, the repair command of the memory page address is issued.

[0033] S3: After the address routing module receives the repair command, the memory page address is replaced and added to the routing table by using the routing table lookup algorithm, and the repair result is reported to the management module; if the table entry of the memory page address can be added, the repair result is successful, otherwise it is failed.

[0034] S4: The management module reports the repair result in the form of a memory repair log, and the memory system queries the RAS log information through the memory repair log.

[0035] Therefore, compared with the prior art, the present application has the following beneficial effects:

[0036] 1、The present application designs an out-of-band storage module independent of the conventional system memory pool, and performs memory repair in memory page granularity, compared with the traditional repair scheme, it is no longer limited to the memory redundancy space of the memory bank itself for memory repair, but provides a new repair scheme that uses the out-of-band storage space as the redundant memory, based on the out-of-band storage space for memory repair, the redundant storage space is no longer limited to the storage medium, the out-of-band storage medium can be DDR, flash, SSD, etc., or the ram space on the chip.

[0037] 2、The application establishes a routing and address conversion table based on memory page address in front of the DDR controller, thereby realizing the feasibility of system memory addressing post-repair, compared with the physical structure of the traditional base DDR memory, the base structure unit of the memory such as ROW, BANK, RANK is no longer distinguished, the memory repair scheme of the application for system addressing has strong affinity with the upstream operating system, and is no longer limited to the memory bar structure itself, and is not limited to the underlying technical structure of the memory manufacturer.

[0038] 3、The application has a flexible configurable memory page size unit in the out-of-band storage module, the minimum unit of the memory page size is 64 Byte, compared with the traditional row (2K), bank (GB level) and other memory repair methods, the resources required for repairing the memory can be saved, and the problem of too large traditional redundant memory is solved; and by dynamically adjusting the memory page size, the repairability of the damaged address is enhanced and the adaptable scene is wider.

[0039] 4、The memory test module of the application is designed by integrating with the DDR controller, error detection and marking are performed based on the cache line as the granularity, the error memory detection mechanism of the application enables the memory system to independently complete the detection of the error address of the memory bar without relying on the external expensive and complex automatic test equipment, significantly reduces the device dependence and test time, and reduces the overall cost.

[0040] 5、The application can perform memory troubleshooting, predictive maintenance and memory resource monitoring in the memory repair log, meets the need of the RAS requirement system to have serviceability, enhances the memory RAS system after memory pooling, and facilitates unified memory management in the data center.

[0041] 6、The application realizes the feasibility of repairing the memory storage unit based on the chip storage unit based on the routing table calculated based on the hash, and guarantees the bandwidth of the repaired memory access.

[0042] 7、The application establishes a complete memory repair RAS system based on the memory page unit, including memory UCE testing and reporting, memory address routing mechanism, memory repair method mechanism, and repair memory log maintenance mechanism, compared with the traditional memory repair scheme, the RAS system of the system memory management is improved, the overall repair strategy can be more flexible and efficient for system error memory repair, enhances the function of the memory RAS system, and improves the reliability, availability and service life of the memory system.

[0043] The application will be further described in detail in combination with the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a system schematic diagram in an embodiment of a high-efficiency memory repair system based on a pooled memory.

[0045] Figure 2 is a method flowchart in an embodiment of a high-efficiency memory repair method based on a pooled memory. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions in the present application will be described below in connection with the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0047] Reference herein to“an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearance of the phrase in various places in the specification indicates that, while all of these phrases can not necessarily be referring to the same embodiment, or to the same alternative embodiment, or to the same alternative embodiment in combination with other claimed embodiments, each of the referenced embodiments is explicitly incorporated in at least one embodiment of the application.

[0048] Referring to Figure 1 , the present application is a high-efficiency memory repair system based on a pooled memory, comprising: a memory test module 10, a management module 20, an address routing module 30, and an out-of-band storage module 40. The memory test module 10 detects error addresses of memory banks in cacheline granularity, and reports the detected UCE error addresses to the management module 20.

[0049] The management module 20 is configured to convert the UCE error addresses into the memory page addresses to which the UCE error addresses belong, and to query the repair states of the memory page addresses. According to the repair states, the management module 20 generates repair commands for the memory page addresses and sends the repair commands to the address routing module 30.

[0050] The address routing module 30 adds the memory page addresses to a routing table according to the repair commands by using a routing lookup table algorithm to complete address repair. According to the repair states of the accessed host memory addresses, the address routing module 30 performs corresponding address conversion and routing to the ports where the memory banks or the out-of-band storage module 40 are located.

[0051] The out-of-band storage module 40 is an out-of-band memory pool independent of the system memory pool, and is configured to repair damaged memory in memory page granularity.

[0052] In the embodiment, the memory test module 10 is integrated in a DDR controller in a memory system, and the detection range is limited to the memory bank on one or more memory channels managed by the DDR controller. The UCE error address detected by the memory test module 10 is the address of the memory channel corresponding to the memory bank with the UCE error.

[0053] Specifically, in the embodiment Figure 1 The black solid line path is a routing path, through which normal memory access is performed. The blue dashed line path is a repair path, through which table_insert is performed, that is, the memory page address is added to the routing table, and log_report is reported to the management module 20. The red solid line path is a detection path, through which the UCE error address is reported to the management module 20 after the memory test module 10 detects the memory UCE error.

[0054] wherein HOST0~HOSTn are different computing units that initiate memory access requests; DIMM0, DIMM1 are memory banks in a memory pool; PORT0~PORTn are different ports for connecting different memory channels; route_table0, route_table1 are routing tables; addr_trf is an address translator of the management module 20, and log_manager is a log manager of the management module 20.

[0055] Specifically, in the embodiment, the DDR controller is a double data rate synchronous DRAM (Dynamic Random Access Memory), which is connected between a processor and a memory in a computer system, is used for processing memory access requests and coordinating read and write operations, and transmits data on both rising and falling edges through a synchronous clock signal to achieve double bandwidth. The working process includes:

[0056] The DDR controller receives a memory access request of the processor, and the memory access request includes logical address, read / write type and other information.

[0057] The logical address is converted into a physical address, and the physical structure of the specific access is determined according to the physical address, including but not limited to a memory bank socket (Socket), a channel (Channel), a rank (Rank), a row (Row), and a column (Column).

[0058] An operation command is generated and dispatched according to the DRAM timing requirement, including a read command and a write command for the memory.

[0059] In some embodiments, the memory test module 10 is connected to the DDR controller through an internal interface as a standalone module. The memory test module 10 sends a test request to the DDR controller. The DDR controller processes the test request, coordinates reading of memory data, and sends the memory data to the memory test module 10. The memory test module 10 detects the error address of the memory data.

[0060] In other embodiments, the memory test module 10 is integrated into the DDR controller by embedding BIST (Built-in Self-Test) logic into key sub-modules of the DDR controller, including but not limited to an address decoding unit, a command scheduling unit, and a data comparison unit. The management module 20 is responsible for coordinating BIST operations on multiple DDR controllers and issuing commands to the memory test module 10 on each DDR controller through a system bus, including but not limited to configuration commands, start commands, and test result reporting commands.

[0061] Specifically, the memory test module 10 of the present embodiment integrates test circuits inside the DDR controller, enabling the memory system to independently detect error addresses of memory modules without relying on external expensive and complex automatic test equipment, significantly reducing device dependence and test time, and reducing overall costs.

[0062] Specifically, the working process of the memory test module 10 of the present embodiment includes:

[0063] During the system startup phase, the memory test module 10 receives a BIST start command, then performs a quick initialization and test parameter configuration, including the memory range to be tested, the test algorithm, and the granularity setting. In the present embodiment, the granularity is set to 64 bytes of cacheline.

[0064] The memory test module 10 detects error addresses of the memory modules on one or more memory channels governed by the DDR controller to which it is bound.

[0065] The detected UCE error addresses are analyzed and UCE error information is generated and reported to the management module 20.

[0066] Specifically, the UCE error information of the present embodiment includes but is not limited to:

[0067] DIMM information: Slot, Device ID;

[0068] Rank / Die information: physical array (Rank), sub-physical array (Sub-Rank), memory die (Die);

[0069] Bank information: logical array group (Bank Group), logical array (Bank);

[0070] Row and column information: row (Row) address and column (Column) address;

[0071] Topology information: socket (Socket), memory controller (IMC), channel (Channel);

[0072] Internal information of the particle: memory particle identification (Chip ID), transfer number (Transfer Number).

[0073] Among them, the device identification is the identification of different manufacturers or types of memory; the row and column information is used to locate the specific position of the cacheline in the Bank; the internal information of the particle is used to locate the DRAM and memory channel where the UCE error information exists.

[0074] In the embodiment, the repair state judgment process of the address routing module 30 on the host memory address includes:

[0075] The host sends a memory access address and performs routing table entry calculation.

[0076] Using the routing table entry calculation result, access the routing table entry and judge the repair state of the host memory address.

[0077] If the host memory address is a normally accessible memory address, its repair state is un-repaired.

[0078] If the host memory address is a repaired memory page address, its repair state is repaired.

[0079] In the embodiment, the routing table entry is an address conversion and address routing combined entry.

[0080] In the embodiment, the address routing module 30 obtains the host memory address HOST PHYSICS ADDRESS (HPA), if it is judged that the address is in the un-repaired state, it converts the HPA into a readable and writable DDR control channel address DDR CHANNEL ADDRESS (CPA), and routes the CPA to the port where the memory stick is located; if it is judged that the address is in the repaired state, it converts the HPA into the address OOB ADDRESS of the out-of-band storage module 40 and routes it to the port where the out-of-band storage module 40 is located.

[0081] In some embodiments, the calculation method of the routing table entry adopts hash calculation, which calculates the host memory address through a hash function and generates a routing table index, and accesses the corresponding entry in the routing table according to the index.

[0082] Specifically, the embodiment inputs the complete host memory address, generates a fixed range of numerical values as the index of the routing table by operating the hash function, thereby mapping the large range of address space to the small range of routing table index. The fixed range of numerical values is calculated as follows:

[0083] Index = Hash_Function(HPA) % Table_Size

[0084] wherein Hash_Function() is the hash function, HPA is the input host memory address, and Table_Size is the size of the routing table, i.e., the value range of Index is: 0≤Index≤Table_Size.

[0085] In other embodiments, the routing table item is calculated by direct address access, which extracts a part of the host memory address as the routing table index, and the index value is HPA[Bit_Mask]. For example, the high bit part of the host memory address is extracted as the input, and the index value can be HPA[63:20], which is directly used to access the corresponding table item in the routing table.

[0086] In the embodiment, the management module 20 generates a memory repair log, and writes the received repair information into the memory repair log. The memory repair log is used to query the repair state of the memory page address and the RAS log information of the memory repair system, which includes: UCE error address and information, repaired memory page address and information, address of the repaired out-of-band storage module 40, repair result information, and abnormal reason information. The memory repair log can be set as shown in Table 1.

[0087] Table 1

[0088]

[0089] Specifically, the memory repair log in the embodiment records the repair situation of the memory system, which can meet the need of the RAS requirement system to have serviceability. Through the memory repair log, memory troubleshooting, predictive maintenance, and memory resource monitoring can be performed, which enhances the memory RAS system after memory pooling, and facilitates unified memory management in the data center.

[0090] In the embodiment, the out-of-band storage module 40 has an address code independent of the system memory pool, which is managed by the management module 20, and the address size is determined in the system initialization with the granularity of memory page.

[0091] The address routing module 30 routes the memory access command of the damaged and repaired address to the out-of-band storage module 40 according to the routing table item, and the out-of-band storage module 40 performs the memory read or write operation according to the memory access command.

[0092] Specifically, the out-of-band storage module 40 of the embodiment is an independent storage hardware, which can be selected from DDR, flash, SSD or RAM space on the chip, and is separate from the memory stick DIMM constituting the system memory pool Memory Pool, and is dedicated to memory repair, and thus is not affected by system memory pool failure or frequent access, thereby improving the reliability of the memory system.

[0093] Specifically, the out-of-band storage module 40 of the embodiment is designed independently of the system memory pool, compared with the traditional PPR memory repair scheme, which solves the limitation of single memory stick structure. The PPR memory repair scheme is repaired in row units, and the number of available ROWs is limited by the factory limit of DDR. According to the spec of DDR4, a spare ROW needs to be configured for a BANK. When an unrepairable error in a BANK involves two ROW units, the PPR repair technology fails. The memory repair technology of the embodiment is no longer limited by the factory limit of the DIMM stick, and can be repaired according to the separate out-of-band storage space as a redundant resource.

[0094] In the embodiment, the memory page of the out-of-band storage space of the out-of-band storage module 40 is defined as the memory page, and the page size of the memory page can be dynamically configured according to the memory damage condition, and the value is:

[0095]

[0096] Wherein, n is a non-negative integer.

[0097] The dynamic configuration range of the page size is:

[0098]

[0099] Wherein, is the maximum capacity of the out-of-band storage space.

[0100] Specifically, the smaller the memory page size of the embodiment is, the smaller the repairable memory granularity is, the higher the repair accuracy is for less bit damage, and the more the redundant memory is saved; and the larger the memory page size is, the larger the repairable memory granularity is, the more the redundant memory is consumed, but the fewer the routing table entries are occupied for repairing the same memory space. Therefore, the selection of the memory page size can be flexible repair according to the memory damage. When the system has more large address damage and the damaged memory address HPA is continuous, a larger memory page size should be selected; when the damaged memory address in the system is not continuous and is damaged in a smaller granularity, a smaller memory page size should be selected.

[0101] Specifically, the out-of-band storage module 40 of the embodiment can flexibly configure the memory page size, which solves the problem of excessive redundant memory compared with the traditional ADDDC memory repair scheme. The ADDDC memory repair scheme is to backup the memory redundancy in units of RANK or BANK, which requires a large amount of memory redundancy resources. The memory repair technology of the embodiment is to repair the memory in units of dynamically adjustable memory page size, which can adapt to a wider range of scenarios and requires less redundant memory resources for repair.

[0102] It can be seen that, compared with the traditional memory repair mode of row (2K), bank (GB level) and the like, the application repairs the memory in units of memory page, improves the utilization efficiency of redundant memory and the compatibility with the operating system, can save the resources required for repair, solves the problem of excessive redundant memory of the traditional scheme, and repairs the memory in units of dynamically adjustable memory page size, enhances the repairability of the damaged address and can adapt to a wider range of scenarios.

[0103] Referring to Figure 2 The application discloses a high-efficiency memory repair method based on a pooling memory, which is applied to a high-efficiency memory repair system based on the pooling memory and comprises the following steps.

[0104] S1: a memory test module detects error addresses in units of a cache line for a memory bar managed by the memory test module, and reports the detected UCE error addresses.

[0105] S2: after receiving the UCE error addresses, a management module converts the UCE error addresses into memory page addresses, queries whether the memory page addresses have been repaired, and if not, issues a repair command for the memory page addresses.

[0106] S3: After receiving the repair command, the address routing module replaces the memory page address into the routing table by using a routing lookup algorithm, and reports the repair result to the management module; if the table entry of the memory page address can be added, the repair result is successful, otherwise, the repair result is failed.

[0107] S4: The management module reports the repair result in the form of a memory repair log, and the memory system queries RAS log information through the memory repair log.

[0108] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present disclosure.

[0109] The above embodiments are only preferred embodiments of the present application, and cannot be used to limit the scope of protection of the present application. Any non-essential changes and replacements made by those skilled in the art based on the present application shall fall within the scope of protection of the present application.

Claims

1. A memory repair system based on pooled memory, characterized by, Comprise: The memory test module, management module, address routing module and out-of-band storage module, the memory test module detects the error address of the memory bank with cacheline as the granularity, and reports the detected UCE error address to the management module; The management module is used for converting the UCE error address into the memory page address to which it belongs, querying the repair state of the memory page address, generating a repair command for the memory page address according to the repair state, and delivering the repair command to the address routing module; The address routing module uses routing table lookup algorithm to insert the memory page address into the table item according to the repair command to complete address repair, and routes the accessed host memory address to the memory bank or the port where the out-of-band storage module is located according to the repair state of the accessed host memory address; The out-of-band storage module is an out-of-band memory pool independent of the system memory pool, and is used for repairing the damaged memory with memory page as the granularity; Wherein, the out-of-band storage module has an address coding independent of the system memory pool, which is managed by the management module, and the address size is determined with memory page as the granularity at system initialization; The address routing module routes the memory access command of the damaged and repaired address to the out-of-band storage module according to the routing table item, and the out-of-band storage module performs memory read or write operation according to the memory access command.

2. The pool-based memory repair system according to claim 1, wherein: The memory test module is integrated in the DDR controller in the memory system, and its detection range is limited to the memory bank on one or more memory channels governed by the DDR controller, and the UCE error address detected by the memory test module is the address of the memory channel corresponding to the memory bank with UCE error.

3. The pool-based memory repair system according to claim 2, wherein: The memory test module reports the UCE error information detected on the memory bank to the management module, and the UCE error information includes: the slot, memory die, memory controller, channel, physical array, sub-physical array, logical array group, logical array and row address and column address, device identification, memory particle identification and transmission number where the error occurs.

4. The pool-based memory repair system according to claim 2, wherein: The repair state judgment process of the address routing module on the host memory address includes: Sending a memory access address to the host and calculating a routing table item; Accessing the routing table item using the routing table item calculation result, and judging the repair state of the host memory address: If the host memory address is a normal accessible memory address, its repair state is unrepaired; If the host memory address is a repaired memory page address, its repair state is repaired.

5. The pool-based memory repair system according to claim 4, wherein: The routing table item is an address conversion and address routing combined table item, and the calculation method adopts hash calculation. The host memory address is calculated by a hash function to generate a routing table index, and the corresponding table item in the routing table is accessed according to the index.

6. The memory repair system based on the pooled memory according to claim 4, wherein: The address routing module obtains the host memory address, and if it is judged that the address is in an unrepaired state, the address is converted into a readable and writable DDR control channel address and routed to the port where the memory bank is located; if it is judged that the address is in a repaired state, the address is converted into the address of the out-of-band storage module and routed to the port where the out-of-band storage module is located.

7. The memory repair system based on the pooled memory according to any one of claims 1-6, wherein: The management module generates a memory repair log, and the memory repair log is used to query the repair state of the memory page address and the RAS log information of the memory repair system, which includes: a UCE error address, a repaired memory page address, an address of a repaired out-of-band storage module, repair result information and abnormal reason information.

8. The memory repair system based on the pooled memory according to claim 6, wherein: The memory page of the out-of-band storage space of the out-of-band storage module is defined as the memory page, and the page size of the memory page can be dynamically configured according to the memory damage condition, and the value is: wherein is a byte, n is a non-negative integer; The dynamic configuration range of the page size is: wherein, is a page size of the memory page, is a maximum capacity of the out-of-band storage space.

9. A memory repair method based on pooled memory, characterized in that, The memory repair system based on the pooled memory is applied to any one of claims 1-8, and includes: S1: The memory test module detects error addresses in cacheline granularity for the memory banks managed by the memory test module, and reports the detected UCE error addresses; S2: After receiving the UCE error address, the management module converts the UCE error address into the memory page address to which the UCE error address belongs, and queries whether the memory page address has been repaired. If not, the management module issues a repair command for the memory page address; S3: After receiving the repair command, the address routing module inserts the memory page address into the table item by using a routing table lookup algorithm, and reports the repair result to the management module. If the table item of the memory page address can be added, the repair result is successful, otherwise, the repair result is failed; S4: The management module reports the repair result in the form of a memory repair log, and the memory system queries the RAS log information through the memory repair log.

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