Chip varistor

Abstract

According to the chip varistor, the width of the function part of the third conductor is enlarged, so that the ESD tolerance is improved. The width of the end portion of the third conductor is shorter than the width of the third electrode and shorter than the width of the functional portion of the third conductor. Therefore, for example, when the third electrode is formed, even if the relative positions of the third electrode and the third conductor in the opposite direction in which the end surfaces exist are shifted, a condition that a part of the third conductor is not covered by the third electrode does not easily occur. That is, the size of the connection area between the third conductor and the third electrode is not changed, and good connection can be realized.

Description

[0001] This application was filed on [date]. November 29, 2022 Application number is 202211508663.5 The invention is named sheet Varistor A divisional application of the patent application. Technical Field

[0002] This disclosure relates to chip varistor. Background Technology

[0003] Currently, a type of chip varistor with a varistor structure disposed inside a substrate is known. Patent Documents 1 and 2 disclose a stacked chip varistor comprising: a plurality of conductors disposed inside a substrate having a stacked structure, and a plurality of electrodes disposed on the surface of the substrate in such a way as to be connected to the plurality of conductors respectively.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. 2018 / 144987

[0007] Patent Document 2: International Publication No. 2021 / 095368 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] In the aforementioned chip varistors, increasing the area of ​​the body region (functional region) sandwiched by conductors in the stacking direction can improve ESD withstand capability. However, increasing the conductor width to increase the area of ​​the functional region may lead to a decrease in the connectivity between the conductor and the electrode.

[0010] The purpose of this disclosure is to provide a chip varistor that can improve ESD tolerance and suppress the degradation of the connection between the conductor and the electrode.

[0011] Technical solutions for solving the problem

[0012] A chip varistor according to one aspect of this disclosure comprises: a substrate having a stacked structure, and having: a first surface and a second surface extending parallel to and opposite to each other with respect to the stacking direction, and a third surface and a fourth surface extending parallel to and opposite to each other with respect to the stacking direction, connecting the first surface and the second surface; a first conductor extending from the first surface within a defined layer of the substrate along the opposite direction of the first surface and the second surface; a second conductor extending from the second surface within a layer of the substrate different from the first conductor, along the opposite direction of the first surface and the second surface, forming an overlapping portion that overlaps with the first conductor in the stacking direction of the substrate; and a third conductor. Within the layer of the substrate located between the first and second conductors, extending from the third surface to the fourth surface, it has: a functional portion overlapping the overlapping portion in the stacking direction of the substrate; a first electrode disposed on the first surface of the substrate and connected to the first conductor; a second electrode disposed on the second surface of the substrate and connected to the second conductor; and a pair of third electrodes disposed on the third and fourth surfaces of the substrate respectively and connected to the ends of the third conductors. When viewed from the stacking direction of the substrate, the length of the end of the third conductor in a direction orthogonal to the relative directions of the third and fourth surfaces is shorter than the length of the third electrode and shorter than the length of the functional portion of the third conductor.

[0013] In the aforementioned chip varistor, the ESD withstand capability is improved by lengthening the functional portion of the third conductor in a direction orthogonal to the relative directions of the third and fourth surfaces of the substrate. The length of the end of the third conductor is shorter than the length of the third electrode and also shorter than the length of the functional portion of the third conductor; therefore, a certain degree of relative positional shift between the third conductor and the third electrode is permissible. That is, even if a relative positional shift occurs between the third conductor and the third electrode, the size of the connection area remains unchanged, enabling a good connection.

[0014] In other types of chip varistors, when viewed from the stacking direction of the substrate, the functional part of the third conductor is longer than the third electrode in terms of length in the direction orthogonal to the relative directions of the third and fourth surfaces.

[0015] In other types of chip varistors, when viewed from the stacking direction of the substrate, the functional part of the third conductor is shorter than that of the third electrode in terms of length in the direction orthogonal to the relative directions of the third and fourth surfaces.

[0016] In other types of chip varistors, the third conductor has a widened portion that gradually increases in width from the end toward the functional part.

[0017] In other types of chip varistors, the substrate has a fifth and a sixth surface that extend orthogonally to the stacking direction and are opposite to each other, and a pair of third electrodes that extend from each of the third and fourth surfaces of the substrate to the fifth and sixth surfaces. When viewed from the stacking direction of the substrate, the portions of the third electrodes disposed on the fifth and sixth surfaces overlap with at least a portion of the widened portion of the third conductor.

[0018] In other types of chip varistors, the third electrode has: a first portion disposed on the third and fourth surfaces respectively, and gradually decreasing in width in a barrel shape towards the edges of the fifth and sixth surfaces; and a second portion disposed on the fifth and sixth surfaces respectively, and gradually decreasing in width in a semi-circular shape away from the edges of the third and fourth surfaces.

[0019] Invention Effects

[0020] According to this disclosure, a chip varistor can be provided that improves ESD tolerance and suppresses the degradation of the connection between the conductor and the electrode. Attached Figure Description

[0021] Figure 1 This is a schematic perspective view showing a chip varistor according to the first embodiment.

[0022] Figure 2 It is shown Figure 1 A three-dimensional view of the conductors inside the solid shown.

[0023] Figure 3 It is shown Figure 1 The diagram shows cross-sectional views of the conductors inside the solid.

[0024] Figure 4 This diagram only shows the first and second conductors.

[0025] Figure 5 This diagram only shows the third conductor.

[0026] Figure 6 It is a cross-sectional view showing the positional relationship of each conductor.

[0027] Figure 7 It is a cross-sectional view showing the positional relationship of each conductor.

[0028] Figure 8 This is a diagram showing different types of chip varistors.

[0029] Figure 9 This is a schematic perspective view showing the chip varistor of the second embodiment.

[0030] Figure 10 This is a side view showing the third electrode disposed on the side of the substrate.

[0031] Figure 11 This is a diagram showing the positional relationship between the third conductor and the third electrode.

[0032] Explanation of reference numerals in the attached figures

[0033] 1, 1A… Chip varistor; 10… Base body; 20A… First electrode; 20B… Second electrode; 20C, 20D… Third electrode; 30A… First conductor; 30B… Second conductor; 30C… Third conductor; 31… End; 32… Main body; 33… Widened portion; 34… Functional portion; 40… Overlapping portion; 42… First functional layer; 44… Second functional layer. Detailed Implementation

[0034] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, in the description, the same symbols are used for the same elements or elements having the same function, and repeated descriptions are omitted.

[0035] (First Implementation)

[0036] First, refer to Figures 1-3 The structure of the chip varistor 1 in the first embodiment will be described.

[0037] The chip varistor 1 is a multi-terminal stacked chip varistor, consisting of a body 10 and four terminal electrodes 20A to 20D. The chip varistor 1 has a roughly cuboid shape, which is the so-called 2012 size (length in the long side direction is 2.0 mm, length in the short side direction is 1.25 mm, and height is 0.8 mm).

[0038] The base body 10 is a stacked structure with a generally cuboid shape. The base body 10 has: rectangular end faces 10a and 10b facing each other along its long side; and four rectangular side faces 10c to 10f orthogonal to the end faces 10a and 10b. The four side faces 10c to 10f extend to connect the end faces 10a and 10b. The end faces 10a and 10b extend parallel to the stacking direction of the base body 10. Side faces 10c and 10d of the four side faces 10c to 10f extend parallel to the stacking direction of the base body 10 and are facing each other. Side faces 10e and 10f of the four side faces 10c to 10f extend orthogonally to the stacking direction of the base body 10 and are facing each other in the stacking direction of the base body 10.

[0039] The substrate 10 is composed of a sintered body (semiconductor ceramic) exhibiting the characteristics of a varistor. The substrate 10 is a stacked structure comprising multiple layers of sintered body exhibiting varistor characteristics. In the actual substrate 10, the constituent layers are integrated to the point that the boundaries between them are indistinguishable. The substrate 10 contains ZnO (zinc oxide) as the main component and contains metal monomers or their oxides, such as Co, rare earth elements, Group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, Rb, Cs), and alkaline earth metal elements (Mg, Ca, Sr, Ba), as secondary components. In this embodiment, the substrate 10 contains Co, Pr, Cr, Ca, K, and Al as secondary components. The ZnO content of the substrate 10 is not particularly limited, but is typically 99.8% to 69.0% by mass when the total material constituting the substrate 10 is set to 100% by mass. Rare earth metal elements (e.g., Pr) function as substances that exhibit the characteristics of varistors. The content of rare earth metal elements in the base 10 is set, for example, to be around 0.01 to 10 atomic percent.

[0040] The surface-mount varistor 1 includes a first conductor 30A, a second conductor 30B, and a third conductor 30C within the body 10. The first conductor 30A, the second conductor 30B, and the third conductor 30C comprise a conductive material. The conductive material comprised in each conductor 30A, 30B, and 30C is not particularly limited and may be made of Pd or an Ag-Pd alloy. The thickness (length in the stacking direction) of each conductor 30A, 30B, and 30C is, for example, between 0.1 and 10 μm.

[0041] The first conductor 30A has a strip-like shape with a uniform width and extends within the layer constituting the body 10 along the opposite directions of the end faces 10a and 10b. One end 30a of the first conductor 30A is exposed above the end face 10a (first face), and the other end 30b is located within the body 10. The width of the first conductor 30A is, for example, 0.4 mm.

[0042] The second conductor 30B has a strip-like shape with a uniform width and extends along the opposite directions of end faces 10a and 10b within a layer different from the layer in which the first conductor 30A is formed. One end 30a of the second conductor 30B protrudes from end face 10b (the second face), while the other end 30b is located within the body 10. The width of the second conductor 30B is designed to be the same as the width of the first conductor 30A, for example, 0.4 mm.

[0043] like Figure 3 and Figure 4As shown, viewed from the stacking direction of the substrate 10, the first conductor 30A and the second conductor 30B are aligned with each other, and the ends 30b located within the substrate 10 completely overlap each other in the stacking direction. The overlapping portion 40 formed by the overlapping ends 30b of the first conductor 30A and the second conductor 30B has a rectangular shape with its long side parallel to the opposite direction of the end faces 10a and 10b when viewed from the stacking direction.

[0044] The third conductor 30C has a shape extending along the opposite directions of the sides 10c and 10d, and extends from side 10c (the third surface) to side 10d (the fourth surface). For example... Figure 5 As shown, the third conductor 30C has: a pair of ends 31, a main body 32 and a pair of widened portions 33.

[0045] Each end 31 of the third conductor 30C is located near the sides 10c and 10d and is exposed from the sides 10c and 10d. Each end 31 has a uniform width W1 (length in the opposite direction of the end faces 10a and 10b), and the width W1 is 0.1 mm for example.

[0046] The main body 32 of the third conductor 30C is located between the two ends 31 and at the center of the third conductor 30C, and intersects (orthogonally) with the first conductor 30A and the second conductor 30B. The main body 32 has a functional part 34 that overlaps with the overlapping portions 40 of the first conductor 30A and the second conductor 30B in the stacking direction of the body 10. The third conductor 30C overlaps with the first conductor 30A only at the overlapping portion 40, and also overlaps with the second conductor 30B only at the overlapping portion 40. Therefore, the area of ​​the functional part 34 is the same as the overlapping area of ​​the third conductor 30C and the first conductor 30A, and also the same as the overlapping area of ​​the third conductor 30C and the second conductor 30B. The main body 32 has a uniform width W2, and is designed such that the width W2 of the main body 32 is wider than the width W1 of the ends 31 (W2 > W1). The width W2 of the main body 32 is 0.2 mm as an example. The width of the functional part 34 is the same as the width W2 of the main body part 32. The ESD tolerance is adjusted (e.g., increased) according to the width of the functional part 34.

[0047] A widening portion 33 is provided between each of the two ends 31 and the main body 32. The widening portion 33 is the portion whose width gradually increases from the end 31 toward the main body 32.

[0048] like Figure 6 and Figure 7As shown, the third conductor 30C extends within a layer located between the first conductor 30A and the second conductor 30B. Therefore, in the stacking direction of the substrate 10, the separation distance between the third conductor 30C and the first conductor 30A is substantially the same as the separation distance between the third conductor 30C and the second conductor 30B. A first functional layer 42 is formed between the functional portion 34 and the end 30b of the first conductor 30A. The first functional layer 42 is a substrate portion sandwiched between the functional portion 34 and the end 30b of the first conductor 30A. The first functional layer 42 has a capacitance of, for example, 20 to 50 pF. Furthermore, a second functional layer 44 is formed between the functional portion 34 and the end 30b of the second conductor 30B. The second functional layer 44 is a substrate portion sandwiched between the functional portion 34 and the end 30b of the second conductor 30B. As described above, the third conductor 30C is separated from the first conductor 30A and the second conductor 30B by substantially the same amount of distance, and the overlap area with the first conductor 30A and the second conductor 30B is substantially the same. Therefore, the second functional layer 44 has a capacitance that is substantially the same as that of the first functional layer 42.

[0049] The first electrode 20A, one of the four terminal electrodes 20A to 20D, is disposed on the end face 10a side of the body 10. The first electrode 20A is formed such that it covers the end face 10a and the portions of the four side faces 10c to 10f near the end face 10a. The first electrode 20A is formed such that it covers one end 30a of the first conductor 30A exposed on the end face 10a of the body 10, and the first electrode 20A is directly connected to the first conductor 30A.

[0050] The second electrode 20B, one of the four terminal electrodes 20A to 20D, is disposed on the end face 10b side of the body 10. The second electrode 20B is formed to cover the end face 10b and the portions of the four side faces 10c to 10f near the end face 10b. The second electrode 20B is formed to cover one end 30a of the second conductor 30B exposed on the end face 10b of the body 10, and the second electrode 20B is directly connected to the second conductor 30B.

[0051] The third electrodes 20C and 20D of the four terminal electrodes 20A to 20D are paired and respectively disposed on the side 10c and side 10d of the substrate 10. Specifically, the third electrode 20C extends along the stacking direction at the middle position of the long side of the rectangular side 10c and wraps around the side 10e (fifth surface) and side 10f (sixth surface), and the third electrode 20D extends along the stacking direction at the middle position of the long side of the rectangular side 10d and wraps around the side 10e and side 10f. The third electrodes 20C and 20D are also formed to cover the two ends 31 of the third conductor 30C exposed on the sides 10c and 10d of the substrate 10, respectively, and the third electrodes 20C and 20D are directly connected to the third conductor 30C. The pair of third electrodes 20C and 20D and the third conductor 30C are symmetrically arranged, thus enabling uniform discharge.

[0052] The width W3 of the third electrodes 20C and 20D is designed to be wider than the width W1 of the end portion 31 of the third conductor 30C (W3 > W1). Furthermore, the width W3 of the third electrodes 20C and 20D is designed to be wider than the width W2 of the main body portion 32 of the third conductor 30C (W3 > W2). For example, the width W3 of the third electrodes 20C and 20D is 0.5 mm. In this embodiment, the width W3 of the third electrode 20C and the width W3 of the third electrode 20D are the same. However, the width W3 of the third electrode 20C and the width W3 of the third electrode 20D may also be different.

[0053] Each terminal electrode 20A to 20D can be a single-layer structure or a multi-layer structure. Each terminal electrode 20A to 20D is, for example, a sintered electrode, formed by applying a conductive paste to the surface of the substrate 10 and then sintering it. The conductive paste is a substance made by mixing glass components, an organic binder, and an organic solvent into a powder composed of a metal (e.g., Pd, Cu, Ag, or Ag-Pd alloy). A plating layer can also be formed on such a sintered electrode. The plating layer may also include a Ni plating layer and a Sn plating layer formed on the Ni plating layer.

[0054] In the aforementioned chip varistor 1, the ESD withstand capability is improved by increasing the width W2 of the functional portion 34 of the third conductor 30C. The width W1 of the end 31 of the third conductor 30C is shorter than the width W3 of the third electrodes 20C and 20D (W3 > W1) and shorter than the width W2 of the functional portion 34 of the third conductor 30C (W2 > W1). Therefore, for example, when forming the third electrodes 20C and 20D, even if there is a relative positional offset between the third electrodes 20C and 20D and the third conductor 30C in the opposite direction of the end faces 10a and 10b, it is less likely that a portion of the third conductor 30C will not be covered by the third electrodes 20C and 20D. That is, even if a relative positional offset occurs between the third conductor 30C and the third electrodes 20C and 20D, the size of the connection area between the third conductor 30C and the third electrodes 20C and 20D remains unchanged, enabling a good connection.

[0055] Assuming the width W1 of the end 31 of the third conductor 30C is greater than or equal to the width W3 of the third electrodes 20C and 20D (W3 ≤ W1), if there is a relative positional offset between the third electrodes 20C and 20D and the third conductor 30C in the opposite directions of the end faces 10a and 10b, a portion of the third conductor 30C may not be covered by the third electrodes 20C and 20D, resulting in the end 31 of the third conductor 30C being exposed from the third electrodes 20C and 20D. This exposure of the end 31 of the third conductor 30C from the third electrodes 20C and 20D may cause product defects. Alternatively, the size of the connection area between the third conductor 30C and the third electrodes 20C and 20D may vary for each product, potentially leading to characteristic deviations for each product.

[0056] Additionally, in the chip varistor 1, such as Figure 5 As shown, the width W3 of the third electrodes 20C and 20D is wider than the width W2 of the main body 32 of the third conductor 30C (W3 > W2). In this way, by setting the third electrodes 20C and 20D to be wide, even when the relative positional offset is large, a good connection between the third conductor 30C and the third electrodes 20C and 20D can be achieved.

[0057] like Figure 8 As shown, the width W3 of the third electrodes 20C and 20D can also be narrower than the width W2 of the main body portion 32 of the third conductor 30C (W3 < W2). By making the width (i.e., the width W2) of the functional portion 34 of the main body portion 32 of the third conductor 30C wider than the width W3 of the third electrodes 20C and 20D, a high ESD tolerance can be achieved. The width W3 of the third electrode 20C and the width W3 of the third electrode 20D can be the same or different.

[0058] Furthermore, in the aforementioned chip varistor 1, the third conductor 30C has a widened portion 33. Therefore, even when the widths of the end portion 31 and the main body portion 32 are different, stress concentration at the boundary between the end portion 31 and the main body portion 32 can be suppressed, and defects such as cracks can be prevented from occurring.

[0059] (Second Implementation)

[0060] Reference Figures 9-11 The structure of the chip varistor 1A according to the second embodiment will be described.

[0061] The shapes of the third electrodes 20C and 20D of the chip varistor 1A in the second embodiment are different from those of the chip varistor 1 in the first embodiment, but other elements are the same as or identical to those of the chip varistor 1 in the first embodiment.

[0062] like Figure 9 As shown, the third electrodes 20C and 20D of the chip varistor 1A have a generally spindle-shaped overall shape. Specifically, each third electrode 20C and 20D is configured to include: a barrel-shaped first portion 21 disposed on the sides 10c and 10d of the substrate 10, and a semi-circular second portion 22 integrally extending from the first portion 21 and wrapping around each of the sides 10e and 10f of the substrate 10. Since the structures of the third electrodes 20C and 20D are substantially the same, the structure of the third electrode 20D will be described below, while the structure of the third electrode 20C will be omitted.

[0063] like Figure 10 As shown, the first part 21 of the third electrode 20D disposed on the side 10d of the substrate 10 has a maximum width w1 at the middle position in the stacking direction of the substrate 10, and gradually narrows in a barrel-shaped manner toward the edge (minimum width w2) of the side 10d and the side 10e, 10f.

[0064] like Figure 11 As shown, the second portion 22 of the third electrode 20D, which is respectively disposed on the sides 10e and 10f of the body 10, gradually narrows in width as its side edge bends in a generally semi-circular shape away from the edges of the sides 10e, 10f and 10d. The second portion 22 of the third electrode 20D is not limited to a semi-circular shape, but can also be semi-elliptical. In addition, the second portion 22 disposed on the side 10e and the second portion 22 disposed on the side 10f can be the same shape or different shapes.

[0065] Viewed from the stacking direction of the substrate 10, the second portion 22 of the third electrode 20D overlaps with at least a portion of the widened portion 33 of the third conductor 30C. In such a way... Figure 11In the manner shown, when viewed from the stacking direction of the substrate 10, the second portion 22 of the third electrode 20D completely overlaps with the widened portion 33 of the third conductor 30C.

[0066] In the second embodiment of the chip varistor 1A, in addition to the effects of the chip varistor 1 of the first embodiment, it also has the following effects.

[0067] That is, since the third electrodes 20C and 20D have a shape without corners (or with fewer corners), electric field concentration at the third electrodes 20C and 20D can be suppressed when the chip varistor 1A is driven. Furthermore, since the width of the third electrodes 20C and 20D narrows towards the edges of the sides 10c, 10d and 10e, 10f, the distance between the edges and the first electrode 20A and the second electrode 20B is intentionally extended, which also suppresses electric field concentration between the third electrodes 20C and 20D and the first electrode 20A and the second electrode 20B. Therefore, in the chip varistor 1A, the deterioration of each terminal electrode 20A to 20D can be suppressed.

[0068] Furthermore, viewed from the stacking direction of the substrate 10, the second portion 22 of the third electrodes 20C and 20D extends considerably from the edge of the substrate 10 to the extent that it overlaps with at least a portion of the widened portion 33 of the third conductor 30C. Therefore, heat generated within the substrate 10 (e.g., the third conductor 30C) can be effectively released from the second portion 22 of the third electrodes 20C and 20D to the outside. Consider the case where heat generated within the substrate 10 is directly transferred to the second portion 22 through the interior of the substrate 10, or indirectly transferred to the second portion 22 via the first portion 21.

[0069] As can be seen from the above description, the following content is disclosed in this specification.

[0070] [Postscript 1]

[0071] A chip varistor, comprising:

[0072] The base body has a layered structure and has: a first surface and a second surface that extend parallel to the layering direction and are opposite to each other, and a third surface and a fourth surface that extend parallel to the layering direction, connect the first surface and the second surface, and are opposite to each other.

[0073] A first conductor extends from the first surface within a defined layer of the substrate, along the opposite directions of the first and second surfaces;

[0074] The second conductor extends from the second surface in a layer of the substrate different from the first conductor, along the opposite direction of the first and second surfaces, forming an overlap portion that overlaps with the first conductor in the stacking direction of the substrate.

[0075] The third conductor, which extends from the third surface to the fourth surface within the layer of the substrate located between the first conductor and the second conductor, has a functional portion that overlaps with the overlapping portion in the stacking direction of the substrate.

[0076] A first electrode is disposed on the first surface of the body and connected to the first conductor;

[0077] The second electrode, disposed on the second surface of the substrate, is connected to the second conductor, and

[0078] A pair of third electrodes, respectively disposed on the third and fourth surfaces of the substrate, are connected to the ends of the third conductor.

[0079] Viewed from the stacking direction of the substrate, the length of the end of the third conductor in the direction orthogonal to the opposite directions of the third and fourth surfaces is shorter than the length of the third electrode and shorter than the length of the functional portion of the third conductor.

[0080] [Postscript 2]

[0081] According to the chip varistor described in Appendix 1, wherein,

[0082] Viewed from the stacking direction of the substrate, in terms of length in a direction orthogonal to the relative directions of the third and fourth surfaces, the functional portion of the third conductor is shorter than the third electrode.

[0083] [Postscript 3]

[0084] According to the chip varistor described in Appendix 1, wherein,

[0085] Viewed from the stacking direction of the substrate, in terms of length in a direction orthogonal to the relative directions of the third and fourth surfaces, the functional portion of the third conductor is longer than the third electrode.

[0086] [Postscript 4]

[0087] The chip varistor according to any one of Appendices 1 to 3, wherein,

[0088] The third conductor has a widened portion that gradually increases in width from the end toward the functional portion.

[0089] [Postscript 5]

[0090] According to Appendix 4, the chip varistor, wherein,

[0091] The substrate has a fifth and a sixth surface that extend orthogonally to the stacking direction and are opposite to each other.

[0092] The pair of third electrodes extend from each of the third and fourth surfaces of the substrate to the fifth and sixth surfaces.

[0093] Viewed from the stacking direction of the substrate, the third electrode disposed on the fifth and sixth surfaces overlaps with at least a portion of the widened portion of the third conductor.

[0094] [Postscript 6]

[0095] According to the chip varistor described in Appendix 5, wherein,

[0096] The third electrode has: a first portion, which is respectively disposed on the third surface and the fourth surface, and gradually decreases in width in a barrel shape towards the edge line of the fifth surface and the sixth surface; and a second portion, which is respectively disposed on the fifth surface and the sixth surface, and gradually decreases in width in a semi-circular shape as it moves away from the edge line of the third surface and the fourth surface.

Claims

1. A chip varistor, comprising: The base body has a layered structure and has: a first surface and a second surface that extend parallel to the layering direction and are opposite to each other, and a third surface and a fourth surface that extend parallel to the layering direction, connect the first surface and the second surface, and are opposite to each other. A first conductor extends from the first surface within a defined layer of the substrate, along the opposite directions of the first and second surfaces; The second conductor extends from the second surface in a layer of the substrate different from the first conductor, along the opposite direction of the first and second surfaces, forming only one overlap with the first conductor in the stacking direction of the substrate. The third conductor, which is located in the layer of the substrate between the first conductor and the second conductor, has only one functional portion that overlaps with the overlapping portion in the stacking direction of the substrate; A first electrode is disposed on the first surface of the body and connected to the first conductor; The second electrode is disposed on the second surface of the body and connected to the second conductor; as well as The third electrode is disposed on the third or fourth surface of the substrate and is connected to the end of the third conductor. Viewed from the stacking direction of the substrate, the length of the end of the third conductor in the direction orthogonal to the opposite directions of the third and fourth surfaces is shorter than the length of the third electrode and shorter than the length of the functional part of the third conductor.

2. The chip varistor according to claim 1, wherein, Viewed from the stacking direction of the substrate, in terms of length in a direction orthogonal to the relative directions of the third and fourth surfaces, the functional portion of the third conductor is shorter than the third electrode.

3. The chip varistor according to claim 1, wherein, Viewed from the stacking direction of the substrate, in terms of length in a direction orthogonal to the relative directions of the third and fourth surfaces, the functional portion of the third conductor is longer than the third electrode.

4. The chip varistor according to any one of claims 1 to 3, wherein, The third conductor has a widened portion that gradually increases in width from the end toward the functional portion.

5. The chip varistor according to claim 4, wherein, The substrate has a fifth and a sixth surface that extend orthogonally to the stacking direction and are opposite to each other. The third electrode extends from the third or fourth surface of the substrate to the fifth and sixth surfaces. Viewed from the stacking direction of the substrate, the third electrode disposed on the fifth and sixth surfaces overlaps with at least a portion of the widened portion of the third conductor.

6. The chip varistor according to claim 5, wherein, The third electrode has: a first portion disposed on the third or fourth surface and gradually decreasing in width in a barrel shape toward the edge line of the fifth and sixth surfaces; and a second portion disposed on the fifth and sixth surfaces respectively and gradually decreasing in width in a semi-circular shape as it moves away from the edge line of the third or fourth surface.

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