A method for manufacturing a multi-processor integrated circuit package structure and the package structure

Abstract

The application relates to the technical field of semiconductor devices, and discloses a preparation method of a multi-processor integrated circuit packaging structure and the packaging structure. The method adds the steps of warping measurement, structure form determination, and rework processing of abnormal forms on the pre-cured packaging structure after pre-curing and before complete curing. The application can discover and correct the packaging structure form abnormality problem caused by stress unevenness due to the multi-processor architecture in time at the stage when the bonding structure has not been completely cured and the rework difficulty is low, so that the product batch yield can reach more than 93%, and the technical problem of low yield and difficult rework of the multi-processor integrated circuit packaging in the related art is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a preparation method of a multi-processor integrated circuit packaging structure and the packaging structure. BACKGROUND

[0002] With the continuous pursuit of miniaturization and light weight of modern electronic terminal equipment, hybrid integrated circuits, as an important form of semiconductor devices, have obtained a broad market space. It can efficiently package multiple functional chips (such as processors, memories, analog-to-digital converters, and drivers) and peripheral resistance and capacitance elements on the same substrate, significantly improving the integration density and performance of semiconductor systems. Moreover, with the evolution of high integration and high density of semiconductor technology, the internal architecture of hybrid integrated circuits has gradually transitioned from the traditional single-processor mode to a more complex multi-processor architecture.

[0003] In the manufacturing process of hybrid integrated circuits, the lidding process is a key step in semiconductor packaging. It protects the internal sensitive functional chips and components by setting a cover plate above the active area, while assisting in heat dissipation. The packaging quality directly determines the reliability of the device and the subsequent soldering success rate.

[0004] Currently, integrated circuit research and manufacturing enterprises generally follow the lidding process designed for traditional single-processor integrated circuits to handle the packaging needs of multi-processor architectures. This lidding process can be summarized into four core steps: dispensing, lidding, pre-curing, and curing. Specifically, dispensing is to accurately apply adhesive along the periphery of the substrate using automated equipment. Lidding is to precisely place a metal cover on the substrate and achieve preliminary bonding through hot pressing. Pre-curing is to perform preliminary curing treatment on the bonding material. Finally, curing completely transforms the bonding material into a stable state through baking to form a firm connection and prevent the cover plate from separating from the substrate. Although this lidding process can well meet the needs of traditional single-processor integrated circuits, for multi-processor integrated circuits, the yield rate of products using this lidding process can only reach about 70%. Moreover, due to the stable glassy state of the adhesive between the cover plate and the substrate after curing, even if product morphology problems are found later and the cover plate needs to be re-lidded, the cured adhesive is difficult to soften, making rework very difficult. SUMMARY

[0005] In view of the low yield rate and high rework difficulty of the multi-processor integrated circuit packaging structure in the related art, the present application provides a preparation method of a multi-processor integrated circuit packaging structure and the packaging structure.

[0006] In one aspect, the present application provides a preparation method of a multi-processor integrated circuit packaging structure, which adopts the following technical solution:

[0007] A method for manufacturing a multi-processor integrated circuit package structure, comprising the following main steps:

[0008] S1, providing a substrate, a surface of the substrate defining an active area and a peripheral area, the active area integrating a plurality of processor chips;

[0009] S2, forming an adhesive structure in the peripheral area;

[0010] S3, disposing a cover plate on the surface of the substrate, the cover plate being connected with the substrate through the adhesive structure, and the cover plate covering the active area;

[0011] S4, performing a pre-curing treatment on the adhesive structure to form a pre-cured package structure;

[0012] S5, performing a warpage measurement on the pre-cured package structure to obtain micro-deformation data;

[0013] S6, determining a structure morphology of the pre-cured package structure according to the micro-deformation data, the structure morphology including a normal morphology and an abnormal morphology;

[0014] S7, when the pre-cured package structure is in the abnormal morphology, performing a rework treatment on the pre-cured package structure;

[0015] S8, when the pre-cured package structure is in the normal morphology, performing a curing treatment on the pre-cured package structure.

[0016] By the above technical solution, after the pre-curing treatment and before the complete curing treatment, the steps of warpage measurement, structure morphology determination, and rework treatment on the abnormal morphology are added. In this way, the abnormal morphology problem of the package structure caused by the stress unevenness due to the multi-processor architecture can be found and corrected in time at the stage when the adhesive structure has not been completely cured and the rework difficulty is low, so that the product batch yield can reach more than 93%, thereby effectively solving the technical problems of low yield and difficult rework of the multi-processor integrated circuit package in the related art.

[0017] Optionally, the main step S5 comprises the following dependent steps:

[0018] S51, calculating a coordinate of a weighted barycenter of the substrate based on a coordinate of a geometric center of the processor chips and a perimeter weight value;

[0019] S52, determining an observation profile according to the weighted barycenter and the geometric center;

[0020] S53, selecting a measurement point on the observation profile for height measurement to obtain the micro-deformation data.

[0021] The technical scheme is further limited to the specific manner of warpage measurement (main step S5), that is, the micro-deformation data is obtained by calculating the weighted center of the processor, determining the observation profile, and selecting the measurement point on the profile for height measurement. In this way, a systematic and quantifiable operation process is provided for warpage measurement, and through the accurate selection of the observation profile and the measurement point, the data reflecting the deformation of the key position of the packaging structure can be accurately obtained, laying a foundation for subsequent accurate judgment of the structure form. Among them, the perimeter of the processor chip is selected as the weight value because the perimeter can better reflect the boundary length of the interaction between the chip edge and the bonding structure, and this boundary is a key area of thermal stress concentration, so using the perimeter as the weight can more accurately represent the overall stress distribution center under the multi-processor architecture.

[0022] Optionally, in the main step S1, the plurality of processor chips includes a first processor chip and a second processor chip.

[0023] The technical scheme is further limited to the specific manner of warpage measurement (main step S5), that is, the micro-deformation data is obtained by calculating the weighted center of the processor, determining the observation profile, and selecting the measurement point on the profile for height measurement. In this way, a systematic and quantifiable operation process is provided for warpage measurement, and through the accurate selection of the observation profile and the measurement point, the data reflecting the deformation of the key position of the packaging structure can be accurately obtained, laying a foundation for subsequent accurate judgment of the structure form. Among them, the perimeter of the processor chip is selected as the weight value because the perimeter can better reflect the boundary length of the interaction between the chip edge and the bonding structure, and this boundary is a key area of thermal stress concentration, so using the perimeter as the weight can more accurately represent the overall stress distribution center under the multi-processor architecture.

[0024] Optionally, in the dependent step S51, the first geometric center A of the first processor chip and the second geometric center B of the second processor chip are connected to form a processor chip associated line segment AB with the first geometric center A and the second geometric center B as the vertices; the perimeter of the first processor chip is represented as L A , the coordinates of the first geometric center A are represented as (x A ,y A ), the perimeter of the second processor is represented as L B , the coordinates of the second geometric center B are represented as (x B ,y B ), the perimeter weight value w A of the first processor chip and the perimeter weight value w B of the second processor chip are set, and are represented as follows: w A : w A =L A : L B ; based on the coordinates (x A ,y A ) of the first geometric center A, the coordinates (x B ,y B ) of the second geometric center B, the perimeter weight value w A of the first processor chip, and the perimeter weight value w B of the second processor chip, the processor chip associated line segment AB is determined.The coordinates P(x, y) of the weighted barycenter of the substrate 10 are calculated and expressed as follows: , ;

[0025] In the dependent step S52, a first observation profile S determined by the first geometric center A, the second geometric center B and the weighted barycenter P is formed;

[0026] In the dependent step S53, measurement points are selected on the first observation profile S, and the height values of the measurement points are normalized to obtain the micro-deformation data, the measurement points including the first geometric center A, the second geometric center B, the weighted barycenter P and first and second substrate edge observation intersection points P E and P E’ .

[0027] With the above technical solution, the calculation method of the weighted barycenter, the determination method of the observation profile and the specific measurement points are accurately defined for the dual-processor architecture. Among them, the barycenter is calculated by taking the perimeter of the processor as the weight value, which can more reasonably reflect the stress distribution caused by multiple processors; the geometric centers of the two chips and the weighted barycenter are determined as the observation profile, and multiple key points including the chip center, the weighted barycenter and the substrate edge intersection points are selected for measurement, which can comprehensively and representatively capture the micro-deformation of the entire packaging structure along the key axis, thereby realizing accurate characterization of the packaging structure morphology.

[0028] Optionally, in the main step S1, the plurality of processor chips includes a first processor chip, a second processor chip and a third processor chip.

[0029] With the above technical solution, the method is specifically applied to a three-processor architecture including a first, second and third processor chip. In this way, the above measurement method is embodied in another more complex multi-processor integrated circuit configuration, verifying the universality of the scheme and making it more instructive for implementation.

[0030] Optionally, in the dependent step S51, the first geometric center A of the first processor chip, the second geometric center B of the second processor chip and the third geometric center C of the third processor chip are connected to each other to form a processor chip associated triangle ABC with the first geometric center A, the second geometric center B and the third geometric center C as vertices; the perimeter of the first processor chip 21 is represented as L A , the coordinates of the first geometric center A are represented as (x A , y A ), and the perimeter of the second processor chip 22 is represented as LB The coordinates of the second geometric center B are represented as (x... B ,y B The perimeter of the third processor chip 23 is represented as L. C The coordinates of the third geometric center C are represented as (x... C ,y C ), set the perimeter weight value w of the first processor chip 21 A The perimeter weight value w of the second processor chip 22 B and the perimeter weight value w of the third processor chip 22 C , expressed as the following formula: w A :w A :w C =L A :L B :L C Based on the coordinates (x) of the first geometric center A A ,y A ), the coordinates (x) of the second geometric center B B ,y B The coordinates (x, y) of the third geometric center C C ,y C The perimeter weight value w of the first processor chip A The second processor chip perimeter weight value w B and the perimeter weight value w of the third processor chip C The coordinates P(x,y) of the weighted center of gravity of the substrate are calculated as follows: , ;

[0031] In the subordinate step S52, a second observation profile S is formed, which is determined by the first geometric center A and the weighted center P. A The third observation profile S determined by the second geometric center B and the weighted center P B And the fourth observation profile S determined by the third geometric center C and the weighted center P. C ;

[0032] In the subordinate step S53, in the second observation profile S A The third observation profile S B and the fourth observation profile S C Measurement points are determined on each side, and the height values ​​of the measurement points are normalized to obtain the micro-deformation data. The measurement points include: the first geometric center A, the weighted center P, and the point located on the second observation profile S. A The third substrate edge observation intersection point P at the junction with the edge of the substrateAE and a fourth substrate edge observation intersection point P AE’ ; the second geometric center B and a fourth observation profile S B a fifth substrate edge observation intersection point P at the intersection with the edge of the substrate BE and a sixth substrate edge observation intersection point P BE’ ; the third geometric center C and a fourth observation profile S C a seventh substrate edge observation intersection point P at the intersection with the edge of the substrate CE and an eighth substrate edge observation intersection point P CE’ .

[0033] By adopting the technical solution, the calculation method of weighted barycenter, the determination method of observation profile, and the specific measurement points are accurately defined for the three-processor architecture. By connecting the geometric centers of the three processor chips with the weighted barycenter respectively to determine a plurality of observation profiles, and measuring the key points on each profile, the more complex package warping forms under the three-processor architecture can be captured and evaluated more comprehensively from multiple dimensions, ensuring the accuracy of structure form judgment under high-density and complex layout.

[0034] Optionally, in the main step S6, when the micro-deformation data shows that the pre-cured package structure has a single concave, and the maximum depth of the concave is less than or equal to 200 um, it is judged that the pre-cured package structure is in a normal form; when the micro-deformation data shows that the pre-cured package structure has a single convex, multiple convexes, or multiple concaves, it is judged that the pre-cured package structure is in an abnormal form.

[0035] By adopting the technical solution, the specific numerical standards for judging whether the pre-cured package structure is in a “normal form” or an “abnormal form” are defined. For example, a single concave with a maximum depth not greater than 200 um is defined as a normal form, and a single convex, multiple convexes, or multiple concaves are defined as an abnormal form. In this way, clear and quantifiable objective basis is provided for quality control in the production process, avoiding inconsistency caused by subjective judgment, realizing standardized and automated screening of product forms, and ensuring that only qualified semi-finished products can enter the subsequent curing process.

[0036] Optionally, in the main step S7, the pre-cured package structure is arranged on a hot-pressing jig, and a weight is arranged on the pre-cured package structure to perform rework processing on the pre-cured package structure.

[0037] By adopting the technical scheme, a specific and feasible rework processing method is provided, that is, a weight is arranged on the hot-pressing jig to apply pressure on the abnormal pre-cured packaging structure. In this way, a simple and effective physical operation means is provided for the correction of abnormal morphology, and the abnormal deformation in the pre-curing stage can be adjusted back to the normal state through external force intervention, which has high practicability and operability.

[0038] Optionally, in the main step S7, the temperature of the hot-pressing jig and the weight of the weight are adjusted to adjust the structural morphology of the pre-cured packaging structure.

[0039] By adopting the technical scheme, the adjustable parameters of the rework processing are further limited, that is, the temperature of the hot-pressing jig and the weight of the weight are adjusted to finely control the structural morphology of the pre-cured packaging structure. In this way, the rework process is given higher flexibility and accuracy, and the temperature and pressure can be adjusted according to different abnormal morphologies (such as "smile" or "M shape") and their severity, so as to significantly improve the success rate of rework and the yield of the final product.

[0040] On the other hand, the application also provides a multi-processor integrated circuit packaging structure, which adopts the following technical scheme:

[0041] A multi-processor integrated circuit packaging structure is prepared according to the preparation method of the multi-processor integrated circuit packaging structure.

[0042] By adopting the technical scheme, the multi-processor integrated circuit packaging structure prepared has a more ideal and flat structural morphology due to the introduction of the pre-cured warpage detection and rework link in the manufacturing process. In this way, the packaging structure has higher reliability and better consistency, which can effectively avoid problems such as poor subsequent soldering contact caused by abnormal packaging structure morphology, thereby improving the performance and service life of the entire electronic device.

[0043] In summary, the application includes at least one of the following beneficial technical effects:

[0044] 1. After the pre-curing process and before the complete curing process, the steps of warping measurement, structural morphology determination, and rework processing of the abnormal morphology of the pre-cured packaging structure are added. In this way, the abnormal packaging structure morphology problem caused by uneven stress due to the multi-processor architecture can be found and corrected in time at the stage when the bonding structure has not yet been completely cured and the rework difficulty is low, so that the product batch yield can reach more than 93%, thereby effectively solving the technical problems of low yield and difficult rework of the multi-processor integrated circuit packaging in the related art.

[0045] 2. The micro-deformation data is obtained by calculating the weighted center of gravity, determining the observation profile, and measuring the height of the measuring point on the profile. In this way, a systematic and quantifiable operation process is provided for warpage measurement. By accurately selecting the observation profile and measuring point, data reflecting the deformation of the key position of the packaging structure can be accurately obtained, laying a foundation for subsequent accurate judgment of the structure morphology.

[0046] 3. For the dual-processor architecture, the calculation method of the weighted center of gravity, the determination method of the observation profile, and the specific measuring point are accurately defined. Among them, the center of gravity is calculated by taking the perimeter of the processor as the weight value, which can more reasonably reflect the stress distribution caused by multiple processors; the geometric centers of the two chips and the weighted center of gravity are determined as the observation profile, and multiple key points including the intersection of the chip center, the weighted center of gravity and the edge of the substrate are selected for measurement, which can comprehensively and representatively capture the micro-deformation of the entire packaging structure along the key axis, thereby realizing accurate characterization of the packaging structure morphology.

[0047] 4. For the three-processor architecture, the calculation method of the weighted center of gravity, the determination method of the observation profile, and the specific measuring point are accurately defined. Multiple observation profiles are determined by connecting the geometric centers of the three processor chips with the weighted center of gravity, and the key points on each profile are measured, which can more comprehensively capture and evaluate the more complex packaging warpage morphology under the three-processor architecture from multiple dimensions, ensuring the accuracy of the structure morphology judgment under high-density and complex layout.

[0048] 5. The prepared multi-processor integrated circuit packaging structure ensures that the final product has a more ideal and flat structure morphology due to the introduction of the pre-cured warpage detection and rework link in its manufacturing process. In this way, the packaging structure has higher reliability and better consistency, which can effectively avoid problems such as poor subsequent soldering contact caused by abnormal packaging structure morphology, thereby improving the performance and service life of the entire electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 is a main step flow diagram of a preparation method of a multi-processor integrated circuit packaging structure according to Embodiment 1 of the present application;

[0050] Figure 2 is a principle diagram of main step S4 of the preparation method corresponding to Embodiment 1 of the present application;

[0051] Figure 3 is a principle diagram of dependent step S51 of the preparation method corresponding to Embodiment 1 of the present application;

[0052] Figure 4 is a principle diagram of dependent step S52 of the preparation method corresponding to Embodiment 1 of the present application;

[0053] Figure 5 is a schematic diagram corresponding to the principle of the dependent step S53 of the preparation method of Embodiment 1 of the present application;

[0054] Figure 6 is a schematic diagram of the normalized distribution of the height values of the measurement points of Embodiment 1 of the present application, wherein Figure 6 (a) in FIG. 1 shows the translation process, Figure 6 (b) in FIG. 1 shows the rotation process;

[0055] Figure 7 is a schematic diagram of the normal form of the pre-cured packaging structure of Embodiment 1 of the present application;

[0056] Figure 8 is a schematic diagram of the abnormal form of the pre-cured packaging structure of Embodiment 1 of the present application, wherein Figure 8 (a) in FIG. 2 shows the "smile" form, Figure 8 (b) in FIG. 2 shows the "M" form, Figure 8 (c) in FIG. 2 shows the "W" form;

[0057] Figure 9 is a schematic diagram of the relationship between the weight of the weight and the warpage of the pre-cured packaging structure of Embodiment 1 of the present application;

[0058] Figure 10 is a schematic diagram corresponding to the principle of the dependent step S51 of the preparation method of Embodiment 2 of the present application;

[0059] Figure 11 is a schematic diagram corresponding to the principle of the dependent step S52 of the preparation method of Embodiment 2 of the present application;

[0060] Figure 12 is a schematic diagram corresponding to the principle of the dependent step S53 of the preparation method of Embodiment 2 of the present application;

[0061] Figure 13 is a schematic diagram of the normalized distribution of the height values of the measurement points of Embodiment 2 of the present application, wherein Figure 13 (a) in FIG. 3 shows the translation process, Figure 13 (b) in FIG. 3 shows the rotation process.

[0062] BRIEF DESCRIPTION OF REFERENCE NUMERALS: 10, substrate; 21, first processor chip; 22, second processor chip; 23, third processor chip; 30, pre-cured packaging structure. DETAILED DESCRIPTION

[0063] The present application is based on the following insight of the applicant:

[0064] In the preparation process of the traditional hybrid integrated circuit packaging structure, the cover plate is usually bonded on the substrate through the steps of dispensing, capping, pre-curing and curing, and then the offset between the cover plate and the substrate and the gap between the cover plate and the substrate and other parameters are detected. The process flow can well meet the needs of single processor integrated circuits, but when applied to multi-processor integrated circuits, the product batch yield can only reach about 70%.

[0065] The applicant found through research that the main reason for the low yield of the traditional process flow when applied to multi-processor integrated circuits is that, compared to single-processor integrated circuits which only have one processor chip, multi-processor integrated circuits integrate multiple processor chips, making it easy to have uneven stress distribution during capping (in contrast, the stress of single-processor integrated circuits is mainly distributed at the center where the processor chip is located), which makes the multi-processor integrated circuit packaging structure after capping prone to abnormal morphology, thereby causing poor contact in the subsequent welding process. And because the bonding glue between the cover plate and the substrate after curing forms a stable glassy state, even if the product morphology problem is found later and needs to be recapped, the cured bonding glue is difficult to soften, and the rework is difficult.

[0066] Based on this, the application discloses a multi-processor integrated circuit packaging structure and a preparation method thereof. By detecting the structure morphology of the packaging structure after pre-curing, and timely reworking when an abnormality is detected, the product batch yield can reach more than 93%. Thus, the technical defects in the related art are well overcome.

[0067] The following will be described in detail Figures 1-13 The application will be further described in detail. Embodiment 1

[0068] Figure 1 FIG. 1 is a main step flow schematic diagram of a multi-processor integrated circuit packaging structure preparation method according to Embodiment 1 of the application. Referring to FIG. 1, Figure 1 The method comprises the following main steps:

[0069] S1, providing a substrate 10, the surface of the substrate 10 is defined with an active area and a peripheral area, and the active area integrates multiple processor chips.

[0070] S2, forming a bonding structure in the peripheral area.

[0071] S3, disposing a cover plate on the surface of the substrate 10, the cover plate is connected with the substrate 10 through the bonding structure, and the cover plate covers the active area.

[0072] S4, pre-curing the bonding structure to form a pre-cured packaging structure 30.

[0073] S5, warpage measurement is performed on the pre-cured packaging structure 30 to obtain micro-deformation data.

[0074] S6, a structure morphology of the pre-cured packaging structure 30 is determined according to the micro-deformation data, the structure morphology including a normal morphology and an abnormal morphology.

[0075] S7, when the pre-cured packaging structure 30 is in the abnormal morphology, rework processing is performed on the pre-cured packaging structure 30.

[0076] S8, when the pre-cured packaging structure 30 is in the normal morphology, curing processing is performed on the pre-cured packaging structure 30.

[0077] The main steps of the method are described in detail below.

[0078] In main step S1, a substrate 10 is provided, a surface of the substrate 10 is defined with an active area and a peripheral area, and a plurality of processor chips are integrated in the active area. Taking a dual-processor architecture as an example, the plurality of processor chips include a first processor chip 21 and a second processor chip 22.

[0079] In main step S2, an adhesive structure is formed in the peripheral area. Here, an automated dispensing device can be used to accurately and discontinuously apply adhesive along the peripheral contour of the substrate 10 to form a uniform and continuous adhesive line. The automated dispensing device can be a screw-type dispensing valve device or a jet-type dispensing valve device. The screw-type dispensing valve device is suitable for dispensing medium-viscosity glue, while the jet-type dispensing valve device can achieve high-speed and high-precision dispensing. The actual production requirements can be selected.

[0080] In main step S3, a cover plate is arranged on the surface of the substrate 10, the cover plate is connected to the substrate 10 through the adhesive structure, and the cover plate covers the active area.

[0081] Figure 2 is a schematic diagram of the principle of main step S4 corresponding to the preparation method of embodiment 1 of the present application. Referring to Figure 2 In main step S4, pre-curing processing is performed on the adhesive structure to form a pre-cured packaging structure 30. After main step S3, the entire assembly is sent into a hot-pressing device. The substrate 10 is arranged on a hot-pressing jig, and a weight is arranged on the cover plate. By adjusting the heating temperature and the heating time, and by applying a vertical pressure to the cover plate through the weight, the cover plate is pre-cured with the substrate 10 through the adhesive structure.

[0082] In main step S5, warpage measurement is performed on the pre-cured encapsulation structure 30 to obtain microscopic deformation data. Main step S5 includes the following subordinate steps:

[0083] S51. Calculate the coordinates of the weighted center of the substrate 10 based on the coordinates of the geometric center of the processor chip and the perimeter weight value.

[0084] S52. Determine the observation profile based on the weighted center and the geometric center.

[0085] S53. Select measurement points on the observation profile to measure the height and obtain the micro-deformation data.

[0086] Figure 3 This is a schematic diagram of the principle of the subordinate step S51 of the preparation method corresponding to Embodiment 1 of this application. (Refer to...) Figure 3 In the subordinate step S51, the weighted center coordinates of the substrate 10 are calculated based on the geometric center coordinates and perimeter weight values ​​of the processor chip.

[0087] First, the geometric centers of multiple processor chips are connected to form a processor chip association diagram. For a dual-processor architecture, the first geometric center A of the first processor chip 21 and the second geometric center B of the second processor chip 22 are connected to form a processor chip association line segment AB with the first geometric center A and the second geometric center B as vertices.

[0088] Furthermore, the perimeter of the first processor chip 21 is denoted as L. A The coordinates of the first geometric center A are represented as (x... A ,y A Let L represent the perimeter of the second processor chip 22. B The coordinates of the second geometric center B are represented as (x... B ,y B ), set the perimeter weight value w of the first processor chip 21 A and the perimeter weight value w of the second processor chip 22 B , expressed as the following formula: w A :w A =L A :L B .

[0089] Furthermore, based on the coordinates (x, y) of the first geometric center A A ,y A ), the coordinates (x) of the second geometric center B B ,y B The perimeter weight value w of the first processor chip 21 Aand the second processor chip 22 perimeter weight value w B The coordinates P(x, y) of the weighted center of gravity of the substrate 10 are calculated and expressed as follows: , .

[0090] Figure 4 is a schematic diagram of the dependent step S52 corresponding to the preparation method of Embodiment 1 of the present application. Referring to Figure 4 In the dependent step S52, the observation profile is determined according to the weighted center of gravity and the geometric center. For a dual-processor architecture, a first observation profile S determined by the first geometric center A, the second geometric center B and the weighted center of gravity P is formed.

[0091] Figure 5 is a schematic diagram of the dependent step S53 corresponding to the preparation method of Embodiment 1 of the present application. Referring to Figure 5 In the dependent step S53, a measurement point is selected on the observation profile for height measurement to obtain the micro-deformation data. Non-contact three-dimensional topography measurement tools such as high-power microscopes, laser profilers or white light interferometers can be used to measure the height of the measurement point to determine the height value of the measurement point. For a dual-processor architecture, the measurement point includes the first geometric center A, the second geometric center B, the weighted center of gravity P and the first substrate edge observation intersection point P E and the second substrate edge observation intersection point P E’ .

[0092] In order to analyze the product morphology data intuitively later, the height value of the measurement point can be normalized. Figure 6 is a normalized distribution diagram of the height value of the measurement point of Embodiment 1 of the present application, wherein Figure 6 (a) in FIG. 1 shows the translation process, Figure 6 (b) in FIG. 1 shows the rotation process. Referring to Figure 6 The height value of the measurement point is normalized so that the longitudinal coordinate of the first substrate edge observation intersection point P E and the second substrate edge observation intersection point P E’ is zero, and the normalized height value of the measurement point after normalization is taken as the micro-deformation data. First, the height value of the measurement point is translated along the Y-axis direction on the coordinate axis so that the longitudinal coordinate of the first substrate edge observation intersection point P E is zero. Then the first geometric center A, the second geometric center B, the weighted center of gravity P and the second substrate edge observation intersection point P E’The intersection point PE is rotated around the first substrate edge, so that the second substrate edge intersects the intersection point PE E’ at a longitudinal coordinate of zero.

[0093] In step S6, a structure morphology of the pre-cured package structure is determined according to the micro-deformation data, and the structure morphology includes a normal morphology and an abnormal morphology. Figure 7 is a structure schematic diagram of the normal morphology of the pre-cured package structure of embodiment 1 of the present application. Figure 8 is a structure schematic diagram of the abnormal morphology of the pre-cured package structure of embodiment 1 of the present application, wherein Figure 8 (a) in (a) shows a "smile" morphology, Figure 8 (b) in (b) shows an "M" morphology, Figure 8 (c) in (c) shows a "W" morphology. Refer to Figure 7 When the micro-deformation data shows that the height value of the middle measuring point is lower than that of the edge measuring point (for example, after normalization processing, the height value of the weighted barycenter P is less than the height values of the first geometric center A and the second geometric center B, the height value of the first geometric center A is less than the height value of the first substrate edge intersection point PE E , and the height value of the second geometric center B is less than the height value of the second substrate edge intersection point PE E’ , and the maximum depth of the concave is less than or equal to 200 um (for example, the difference between the height value of the weighted barycenter P and the height values of the first substrate edge intersection point PE E and the second substrate edge intersection point PE E’ is less than 200 um), it is judged that the pre-cured package structure 30 is in a "cry face" morphology (that is, a normal morphology), and the main step S8 can be subsequently executed.

[0094] Refer to Figure 8 When it is determined according to the micro-deformation data that the pre-cured package structure 30 is in an abnormal morphology, the main step S7 can be subsequently executed. The abnormal morphology can include a "smile" morphology, an "M" morphology, and a "W" morphology.

[0095] The "smile" morphology refers to a state in which the pre-cured package structure 30 is convex in the middle. In this morphology, the height value of the middle measuring point is higher than that of the edge measuring point. For example, after normalization processing, the height value of the weighted barycenter P is greater than the height values of the first geometric center A and the second geometric center B, the height value of the first geometric center A is greater than the height value of the first substrate edge intersection point PE E , and the height value of the second geometric center B is greater than the height value of the second substrate edge intersection point PE E’ . In this morphology, the main step S7 needs to be subsequently executed.

[0096] The "M-shaped" morphology refers to a state in which the pre-cured packaging structure 30 presents multiple recesses. In this morphology, the height value of multiple intermediate measurement points is lower than that of the adjacent points of the intermediate measurement points, presenting multiple valleys and peaks. For example, after normalization, the height value of the first geometric center A is less than the height value of the first substrate edge observation intersection P E and the height value of the weighted barycenter P, and the height value of the second geometric center B is less than the height value of the second substrate edge observation intersection P E’ and the height value of the weighted barycenter P. Subsequently, main step S7 also needs to be performed in this morphology.

[0097] The "W-shaped" morphology refers to a state in which the pre-cured packaging structure 30 presents multiple protrusions. In this morphology, the height value of multiple intermediate measurement points is higher than that of the adjacent points of the intermediate measurement points, presenting multiple peaks and valleys. For example, after normalization, the height value of the first geometric center A is greater than the height value of the first substrate edge observation intersection P E and the height value of the weighted barycenter P, and the height value of the second geometric center B is greater than the height value of the second substrate edge observation intersection P E’ and the height value of the weighted barycenter P. Subsequently, main step S7 also needs to be performed in this morphology.

[0098] In main step S7, when the pre-cured packaging structure 30 is in an abnormal morphology, the pre-cured packaging structure 30 is subjected to rework processing. Referring again to Figure 2 , in main step S7, the pre-cured packaging structure 30 is arranged on a hot-pressing jig, and a weight is arranged on the pre-cured packaging structure 30. The structure morphology of the pre-cured packaging structure 30 can be changed by adjusting the weight of the weight and the temperature of the hot-pressing jig. Since the temperature of the hot-pressing jig is usually highly relevant to the bonding material, the adjustable range is relatively small. Preferably, the structure morphology of the pre-cured packaging structure 30 can be changed by adjusting the weight of the weight, so that the structure morphology of the pre-cured packaging structure 30 is converted from an abnormal morphology to a normal morphology. Figure 9 is a schematic view of the relationship between the weight of the weight and the warpage of the pre-cured packaging structure according to Embodiment 1 of the present application. Referring to Figure 9 , the weight of the weight and the warpage are basically in a linear relationship. The greater the weight of the weight, the greater the warpage of the pre-cured packaging structure 30. When the warpage is too large, the weight of the weight is appropriately reduced until the warpage of the pre-cured packaging structure 30 is appropriate.

[0099] In main step S8, the pre-cured packaging structure 30 is cured when it is in a normal form. For the pre-cured packaging structure 30 in the normal form, the pre-cured bonding structure is baked at a high temperature to completely change from a semi-solid state to a stable glass state, thereby achieving a durable and reliable connection between the substrate 10 and the cover plate.

[0100] The implementation principle of the method for manufacturing the multi-processor integrated circuit packaging structure in Embodiment 1 is that, after the pre-curing process and before the complete curing process, the steps of warping measurement, form determination, and rework of the pre-cured packaging structure 30 are added. In this way, the abnormal form problem of the packaging structure caused by stress unevenness due to the multi-processor architecture can be found and corrected in time at a stage when the bonding structure has not yet been completely cured and the rework is relatively easy, so that the product batch yield can reach more than 93%, thereby effectively solving the technical problems of low yield and difficult rework of the multi-processor integrated circuit packaging in the related art. Embodiment 2

[0101] Embodiment 2 of the present application discloses another method for manufacturing a multi-processor integrated circuit packaging structure. The main step flow of the method is basically the same as that of Embodiment 1, but the core is that the three-processor architecture is optimized. Compared with Embodiment 1, the main difference of the present embodiment is reflected in the specific implementation of main step S1 (providing a substrate) and main step S5 (warping measurement), which will be described in detail below.

[0102] In main step S1, a substrate 10 is provided, and the surface of the substrate 10 is defined with an active area and a peripheral area, and the active area integrates a plurality of processor chips. Taking a three-processor architecture as an example, the plurality of processor chips include a first processor chip 21, a second processor chip 22, and a third processor chip 23.

[0103] In main step S5, the pre-cured packaging structure 30 is subjected to warping measurement to obtain micro-deformation data. Main step S5 includes the following dependent steps:

[0104] S51, coordinates of a weighted barycenter of the substrate 10 are calculated based on the coordinates of the geometric centers of the processor chips and the perimeter weight values.

[0105] S52, an observation profile is determined according to the weighted barycenter and the geometric centers.

[0106] S53, a measurement point is selected on the observation profile for height measurement to obtain the micro-deformation data.

[0107] Figure 10This is a schematic diagram of the principle of the subordinate step S51 of the preparation method corresponding to Embodiment 2 of this application. (Refer to...) Figure 10 In the subordinate step S51, the weighted center coordinates of the substrate 10 are calculated based on the geometric center coordinates and perimeter weight values ​​of the processor chip.

[0108] First, the geometric centers of multiple processor chips are connected to form a processor chip association diagram. For a three-processor architecture, the first geometric center A of the first processor chip 21, the second geometric center B of the second processor chip 22, and the third geometric center C of the third processor chip 23 are interconnected to form a processor chip association triangle ABC with the first geometric center A, the second geometric center B, and the third geometric center C as vertices.

[0109] Furthermore, the perimeter of the first processor chip 21 is denoted as L. A The coordinates of the first geometric center A are represented as (x... A ,y A Let L represent the perimeter of the second processor chip 22. B The coordinates of the second geometric center B are represented as (x... B ,y B The perimeter of the third processor chip 23 is represented as L. C The coordinates of the third geometric center C are represented as (x... C ,y C ), set the perimeter weight value w of the first processor chip 21 A The perimeter weight value w of the second processor chip 22 B and the perimeter weight value w of the third processor chip 23 C , expressed as the following formula: w A :w A :w C =L A :L B :L C .

[0110] Furthermore, based on the coordinates (x, y) of the first geometric center A A ,y A ), the coordinates (x) of the second geometric center B B ,y B The coordinates (x, y) of the third geometric center C C ,y C The perimeter weight value w of the first processor chip 21 A The second processor chip 22-cycle weight value w B And calculate the perimeter weight value w of the third processor chip 23.C The coordinates P(x, y) of the weighted center of gravity of the substrate 10 are calculated and represented by the following formula: , .

[0111] Figure 11 is a schematic diagram corresponding to the principle of the dependent step S52 of the preparation method of Embodiment 2 of the present application. Referring to Figure 11 , in the dependent step S52, the observation profile is determined according to the weighted center of gravity and the geometric center. For a three-processor architecture, a second observation profile S A determined by the first geometric center A and the weighted center of gravity P, a third observation profile S B determined by the second geometric center B and the weighted center of gravity P, and a fourth observation profile S C determined by the third geometric center C and the weighted center of gravity P are formed.

[0112] Figure 12 is a schematic diagram corresponding to the principle of the dependent step S53 of the preparation method of Embodiment 2 of the present application. Referring to Figure 12 , in the dependent step S53, the measurement points are selected on the observation profile for height measurement to obtain the micro-deformation data. The height measurement of the measurement points can be performed by using non-contact three-dimensional topography measurement tools such as a high-power microscope, a laser profiler, or a white light interferometer to determine the height values of the measurement points. For a three-processor architecture, the measurement points are determined on the second observation profile S A , the third observation profile S B , and the fourth observation profile S C , respectively. The measurement points include the first geometric center A on the second observation profile S A , the weighted center of gravity P, and the third substrate edge observation intersection P A and the fourth substrate edge observation intersection P AE located at the intersection of the second observation profile S AE’ and the edge of the substrate 10; the second geometric center B on the third observation profile S B , and the fifth substrate edge observation intersection P B and the sixth substrate edge observation intersection P BE located at the intersection of the third observation profile S BE’ and the edge of the substrate 10; the third geometric center C on the fourth observation profile S C , and the seventh substrate edge observation intersection P C and the eighth substrate edge observation intersection P CE located at the intersection of the fourth observation profile S CE’ and the edge of the substrate 10.

[0113] In order to intuitively analyze the product shape data later, the height values of the measurement points can be normalized. Figure 13 is a normalized distribution diagram of the height values of the measurement points in Embodiment 2 of the present application, wherein Figure 13 (a) in (a) shows the translation process, Figure 13 (b) in (b) shows the rotation process. Refer to Figure 13 The height values of the measurement points are normalized so that the longitudinal coordinate of the substrate edge observation intersection point P XE and P XE’ (P XE may be P AE , P BE and P CE , P XE’ may be P AE’ , P BE’ and P CE’ ) is zero, and the normalized height values of the measurement points after normalization are taken as the micro-deformation data. First, the height values of the measurement points are translated along the Y-axis direction on the coordinate axis so that the longitudinal coordinate of the substrate edge observation intersection point P XE is zero. Then, the other observation points are rotated around the substrate edge observation intersection point P XE so that the longitudinal coordinate of the substrate edge observation intersection point P XE’ is zero.

[0114] The implementation principle of the preparation method of the multi-processor integrated circuit package structure in Embodiment 2 of the present application is that for a three-processor architecture, the calculation method of the weighted barycenter, the determination method of the observation profile, and the specific measurement points are precisely defined. By connecting the geometric centers of the three processor chips with the weighted barycenter respectively to determine a plurality of observation profiles, and measuring the key points on each profile, the more complex package warping shape under the three-processor architecture can be captured and evaluated more comprehensively from multiple dimensions, ensuring the accuracy of structure shape judgment under high density and complex layout.

[0115] It should be understood that although Embodiments 1 and 2 of the present application respectively take the dual-processor architecture and the three-processor architecture as examples to explain the preparation method of the multi-processor integrated circuit package structure in detail, these embodiments are only used to illustrate the principles of the present application and should not be regarded as limiting the protection scope of the present application. It can be foreseen by those skilled in the art that the preparation method of the present application is also applicable to other multi-processor integrated circuit package structures integrated with any number of processor chips. Embodiment 3

[0116] The application further discloses a multi-processor integrated circuit packaging structure prepared based on the preparation method of the multi-processor integrated circuit packaging structure as described in the embodiment 1 or the embodiment 2.

[0117] The application discloses a multi-processor integrated circuit packaging structure.

[0118] The above are preferred embodiments of the application, and do not limit the protection scope of the application, so: all equivalent changes made according to the structure, shape, principle of the application should be covered in the protection scope of the application.

Claims

1. A method for fabricating a multiprocessor integrated circuit package structure, characterized in that, The main steps include the following: S1. Provide a substrate (10), the surface of which is defined as an active region and a peripheral region, the active region integrating a plurality of processor chips, the plurality of processor chips including a first processor chip (21) and a second processor chip (22); S2. An adhesive structure is formed in the peripheral area; S3. A cover plate is provided on the surface of the substrate (10), the cover plate is connected to the substrate (10) through the adhesive structure, and the cover plate covers the active area; S4. The adhesive structure is pre-cured to form a pre-cured encapsulation structure (30); S5. Perform warpage measurement on the pre-cured encapsulation structure (30) to obtain microscopic deformation data; S6. Determine the structural morphology of the pre-cured encapsulation structure (30) based on the micro-deformation data. The structural morphology includes normal morphology and abnormal morphology. S7. When the pre-cured encapsulation structure (30) is in an abnormal state, the pre-cured encapsulation structure (30) shall be reworked. S8. When the pre-cured encapsulation structure (30) is in its normal state, the pre-cured encapsulation structure (30) is cured. Main step S5 includes the following subordinate steps: S51. Calculate the coordinates of the weighted center of the substrate (10) based on the coordinates of the geometric center of the processor chip and the perimeter weight value; S52. Determine the observation profile based on the weighted center and the geometric center; S53. Select a measurement point on the observation profile to measure the height and obtain the micro-deformation data; In the subordinate step S51, the first geometric center A of the first processor chip (21) and the second geometric center B of the second processor chip (22) are connected to form a processor chip association line segment AB with the first geometric center A and the second geometric center B as vertices; the perimeter of the first processor chip (21) is represented as L. A The coordinates of the first geometric center A are represented as (x... A ,y A Let L represent the perimeter of the second processor chip (22). B The coordinates of the second geometric center B are represented as (x... B ,y B Set the perimeter weight value w of the first processor chip (21). A and the perimeter weight value w of the second processor chip (22) B , expressed as the following formula: w A :w A =L A :L B Based on the coordinates (x) of the first geometric center A A ,y A ), the coordinates (x) of the second geometric center B B ,y B The perimeter weight value w of the first processor chip (21) A and the perimeter weight value w of the second processor chip (22) B The coordinates P(x,y) of the weighted center of gravity of the substrate (10) are calculated as follows: In the subordinate step S52, a first observation profile S is formed by the first geometric center A, the second geometric center B and the weighted center P; In subordinate step S53, measurement points are selected on the first observation profile S, and the height values ​​of the measurement points are normalized to obtain the micro-deformation data. The measurement points include: the first geometric center A, the second geometric center B, the weighted center P, and the first substrate edge observation intersection point P located at the junction of the first observation profile S and the edge of the substrate (10). E Intersection P of the second substrate edge observation point E’ .

2. The method for fabricating a multiprocessor integrated circuit packaging structure according to claim 1, characterized in that, In the main step S1, the plurality of processor chips include a first processor chip (21), a second processor chip (22), and a third processor chip (23).

3. The method for fabricating a multiprocessor integrated circuit packaging structure according to claim 2, characterized in that, In subordinate step S51, the first geometric center A of the first processor chip (21), the second geometric center B of the second processor chip (22), and the third geometric center C of the third processor chip (23) are connected to each other to form a processor chip association triangle ABC with the first geometric center A, the second geometric center B, and the third geometric center C as vertices; the perimeter of the first processor chip (21) is represented as L. A The coordinates of the first geometric center A are represented as (x... A ,y A Let L represent the perimeter of the second processor chip (22). B The coordinates of the second geometric center B are represented as (x... B ,y B Let L represent the perimeter of the third processor chip (23). C The coordinates of the third geometric center C are represented as (x... C ,y C Set the perimeter weight value w of the first processor chip (21). A The perimeter weight value w of the second processor chip (22) B and the perimeter weight value w of the third processor chip (23) C , expressed as the following formula: w A :w A :w C =L A :L B :L C Based on the coordinates (x) of the first geometric center A A ,y A ), the coordinates (x) of the second geometric center B B ,y B The coordinates (x) of the third geometric center C C ,y C The perimeter weight value w of the first processor chip (21) A The perimeter weight value w of the second processor chip (22) B and the perimeter weight value w of the third processor chip (23) C The coordinates P(x,y) of the weighted center of gravity of the substrate (10) are calculated as follows: In the subordinate step S52, a second observation profile S is formed, which is determined by the first geometric center A and the weighted center P. A The third observation profile S determined by the second geometric center B and the weighted center P B And the fourth observation profile S determined by the third geometric center C and the weighted center P. C ; In the subordinate step S53, in the second observation profile S A The third observation profile S B and the fourth observation profile S C Measurement points are determined on each side, and the height values ​​of the measurement points are normalized to obtain the micro-deformation data. The measurement points include: the first geometric center A, the weighted center P, and the point located on the second observation profile S. A The third substrate edge observation intersection point P at the junction with the edge of the substrate (10) AE Intersection point P with the fourth substrate edge observation point AE’ The second geometric center B and the third observation profile S B The fifth substrate edge observation intersection point P at the junction with the edge of the substrate (10) BE Intersection point P with the sixth substrate edge observation point BE The third geometric center C and the fourth observation profile S C The seventh substrate edge observation intersection point P at the junction with the edge of the substrate (10) CE Intersection point P with the edge observation of the eighth substrate CE’ .

4. The method for fabricating a multiprocessor integrated circuit packaging structure according to any one of claims 1-3, characterized in that, In the main step S6, when the micro-deformation data shows that the pre-cured encapsulation structure (30) has a single depression and the maximum depth of the depression is less than or equal to 200um, it is determined that the pre-cured encapsulation structure (30) is in a normal state. When the microscopic deformation data shows that the pre-cured encapsulation structure (30) has a single protrusion, multiple protrusions, or multiple depressions, it is determined that the pre-cured encapsulation structure (30) is in an abnormal state.

5. The method for fabricating a multiprocessor integrated circuit packaging structure according to claim 1, characterized in that, In the main step S7, the pre-cured encapsulation structure (30) is placed on a hot press fixture, and weights are placed on the pre-cured encapsulation structure (30) to rework the pre-cured encapsulation structure (30).

6. The method for fabricating a multiprocessor integrated circuit packaging structure according to claim 5, characterized in that, In the main step S7, the structural form of the pre-cured encapsulation structure (30) is adjusted by adjusting the temperature of the hot pressing fixture and the weight of the weight.

7. A multiprocessor integrated circuit packaging structure, characterized in that, The multiprocessor integrated circuit package structure is prepared according to the preparation method of any one of claims 1-6.

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