Etching method of bonding pad covering layer
By combining Ar treatment and N111 reagent wet cleaning during the pad etching process, fluorine on the pad surface is completely removed, solving the problem of fluorine crystallization defects and improving the reliability and storage stability of semiconductor packaging.
Patent Information
- Application Number
- CN202511044675.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-14
AI Technical Summary
In the semiconductor packaging process, fluorine crystal defects (PDCY) on the surface of the pads lead to bonding failure and reduced reliability. Existing technologies are unable to effectively remove fluorine from the surface of the pads.
A combination of Ar treatment and N111 reagent wet cleaning was used to remove the metal layer, oxide layer and second interlayer dielectric layer on the surface of the pads by etching. After each etching pass, Ar treatment was performed, followed by Ar bombardment and high-temperature annealing to completely remove the fluorine from the surface of the pads.
It effectively prevents the formation of fluorine crystals on the solder pad surface, extends the safe storage time of the product, and improves bonding quality and reliability.
Smart Images
Figure CN120954984A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for etching a pad cover layer. Background Technology
[0002] Bonding is a crucial process in semiconductor packaging, where different metal wires are bonded to interconnect the internal chip and external leads of the device, enabling the chip to perform its functions. In modern semiconductor processes, with increasing chip integration and shrinking dimensions, the precision requirements for microelectronic packaging are becoming increasingly stringent, making it more challenging to control and improve bonding quality and reliability.
[0003] In the process of aluminum pad (Al PAD), the gas used to etch the top passivation layer contains fluorine, and the reagents used for wet cleaning of aluminum pad (Al PAD) also usually contain fluorine. When the device is in a suitable environment for a long time, the aluminum pad will react with H2O / O2 in the air and fluorine crystal defects will occur. Fluorine crystal defects (Pad crystal defect, PDCY) of aluminum pads are one of the main causes of bonding failure in the process, which will lead to a decrease in device reliability.
[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide an etching method for pad cover layers to solve the problem of crystal formation on the pad surface.
[0006] To solve the above technical problems, the present invention provides a method for etching a pad cover layer, comprising the following steps:
[0007] Provide a pad, and sequentially remove the metal layer, oxide layer and second interlayer dielectric layer on the surface of the pad by etching. After etching, treat the pad with Ar.
[0008] The pads were wet-cleaned using N111 reagent, and bombarded with Ar to remove fluorine from the surface of the pads. The pads were then annealed.
[0009] Preferably, the metal layer, oxide layer and second interlayer dielectric layer on the surface of the pad are removed sequentially by etching, including: covering the second interlayer dielectric layer with photoresist and photolithographically exposing the area to be etched, and removing the metal layer, oxide layer and second interlayer dielectric layer by at least three etching processes.
[0010] Preferably, the metal layer, oxide layer, and second interlayer dielectric layer are removed by a three-stage etching process.
[0011] Preferably, the second interlayer dielectric layer and part of the oxide layer are removed by a first etching pass.
[0012] Preferably, the remaining oxide and metal layers are removed by a second etching process, and a polymer is also formed on the etched pads.
[0013] Preferably, the polymer is removed by a third etching pass.
[0014] Preferably, the pads are treated with Ar after each etching pass.
[0015] Preferably, the pads are treated with Ar after three etching processes.
[0016] Preferably, the pads are annealed at 420°C.
[0017] Preferably, the annealing time for the solder pads is 1 hour.
[0018] In the etching method for the pad cover layer provided by this invention, the pads are treated with Ar after etching the metal layer, oxide layer, and second interlayer dielectric layer on the pad surface, and then bombarded with Ar after wet cleaning with N111 reagent. This thoroughly removes residual fluorine from the pad surface, prevents crystal formation, and extends the safe storage time. Furthermore, using Ar bombardment to remove the fluorinated aluminum layer on the pad surface facilitates batch processing of pads in this process. Attached Figure Description
[0019] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0020] Figure 1 This is a schematic diagram of photoresist in existing technology;
[0021] Figure 2 This is a schematic diagram of the structure of the first etching step in existing technology;
[0022] Figure 3 This is a schematic diagram of the structure of the second etching step in existing technology;
[0023] Figure 4 This is a schematic diagram of the structure of the third etching step in existing technology;
[0024] Figure 5 This is a schematic diagram of the structure of existing Ar processing technology;
[0025] Figure 6 This is a schematic diagram of the structure of existing wet cleaning technology;
[0026] Figure 7 This is a schematic diagram of the structure after annealing in the prior art;
[0027] Figure 8 This is an execution flowchart of an embodiment of the present invention;
[0028] Figure 9 This is a schematic diagram of photoresist coverage according to an embodiment of the present invention;
[0029] Figure 10 This is a schematic diagram of the structure of the first etching step in an embodiment of the present invention;
[0030] Figure 11 This is a schematic diagram of the structure of the second etching step in an embodiment of the present invention;
[0031] Figure 12 This is a schematic diagram of the third etching step in an embodiment of the present invention;
[0032] Figure 13 This is a schematic diagram of the structure of the first Ar process according to an embodiment of the present invention;
[0033] Figure 14 This is a schematic diagram of a wet cleaning method according to an embodiment of the present invention;
[0034] Figure 15 This is a schematic diagram of the second Ar process according to an embodiment of the present invention;
[0035] Figure 16 This is a schematic diagram of the annealing structure according to an embodiment of the present invention;
[0036] Figure 17 This is a graph illustrating the improvement of Auger results by the PDCY process according to an embodiment of the present invention.
[0037] In the attached image:
[0038] 100. First interlayer dielectric layer; 101. Oxide layer; 102. Pad; 103. Second interlayer dielectric layer; 104. Metal layer; 105. Photoresist; 106. Polymer. Detailed Implementation
[0039] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0040] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0041] The inventors discovered that the formation mechanism of fluorine crystal defect (PDCY) is mainly due to the presence of trace amounts of fluorine on the surface of pad 102. Long-term storage can cause the fluorine on the surface to react with moisture in the storage environment and pad 102 to form crystals, as shown in the following reaction formula.
[0042]
[0043] like Figures 1 to 4 As shown, during the sequential etching of the second interlayer dielectric layer 103, oxide layer 101, and metal layer 104 using photoresist 105, fluorine is introduced with each etching step, even after Ar treatment following etching. Figure 5 As shown, however, during the subsequent wet cleaning process, the cleaning reagent will still introduce fluorine elements, such as... Figure 6 and Figure 7 As shown, this results in fluorine residue on the surface of pad 102, forming crystals.
[0044] Based on this, the core idea of this invention is to remove fluorine elements by treating the pad 102 with Ar after etching, and by bombarding the pad 102 with Ar after wet cleaning, thus removing fluorine elements before crystal formation and preventing fluorine elements from remaining on the surface of the pad 102 and forming crystals. Furthermore, using Ar bombardment to remove the fluorine-containing aluminum layer on the surface of the pad 102 facilitates the batch processing of pads in this process.
[0045] For details, please refer to Figures 8-17 This is a schematic diagram of an embodiment of the present invention. Figure 8 As shown, a method for etching a pad cover layer includes the following steps:
[0046] S1, provide pad 102, and sequentially remove the metal layer 104, oxide layer 101 and second interlayer dielectric layer 103 on the surface of the pad 102 by etching, and treat the pad 102 with Ar after etching.
[0047] S2, the pad 102 is wet-cleaned using N111 reagent, the pad 102 is bombarded with Ar to remove fluorine from the surface of the pad 102, and then the pad 102 is annealed.
[0048] In one embodiment, after etching the metal layer 104, oxide layer 101, and second interlayer dielectric layer 103 on the surface of the pad 102, the pad 102 is treated with Ar, and after wet cleaning with N111 reagent, the pad 102 is bombarded with Ar to thoroughly remove residual fluorine from the surface of the pad 102, prevent crystal formation, and extend the safe storage time. Further, the fluorinated aluminum layer on the surface of the pad 102 is removed by Ar bombardment. Since PVD cannot be mass-produced, Ar etching is used to remove the fluorinated aluminum layer. Understandably, after etching and preliminary Ar treatment, wet cleaning with NE111 solution is performed first, such as... Figure 14 As shown, the NE111 solution also contains a certain amount of fluorine. Therefore, Ar etching was used to remove the fluorine after cleaning.
[0049] like Figure 17The chart showing the improvement of Auger results by the PDCY process illustrates the fluorine content in the depth of the aluminum pad 102 after conventional treatment (BSL, Baseline), final annealing (FinalANN, FinalAnneal), Ar deposition (PVDAr), EKC cleaning, and Ar etching (EtchAr). Removing the fluorinated aluminum layer on the surface of the aluminum pad 102 via Ar bombardment significantly reduces the fluorine content, preventing crystallization during product storage and extending the safe storage time. Since PVD cannot be mass-produced, Ar etching is used to remove the fluorinated aluminum layer. EKC is a specially designed cleaning agent typically used to remove residues and impurities after etching, especially those left after copper etching. The EKC formulation is optimized to clean even stubborn residues.
[0050] Specifically, the metal layer 104, oxide layer 101 and second interlayer dielectric layer 103 on the surface of the pad 102 are removed sequentially by etching, including: covering the second interlayer dielectric layer 103 with photoresist 105 and photolithographically exposing the area to be etched, and removing the metal layer 104, oxide layer 101 and second interlayer dielectric layer 103 by at least three etching processes.
[0051] like Figure 9 As shown, photoresist 105 is coated on the second interlayer dielectric layer 103, and photolithography is performed through processes such as exposure and development to form a pattern that exposes the top area of the pad 102. The photoresist 105 is, for example, an adhesive photoresist film used in semiconductor chip packaging or printed circuit board manufacturing. It is usually a photosensitive polymer material, such as polyimide (PI), bis-benzocyclobutene (BCB), or poly(p-phenylene-2,6-BenzobisOxazole).
[0052] In one embodiment, the metal layer 104, oxide layer 101, and second interlayer dielectric layer 103 are removed by a three-stage etching process. Here, we will only illustrate the removal of the metal layer 104, oxide layer 101, and second interlayer dielectric layer 103 on the top of the aluminum pad 102 using a three-stage plasma gas etching process. It should be noted that the method of removing the dielectric layer on the top of the aluminum pad 102 is not limited to this.
[0053] First, a main etching process is performed on multiple dielectric layers on pad 102, removing the second interlayer dielectric layer 103 and part of the oxide layer 101 through a first etching pass. For example... Figure 10 As shown, the second interlayer dielectric layer 103 and part of the oxide layer 101 are etched by fluorine-containing gas.
[0054] The oxide layer 101 is PEOX, which is a SiO2 thin film grown by chemical vapor deposition (PECVD). The oxide layer 101 is disposed on the first interlayer dielectric layer 100, and part of the oxide layer 101 also covers the metal layer 104; the pad 102 is made of aluminum. The first interlayer dielectric layer 100 and the second interlayer dielectric layer 103 are both silicon nitride. Metal layers 104 are disposed on the top and bottom of the pad 102, and the metal layers 104 are Ti or TiN.
[0055] Secondly, etching is performed to remove the remaining oxide layer 101 and metal layer 104 through a second etching pass, and polymer 106 is formed on the etched pads 102. For example... Figure 11 As shown, the remaining oxide layer 101 and metal layer 104 are etched using a fluorine-containing gas. During over-etching, a polymer layer 106 is also formed on the pad 102.
[0056] Finally, the polymer 106 is removed by a third etching pass. During the second etching process, a layer of polymer 106 is formed on the pad 102, such as... Figure 12 As shown, fluorine-containing gas etching is used to thin the polymer 106. Removing the fluorine-containing aluminum layer on the surface of the aluminum pad 102 by Ar bombardment can significantly reduce the fluorine content on the surface of the pad 102, prevent crystallization during product storage, and extend the safe storage time of the product.
[0057] In one embodiment, the pad 102 is treated with Ar after each etching pass. Fluorine is introduced into the etching gas in each pass, and an additional Ar treatment of the pad 102 after each etching pass can remove any residual fluorine. This reduces the fluorine content on the surface of the aluminum pad 102; typically, the thickness of the fluorinated aluminum layer is approximately [missing information]. Removing fluorine from the fluorinated aluminum layer can improve subsequent crystallization issues.
[0058] In one embodiment, the pad 102 is treated with Ar after three etching processes. For example... Figure 13 As shown, the metal layer 104, oxide layer 101 and second interlayer dielectric layer 103 on the top of the pad 102 are removed by the above etching process. After etching, Ar is used to remove the residual fluorine on the surface of the pad 102.
[0059] Understandably, after etching and initial Ar treatment, a wet cleaning process is performed using NE111 solution, such as... Figure 14 As shown, the NE111 solution also contains a certain amount of fluorine. Therefore, after cleaning, Ar etching is used to remove the fluorine. Figure 15 As shown, further treatment of pad 102 using high-temperature annealing can appropriately increase the annealing temperature, causing the fluorine on the surface of aluminum pad 102 to volatilize, thereby reducing the fluorine content. Figure 16 As shown.
[0060] Specifically, the pad 102 is annealed at 420°C for 1 hour. High-temperature annealing of the pad 102 increases the final annealing temperature, causing fluorine to evaporate from the surface of the aluminum pad 102, thereby reducing the fluorine content.
[0061] like Figure 17 The chart showing the improvement of Auger process by PDCY technology illustrates the fluorine content in the depth of aluminum pad 102 after conventional treatment (BSL, Baseline), final annealing (FinalANN, FinalAnneal), Ar deposition (PVD Ar), EKC cleaning, and Ar etching (EtchAr). EKC effectively removes some of the fluorinated aluminum layer on the surface of pad 102. The fluorine content of the aluminum layer on the EKC BSL surface is significantly lower than that of NE111 BSL, which matches the fact that the safe storage time of EKC BSL products is greater than that of NE111 BSL products. The fluorinated aluminum layer on the surface of aluminum pad 102 is removed by Ar bombardment. Since PVD cannot be mass-produced, the EtchAr method is used to remove the fluorinated aluminum layer. During the final annealing (FinalANN, FinalAnneal), the pad 102 is treated with high-temperature annealing. The annealing temperature can be appropriately increased to allow fluorine on the surface of the aluminum pad 102 to evaporate, thereby reducing the fluorine content. For example, the pad 102 is annealed at 420°C. The annealing time for the pad 102 is 1 hour.
[0062] In the etching method for the pad cover layer provided by this invention, after etching the metal layer 104, oxide layer 101, and second interlayer dielectric layer 103 on the surface of the pad 102, the pad 102 is treated with Ar, and after wet cleaning with N111 reagent, the pad 102 is bombarded with Ar to thoroughly remove residual fluorine on the surface of the pad 102, prevent crystal formation, and extend the safe storage time. Further, the fluorine-containing aluminum layer on the surface of the pad 102 is removed by Ar bombardment. Since PVD cannot be mass-produced, the fluorine-containing aluminum layer is removed by etching with Ar. The pad 102 is annealed at 420°C for 1 hour. High-temperature annealing of the pad 102 allows for an appropriate increase in annealing temperature, causing fluorine on the surface of the aluminum pad 102 to volatilize and reducing the fluorine content.
[0063] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for etching a pad cover layer, characterized in that, Includes the following steps: Provide a pad, and sequentially remove the metal layer, oxide layer and second interlayer dielectric layer on the surface of the pad by etching. After etching, treat the pad with Ar. The pads were wet-cleaned using N111 reagent, and bombarded with Ar to remove fluorine from the surface of the pads. The pads were then annealed.
2. The etching method for the pad cover layer according to claim 1, characterized in that, The metal layer, oxide layer and second interlayer dielectric layer on the surface of the pad are removed sequentially by etching, including: covering the second interlayer dielectric layer with photoresist and photolithographically exposing the area to be etched, and removing the metal layer, oxide layer and second interlayer dielectric layer by at least three etching processes.
3. The etching method for the pad cover layer according to claim 2, characterized in that, The metal layer, oxide layer, and second interlayer dielectric layer are removed by a three-stage etching process.
4. The etching method for the pad cover layer according to claim 3, characterized in that, The second interlayer dielectric layer and part of the oxide layer are removed by the first etching pass.
5. The etching method for the pad cover layer according to claim 4, characterized in that, The second etching process removes the remaining oxide and metal layers, and also forms a polymer on the etched pads.
6. The etching method for the pad cover layer according to claim 5, characterized in that, The polymer is removed by a third etching pass.
7. The etching method for the pad cover layer according to claim 2, characterized in that, The pads are treated with Ar after each etching pass.
8. The etching method for the pad cover layer according to claim 3, characterized in that, The pads are treated with Ar after three etching processes.
9. The etching method for the pad cover layer according to claim 1, characterized in that, The pads are annealed at 420°C.
10. The etching method for the pad cover layer according to claim 9, characterized in that, The annealing time for the pads is 1 hour.