Method for reducing relaxation and distinguishing thickness of epitaxial layer

Abstract

The invention discloses an epitaxial layer thickness distinguishing method for reducing relaxation, which at least comprises the following steps of: S1, providing a wafer, and epitaxially growing a seed layer on the surface of the wafer; s2, epitaxially growing a mark layer on the surface of the seed layer; s3, epitaxially growing a main body layer on the surface of the marking layer; wherein the difference value between the atomic number of a marking element in the marking layer and the atomic number of a doping element in the main body layer is greater than or equal to 5. The mark layer is epitaxially grown between the epitaxial layers, so that the brightness of the Z contrast images of the epitaxial layers and the mark layer is remarkably different, the thickness of each epitaxial layer can be accurately distinguished, and the relaxation is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for reducing relaxation in distinguishing epitaxial layer thickness. Background Technology

[0002] In the semiconductor manufacturing field, the quality of epitaxial thin films is a key factor determining the performance and reliability of semiconductor devices. Among these, film thickness, thickness uniformity, film concentration, and concentration uniformity are crucial indicators for measuring film quality. In material systems such as germanium-silicon, carbon-silicon, and phosphorus-silicon, testing and characterizing the content of doping elements such as germanium, carbon, and phosphorus to achieve target concentrations is essential for realizing the desired performance of semiconductor devices.

[0003] Currently, techniques such as ellipsometry (SE), transmission electron microscopy (TEM), X-ray diffraction (XRD), and secondary ion mass spectrometry (SIMS) are widely used to measure the thickness and concentration of epitaxial thin films. These techniques are particularly effective for high-quality thin films grown on planarized wafers (unpatterned wafers), allowing for precise measurement of thickness and concentration. However, when dealing with patterned wafers, the complex trench structure on their surface renders SE and XRD techniques unsuitable. In such cases, high-angle annular dark-field (HAADF) imaging in scanning transmission electron microscopy (STEM) mode is required to measure the thickness of epitaxial films on patterned wafers, combined with the line scan and mapping functions of energy dispersive X-ray spectroscopy (EDS) for micro-area elemental analysis.

[0004] However, as semiconductor processes evolve towards advanced nodes, the application of composite epitaxial layers, such as multilayer germanium-silicon epitaxial layers and multilayer phosphorus-silicon epitaxial layers, is becoming increasingly common. In composite epitaxial layers, the doping element concentrations between adjacent epitaxial layers are similar, and the brightness of their Z-contrast images is also similar. Existing characterization techniques struggle to accurately distinguish the interfaces between these adjacent film layers with similar doping element concentrations, thus affecting the accurate measurement of the thickness of each layer in multilayer epitaxial films and consequently hindering the development and optimization of advanced processes. Summary of the Invention

[0005] The purpose of this invention is to accurately distinguish the thickness of each epitaxial layer by epitaxially growing a marker layer between epitaxial layers with similar doping element concentrations during the epitaxial growth process, thereby creating a significant difference in the brightness of the Z-contrast images of each epitaxial layer and the marker layer.

[0006] To achieve the above objectives, the present invention provides a method for reducing relaxation in distinguishing epitaxial layer thicknesses, comprising at least the following steps:

[0007] Step S1: Provide a wafer and epitaxially grow a seed layer on the surface of the wafer;

[0008] Step S2: An epitaxial marker layer is grown on the surface of the seed layer;

[0009] Step S3: Epitaxially grow the main body layer on the surface of the marking layer;

[0010] Wherein, the difference between the atomic number of the marker element in the marker layer and the atomic number of the dopant element in the main layer is ≥5.

[0011] Optionally, the main layer is any one of germanium-silicon, boron-doped germanium-silicon, germanium-tin, or pure germanium, and the marking layer is silicon.

[0012] Optionally, the host layer is any one of germanium-silicon, boron-doped germanium-silicon, and germanium-tin, and the content of doped elements in the host layer is 15%-40%.

[0013] Optionally, the process temperature for epitaxially growing the host layer is 300℃-800℃, and the process pressure for epitaxially growing the host layer is 5 Torr-300 Torr.

[0014] Optionally, the process temperature for epitaxially growing the marker layer does not exceed 10% of the process temperature for epitaxially growing the main layer.

[0015] Optionally, the main body layer is any one of tin silicon, phosphorus silicon, phosphorus-doped silicon carbide, silicon carbide, silicon arsenide, and phosphorus-doped silicon arsenide, and the doping element content in the main body layer is 5%-20%; the marking layer is germanium silicon, and the marking element content in the marking layer is 5%-20%.

[0016] Optionally, the process temperature for epitaxially growing the host layer is 450℃-800℃, and the process pressure for epitaxially growing the host layer is 100Torr-700Torr.

[0017] Optionally, the main body layer is at least one layer, and the difference in the content of doped elements in each main body layer does not exceed 5%.

[0018] Optionally, the marker layer may be epitaxially grown between adjacent main layers.

[0019] Optionally, the thickness of the marking layer is 1nm-20nm.

[0020] Optionally, the wafer is a planarized wafer or a patterned wafer.

[0021] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0022] 1) During wafer epitaxial growth, a marker layer is epitaxially grown between the seed layer and the main layer, and between adjacent main layers in multiple main layers. When the difference between the atomic number of the marker element in the marker layer and the atomic number of the doped element in the main layer is ≥5, there is a significant difference in the brightness of the Z-contrast image between the marker layer and the main layer, making the interface between adjacent film layers very clear, which is beneficial for accurately distinguishing the thickness of each epitaxial layer.

[0023] 2) The material and process parameters of the marker layer have been optimized for different host layer systems to reduce relaxation risk;

[0024] When the host layer is any one of germanium-silicon, boron-doped germanium-silicon, or germanium-tin and the doping element content is 15%-40%, a silicon marker layer is used. Since the doping element content in the host layer is high, lattice distortion and relaxation are prone to occur during the growth process. Therefore, the process temperature for epitaxial growth of the silicon marker layer should not exceed 10% of the process temperature for epitaxial growth of the host layer, thereby reducing the risk of lattice mismatch, dislocations and defects in the host layer and helping to reduce relaxation.

[0025] When the host layer is any one of tin-silicon, phosphorus-silicon, phosphorus-doped silicon carbide, silicon carbide, silicon arsenide, or phosphorus-doped silicon arsenide and the doping element content is 5%-20%, a germanium-silicon labeling layer is used. Since the doping element content in the host layer is low, lattice distortion and relaxation are less likely to occur during the growth process. Therefore, the process temperature for epitaxial growth of the germanium-silicon labeling layer can be similar to that for epitaxial growth of the host layer. At the same time, the content of the labeling element (germanium) in the germanium-silicon labeling layer is controlled at 5%-20% to avoid lattice mismatch and relaxation problems caused by excessive germanium content.

[0026] 3) This invention distinguishes the thickness of each epitaxial layer by epitaxially growing a marker layer between multiple epitaxial layers, which enables the process conditions for developing multiple epitaxial layers to be verified simultaneously on a single planarized / patterned wafer, thereby reducing wafer consumption, shortening process development time, and significantly reducing costs. Attached Figure Description

[0027] Figure 1 This is a flowchart of the method for reducing relaxation and differentiating epitaxial layer thickness according to the present invention.

[0028] Figure 2 This is a schematic diagram of the structure of the present invention, which involves epitaxially growing a three-layer phosphosilicate epitaxial layer on a planarized wafer.

[0029] Figure 3 This is a schematic diagram of the structure of the present invention, in which a germanium-silicon marker layer is epitaxially grown between three phosphorus-silicon epitaxial layers.

[0030] Figure 4 This is a schematic diagram of the structure of the present invention, which involves epitaxially growing a germanium-silicon seed layer, a germanium-silicon host layer, and a silicon capping layer on a planarized wafer.

[0031] Figure 5 This is a schematic diagram of the structure of the present invention, which involves epitaxially growing a germanium-silicon seed layer, a silicon marker layer, a germanium-silicon host layer, and a silicon capping layer on a planarized wafer.

[0032] Figure 6 This is a graph showing the relationship between the haze value of the wafer surface and the process temperature of the silicon marking layer in this invention.

[0033] Figure 7 This is a schematic diagram of the structure of the present invention, which involves epitaxially growing a multilayer germanium-silicon host layer and a silicon marker layer on a planarized wafer.

[0034] Figure 8 This is a schematic diagram of the structure of the present invention, which involves epitaxially growing a germanium-silicon seed layer, a silicon marker layer, a germanium-silicon body layer, and a silicon capping layer on a patterned wafer.

[0035] Attached image labels:

[0036] Silicon substrate 10, first phosphosilicate epitaxial layer 20, second phosphosilicate epitaxial layer 21, third phosphosilicate epitaxial layer 22, first germanium-silicon marker layer 30, second germanium-silicon marker layer 31, germanium-silicon seed layer 40, germanium-silicon host layer 50, first germanium-silicon host layer 51, second germanium-silicon host layer 52, third germanium-silicon host layer 53, silicon cap layer 60, silicon marker layer 70, first silicon marker layer 71, and second silicon marker layer 72. Detailed Implementation

[0037] The method for reducing relaxation and differentiating epitaxial layer thickness proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0038] This invention grows a marker layer epitaxially between the seed layer and the main layer, and between adjacent main layers in a multilayer main layer. When the difference between the atomic number of the marker element in the marker layer and the atomic number of the dopant element in the main layer is ≥5, there is a significant difference in the brightness of the Z-contrast image between the marker layer and the main layer, making the interface between adjacent film layers very clear, which is beneficial for accurately distinguishing the thickness of each epitaxial layer.

[0039] The labeling layer includes at least one labeling element with an atomic number difference of ≥5 from the doping element in the host layer, ensuring that the Z-contrast difference between the two elements can be clearly distinguished, thus forming a clear contrast in the image. For example, the labeling layer can be a single-element material layer consisting only of the labeling element; or, the labeling layer can be a multi-element material layer containing both the labeling element and non-labeling elements. When the host layer is any one of germanium-silicon, boron-doped germanium-silicon, or germanium-tin and the doping element content is 15%-40%, a silicon labeling layer (single-element material layer) is used, and the process temperature for epitaxial growth of the silicon labeling layer is controlled to not exceed 10% of the process temperature for epitaxial growth of the host layer, which helps to reduce relaxation. When the host layer is any one of tin-silicon, phosphorus-silicon, phosphorus-doped silicon carbide, silicon carbide, silicon arsenide, or phosphorus-doped silicon arsenide and the doping element content is 5%-20%, a germanium-silicon labeling layer (multi-element material layer) is used, and the content of the labeling element (germanium) in the germanium-silicon labeling layer is controlled to be 5%-20%, which helps to reduce relaxation.

[0040] Specifically, such as Figure 1 As shown, the present invention provides a method for reducing relaxation in distinguishing epitaxial layer thicknesses, comprising at least the following steps:

[0041] Step S1: Provide a wafer and epitaxially grow a seed layer on the surface of the wafer;

[0042] Step S2: An epitaxial marker layer is grown on the surface of the seed layer;

[0043] Step S3: Epitaxially grow the main body layer on the surface of the marking layer;

[0044] Wherein, the difference between the atomic number of the marker element in the marker layer and the atomic number of the dopant element in the main layer is ≥5.

[0045] After step S3, a capping layer is also epitaxially grown on the surface of the main layer.

[0046] In epitaxial process development, when the dopant content in the seed layer is close to that in the host layer (e.g., the difference in dopant content does not exceed 5%), the brightness of their Z-contrast images is similar, making it impossible to accurately distinguish the thicknesses of the seed layer and the host layer. To accurately distinguish their thicknesses, a marker layer is epitaxially grown between the seed layer and the host layer. In some embodiments, the host layer is any one of tin-silicon, phosphosilicon, phosphorus-doped silicon carbide, silicon carbide, silicon arsenide, and phosphorus-doped silicon arsenide, and the dopant content in the host layer is 5%-20%; the marker layer is germanium-silicon, and the marker element content in the marker layer is 5%-20%.

[0047] As an example, such as Figure 2As shown, in the development of source-drain region epitaxial processes for N-type metal-oxide-semiconductor (NMOS) devices, the wafer includes a silicon substrate 10. Three silicon phosphide epitaxial layers are grown on the surface of the silicon substrate 10. The process temperature is 450℃-800℃, and the process pressure is 100Torr-700Torr, resulting in a first silicon phosphide epitaxial layer 20 (equivalent to a seed layer), a second silicon phosphide epitaxial layer 21 (equivalent to a first host layer), and a third silicon phosphide epitaxial layer 22 (equivalent to a second host layer). The doping element (phosphorus) content in the three silicon phosphide epitaxial layers is different and less than 10%. Their Z-contrast image (darker) is similar to that of the silicon substrate 10, and the interfaces between the different film layers are very difficult to distinguish, making it impossible to obtain accurate film thickness and causing difficulties in process development. Therefore, a germanium-silicon marker layer is epitaxially grown between the three phosphorus-silicon epitaxial layers. Specifically, a first germanium-silicon marker layer 30 is epitaxially grown between the first phosphorus-silicon epitaxial layer 20 and the second phosphorus-silicon epitaxial layer 21, and a second germanium-silicon marker layer 31 is epitaxially grown between the second phosphorus-silicon epitaxial layer 21 and the third phosphorus-silicon epitaxial layer 22 (see [reference]). Figure 3 The germanium-silicon labeled layer is grown instead of a germanium labeled layer directly because silicon and germanium have significantly different lattice constants, making them prone to dislocations and defects. The thickness of both the first germanium-silicon labeled layer 30 and the second germanium-silicon labeled layer 31 is 1 nm-20 nm, and their combined thickness is 2%-10% of the overall film thickness. Since the dopant element (phosphorus) content in the three-layer phosphorus-silicon epitaxial layer is relatively low, it is less prone to lattice distortion and relaxation. Therefore, the process temperature and pressure for epitaxially growing the first germanium-silicon labeled layer 30 and the second germanium-silicon labeled layer 31 can be similar to those for epitaxially growing the three-layer phosphorus-silicon epitaxial layer, thus avoiding thermal mismatch. Simultaneously, the content of the labeled element (germanium) in the first germanium-silicon labeled layer 30 and the second germanium-silicon labeled layer 31 should be controlled between 5%-20%, preferably 10%. Too low a content makes it difficult to detect, while too high a content affects the film structure and can induce relaxation.

[0048] In addition, the atomic number of the marker element (germanium) in the first germanium-silicon marker layer 30 and the second germanium-silicon marker layer 31 is relatively large, and the difference between the atomic number of the marker element (phosphorus) and the atomic number of the dopant element (phosphorus) in the three-layer phosphorus-silicon epitaxial layer is 17 (greater than 5). The Z-contrast image of the first germanium-silicon marker layer 30 and the second germanium-silicon marker layer 31 is brighter (the larger the atomic number, the brighter the image), which can accurately distinguish the interface of the darker three-layer phosphorus-silicon epitaxial layer, thereby obtaining a precise film thickness.

[0049] In the development of epitaxial processes for the source and drain regions of P-type metal-oxide-semiconductor (PMOS) devices, such as Figure 4As shown, a germanium-silicon seed layer 40, a germanium-silicon host layer 50, and a silicon capping layer 60 are sequentially epitaxially grown on the surface of a silicon substrate 10. To reduce relaxation and defects between the germanium-silicon seed layer 40 and the germanium-silicon host layer 50, a gradual increase in germanium concentration is used, such as gradually increasing the germanium concentration of the germanium-silicon seed layer 40 to reach the germanium concentration of the germanium-silicon host layer 50. This reduces the difference in lattice constant between the two thin films, thereby reducing relaxation and defects. Simultaneously, because the germanium concentration of the germanium-silicon host layer 50 is high, directly epitaxially growing the silicon capping layer 60 on it would induce relaxation, causing dislocations and defects. Therefore, the concentration of the germanium-silicon host layer 50 is gradually decreased. However, this gradual change in germanium concentration results in similar brightness levels in the Z-contrast images of the germanium-silicon seed layer 40 and the germanium-silicon host layer 50, making it difficult to distinguish the interface and thus determine the thickness.

[0050] To accurately distinguish the thicknesses of the seed layer and the main layer, this invention epitaxially grows a marker layer between the seed layer and the main layer. In some embodiments, the main layer is any one of germanium-silicon, boron-doped germanium-silicon, germanium-tin, or pure germanium, and the marker layer is silicon; when the main layer is any one of germanium-silicon, boron-doped germanium-silicon, or germanium-tin, the doping element content in the main layer is 15%-40%.

[0051] As an example, such as Figure 5 As shown, in the development of epitaxial growth technology for the source and drain regions of a P-type metal-oxide-semiconductor (PMOS) device, a germanium-silicon seed layer 40, a silicon marker layer 70, a germanium-silicon host layer 50, and a silicon cap layer 60 are sequentially epitaxially grown on the surface of a silicon substrate 10. The epitaxial growth temperature of the germanium-silicon host layer 50 is 300℃-800℃, and the process pressure is 5 Torr-300 Torr; the thickness of the silicon marker layer 70 is 1nm-20nm.

[0052] On the one hand, the atomic number of the dopant element (germanium) in the germanium-silicon host layer 50 is relatively large, and the difference between the atomic number of the dopant element (silicon) in the silicon labeling layer 70 and the atomic number of the dopant element (silicon) is 18 (greater than 5). The Z-contrast image of the silicon labeling layer 70 is relatively dark, which can accurately distinguish the interface between the germanium-silicon seed layer 40 and the germanium-silicon host layer 50, which has a brighter Z-contrast image, thereby obtaining a precise film thickness.

[0053] On the other hand, because the germanium content of the dopant element 50 in the germanium-silicon host layer is relatively high, generally controlled between 15% and 40%, and even higher at more advanced process nodes, it can easily cause lattice distortion and relaxation during growth. Therefore, it is necessary to control the process temperature of the epitaxial growth of the silicon marker layer 70, ensuring it does not exceed 10% of the process temperature of the epitaxial growth of the germanium-silicon host layer 50. If the process temperature is too high (>15%), it will cause lattice mismatch in the germanium-silicon host layer 50 itself, increasing dislocations and defects. For example, Figure 6 This represents the relationship between the haze value of the wafer surface and the processing temperature of the silicon marking layer, with the horizontal axis representing (T)标记层 -T 主体层 ) / T 主体层 The vertical axis represents the haze value of the wafer surface after the process is completed. When the process temperature for epitaxially growing the silicon marker layer does not exceed 10% of the process temperature for epitaxially growing the germanium-silicon substrate layer, the haze value is less than 5 ppm; when the process temperature for epitaxially growing the silicon marker layer exceeds 20% of the process temperature for epitaxially growing the germanium-silicon substrate layer, the haze value is greater than 15 ppm. This is because the relaxation degree of the germanium-silicon substrate layer increases, the surface atomic arrangement deviates from the ideal crystal structure, and more defects, lattice distortions, or irregularities appear on the surface. These surface defects and undulations enhance the light scattering effect, resulting in more diffuse reflection light, thus increasing the haze value.

[0054] In other embodiments, the germanium-silicon host layer 50 is at least one layer; for example, it can be three layers: a first germanium-silicon host layer 51, a second germanium-silicon host layer 52, and a third germanium-silicon host layer 53 (see [link to documentation]). Figure 7 The difference in dopant content among the main layers does not exceed 5%, resulting in similar brightness in the Z-contrast images of each main layer, making it difficult to distinguish the film interfaces between the main layers. Therefore, marker layers are epitaxially grown between adjacent main layers. Specifically, a first silicon marker layer 71 is epitaxially grown between the first germanium-silicon main layer 51 and the second germanium-silicon main layer 52, and a second silicon marker layer 72 is epitaxially grown between the second germanium-silicon main layer 52 and the third germanium-silicon main layer 53. The thickness of both the first silicon marker layer 71 and the second silicon marker layer 72 is 1 nm-20 nm, and their combined thickness is 2%-10% of the total film thickness. Compared to the brighter Z-contrast images of the main layers, the Z-contrast images of the first silicon marker layer 71 and the second silicon marker layer 72 are relatively dark, allowing for accurate distinction of the interfaces between the first germanium-silicon main layer 51 and the second germanium-silicon main layer 52, and between the second germanium-silicon main layer 52 and the third germanium-silicon main layer 53, thus obtaining a precise film thickness. Traditional methods typically involve epitaxially growing one or at most two host layers on a single wafer. However, this invention distinguishes the thickness of multiple host layers by epitaxially growing a marker layer between them. This allows for simultaneous verification of the process conditions (including growth rate, concentration, etc.) for developing multiple host layers on a single planarized wafer, thereby shortening process development time and significantly reducing costs.

[0055] In practical epitaxial process development, either planarized wafers or patterned wafers can be used. In advanced processes, patterned wafers require multiple processing steps to form complex trench structures on their surface, resulting in higher costs. To minimize the use of patterned wafers, such as... Figure 8As shown, a germanium-silicon seed layer 40, a germanium-silicon host layer 50, and a silicon cap layer 60 can be epitaxially grown on the surface of the silicon substrate 10. By epitaxially growing a silicon marker layer 70 between the germanium-silicon seed layer 40 and the germanium-silicon host layer 50, the process conditions for developing multi-layer epitaxial layers can be verified on a single-layer patterned wafer, rather than on a single-layer patterned wafer. This achieves the goal of saving wafers and reducing costs. Furthermore, due to the loading effect in the patterned wafer, the thickness of the silicon marker layer 70 is thinner, typically between 1 nm and 10 nm.

[0056] In summary, this invention epitaxially grows marker layers between the seed layer and the main layer, and between adjacent main layers in multiple main layers. When the difference between the atomic number of the marker element in the marker layer and the atomic number of the dopant element in the main layer is ≥5, there is a significant difference in brightness between the Z-contrast images of the marker layer and the main layer, making the interface between adjacent layers very clear and facilitating accurate differentiation of the thickness of each epitaxial layer. Furthermore, by epitaxially growing marker layers between multiple epitaxial layers to differentiate their thicknesses, the process conditions for developing multiple epitaxial layers can be simultaneously verified on a single planarized / patterned wafer, reducing wafer consumption, shortening process development time, and significantly lowering costs.

[0057] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0059] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for reducing relaxation in distinguishing epitaxial layer thickness, characterized in that, Include at least the following steps: Step S1: Provide a wafer and epitaxially grow a seed layer on the surface of the wafer; Step S2: An epitaxial marker layer is grown on the surface of the seed layer; Step S3: Epitaxially grow the main body layer on the surface of the marking layer; Wherein, the difference between the atomic number of the marker element in the marker layer and the atomic number of the dopant element in the main layer is ≥5.

2. The method as described in claim 1, characterized in that, The main layer is any one of germanium-silicon, boron-doped germanium-silicon, germanium-tin, or pure germanium, and the marking layer is silicon.

3. The method as described in claim 2, characterized in that, The main body layer is any one of germanium-silicon, boron-doped germanium-silicon, and germanium-tin, and the content of doped elements in the main body layer is 15%-40%.

4. The method as described in claim 2, characterized in that, The epitaxial growth temperature of the host layer is 300℃-800℃, and the epitaxial growth pressure of the host layer is 5 Torr-300 Torr.

5. The method as described in claim 4, characterized in that, The process temperature for epitaxially growing the marker layer does not exceed 10% of the process temperature for epitaxially growing the main layer.

6. The method as described in claim 1, characterized in that, The main body layer is any one of tin silicon, phosphorus silicon, phosphorus-doped silicon carbide, silicon carbide, silicon arsenide, and phosphorus-doped silicon arsenide, and the doping element content in the main body layer is 5%-20%; the marking layer is germanium silicon, and the marking element content in the marking layer is 5%-20%.

7. The method as described in claim 6, characterized in that, The epitaxial growth temperature of the host layer is 450℃-800℃, and the epitaxial growth pressure of the host layer is 100Torr-700Torr.

8. The method as described in claim 1, characterized in that, The main body layer is at least one layer, and the difference in the content of doped elements in each main body layer does not exceed 5%.

9. The method as described in claim 8, characterized in that, The marker layer is epitaxially grown between adjacent main layers.

10. The method as described in claim 1, characterized in that, The thickness of the marking layer is 1nm-20nm.

11. The method as described in claim 1, characterized in that, The wafer is a planarized wafer or a patterned wafer.

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