A method of manufacturing a semiconductor structure and a semiconductor structure

Abstract

The application provides a semiconductor structure manufacturing method and a semiconductor structure. The method comprises the following steps: providing a substrate; forming a substrate oxide layer on the substrate, and forming a first nitride layer on the substrate oxide layer; etching part of the first nitride layer and the substrate oxide layer to expose the surface of the substrate and form a first groove; forming a second nitride layer on the groove wall of the first groove and on the first nitride layer; etching the second nitride layer on the surface of the substrate and the second nitride layer on the first nitride layer to expose the surface of the substrate and the surface of the first nitride layer, and etching the substrate to form a shallow trench; filling the shallow trench and the first groove to form a shallow trench isolation structure; sequentially removing part of the first nitride layer, removing the second nitride layer, and exposing the surface of the shallow trench isolation structure; forming a protective layer on the exposed surface of the shallow trench isolation structure; and sequentially removing the first nitride layer, the substrate oxide layer and the protective layer. The application can reduce the probability of leakage current of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] Shallow trench isolation (STI) is widely used in submicron-level semiconductor processes. STI reduces the area of ​​the isolation region, providing minimal active area intrusion and a flatter surface. However, due to localized stress concentration, the oxide layer in the STI corner region is over-etched during substrate oxide etching, resulting in lateral erosion. Consequently, when the substrate oxide is stripped, the oxide layer in the STI corner region is inadvertently removed preferentially from the trench corner, forming a recessed structure (as shown in the attached figure). Figure 11 (As shown). During the formation of the gate structure, the presence of the recessed structure can lead to overfilling of the polysilicon, resulting in parasitic transistors. The presence of parasitic transistors increases the probability of leakage current in the device. Summary of the Invention

[0003] The purpose of this invention is to provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to improve the manufacturing yield of shallow trench isolation structures and thereby reduce the probability of leakage current in the device.

[0004] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0005] This invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0006] Provide a substrate;

[0007] A substrate oxide layer is formed on the substrate, and a first nitride layer is formed on the substrate oxide layer;

[0008] The first nitride layer and the substrate oxide layer are etched to expose the substrate surface and form a first trench;

[0009] A second nitriding layer is formed on the trench wall of the first trench and on the first nitriding layer;

[0010] The second nitride layer located on the substrate surface and the second nitride layer located on the first nitride layer are etched to expose the surface of the substrate and the surface of the first nitride layer, and the substrate is etched to form a shallow trench;

[0011] Fill the shallow trench and the first trench to form a shallow trench isolation structure;

[0012] Sequentially remove a portion of the first nitrided layer, then remove the second nitrided layer to expose the surface of the shallow trench isolation structure;

[0013] forming a protective layer on the exposed surface of the shallow trench isolation structure, wherein the protective layer has amine groups therein; and

[0014] sequentially removing the first nitride layer, the substrate oxide layer, and the protective layer.

[0015] In one embodiment of the present application, in the step of forming the shallow trench isolation structure, the first trench is filled, the step portion of the shallow trench isolation structure is formed, and the material of the shallow trench isolation structure is continuously deposited to form a filling layer on the first nitride layer and on the second nitride layer.

[0016] In one embodiment of the present application, before the first nitride layer is removed, the filling layer is polished until the step portion reaches a preset height.

[0017] In one embodiment of the present application, in the step of removing the second nitride layer, the second nitride layer is wet-etched to form a second trench between the step portion and the substrate oxide layer, exposing the surface of the step portion and the surface of the substrate.

[0018] In one embodiment of the present application, in the step of forming the protective layer, a reaction layer is formed on the surface of the step portion, and the reaction layer is treated with an organic solvent in a heated environment to form the protective layer.

[0019] In one embodiment of the present application, the etching solution for removing the first nitride layer is a phosphoric acid solution, the etching solution for removing the substrate oxide layer is a hydrofluoric acid solution, and the etching solution for removing the protective layer is a mixed solution of sulfuric acid and hydrogen peroxide.

[0020] In one embodiment of the present application, before the second nitride layer is removed, part of the first nitride layer is removed by wet etching, wherein the etching ratio of the first nitride layer is 50% to 99%.

[0021] In one embodiment of the present application, the second nitride layer is titanium nitride, and the thickness of the second nitride layer is 5 angstroms to 200 angstroms.

[0022] The present application provides a semiconductor structure, comprising:

[0023] a substrate;

[0024] a substrate oxide layer disposed on the substrate;

[0025] a first nitride layer disposed on the substrate oxide layer;

[0026] a shallow trench isolation structure, part of the shallow trench isolation structure being disposed in the substrate and part of the shallow trench isolation structure being disposed on the substrate.

[0027] a protective layer covering exposed surfaces of the shallow trench isolation structure, wherein the protective layer has amine groups therein; and

[0028] a second trench connecting a surface of the substrate through the substrate oxide layer and the first nitride layer, wherein the second trench is adjacent to the shallow trench isolation structure.

[0029] In one embodiment of the present application, the shallow trench isolation structure includes a step portion on the substrate, wherein the protective layer covers a surface of the step portion.

[0030] As described above, the present application provides a method for manufacturing a semiconductor structure and a semiconductor structure, which have unexpected technical effects in that: a shallow trench isolation structure with complete surface can be formed, any recessed structure on the shallow trench isolation structure or the substrate surface during the process of forming the shallow trench isolation structure is avoided, the forming yield of semiconductor devices in subsequent semiconductor processes is improved, and the probability of leakage current in semiconductor devices is reduced. The method for manufacturing a semiconductor structure and the semiconductor structure provided by the present application are especially suitable for semiconductor processes below sub-micron technology, and can significantly improve the yield of semiconductor processes.

[0031] Of course, implementing any product of the present application does not necessarily need to achieve all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed for the description of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 Structure schematic diagram for forming a substrate oxide layer, a first nitride layer and a photoresist pattern in one embodiment of the present application.

[0034] Figure 2 Structure schematic diagram for forming a first trench in one embodiment of the present application.

[0035] Figure 3 Structure schematic diagram for forming a second nitride layer in one embodiment of the present application.

[0036] Figure 4 Structure schematic diagram for forming a shallow trench in one embodiment of the present application.

[0037] Figure 5 Structure schematic diagram for forming a filling layer in one embodiment of the present application.

[0038] Figure 6 Structure diagram of removing part of the filling layer and part of the first nitride layer in an embodiment of the present application.

[0039] Figure 7 Structure diagram of forming the second trench in an embodiment of the present application.

[0040] Figure 8 Structure diagram of forming the protection layer in an embodiment of the present application.

[0041] Figure 9 Structure diagram of removing the first nitride layer, the substrate oxide layer and the protection layer in an embodiment of the present application.

[0042] Figure 10 Structure diagram of the shallow trench isolation structure in an embodiment of the present application.

[0043] Figure 11 Electron microscope diagram of the shallow trench isolation structure appearing the recess structure due to over-etching in an embodiment of the present application.

[0044] Figure 12 Planar structure diagram of forming the protection layer in an embodiment of the present application.

[0045] Figure 13 Principle diagram of the protection layer adsorbing fluorine ions in an embodiment of the present application.

[0046] In the figure: 100, substrate; 101, first trench; 102, second nitride layer; 103, shallow trench; 104, filling layer; 105, shallow trench isolation structure; 1051, step part; 106, second trench; 200, substrate oxide layer; 300, first nitride layer; 400, photoresist pattern; 500, protection layer; 600, recess structure. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0048] The present application provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure is a structure for forming a semiconductor device. The semiconductor device can be one or more of a Field Effect Transistor (FET), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Complementary Metal Oxide Semiconductor (CMOS), an Insulated Gate Bipolar Transistor (IGBT), a Fast Recovery Diode (FRD), a Figh Efficiency Diode (HED), a Zener diode, a high frequency diode, a Light-Emitting Diode (LED), a Gate Turn off Thyristor (GTO), a Light Triggered Thyristor (LTT), a Thyristor, a Charge Coupled Device (CCD image sensor), a Digital Signal processor (DSP), a Photo Relay, or a Micro Processor.

[0049] Referring to Figure 1 As shown in the drawings, in the manufacturing method of the semiconductor structure provided by the present application, a substrate 100 is provided. In the present embodiment, the substrate 100 can also be referred to as a wafer used in semiconductor processing. Furthermore, the substrate 100 can include doped and undoped semiconductor or epitaxial semiconductor layers, which can be supported by a base of semiconductor or insulator material and other semiconductor structures known to those skilled in the art. In addition, the term conductor can include a semiconductor. Specifically, the substrate 100 is, for example, a silicon base material for forming a semiconductor structure. The substrate 100 can include a base material, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), and a silicon layer formed above the base material.

[0050] Referring to Figure 1As shown in the embodiment of the present application, a substrate oxide layer 200 is formed on the substrate 100, and a first nitride layer 300 is formed on the substrate oxide layer 200. In this embodiment, the substrate oxide layer 200 is formed by depositing silicon oxide on the substrate 100 by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD), etc. The present application does not limit the thickness of the substrate oxide layer 200. Then, the first nitride layer 300 is formed by depositing silicon nitride on the substrate oxide layer 200 by chemical vapor deposition or plasma enhanced chemical vapor deposition, etc. The present application does not limit the thickness of the first nitride layer 300. In this embodiment, the thickness of the first nitride layer 300 is greater than the thickness of the substrate oxide layer 200. In this embodiment, after the first nitride layer 300 is formed, a photoresist pattern 400 is formed on the first nitride layer 300. Specifically, a photoresist layer is formed on the first nitride layer 300 by spin coating, and the photoresist layer is patterned by exposure and etching, etc. to form the photoresist pattern 400. The photoresist pattern 400 is used to help define the maximum width of the shallow trench.

[0051] Referring to Figures 1 to 3 As shown in the embodiment of the present application, after the first nitride layer 300 is formed, the first nitride layer 300 and the substrate oxide layer 200 are etched using the photoresist pattern 400 as a mask to expose the surface of the substrate 100 and form a first trench 101. Then, a second nitride layer 102 is formed on the sidewall and bottom wall of the first trench 101 and on the first nitride layer 300. In this embodiment, the first nitride layer 300 and the substrate oxide layer 200 are removed in sequence by dry etching until the surface of the substrate 100 is exposed. The first trench 101 penetrates the first nitride layer 300 and the substrate oxide layer 200 and connects the surface of the substrate 100. Then, the second nitride layer 102 is formed by depositing titanium nitride on the first trench 101 and the first nitride layer 300 by chemical vapor deposition or plasma enhanced chemical vapor deposition, etc. At this time, the second nitride layer 102 covers the sidewall and bottom wall of the first trench 101 and the top surface of the first nitride layer 300. In this embodiment, the thickness of the second nitride layer 102 is 5-200 angstroms. After the first trench 101 is formed, the photoresist pattern 400 is removed by ashing before the second nitride layer 102 is formed.

[0052] Referring to Figure 3 and Figure 4As shown, in one embodiment of the present application, after the first trench 101 is formed, the second nitride layer 102 on the first nitride layer 300 and the second nitride layer 102 covering the surface of the substrate 100 are etched away, and part of the substrate 100 is etched away to form a shallow trench 103. In this etching step, the bottom of the first trench 101 is deepened, and the original first trench 101 is converted into a via structure. In this embodiment, the second nitride layer 102 and part of the substrate 100 are removed by dry etching to form a shallow trench 103 which is in communication with the first trench 101, and the shallow trench 103 is located at the bottom of the first trench 101. In this embodiment, the second nitride layer 102 on the hole wall of the first trench 101 is retained. As shown in Figure 3 and Figure 4 As shown, the cross section of the first trench 101 in the present application is rectangular, and the surface flatness of the first nitride layer 300 can be maintained under the action of the second nitride layer 102.

[0053] Please refer to Figure 4 and Figure 5As shown, in one embodiment of the present application, after the formation of the shallow trench 103, a shallow trench isolation structure 105 is formed in the first trench 101 and the shallow trench 103, and a fill layer 104 is formed on the second nitride layer 102 and the first nitride layer 300. In this embodiment, the shallow trench 103 and the first trench 101 are sequentially filled by chemical vapor deposition or plasma enhanced chemical vapor deposition until the shallow trench 103 and the first trench 101 are filled, thereby forming the shallow trench isolation structure 105. After the shallow trench 103 is filled, the first trench 101 is continuously filled, thereby forming a step portion 1051 of the shallow trench isolation structure 105. The step portion 1051 is the portion of the shallow trench isolation structure 105 that is higher than the substrate 100. The portion of the shallow trench isolation structure 105 filled in the shallow trench 103 can be used to isolate active regions in the substrate 100, thereby forming a plurality of well structures in the substrate 100. After the first trench 101 is filled, a thin film structure is continuously deposited on the second nitride layer 102 and the first nitride layer 300, thereby forming the fill layer 104. The material of the shallow trench isolation structure 105 and the fill layer 104 is, for example, tetraethyl orthosilicate (TEOS). It is to be noted that the shallow trench isolation structure 105 and the fill layer 104 can also be formed of a material containing silicon oxide, silicon dioxide, carbon-doped silicon dioxide, nitrogen-doped silicon dioxide, germanium-doped silicon dioxide, or phosphorus-doped silicon dioxide, and the shallow trench isolation structure 105 and the fill layer 104 can be deposited by conformal deposition through atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, sub atmospheric chemical vapor deposition (SACVD), high density plasma chemical vapor deposition (HDPCVD), and photo induced chemical vapor deposition. Those skilled in the art can understand that other insulating materials can be used to deposit in the shallow trench 103 and the first trench 101 as long as the purpose of electrically isolating the respective component regions is achieved. Furthermore, other known methods can be used to deposit the shallow trench isolation structure 105 and the fill layer 104 in the art as understood by those skilled in the art.

[0054] Please refer to Figure 5 and Figure 6As shown in FIG. 1, in one embodiment of the present application, after the shallow trench isolation structure 105 and the filling layer 104 are formed, the filling layer 104 and part of the first nitride layer 300 are removed. In this embodiment, after the filling layer 104 is formed, the filling layer 104 on the second nitride layer 102 and the first nitride layer 300 is polished by chemical mechanical polishing (CMP) with the second nitride layer 102 and the first nitride layer 300 as the etching stop layer, so as to expose the surface of the second nitride layer 102 and the first nitride layer 300. Then part of the first nitride layer 300 is removed by wet etching. In this embodiment, for example, 50% to 99% of the first nitride layer 300 is removed. Specifically, the etching solution used in the wet etching can be phosphoric acid solution. In this embodiment, in the process of chemical mechanical polishing, the etching can be stopped when the height of the step portion 1051 reaches the preset height H, wherein the preset height H is set by the designer. During the process of chemical mechanical polishing, the height of the step portion 1051 can be observed to ensure that the step portion 1051 of the shallow trench isolation structure 105 reaches the process requirement at the end of the step of chemical mechanical polishing, so as to avoid defects. In other embodiments of the present application, when the first nitride layer 300 is deposited, the total thickness of the first nitride layer 300 and the substrate oxide layer 200 is greater than the preset height H, so as to leave an adjustment allowance for the shallow trench isolation structure 105 in the subsequent process. In this etching step, most of the first nitride layer 300 is removed, which protects the surface flatness of the substrate oxide layer 200 and facilitates the removal of the substrate oxide layer 200 in the subsequent process, so as to complete the removal of the substrate oxide layer 200 as quickly as possible without damaging the shallow trench isolation structure 105.

[0055] Referring to FIG. 1, Figure 6 and Figure 7 As shown in FIG. 1, in one embodiment of the present application, after part of the first nitride layer 300 is removed, the second nitride layer 102 is removed, part of the surface of the substrate 100 is exposed, and the second trench 106 is formed. In this embodiment, the second nitride layer 102 is removed by wet etching, wherein the etching solution is a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). The substrate oxide layer 200 and the first nitride layer 300 form a stacked structure. The second trench 106 is located between the step portion 1051 and the stacked structure, and the surface of the substrate 100 is the bottom of the second trench 106. The width of the second trench 106 is greater than the critical dimension of the semiconductor structure. The present application does not limit the specific width of the second trench 106. After the second nitride layer 102 is removed, space is left for the formation of the protection layer 500 in the subsequent process, so as to facilitate the complete adhesion of the protection layer 500 to the surface of the step portion 1051.

[0056] Referring to FIG. 1, Figure 7 and Figure 8, Figure 12 and Figure 13 As shown, in one embodiment of the present invention, after forming the second trench 106, the surface of the step portion 1051 is treated to form a protective layer 500 on the surface of the step portion 1051. In this embodiment, a reactive layer, such as a chitosan layer, is attached to the surface of the step portion 1051. The chitosan layer is heated and treated in an organic solvent environment at a temperature of, for example, 50°C to 200°C, thereby modifying the chitosan layer and forming the protective layer 500 on the surface of the step portion 1051. The protective layer 500 is a nanocomposite material. Figure 12 As shown, silicon dioxide is linked to the amino groups of chitosan, thereby forming a protective layer 500 on the exposed surface of the step portion 1051. In this embodiment, the organic solvent can be any one of toluene, acetone, and N-methylpyrrolidone, or any mixture of multiple solvents. Since the surface of the step portion 1051 has more -OH groups than the surface of the substrate oxide layer 200, the protective layer 500 is preferentially formed on the surface of the step portion 1051. It should be noted that due to the etching solutions such as phosphoric acid and hydrofluoric acid, the step portion 1051 is under acidic conditions, causing the free amino groups in the chitosan structure to protonate, resulting in a positively charged substance, namely -NH3, appearing on the surface of the nanocomposite material. + .like Figure 13 As shown, under the action of electrostatic adsorption, -NH3 + It can attract F- ions and reduce the etching effect of F- ions on the connection between the step portion 1051 and the substrate 100, thereby protecting the shallow trench isolation structure 105 from excessive etching.

[0057] Please see Figures 8 to 10 As shown, in one embodiment of the present invention, the first nitride layer 300, the substrate oxide layer 200, and the protective layer 500 are removed sequentially. In this embodiment, phosphoric acid is used to remove the residual first nitride layer 300 on the surface of the substrate oxide layer 200. Then, hydrofluoric acid is used to remove the substrate oxide layer 200. Under the protection of the protective layer 500, the corners of the shallow trench isolation structure 105 connecting to the substrate 100 will not experience over-etching. The corners of the shallow trench isolation structure 105 connecting to the substrate 100 are... Figure 9 and Figure 10 The circled area. Next, the protective layer 500 is removed using sulfuric acid and hydrogen peroxide, exposing the surface of the stepped portion 1051, thus forming a shallow groove isolation structure 105 with a complete surface. In this embodiment, the chitosan-modified layer is removed using sulfuric acid and hydrogen peroxide, thereby removing the protective layer 500.

[0058] Please see Figure 10 and Figure 11 As shown, Figure 11 Electron micrograph of the corner of the shallow trench isolation structure 105 showing excessive etching. Figure 10The corner structure diagram of the shallow trench isolation structure 105 obtained by the control method provided by the present application is shown in the figure. Figure 11 As shown in the figure, when the corner of the shallow trench isolation structure 105 has the over-etching recess structure 600, then in the forming process of the gate structure, or even in the forming process of the metal interconnection structure, the recess structure 600 will continue when depositing the dielectric layer, the polysilicon layer and the metal layer, and in order to fill the recess structure 600, there will be excess polysilicon material filling or metal material filling, which will cause the parasitic device structure in the original device structure. The shallow trench isolation structure 105 provided by the present application not only avoids the formation of the recess structure 600, thereby improving the integrity of the shallow trench isolation structure 105, but also can avoid the appearance of the non-design parasitic device in the semiconductor device, thereby reducing the possibility of the leakage current of the device, thereby improving the manufacturing yield of the chip and improving the yield of the single wafer.

[0059] The present application provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises the following steps: providing a substrate. Forming a substrate oxide layer on the substrate, and forming a first nitride layer on the substrate oxide layer. Etching part of the first nitride layer and the substrate oxide layer to expose the surface of the substrate and form a first trench. Forming a second nitride layer on the trench wall of the first trench and on the first nitride layer. Etching the second nitride layer on the surface of the substrate and the second nitride layer on the first nitride layer to expose the surface of the substrate and the surface of the first nitride layer, and etching the substrate to form a shallow trench. Filling the shallow trench and the first trench to form a shallow trench isolation structure. Removing part of the first nitride layer and the second nitride layer in sequence to expose the surface of the shallow trench isolation structure. Forming a protective layer on the exposed surface of the shallow trench isolation structure. Removing the first nitride layer, the substrate oxide layer and the protective layer in sequence. The semiconductor structure manufacturing method and the semiconductor structure provided by the present application have the unexpected technical effect that the present application can form a shallow trench isolation structure with complete surface, avoid forming any recess structure on the shallow trench isolation structure or the surface of the substrate in the process of forming the shallow trench isolation structure, which is beneficial to improving the forming yield of the semiconductor device in the subsequent semiconductor process and reducing the probability of leakage current in the semiconductor device. The semiconductor structure manufacturing method and the semiconductor structure provided by the present application are especially suitable for semiconductor processes below submicron process and can significantly improve the yield of semiconductor process.

[0060] The above disclosed embodiments of the present application are only used to help explain the present application. The embodiments do not describe all of the details of the present application, and the present application is not limited to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the present specification. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well understand and utilize the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: Provide a substrate; A substrate oxide layer is formed on the substrate, and a first nitride layer is formed on the substrate oxide layer; The first nitride layer and the substrate oxide layer are etched to expose the substrate surface and form a first trench; A second nitriding layer is formed on the trench wall of the first trench and on the first nitriding layer; The second nitride layer located on the substrate surface and the second nitride layer located on the first nitride layer are etched to expose the surface of the substrate and the surface of the first nitride layer, and the substrate is etched to form a shallow trench; Fill the shallow trench and the first trench to form a shallow trench isolation structure; Sequentially remove a portion of the first nitrided layer, then remove the second nitrided layer to expose the surface of the shallow trench isolation structure; A protective layer is formed on the exposed surface of the shallow trench isolation structure, wherein the protective layer has amine groups; as well as The first nitride layer, the substrate oxide layer, and the protective layer are removed sequentially.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, In the step of forming the shallow trench isolation structure, the first trench is filled to form the stepped portion of the shallow trench isolation structure, and the material of the shallow trench isolation structure is deposited to form a filling layer on the first nitrided layer and the second nitrided layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Before removing the first nitrided layer, the filler layer is ground off until the stepped portion reaches a preset height.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, In the step of removing the second nitride layer, the second nitride layer is wet-etched to form a second trench between the step portion and the substrate oxide layer, exposing the surface of the step portion and the surface of the substrate.

5. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, In the step of forming the protective layer, a reaction layer is formed on the surface of the step portion, and the reaction layer is treated with an organic solvent under a heating environment to form the protective layer.

6. A method for manufacturing a semiconductor structure according to claim 1 ， Its features are, The etching solution for removing the first nitride layer is a phosphoric acid solution, the etching solution for removing the substrate oxide layer is a hydrofluoric acid solution, and the etching solution for removing the protective layer is a mixed solution of sulfuric acid and hydrogen peroxide.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before removing the second nitride layer, a portion of the first nitride layer is removed by wet etching, wherein the etching ratio of the first nitride layer is 50% to 99%.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The second nitride layer is titanium nitride, and the thickness of the second nitride layer is 5 angstroms to 200 angstroms.

9. A semiconductor structure, characterized in that, include: Substrate; A substrate oxide layer is disposed on the substrate; A first nitride layer is disposed on the substrate oxide layer, and the substrate oxide layer and the first nitride layer are connected to form a stacked structure; A shallow trench isolation structure, wherein a portion of the shallow trench isolation structure is disposed in the substrate, and a portion of the shallow trench isolation structure is located on the substrate, and the shallow trench isolation structure includes a stepped portion located on the substrate; A protective layer covers the exposed surface of the shallow trench isolation structure, and the protective layer covers the surface of the step portion, wherein the protective layer has amine groups; as well as The second trench passes through the substrate oxide layer and the first nitride layer and connects to the surface of the substrate, wherein the second trench is adjacent to the shallow trench isolation structure and is located between the stepped portion on both sides of the shallow trench isolation structure and the stacked structure.

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