Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, comprising a packaging substrate, a plurality of first copper foil lines are fixed equidistantly on the top of the packaging substrate, the semiconductor device has the beneficial effects that: the semiconductor device is designed with a partition heat conduction plate and a multilayer heat dissipation structure, which significantly improves the heat dissipation performance of the device, not only ensures that the heat generated by each die during work can be effectively dissipated in time, avoids performance degradation or damage caused by excessive temperature, but also enhances the stability and reliability of the entire packaging structure through the reinforcing effect of the supporting partition block and the closed side plate, the improvement of the efficient heat dissipation and the structural stability makes the semiconductor device have a longer service life and higher working performance in high-power and high-density application scenarios.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a semiconductor device and its manufacturing method. Background Technology

[0002] Semiconductor devices are devices that utilize the properties of semiconductors. They typically include semiconductor elements (such as transistors, diodes, and photodiodes) and circuits composed of these elements. Semiconductor devices are electronic devices or systems with specific functions manufactured using specific processes and technologies, taking advantage of the conductivity of semiconductor materials, which lies between that of conductors and insulators. There are many types of semiconductor devices, which can be categorized according to their functions and applications, including integrated circuits, discrete devices, optoelectronic devices, and sensors. Integrated circuits are the core of the semiconductor industry and are widely used in communications, computers, and consumer electronics. The working principle of semiconductor devices is primarily based on the physical and chemical properties of semiconductor materials. By precisely controlling the growth, doping, photolithography, and etching processes of semiconductor materials, semiconductor chips with specific functions can be manufactured. These chips, under the influence of current or voltage, can amplify, transmit, and process signals. The side-by-side arrangement of bare dies not only limits the further improvement of package density but also poses a significant challenge to heat dissipation performance. Traditional heat dissipation devices are often bulky and occupy a large amount of space in the package structure. This not only limits the further reduction of package size but also increases manufacturing costs and complexity. The side-by-side arrangement of bare dies limits the space for increasing package density. Since a certain amount of space needs to be reserved between the dies to avoid mutual interference, and the layout of the interconnects also occupies additional area, this limits the compactness of the entire package structure. The traditional side-by-side arrangement can no longer meet this requirement. Moreover, in high power density applications, if the heat generated by the dies cannot be dissipated in time, it will lead to excessively high temperatures, which in turn will cause performance degradation or even damage. Traditional heat dissipation devices are difficult to work effectively in high-density packages due to their large size and low heat dissipation efficiency. This limits the widespread application of semiconductor devices in high-performance, high-density applications.

[0003] To address the aforementioned issues, this invention proposes an innovative semiconductor device solution. By designing a heat-conducting separator and a multi-layer heat dissipation structure, the heat dissipation performance of the device is significantly improved. The heat-conducting separator not only effectively isolates the heat generated by each die but also rapidly dissipates the heat through the multi-layer heat dissipation structure, preventing performance degradation or damage caused by excessive temperature. Through optimized design, a high degree of integration is achieved. Multiple dies are arranged in a stacked manner on both sides of the heat-conducting separator and interconnected through multi-layer metallized patterns and dielectric layers. This design not only increases packaging density and makes full use of the space on both sides of the heat-conducting separator and dies, increasing heat dissipation, but also reduces connection paths and shrinks the overall size. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method to address the problems mentioned in the background art. Traditional heat dissipation devices are often bulky and occupy a large amount of space in the packaging structure. This not only limits the further reduction of package size but also increases manufacturing costs and complexity. The side-by-side arrangement of bare dies limits the potential for increasing package density. Since a certain space needs to be reserved between the dies to avoid mutual interference, and the layout of the interconnects also occupies additional area, this limits the compactness of the entire package structure. The traditional side-by-side arrangement can no longer meet this requirement. Furthermore, in high power density applications, if the heat generated by the dies cannot be dissipated in time, it will lead to excessively high temperatures, resulting in performance degradation or even damage. Traditional heat dissipation devices are large and have low heat dissipation efficiency, making it difficult for them to work effectively in high-density packages. This limits the widespread application of semiconductor devices in high-performance, high-density applications.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A semiconductor device includes a packaging substrate. A plurality of first-order copper foil lines are equidistantly fixed to the top of the packaging substrate. A plurality of second-order copper foil lines are also equidistantly fixed to the top of the packaging substrate. The second-order copper foil lines are fixedly connected to the first-order copper foil lines. An organic substrate is fixed to the top of the second-order copper foil lines. A plurality of internal connecting slots are equidistantly formed on the top of the organic substrate. A connecting substrate is fixed to the top of the organic substrate. A heat-conducting separator plate is fixed to the top of the connecting substrate. First-order dies are disposed on both sides of the heat-conducting separator plate. Second-order dies are disposed on both sides of the heat-conducting separator plate, with the second-order dies positioned above the first-order dies. Third-order dies are disposed on both sides of the heat-conducting separator plate, with the third-order dies positioned above the second-order dies. Above the first bare die, a fourth bare die is disposed on both sides of the separating heat-conducting plate, and the fourth bare die is located above the third bare die. A sixth bare die is disposed on both sides of the separating heat-conducting plate, and the sixth bare die is located above the fourth bare die. A fifth bare die is disposed on both sides of the separating heat-conducting plate, and the fifth bare die is located above the sixth bare die. A connecting substrate is disposed on the top of the fifth bare die. The bottom of the connecting substrate is fixed to the separating heat-conducting plate. A second gate insulating film is fixed to the top of the connecting substrate. Multiple gate electrodes are fixed to the top of the second gate insulating film at equal intervals. A first gate insulating film is disposed on the top of the second gate insulating film and the gate electrodes. A sealing element is disposed on the top of the first gate insulating film. An interconnect metal circuit is disposed on the top of the sealing element.

[0006] Each of the No. 1, No. 2, No. 3, No. 4, No. 6 and No. 5 bare wafers is fixedly connected to a heat dissipation and heat conduction plate between itself and the heat-conducting plate.

[0007] The outer side of the No. 1 bare die is fixed with the No. 5 heat sink, the outer side of the No. 2 bare die is fixed with the No. 4 heat sink, the outer side of the No. 3 bare die is fixed with the No. 3 heat sink, the outer side of the No. 4 bare die is fixed with the No. 2 heat sink, and the outer side of the No. 6 bare die is fixed with the No. 1 heat sink.

[0008] The outer side of the encapsulation substrate is symmetrically fixed with a second closed side plate, and multiple second heat sinks are fixedly fixed at equal intervals inside the second closed side plate. The outer sides of the fifth heat sink, fourth heat sink, third heat sink, second heat sink, and first heat sink are all fixedly connected to the second heat sink.

[0009] Preferably, the interconnect metal circuit includes a first metallization pattern, a plurality of first metallization patterns are equidistantly arranged on the top of the sealing element, a plurality of die connection elements are equidistantly arranged on the bottom of the sealing element, a first dielectric layer is disposed on the top of the first metallization pattern, and the bottom of the first dielectric layer is fixedly connected to the sealing element.

[0010] Preferably, a second dielectric layer is fixed to the top of the first dielectric layer, a plurality of third metallization patterns are equidistantly arranged between the second dielectric layer and the first dielectric layer, a plurality of fourth metallization patterns are equidistantly fixed to the top of the second dielectric layer, a third dielectric layer is fixed to the top of the second dielectric layer, and a plurality of first bump regions are equidistantly fixed to the top of the third dielectric layer.

[0011] Preferably, a plurality of external connecting elements are equidistantly arranged on the top of the first protrusion area.

[0012] Preferably, a first closed side plate is symmetrically fixed to the outer side of the packaging substrate, and a first heat sink is fixed to the inside of the first closed side plate. The first, second, third, fourth, sixth, and fifth bare dies are all fixed to the first heat sink, and multiple support blocks are equidistantly fixed between the first, second, third, fourth, sixth, and fifth bare dies.

[0013] Preferably, a plurality of second metallization patterns are equidistantly arranged between the sealing element and the first dielectric layer.

[0014] A method for manufacturing a semiconductor device includes the following steps:

[0015] S1. Use laser cutting technology to cut the packaging substrate of the required shape and size from the packaging substrate material;

[0016] S2. Connect the No. 1 copper foil line and the No. 2 copper foil line to the top of the packaging substrate using conductive adhesive.

[0017] S3. Use adhesive to fix the organic substrate to the top of the No. 2 copper foil line, and then use laser cutting technology to open the internal connecting groove on the organic substrate.

[0018] S4. The connecting substrate and the heat-conducting partition plate are fixed to the top of the organic substrate by welding;

[0019] S5. Using chip mounting technology, die 1, die 2, die 3, die 4, die 6 and die 5 are fixed to both sides of the heat-conducting partition plate in sequence. Each die is fixed to the heat-conducting partition plate through a heat dissipation plate. Supporting spacers are welded between die 1, die 2, die 3, die 4, die 6 and die 5 for separation.

[0020] S6. Use adhesive to fix heat sink No. 1, heat sink No. 2, heat sink No. 3, heat sink No. 4 and heat sink No. 5 to the outside of the corresponding bare plate respectively;

[0021] S7. By welding, the No. 1 closed side plate and the No. 2 closed side plate are fixed to the outside of the packaging substrate, the No. 1 heat sink is fixed to the inside of the No. 1 closed side plate, and the No. 2 heat sink is fixed to the inside of the No. 2 closed side plate, thus realizing heat dissipation of each bare chip.

[0022] S8. A first gate insulating film and a second gate insulating film are formed on the top of the connecting substrate by chemical vapor deposition, and a gate electrode is formed by electroplating.

[0023] S9. Use an adhesive to fix the sealing element to the top of the first gate insulating film. Form a first metallization pattern, a second metallization pattern, and a die connection element on the top and bottom of the sealing element through an electroplating process. The metallization pattern and the die connection element are interconnected through metallized vias.

[0024] S10. A second dielectric layer is formed on top of the first dielectric layer. A patterned opening for metallization is formed between the dielectric layers by photolithography. Metal is deposited in the patterned opening by electroplating to form a third and fourth metallization pattern. A third dielectric layer is constructed above the first and second dielectric layers. A first bump region is formed on top of the third dielectric layer. An external connection element is placed on top of the first bump region.

[0025] S11. After the semiconductor device is manufactured, it is packaged with plastic. During the packaging process, the packaging material is fixed to the semiconductor device by injection molding to form a complete package.

[0026] S12. Test the packaged semiconductor device, including performance testing, reliability testing and environmental testing.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows: The semiconductor device of the present invention significantly improves the heat dissipation performance of the device by designing a heat-conducting plate and a multi-layer heat dissipation structure. This not only ensures that the heat generated by each die during operation can be dissipated in a timely and effective manner, avoiding performance degradation or damage caused by excessive temperature, but also enhances the stability and reliability of the entire packaging structure through the reinforcement of the support partition and the closed side plate. This efficient heat dissipation and improved structural stability enable the semiconductor device of the present invention to have a longer service life and higher operating performance in high-power, high-density applications. The semiconductor device of the present invention achieves a high degree of integration by optimizing the packaging layout and the design of the interconnect metal circuit. Multiple dies are arranged in a stacked manner on both sides of the heat-conducting plate and interconnected through multi-layer metallized patterns and dielectric layers. This not only increases the packaging density, but also reduces the connection path and signal loss. The connection reliability is enhanced by the connection substrate, gate insulating film and sealing element structure, reducing the risk of failure due to poor connection or aging.

[0029] By designing a heat-conducting partition plate and a multi-layer heat dissipation structure, the heat dissipation performance of the device is significantly improved. The heat-conducting partition plate not only effectively isolates the heat generated by each die, but also dissipates the heat quickly through the multi-layer heat dissipation structure, avoiding performance degradation or damage caused by excessive temperature. Through optimized design, a high degree of integration is achieved. Multiple dies are arranged in a stacked manner on both sides of the heat-conducting partition plate and interconnected through multi-layer metallized patterns and dielectric layers. This design not only improves the packaging density, makes full use of the space on both sides of the heat-conducting partition plate and the dies, and increases heat dissipation, but also reduces the connection path and shrinks the overall size. Attached Figure Description

[0030] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the internal structure of the present invention;

[0032] Figure 2 This is a schematic diagram of the overall structure of the present invention;

[0033] Figure 3 This is a front view of the present invention;

[0034] Figure 4 This is a schematic diagram of the organic substrate structure of the present invention;

[0035] Figure 5 This is a schematic diagram of the structure of the heat-conducting plate and the first bare die of the present invention;

[0036] Figure 6 This is a three-dimensional structural diagram of the present invention;

[0037] Figure 7 This is a schematic diagram of the interconnect metal circuit structure of the present invention;

[0038] Figure 8 This is a schematic diagram of the bare die structure of the present invention.

[0039] In the diagram: 1. Packaging substrate; 2. Copper foil circuit No. 1; 3. Copper foil circuit No. 2; 4. Organic substrate; 5. Internal connecting groove; 6. Connecting substrate; 7. Heat-conducting separator; 8. Die No. 1; 9. Die No. 2; 10. Die No. 3; 11. Die No. 4; 12. Die No. 5; 13. Connecting substrate; 14. Gate insulating film No. 1; 15. Gate electrode; 16. Gate insulating film No. 2; 17. Sealing element; 18. Die connection element; 19. Metallization pattern No. 1; 20. Metallization pattern No. 2 Case; 21. Dielectric layer 1; 22. Dielectric layer 2; 23. Metallization pattern 3; 24. Metallization pattern 4; 25. Dielectric layer 3; 26. Bump area 1; 27. External connecting element; 28. Heat sink 1; 29. ​​Heat sink 2; 30. Heat sink 3; 31. Heat sink 4; 32. Heat sink 5; 33. Support block; 34. Heat sink 1; 35. Closed side plate 1; 36. Closed side plate 2; 37. Heat sink 2; 38. Bare die 6. Detailed Implementation

[0040] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0042] See Figures 1 to 8As shown, a semiconductor device according to an embodiment of the present invention includes a packaging substrate 1. A plurality of first-order copper foil lines 2 are equidistantly fixed to the top of the packaging substrate 1. A plurality of second-order copper foil lines 3 are equidistantly fixed to the top of the packaging substrate 1, and the second-order copper foil lines 3 are fixedly connected to the first-order copper foil lines 2. An organic substrate 4 is fixedly fixed to the top of the second-order copper foil lines 3. A plurality of internal connecting grooves 5 are equidistantly formed on the top of the organic substrate 4. A connecting substrate 6 is fixedly fixed to the top of the organic substrate 4. A heat-conducting partition plate 7 is fixedly fixed to the top of the connecting substrate 6. First-order dies 8 are disposed on both sides of the heat-conducting partition plate 7. Second-order dies 9 are disposed on both sides of the heat-conducting partition plate 7, and the second-order dies 9 are located above the first-order dies 8. Third-order dies 10 are disposed on both sides of the heat-conducting partition plate 7, and the third-order dies 10 are located above the second-order dies 9. Fourth-order dies 11 are disposed on both sides of the heat-conducting partition plate 7, and the fourth-order dies 11 are located above the third-order dies 10. Both sides of the heat-conducting plate 7 are provided with No. 6 bare die 38, which is located above No. 4 bare die 11. Both sides of the heat-conducting plate 7 are provided with No. 5 bare die 12, which is located above No. 6 bare die 38. A connecting substrate 13 is provided on the top of No. 5 bare die 12. The bottom of the connecting substrate 13 is fixed to the heat-conducting plate 7. A No. 2 gate insulating film 16 is fixed on the top of the connecting substrate 13. Multiple gate electrodes 15 are fixed at equal intervals on the top of the No. 2 gate insulating film 16 and the gate electrodes 15. A No. 1 gate insulating film 14 is provided on the top of the No. 1 gate insulating film 14. A sealing element 17 is provided on the top of the sealing element 17. An interconnect metal circuit is provided on the top of the sealing element 17. Through precise stacking and connection, efficient electrical connection and thermal management are achieved, providing a semiconductor device with a compact structure and excellent thermal conductivity, which can meet the needs of high-performance electronic products.

[0043] A heat dissipation and heat conduction plate is fixed between bare die 8, bare die 9, bare die 10, bare die 11, bare die 38 and bare die 12 and the heat-conducting plate 7, which improves the heat conduction efficiency of the semiconductor device, further enhances the heat dissipation performance of the semiconductor device, and ensures the stability and reliability of the semiconductor device during high-power operation.

[0044] The outer side of bare plate 8 is fixed with heat sink 32 (No. 5), the outer side of bare plate 9 is fixed with heat sink 31 (No. 4), the outer side of bare plate 10 is fixed with heat sink 30 (No. 3), the outer side of bare plate 11 is fixed with heat sink 29 (No. 2), and the outer side of bare plate 38 is fixed with heat sink 28 (No. 1), which further increases the heat dissipation area, improves the heat dissipation efficiency, and extends the service life of the device.

[0045] A second closed side plate 36 is symmetrically fixed to the outer side of the packaging substrate 1. Multiple second heat sinks 37 are fixed at equal intervals inside the second closed side plate 36. The outer sides of the fifth heat sink 32, the fourth heat sink 31, the third heat sink 30, the second heat sink 29 and the first heat sink 28 are all fixed to the second heat sink 37, which further enhances the heat dissipation performance of the semiconductor device and ensures stable operation under high power density.

[0046] The interconnect metal circuit includes a first metallization pattern 19, multiple first metallization patterns 19 are equidistantly arranged on the top of the sealing element 17, multiple die connection elements 18 are equidistantly arranged on the bottom of the sealing element 17, a first dielectric layer 21 is arranged on the top of the first metallization pattern 19, and the bottom of the first dielectric layer 21 is fixedly connected to the sealing element 17, which enhances the stability and reliability of the electrical connection inside the semiconductor device, improves the electrical performance of the semiconductor device, and ensures accurate signal transmission.

[0047] Among them, a second dielectric layer 22 is fixed to the top of the first dielectric layer 21, and multiple third metallization patterns 23 are equidistantly arranged between the second dielectric layer 22 and the first dielectric layer 21. Multiple fourth metallization patterns 24 are equidistantly fixed to the top of the second dielectric layer 22, and a third dielectric layer 25 is fixed to the top of the second dielectric layer 22. Multiple first bump regions 26 are equidistantly fixed to the top of the third dielectric layer 25. This increases the electrical connection layers inside the semiconductor device, improves the complexity and functionality of the circuit, expands the application range of the semiconductor device, and enables it to support higher-level electronic design and functions.

[0048] Among them, multiple external connection elements 27 are equidistantly arranged on the top of the first bump area 26, which enhances the interconnectivity and scalability of the semiconductor device, making it easier to integrate the semiconductor device into a larger electronic system.

[0049] In this package, a first closed side plate 35 is symmetrically fixed to the outer side of the packaging substrate 1, and a first heat sink 34 is fixed to the inside of the first closed side plate 35. The first die 8, the second die 9, the third die 10, the fourth die 11, the sixth die 38 and the fifth die 12 are all fixed to the first heat sink 34. Multiple support blocks 33 are fixed at equal intervals between the first die 8, the second die 9, the third die 10, the fourth die 11, the sixth die 38 and the fifth die 12, providing additional heat dissipation paths, ensuring the internal stability and structural integrity of the semiconductor device, and improving the heat dissipation performance and structural strength of the semiconductor device.

[0050] Among them, multiple second metallization patterns 20 are equidistantly arranged between the sealing element 17 and the first dielectric layer 21, which improves the electrical performance and interconnectivity of the semiconductor device, enabling the device to support more complex circuit designs and functions.

[0051] A method for manufacturing a semiconductor device includes the following steps:

[0052] S1. Use laser cutting technology to cut the packaging substrate 1 into the required shape and size from the packaging substrate material;

[0053] S2. Connect copper foil line 2 and copper foil line 3 to the top of the packaging substrate 1 using conductive adhesive.

[0054] S3. Use adhesive to fix the organic substrate 4 to the top of the second copper foil line 3, and then use laser cutting technology to open the internal connecting groove 5 on the organic substrate 4.

[0055] S4. The connecting substrate 6 and the heat-conducting partition plate 7 are fixed to the top of the organic substrate 4 by welding.

[0056] S5. Using chip mounting technology, die 8, die 9, die 10, die 11, die 38, and die 12 are fixed to both sides of the heat-conducting partition plate 7 in sequence. Each die is fixed to the heat-conducting partition plate 7 through a heat dissipation plate. Supporting blocks 33 are welded between die 8, die 9, die 10, die 11, die 38, and die 12 for separation.

[0057] S6. Use adhesive to fix heat sink 28, heat sink 29, heat sink 30, heat sink 31 and heat sink 32 to the outside of the corresponding bare plate respectively.

[0058] S7. The first closed side plate 35 and the second closed side plate 36 are fixed to the outside of the packaging substrate 1 by welding, the first heat sink 34 is fixed to the inside of the first closed side plate 35, and the second heat sink 37 is fixed to the inside of the second closed side plate 36, thereby realizing the heat dissipation of each bare chip.

[0059] S8. A first gate insulating film 14 and a second gate insulating film 16 are formed on the top of the connecting substrate 13 by chemical vapor deposition, and a gate electrode 15 is formed by electroplating.

[0060] S9. Use an adhesive to fix the sealing element 17 to the top of the first gate insulating film 14. Form a first metallization pattern 19, a second metallization pattern 20 and a die connection element 18 on the top and bottom of the sealing element 17 by electroplating. The metallization pattern and the die connection element 18 are interconnected through metallized vias.

[0061] S10. A second dielectric layer 22 is formed on top of the first dielectric layer 21. A patterned opening for metallization pattern is formed between the dielectric layers by photolithography. Metal is deposited in the patterned opening by electroplating to form a third metallization pattern 23 and a fourth metallization pattern 24. A third dielectric layer 25 is constructed above the first dielectric layer 21 and the second dielectric layer 22. A first bump region 26 is formed on top of the third dielectric layer 25. An external connection element 27 is disposed on top of the first bump region 26.

[0062] S11. After the semiconductor device is manufactured, it is packaged with plastic. During the packaging process, the packaging material is fixed to the semiconductor device by injection molding to form a complete package.

[0063] S12. Test the packaged semiconductor device, including performance testing, reliability testing and environmental testing.

[0064] Specifically, in use, the packaging substrate 1 serves as the base of the entire semiconductor device, providing stable support and a foundation for electrical connections. Copper foil lines 2 and 3 are equidistantly fixed to the top of the packaging substrate 1, forming an electrical connection network. Copper foil line 3 is not only fixed to copper foil line 2 but also extends upwards to the organic substrate 4, enabling the transmission and distribution of electrical signals. Multiple interconnecting slots 5 equidistantly formed on the top of the organic substrate 4 facilitate heat dissipation and electrical signal transmission. The organic substrate, as the support for the connecting substrate 6, ensures structural stability and reliable electrical connections. The connecting substrate 6 is fixed... At the top of the organic substrate 4, the heat-conducting partition plate 7, which is fixed to the top, plays a crucial role in heat dissipation. Dies 8 through 38 are stacked in a specific order on both sides of the heat-conducting partition plate 7, forming a multi-layered circuit structure. Each die performs a different electrical function. A heat-conducting plate is fixed between each die and the heat-conducting partition plate 7, effectively conducting the heat generated by the die. Different heat sinks are also fixed to the outside of each die, further enhancing the heat dissipation effect. By increasing the heat dissipation area and providing additional heat dissipation paths, stable operation of the device under high power is ensured. The bottom of the connecting substrate 13... Fixed to the heat-conducting plate 7, a second gate insulating film 16 is fixed on top. The connecting substrate 13 not only provides the basis for electrical connection, but also participates in the heat dissipation process of the entire device through its thermal conductivity. These insulating films not only protect the gate electrode 15, but also ensure the electrical isolation between the gate electrode 15 and the surrounding circuit. At the same time, they also participate in the conduction and dissipation of heat. The sealing element 17 is located on top of the first gate insulating film 14, which plays the role of sealing and protecting the internal circuit. At the same time, it also serves as the substrate for the interconnect metal circuit, which includes the first metallization pattern 19, the die connection element 18, and the second metallization pattern 19. Pattern 20, along with multiple dielectric layers and metallized patterns, together form a complex electrical connection network, enabling signal transmission between different dies and between dies and external circuits. The first bump area 26 and the external connection element 27 provide connection points to external circuits, ensuring that the semiconductor device can communicate and transmit data with other electronic components. The first closed side plate 35 and the second closed side plate 36 fixed to the outside of the packaging substrate 1 are respectively fixed to the first heat sink 34 and the second heat sink 37. These heat sinks further enhance the heat dissipation performance of the entire device by increasing the heat dissipation area and providing additional heat dissipation paths.

[0065] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0066] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope of this disclosure is indicated by the following claims.

Claims

1. A semiconductor device, characterized in that, The package includes a packaging substrate (1), on which a plurality of first-order copper foil lines (2) are fixedly and equidistantly attached at the top. A plurality of second-order copper foil lines (3) are also fixedly and equidistantly attached at the top of the packaging substrate (1), and the second-order copper foil lines (3) are fixedly connected to the first-order copper foil lines (2). An organic substrate (4) is fixedly attached to the top of the second-order copper foil lines (3). A plurality of internal connecting grooves (5) are equidistantly formed on the top of the organic substrate (4). A connecting substrate (6) is fixedly attached to the top of the organic substrate (4). The top of the connecting substrate (6) is fixedly connected to a heat-conducting partition plate (7). A first bare plate (8) is provided on both sides of the heat-conducting partition plate (7). A second bare plate (9) is provided on both sides of the heat-conducting partition plate (7), with the second bare plate (9) located above the first bare plate (8). A third bare plate (10) is provided on both sides of the heat-conducting partition plate (7), with the third bare plate (10) located above the second bare plate (9). Four... The fourth bare die (11) is located above the third bare die (10). A sixth bare die (38) is disposed on both sides of the separating heat-conducting plate (7), located above the fourth bare die (11). A fifth bare die (12) is disposed on both sides of the separating heat-conducting plate (7), located above the sixth bare die (38). A connecting substrate (13) is disposed on the top of the fifth bare die (12). 3) The bottom is fixed to the heat-conducting plate (7). The top of the connecting substrate (13) is fixed to a second gate insulating film (16). Multiple gate electrodes (15) are fixed at equal intervals on the top of the second gate insulating film (16). A first gate insulating film (14) is provided on the top of the second gate insulating film (16) and the gate electrodes (15). A sealing element (17) is provided on the top of the first gate insulating film (14). An interconnect metal circuit is provided on the top of the sealing element (17). Each of the No. 1 bare plate (8), No. 2 bare plate (9), No. 3 bare plate (10), No. 4 bare plate (11), No. 6 bare plate (38) and No. 5 bare plate (12) is fixedly connected to a heat dissipation and heat conduction plate (7); The outer side of the first bare plate (8) is fixed with the fifth heat sink (32), the outer side of the second bare plate (9) is fixed with the fourth heat sink (31), the outer side of the third bare plate (10) is fixed with the third heat sink (30), the outer side of the fourth bare plate (11) is fixed with the second heat sink (29), and the outer side of the sixth bare plate (38) is fixed with the first heat sink (28). The outer side of the encapsulation substrate (1) is symmetrically fixed with a second closed side plate (36), and a plurality of second heat sinks (37) are fixed at equal intervals inside the second closed side plate (36). The outer sides of the fifth heat sink (32), the fourth heat sink (31), the third heat sink (30), the second heat sink (29), and the first heat sink (28) are all fixed to the second heat sink (37).

2. A semiconductor device according to claim 1, characterized in that, The interconnecting metal circuit includes a first metallization pattern (19), and a plurality of first metallization patterns (19) are equidistantly arranged on the top of the sealing element (17). A plurality of die connection elements (18) are equidistantly arranged on the bottom of the sealing element (17). A first dielectric layer (21) is provided on the top of the first metallization pattern (19), and the bottom of the first dielectric layer (21) is fixedly connected to the sealing element (17).

3. A semiconductor device according to claim 2, characterized in that, A second dielectric layer (22) is fixed to the top of the first dielectric layer (21). Multiple third metallization patterns (23) are equidistantly arranged between the second dielectric layer (22) and the first dielectric layer (21). Multiple fourth metallization patterns (24) are equidistantly fixed to the top of the second dielectric layer (22). A third dielectric layer (25) is fixed to the top of the second dielectric layer (22). Multiple first bump regions (26) are equidistantly fixed to the top of the third dielectric layer (25).

4. A semiconductor device according to claim 3, characterized in that, Multiple external connecting elements (27) are equidistantly arranged on the top of the first protrusion area (26).

5. A semiconductor device according to claim 4, characterized in that, A first closed side plate (35) is symmetrically fixed to the outer side of the packaging substrate (1). A first heat sink plate (34) is fixed to the inside of the first closed side plate (35). The first die (8), the second die (9), the third die (10), the fourth die (11), the sixth die (38), and the fifth die (12) are all fixed to the first heat sink plate (34). Multiple support blocks (33) are fixed at equal intervals between the first die (8), the second die (9), the third die (10), the fourth die (11), the sixth die (38), and the fifth die (12).

6. A semiconductor device according to claim 5, characterized in that, Multiple second metallization patterns (20) are equidistantly arranged between the sealing element (17) and the first dielectric layer (21).

7. A method for manufacturing a semiconductor device according to any one of claims 1-6, characterized in that, Includes the following steps: S1. Use laser cutting technology to cut the packaging substrate of the required shape and size from the packaging substrate material (1); S2. The No. 1 copper foil line (2) and the No. 2 copper foil line (3) are connected to the top of the packaging substrate (1) by means of conductive adhesive bonding. S3. Use adhesive to fix the organic substrate (4) to the top of the second copper foil line (3), and then use laser cutting technology to open the internal connecting groove (5) on the organic substrate (4); S4. The connecting substrate (6) and the heat-conducting partition plate (7) are fixed to the top of the organic substrate (4) by welding; S5. Using chip mounting technology, the No. 1 bare die (8), No. 2 bare die (9), No. 3 bare die (10), No. 4 bare die (11), No. 6 bare die (38) and No. 5 bare die (12) are fixed to both sides of the partition heat-conducting plate (7) in sequence. Each bare die is fixed to the partition heat-conducting plate (7) through a heat dissipation heat-conducting plate. Supporting blocks (33) are welded between the No. 1 bare die (8), No. 2 bare die (9), No. 3 bare die (10), No. 4 bare die (11), No. 6 bare die (38) and No. 5 bare die (12) for separation. S6. Use adhesive to fix the No. 1 heat sink (28), No. 2 heat sink (29), No. 3 heat sink (30), No. 4 heat sink (31) and No. 5 heat sink (32) to the outside of the corresponding bare plate respectively; S7. The first closed side plate (35) and the second closed side plate (36) are fixed to the outside of the packaging substrate (1) by welding, the first heat sink (34) is fixed to the inside of the first closed side plate (35), and the second heat sink (37) is fixed to the inside of the second closed side plate (36), thereby realizing the heat dissipation of each bare chip. S8. A first gate insulating film (14) and a second gate insulating film (16) are formed on the top of the connecting substrate (13) by chemical vapor deposition, and a gate electrode (15) is formed by electroplating. S9. Use an adhesive to fix the sealing element (17) to the top of the first gate insulating film (14). Form a first metallization pattern (19), a second metallization pattern (20), and a die connection element (18) on the top and bottom of the sealing element (17) by electroplating. The metallization pattern and the die connection element (18) are interconnected through metallization vias. S10. A second dielectric layer (22) is coated on top of the first dielectric layer (21). A patterned opening for metallization pattern is formed between the dielectric layers by photolithography. Metal is deposited in the patterned opening by electroplating to form a third metallization pattern (23) and a fourth metallization pattern (24). A third dielectric layer (25) is constructed above the first dielectric layer (21) and the second dielectric layer (22). A first bump region (26) is formed on top of the third dielectric layer (25). An external connection element (27) is set on top of the first bump region (26). S11. After the semiconductor device is manufactured, it is packaged with plastic. During the packaging process, the packaging material is fixed to the semiconductor device by injection molding to form a complete package. S12. Test the packaged semiconductor device, including performance testing, reliability testing and environmental testing.

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