Test structure for detecting Si dislocation and Si dislocation detection method

Abstract

The invention provides a test structure for detecting Si dislocation and a Si dislocation detection method.The test structure is integrated in a cutting channel of a wafer to be detected, the test structure and a device in the wafer to be detected are synchronously formed, the test structure comprises an isolation groove and active areas, the active areas are located on the two sides of the isolation groove and connected with each other, and the active areas are located in the isolation groove. A source-drain doped region is arranged in the active region; the length of the isolation groove is larger than a set value, the isolation groove is of a discrete structure, and a filling layer is arranged in the isolation groove. According to the wafer defect monitoring method and device, wafer scrapping can be avoided, defect monitoring of zero loss of the wafer is achieved, the Si dislocation defect can be quantified through the electrical parameters, and the wafer yield can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a test structure for detecting Si dislocations and a method for detecting Si dislocations. Background Technology

[0002] In the semiconductor industry, silicon (Si) substrates are the core material for manufacturing integrated circuit chips, and the integrity of their crystal structure directly determines the electrical performance and reliability of the chips. As semiconductor devices develop towards higher integration and smaller size, silicon substrates are prone to dislocation defects due to uneven stress distribution during manufacturing processes such as shallow trench isolation (STI), high-temperature annealing, and epitaxial growth. These defects are particularly concentrated in the top and bottom regions of the active area, becoming one of the key factors affecting chip yield.

[0003] Currently, the industry mainly relies on two technical methods for detecting dislocation defects in silicon substrates: one is to slice the wafer after hot spot localization and then observe the defects using a transmission electron microscope, such as... Figure 1 As shown; secondly, acid etching is used to treat the wafer surface, and then the exposed dislocation traces are observed under a microscope, such as... Figure 2 As shown.

[0004] However, both of the above-mentioned detection methods are destructive tests, requiring irreversible processing of the wafer. They can only be implemented after the wafer is scrapped and cannot be used for online monitoring of wafers in normal production. Secondly, these two detection methods can only determine the presence of dislocations by observation and cannot quantify the density and impact range of defects, making it difficult to meet the quantitative data requirements of high-precision process optimization. Finally, the offline operation mode leads to a lag in detection results, which cannot provide timely feedback on process problems and can easily cause defects to continue to appear in subsequent batches of wafers, increasing production costs and yield losses. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a test structure and a method for detecting Si dislocations, which can avoid wafer scrapping, achieve zero-loss defect monitoring of wafers, and quantify Si dislocation defects through electrical parameters, thereby helping to improve wafer yield.

[0006] In a first aspect, embodiments of this application provide a test structure for detecting Si dislocations, integrated in the dicing channel of a wafer under test and formed synchronously with the devices in the wafer under test. The test structure includes: an isolation trench and an active region, the active region being located on both sides of the isolation trench and interconnected, and source / drain doped regions being provided in the active region; the length of the isolation trench is greater than a set value and the isolation trench is a discrete structure, and a filling layer is provided in the isolation trench.

[0007] In one optional embodiment, the length of the isolation trench is greater than or equal to 50 μm.

[0008] In one optional embodiment, the test structure further includes a polysilicon gate, which cooperates with the active region to form a current control path to control the on / off state of the current.

[0009] In one optional embodiment, the polysilicon gate is strip-shaped, and the length direction of the polysilicon gate is perpendicular to the length direction of the isolation trench.

[0010] In one optional embodiment, the test structure further includes a contact hole through which the internal electrical connection of the test structure is achieved, and in conjunction with an external dedicated measurement circuit, the electrical parameters of the test structure are read.

[0011] Secondly, embodiments of this application provide a Si dislocation detection method, which uses the test structure described above to perform Si dislocation detection on the wafer under test. The detection method includes: The test structure is arranged in the dicing channel of the wafer under test according to the layout of the exposure units, wherein at least one test structure is arranged in each exposure unit; under the condition that the gate voltage is zero, the source-drain voltage signal is applied to the device in the test structure, and an electrical characteristic curve is output, wherein the electrical characteristic curve characterizes the change of electrical parameters with the source-drain voltage; Based on the relationship between the electrical parameter values ​​on the electrical characteristic curve and the preset parameter threshold, it is determined whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located.

[0012] In one optional embodiment, the electrical parameters include drain current, and the electrical characteristic curve includes a first characteristic curve, which characterizes the change of drain current with source-drain voltage. The step of determining whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located based on the electrical parameter values ​​on the electrical characteristic curve includes: If the drain current on the first characteristic curve exceeds the first preset threshold, it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

[0013] In one optional embodiment, the electrical parameters include drain current and substrate current, and the electrical characteristic curves include a first characteristic curve and a second characteristic curve. The first characteristic curve characterizes the change of drain current with source-drain voltage, and the second characteristic curve characterizes the change of substrate current with source-drain voltage. The step of determining whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located based on the electrical parameter values ​​on the electrical characteristic curve includes: If the drain current on the first characteristic curve exceeds the first preset threshold and the substrate current on the second characteristic curve is within the normal range, then it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

[0014] In one optional embodiment, the electrical parameters include drain current, substrate current, gate current, and source current, and the electrical characteristic curves include a first characteristic curve, a second characteristic curve, a third characteristic curve, and a fourth characteristic curve. The first characteristic curve characterizes the change of the drain current with the source-drain voltage, the second characteristic curve characterizes the change of the substrate current with the source-drain voltage, the third characteristic curve characterizes the change of the gate current with the source-drain voltage, and the fourth characteristic curve characterizes the change of the source current with the source-drain voltage. The step of determining whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located based on the electrical parameter values ​​on the electrical characteristic curve includes: If the drain current on the first characteristic curve exceeds the first preset threshold, the substrate current on the second characteristic curve is within the normal range, the gate current on the third characteristic curve exceeds the second preset threshold, and the source current on the fourth characteristic curve exceeds the third preset threshold, then it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

[0015] In an optional embodiment, the detection method further includes: The number of failure test structures in the wafer under test whose electrical parameter values ​​exceed a preset parameter threshold is counted, and the failure ratio of chips in the wafer under test is calculated based on the total number of test structures on the wafer under test. Extract the abnormal values ​​of the electrical parameters for each failure test structure; Based on the pre-established mapping model between abnormal electrical parameters and dislocation density, the abnormal electrical parameters of each failure test structure are converted into the dislocation density of the corresponding exposure unit. The overall defect level of the wafer under test is evaluated based on the dislocation density of each exposure unit and the failure rate of the chip.

[0016] This application provides a test structure and method for detecting Si dislocations. By combining discrete isolation trenches with interconnect active regions, the stress concentration effect at the bottom of the isolation trenches is used to enhance the electrical response signal of Si dislocations. Simultaneously, it is integrated into the wafer dicing channel and formed synchronously with the devices in the wafer, requiring no additional process steps and enabling non-destructive testing. Compared with existing destructive methods such as slicing and acid etching, it can avoid wafer scrapping, achieve zero-loss defect monitoring of the wafer, and quantify Si dislocation defects through electrical parameters.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A semiconductor dislocation slice image provided for existing technology; Figure 2 An acid-based image of semiconductor dislocation defects provided for existing technology; Figure 3 This is a schematic diagram of a test structure for detecting Si dislocations provided in an embodiment of this application; Figure 4 A flowchart of a Si dislocation detection method provided in an embodiment of this application; Figure 5 This is a schematic diagram of multiple feature curves provided in an embodiment of this application; Figure 6 This is a flowchart of another Si dislocation detection method provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0021] like Figure 3As shown in the figure, this application provides a test structure for detecting Si dislocations. The test structure 30 is integrated into the dicing channel of the wafer under test and is formed synchronously with the devices in the wafer under test. The test structure 30 includes an isolation trench 301, an active region 302, source and drain doped regions (not shown in the figure), and a filling layer (not shown in the figure). The active region 302 is located on both sides of the isolation trench 301 and interconnected. The source and drain doped regions are disposed in the active region 302. The length of the isolation trench 301 is greater than a set value and is a discrete structure. The filling layer is disposed in the isolation trench 301.

[0022] The dicing channels on the wafer under test are reserved areas on the wafer used to separate adjacent dies for subsequent dicing processes. These areas are not used to form functional chips; they only house auxiliary components such as test structures or alignment marks, thus avoiding the occupation of effective chip area. For example, the dicing channels are distributed in a grid pattern along the radial and circumferential directions of the wafer, dividing it into multiple exposure units. The test structures are then placed within these grid-like dicing channels, aligned with the extension direction of the dicing channels. Furthermore, the manufacturing process of the test structures is integrated into the standard wafer device manufacturing process, such as shallow trench isolation, doping, and deposition processes, eliminating the need for additional process steps after device manufacturing is complete.

[0023] In an optional implementation, when the wafer is subjected to shallow trench isolation (STI) to form the isolation structure of the device, the isolation trench 301 of the test structure is simultaneously etched in the dicing area; when the active region of the device is subjected to source and drain doping, the active region 302 of the test structure 30 is subjected to the same doping process simultaneously, to ensure that the process environment of the test structure 30 is consistent with that of the device, so that the dislocation formation pattern of the test structure 30 matches that of the device.

[0024] Here, the isolation trench 301 refers to the trench structure etched in the wafer substrate, which is used to achieve physical separation and electrical isolation of the active regions 302 on both sides. Its discrete structure means that the transistors are distributed on the upper and lower sides of the long STI trench, which can enhance the stress concentration effect at the bottom of the trench and make it easier to induce the formation of Si dislocations.

[0025] Optionally, long STI trenches are the main structure for detecting Si dislocations. Specifically, long STI trenches themselves will induce certain stress. If there are dislocations in silicon, the behavior of dislocations will be more easily observed under the stress environment of long STI trenches. By observing the condition of silicon near long STI trenches, it can be determined whether there are dislocations.

[0026] Among them, such as Figure 3As shown, the active region 302 refers to the doped region in the wafer substrate that has conductive properties. It is the core region for current conduction in the test structure 30. The interconnection of the active regions 302 refers to the electrical connection between the two active regions 302 through metal wires or contact holes 304 to form a complete current path, ensuring that current changes can be detected by external circuits.

[0027] For example, the active region is doped with P-type or N-type doping, consistent with the doping type of the active region of the device, to ensure good conductivity; it is connected to the aluminum wire through contact holes located at the edge of the active region to ensure no significant loss during current transmission. For instance, when the test structure is used to detect dislocation defects in an N-type device, the active region is doped with phosphorus, with doping process parameters completely consistent with those of the device's active region, so that the electrical characteristics of the test structure match those of the device.

[0028] Specifically, the source and drain doped regions are regions formed by further high-concentration doping within the active region. They serve as the source and drain of the test structure, respectively, for applying voltage signals and outputting current signals. Their doping concentration is higher than that of the main active region to reduce contact resistance.

[0029] Specifically, the filler layer is an insulating material filled within the isolation trench, used to achieve physical filling and electrical insulation of the isolation trench, preventing current crosstalk between active regions on both sides of the trench through the bottom or sidewalls of the trench. For example, the filler layer can be made of silicon oxide, filled using a chemical vapor deposition process, with the deposition thickness consistent with the depth of the isolation trench. After filling, it undergoes chemical mechanical polishing to make the surface of the filler layer flush with the wafer surface, ensuring the flatness of subsequent processes and preventing short circuits in subsequent metal interconnects due to uneven filler layer surfaces.

[0030] In one optional embodiment, the length of the isolation trench is greater than or equal to 50 μm.

[0031] Here, setting the length of the isolation trench to be greater than or equal to 50 μm amplifies the stress effect. This ensures that when detecting stress-related defects such as Si dislocations, a sufficiently significant stress effect allows for accurate detection and analysis. The amplified stress effect of a longer isolation trench makes it easier to excite and detect defects such as dislocations in the silicon substrate. For example, in a detection structure, when the isolation trench length reaches 50 μm or greater, the amplified stress effect means that even small dislocations will have a more significant impact on the device's electrical performance due to the greater stress, thus facilitating detection through electrical testing methods.

[0032] In one optional embodiment, the test structure further includes a polysilicon gate 303, which cooperates with the active region 302 to form a current control path to control the current on / off.

[0033] Among them, the polysilicon gate 303 is a gate structure made of polysilicon material, located above the active region 302, and isolated from the active region 302 by the gate oxide layer. Its function is to control the formation and conduction of the channel in the active region 302 by applying the gate voltage, thereby regulating the current between the source and drain, so that the test structure has current control characteristics similar to the field effect transistor, which makes it easy to fix the test conditions by the gate voltage, such as the gate voltage being 0V, to ensure the stability of current detection.

[0034] In an optional implementation, the width of the polysilicon gate 303 can be related to the target device type and typical chip size to avoid test failures caused by parameter deviations. Details are as follows: Firstly, the width of the polysilicon gate is related to the type of target device. Specifically, different types of devices exist within a semiconductor chip, and the gate width design varies between these types. The test structure can be designed with a gate width tailored to the type of target device to accurately capture the effects of dislocations on that type of device.

[0035] Secondly, the width of the polysilicon gate should be consistent with the typical size of the device used in the chip. For example, for a 180nm 5V device (i.e., a chip using a 180nm process and operating at 5V), the standard value for the PMOS gate width is 0.5μm, and for NMOS it is 0.6μm. The gate width of the test structure can directly use this value. If the PMOS gate width of the test structure is increased, such as 1μm, which is much larger than the standard value of 0.5μm, the leakage signal caused by dislocations may be diluted by the large size of the device itself, failing to accurately reflect the defects of a 0.5μm PMOS in mass production. If the gate width is decreased, such as 0.2μm, additional process defects may be introduced due to the excessively small size, interfering with the test results.

[0036] Furthermore, the gate oxide (silicon oxide insulating layer between the gate and the substrate) thickness can also be determined by the characteristics of the device itself, covering a common thickness range for devices. Specifically, the gate oxide thickness can directly affect the threshold voltage, breakdown voltage, leakage characteristics, etc. Devices with different performance requirements can have different gate oxide thicknesses. For example, for high-frequency logic devices, the gate oxide thickness may be only a few nanometers, such as 5nm or 8nm; for high-voltage power devices, the gate oxide thickness needs to be tens of nanometers, such as 20nm or 50nm.

[0037] In another optional implementation, the polysilicon gate can be doped to reduce gate resistance and prevent gate voltage drop from affecting the detection results; the alignment accuracy between the gate and the active region is controlled within ±0.1 μm to ensure that the gate accurately covers the current conduction area of ​​the active region. For example, in the test structure of high-voltage device wafers, the polysilicon gate is boron-doped (P-type) with a gate oxide layer thickness of 20 nm to withstand higher source-drain voltages and meet the testing requirements of high-voltage devices.

[0038] Specifically, the polysilicon gate is strip-shaped, and the length direction of the polysilicon gate is perpendicular to the length direction of the isolation trench.

[0039] Here, the polysilicon gate structure is elongated, with its length direction perpendicular to the current conduction direction, which maximizes the coverage of the current conduction area of ​​the active region and ensures effective current control. The polysilicon gate is set along a direction perpendicular to the extension of the isolation trench, so that the gate can simultaneously cover part of the active regions on both sides, further optimizing the current control effect.

[0040] Furthermore, the length direction of the polysilicon gate is perpendicular to the length direction of the isolation trench, and the central axis of the gate is aligned with the central axis of the isolation trench. The deviation range can be controlled within 10nm~30nm, which can ensure the symmetry of gate control over the active regions on both sides and avoid current detection deviation caused by gate offset. For example, in high-precision detection scenarios, the center of the strip gate is aligned with the center of the isolation trench through photolithography alignment technology, so that the area of ​​the active regions on both sides covered by the gate is 1μm×1.5μm, ensuring consistent current conduction characteristics on both sides and improving detection accuracy.

[0041] In one optional embodiment, the test structure further includes a contact hole 304, through which the test structure 30 achieves internal electrical connection and cooperates with an external dedicated measurement circuit to read the electrical parameters of the test structure 30.

[0042] Among them, contact hole 304 refers to a hole-like structure that penetrates the dielectric layer on the wafer surface, such as the silicon oxide layer, with the inner wall covered by metal, such as titanium, titanium nitride, or aluminum. It is used to realize the electrical connection between the internal components of the test structure, such as the active region, the source and drain doped regions, the polysilicon gate, and the external metal connection, and is a key interface for current signal transmission. The external dedicated measurement circuit is mainly used to apply voltage and collect current, and can accurately control the voltage signal and detect minute current changes.

[0043] For example, the contact hole can be formed using a dry etching process, with titanium, titanium nitride, and aluminum deposited sequentially on the inner wall to form a low-resistance metal contact; such as Figure 3 As shown, the contact holes are located at the center of the source / drain doped region and the end of the polysilicon gate, respectively. Two contact holes are provided in each region to ensure stable current transmission. For example, an external dedicated measurement circuit applies a source / drain voltage (Vds) of 0-5V to the source / drain doped region through the contact holes, while applying a gate voltage (Vg) of 0V through the gate contact hole, and detecting the substrate current (Ib) through the substrate contact hole, thereby achieving accurate reading of electrical parameters.

[0044] Optionally, the contact hole is connected to an external dedicated measurement circuit via metal wiring; the external dedicated measurement circuit can have nanoampere-level current detection accuracy to meet the current detection requirements under normal and abnormal conditions. For example, when there are no Si dislocations at the bottom of the isolation trench of the test structure, the Ib detected by the external circuit is less than 10nA; when there are Si dislocations, Ib increases to more than 100nA, and the circuit can quickly identify this abnormal change and record the data.

[0045] This application provides a test structure for detecting Si dislocations. By combining discrete isolation trenches with interconnect active regions, the stress concentration effect at the bottom of the isolation trenches is used to enhance the electrical response signal of Si dislocations. Simultaneously, it is integrated into the wafer dicing channel and formed synchronously with the devices in the wafer, requiring no additional process steps and enabling non-destructive testing. Compared with existing destructive methods such as slicing and acid etching, it can avoid wafer scrapping, achieve zero-loss defect monitoring of the wafer, and quantify Si dislocation defects through electrical parameters.

[0046] Secondly, embodiments of this application provide a Si dislocation detection method, which applies as follows: Figure 1 The test structure described above performs Si dislocation detection on the wafer under test, such as... Figure 4 As shown, the method includes: S401. The test structure is arranged in the dicing path of the wafer to be tested according to the layout of the exposure units, wherein at least one test structure is arranged in each exposure unit. S402. Under the condition that the gate voltage is zero, the source-drain voltage signal is applied to the device in the test structure, and the electrical characteristic curve is output. The electrical characteristic curve characterizes the change of electrical parameters with the source-drain voltage. S403. Based on the relationship between the electrical parameter values ​​on the electrical characteristic curve and the preset parameter threshold, determine whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located.

[0047] In step S401, an exposure unit (shot) is a wafer area that can be covered by a single exposure of a lithography machine. Each exposure unit contains multiple chips (dies) and peripheral dicing channels, and is the basic unit for pattern transfer in wafer manufacturing. In this embodiment, the exposure units are arranged in a layout such that the position of the test structure corresponds to the boundary of the exposure unit, ensuring that the test structure of each exposure unit can reflect the dislocation situation of the chips in that unit.

[0048] For example, the exposure units of the wafer under test can be arranged in a matrix, with each exposure unit containing multiple chips and dicing tracks distributed along the boundaries of the exposure units. At least one test structure is arranged at the intersection of the dicing tracks in each exposure unit, so that the stress environment of the test structure is consistent with the stress environment of the chips within the exposure unit. For example, for a 12-inch wafer, a total of 10×10=100 exposure units are divided, and one test structure is set at the intersection of the dicing tracks in each exposure unit, for a total of 100 test structures, covering the dislocation detection requirements of the entire wafer.

[0049] It should be noted that each exposure unit should have at least one test structure. If the exposure unit area is large or the number of chips is large, the number of test structures can be increased to improve the accuracy and coverage of the detection and avoid missed detections due to the failure of a single test structure. For example, for a large exposure unit containing a large number of chips, five test structures can be arranged at the four corners and the center of its dicing path to detect dislocations in different areas of the exposure unit. If one test structure fails due to process deviation, the other four can still detect normally, ensuring that no dislocations in the exposure unit are missed. By arranging multiple test structures, high-risk dislocation areas within the exposure unit can be accurately located, improving chip yield.

[0050] In step S402, the gate voltage is zero as the standardized test condition. At this time, the polysilicon gate cannot form a conductive channel on the surface of the active region, and the current between the source and drain is only conducted by the active region body. This eliminates the influence of the gate voltage on the current and ensures that the electrical characteristic curve only reflects the dislocation situation of the active region and the isolation trench.

[0051] For example, a 0V DC voltage can be applied to the polysilicon gate of the test structure via the gate interface of an external dedicated measurement circuit. The voltage accuracy is controlled within ±0.01V, while the gate current (Ig) is monitored to ensure there is no leakage in the gate insulation layer and to avoid gate voltage deviation affecting the test results. For instance, before testing, a 0V voltage is applied to the gate and Ig is measured. If Ig is less than 1nA, it indicates that the gate insulation is normal, and subsequent testing can begin; if Ig is greater than 10nA, it indicates that there is a defect in the gate, and the data of this test structure must be excluded.

[0052] Here, the source-drain voltage signal is a DC voltage signal applied to the source-drain doped regions of the test structure. A step-up voltage approach can be used to obtain electrical parameters at different voltages. The electrical characteristic curve is a curve with the source-drain voltage (Vds) on the x-axis and electrical parameters (such as Ib, Id, Ig, and Is) on the y-axis, which can intuitively reflect the change of electrical parameters with voltage. Electrical parameters may include substrate current (Ib), drain current (Id), gate current (Ig), and source current (Is). Data is collected and four electrical characteristic curves are plotted. For example, when Vds increases from 0V to 5V, a total of 50 data points are collected, forming four curves: Ib-Vds, Id-Vds, Ig-Vds, and Is-Vds. The Ib-Vds curve is used to determine the presence of dislocations, the Id-Vds and Is-Vds curves are used for auxiliary verification, and the Ig-Vds curve is used to eliminate gate defect interference.

[0053] In step S403, the preset parameter threshold refers to the critical value determined based on the electrical parameters of a normal test structure without Si dislocations. It is the standard for distinguishing between normal and abnormal states. The preset parameter threshold needs to be calibrated through a large number of experiments to ensure the accuracy and reliability of the threshold.

[0054] This application embodiment locates the exposure unit where the electrical parameters of a single test structure are abnormal by identifying the abnormality. This determines that there is a risk of Si dislocation in the chip area within the exposure unit, achieving qualitative and qualitative location of the dislocation and providing precise area guidance for subsequent process adjustments.

[0055] For example, if the Ib value of the test structure corresponding to the exposure unit in the 5th row and 3rd column of the wafer exceeds the first preset threshold, it indicates the presence of Si dislocations in the chip region within that exposure unit. Further focused sampling inspection of the chip in this exposure unit can confirm the actual dislocation situation. Simultaneously, the process parameters of this exposure unit, such as STI etching depth and annealing temperature, should be recorded to analyze the cause of the dislocations. For instance, if the STI etching depth of this exposure unit is deeper than normal, it can be determined that etching process deviation is the main cause of the dislocations, and the etching parameters need to be adjusted.

[0056] The following example illustrates this using electrical parameters including different currents: In one optional embodiment, the electrical parameters include drain current, and the electrical characteristic curve includes a first characteristic curve, which characterizes the change of drain current with source-drain voltage; step S403 specifically includes: if the drain current on the first characteristic curve exceeds a first preset threshold, then it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

[0057] Here, the drain current (Id) is the current between the source and drain of the device in the test structure. Without dislocations, since Vg = 0V and there is no conductive channel, Id is mainly the reverse saturation current of the source-drain PN junction, with a small value and a gradual change with Vds. When Si dislocations are present, the dislocations form additional conductive paths between the source and drain, causing Id to increase significantly and its slope with Vds to become steeper. Figure 5 As shown, the first characteristic curve has Vds (unit: V) as the abscissa and Id (unit: A) as the ordinate. Its curve trend can reflect the rate of change of drain current with Vds. Under normal circumstances, the curve is flat, and the slope of the curve increases significantly when there is Si dislocation.

[0058] The first preset threshold refers to the preset parameter threshold set for the drain current. It is the standard for judging whether the drain current is abnormal. Its value is determined based on the statistical results of the drain current under different source and drain voltages of a normal test structure without dislocation defects. It is used to distinguish between normal drain current and abnormal drain current caused by dislocation defects. In an optional implementation, to avoid misjudgments caused by voltage fluctuations, a threshold can be set so that the presence of a Si dislocation is only determined after Id exceeds the threshold for more than three consecutive boost steps. In this way, if multiple Id values ​​exceed the threshold consecutively under multiple Vg values, random errors can be eliminated, and the presence of a Si dislocation can be accurately determined.

[0059] In one optional embodiment, the electrical parameters include drain current and substrate current, and the electrical characteristic curves include a first characteristic curve and a second characteristic curve. The first characteristic curve characterizes the change of drain current with source-drain voltage, and the second characteristic curve characterizes the change of substrate current with source-drain voltage. Step S403 specifically includes: if the drain current on the first characteristic curve exceeds a first preset threshold and the substrate current on the second characteristic curve exceeds a second preset threshold, then it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

[0060] The substrate current, defined as the current between the device substrate and other electrodes in the test structure, is a parameter reflecting the presence of defects in the substrate region. Specifically, the substrate current is caused by carrier recombination or generation within the substrate. Normally, it is on the order of nA and negligible. However, if Si dislocations exist in the substrate, these dislocations become carrier generation centers, significantly increasing the substrate current. Figure 5 As shown.

[0061] Here, the second characteristic curve is a curve specifically characterizing the relationship between substrate current and source / drain voltage, such as... Figure 5 As shown, the second characteristic curve has Vds (unit: V) as the abscissa and Ib (unit: A) as the ordinate. Under normal circumstances, the curve value is extremely low and the fluctuation is small. When there is a Si dislocation, the overall absolute value of the curve increases and the value increases significantly with Vds.

[0062] The second preset threshold is a preset parameter threshold set for the substrate current. It is the standard for judging whether the substrate current is abnormal. Since the substrate current is very small under normal circumstances (nA level), its threshold setting needs to be combined with the statistical results of normal substrate current to ensure that the increase in substrate current caused by dislocation defects can be accurately captured. The second preset threshold is a preset parameter threshold set for the substrate current. It is the standard for judging whether the substrate current is abnormal. Since the substrate current is very small under normal circumstances (nA level), its threshold setting needs to be combined with the statistical results of normal substrate current to ensure that the increase in substrate current caused by dislocation defects can be accurately captured. In another optional embodiment, the electrical parameters include drain current, substrate current, gate current, and source current, and the electrical characteristic curves include a first characteristic curve, a second characteristic curve, a third characteristic curve, and a fourth characteristic curve. The first characteristic curve characterizes the change of the drain current with the source-drain voltage, the second characteristic curve characterizes the change of the substrate current with the source-drain voltage, the third characteristic curve characterizes the change of the gate current with the source-drain voltage, and the fourth characteristic curve characterizes the change of the source current with the source-drain voltage; step S403 specifically includes: If the drain current on the first characteristic curve exceeds the first preset threshold, the substrate current on the second characteristic curve exceeds the second preset threshold, the gate current on the third characteristic curve is within the normal range, and the source current on the fourth characteristic curve exceeds the third preset threshold, then it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

[0063] The gate current is the current flowing into or out of the gate when a fixed voltage (e.g., Vg=0V) is applied to the gate and Vds is applied to the source and drain. Under normal circumstances, the gate current is extremely small (pA level) due to the good insulation of the gate oxide layer. If the gate oxide layer is damaged, the gate current will increase significantly. Its value can be used to determine whether the abnormality is caused by a gate fault. Here, under normal circumstances, Ig is extremely small because the gate is insulated from other areas. If Ig increases abnormally, it indicates that the drain source is due to a gate defect, rather than a Si dislocation, and such cases need to be ruled out. Only when the drain source is a Si dislocation, i.e., Ib, Id, and Is are abnormal while Ig is normal, is the test structure considered to be faulty.

[0064] Optionally, the source current and drain current are related. Under normal circumstances, the absolute value of the source current is close to that of the drain current. If there is an additional leakage path formed by Si dislocations, the source current will deviate from the normal value due to carrier shunting, which can be used as an auxiliary verification basis for abnormal drain current.

[0065] like Figure 5As shown, the third characteristic curve uses Vds (unit: V) as the abscissa and gate current (Ig, unit: A) as the ordinate. When there are no defects in the gate, the Is-Vds curve has extremely low values ​​and basically does not change with Vds. The fourth characteristic curve uses Vds (unit: V) as the abscissa and source current (Is, unit: A) as the ordinate. Under normal circumstances, the curve is symmetrical to the first characteristic curve (Id-Vds) (the values ​​are close, but the directions are opposite). When there are Si dislocations, the curve will deviate from the symmetrical trend.

[0066] The detection method provided in this application embodiment also includes: S601. Count the number of failure test structures in the wafer under test whose electrical parameter values ​​exceed the preset parameter threshold, and calculate the failure ratio of the chips in the wafer under test based on the total number of test structures on the wafer under test. S602. Extract the abnormal values ​​of electrical parameters for each failed test structure; S603. Based on the pre-established mapping model between abnormal electrical parameters and dislocation density, the abnormal electrical parameters of each failure test structure are converted into the dislocation density of the corresponding exposure unit. S604. Evaluate the overall defect level of the wafer under test based on the dislocation density of each exposure unit and the failure ratio of the chip.

[0067] In steps S601 to S604 above, the failure test structure refers to a test structure that meets the anomaly determination conditions. These anomaly determination conditions include, but are not limited to: drain current exceeding a first preset threshold, drain current exceeding the first preset threshold and substrate current exceeding a second preset threshold, and drain current exceeding the first preset threshold, substrate current exceeding the second preset threshold, gate current within the normal range, and source current exceeding a third preset threshold. Test structure failure is directly related to the failure of the chip within the corresponding exposure unit. The number of failures is the total number of all failure test structures on the wafer, and the total number of test structures is the total number of test structures arranged on the wafer. The ratio of these two is the chip failure ratio. Since each test structure corresponds to a chip in one exposure unit, this ratio can approximately reflect the proportion of chips in the wafer with dislocation risk.

[0068] Among them, abnormal electrical parameter values ​​refer to the difference between the actual electrical parameter values ​​of the failure test structure and the normal parameter benchmark values. The normal parameter benchmark values ​​are the average values ​​of the parameters of the dislocation-free test structure. The larger the abnormal value, the more severe the dislocation defect.

[0069] Furthermore, the mapping model between electrical parameter anomalies and dislocation density refers to a mathematical relationship model established through experiments. The establishment process is as follows: multiple sets of wafer samples with known dislocation densities are prepared, where the dislocation density can be determined by TEM detection. The electrical parameter anomalies of each set of samples are tested, and the two are fitted together to obtain the conversion formula between the anomalies and the dislocation density. This model can transform abstract electrical signals into specific dislocation density values, thereby achieving quantitative evaluation.

[0070] For example, a linear regression model can be used to establish a mapping relationship between Id outliers and dislocation density (ρ). Through this model, electrical anomalies of different failure test structures can be transformed into a unified dislocation density index, which facilitates horizontal comparison of the severity of defects in different exposure units.

[0071] Finally, the overall defect severity is assessed. Specifically, this involves combining the dislocation density of each exposure unit, such as maximum, minimum, and average values, distribution concentration, and chip failure rate, to comprehensively determine the wafer's dislocation defect level, such as mild, moderate, or severe. If the failure rate is less than a first predetermined rate and the average dislocation density is less than the first predetermined average, it is classified as a mild defect. If the failure rate is greater than the first predetermined rate but less than a second predetermined rate, and the average dislocation density is greater than the first predetermined average but less than the second predetermined average, it is classified as a moderate defect. If the failure rate is greater than the second predetermined rate and the average dislocation density is greater than the second predetermined average, it is classified as a severe defect, requiring production to be halted and the process optimized. Here, the first predetermined rate is less than the second predetermined rate, and the first predetermined average is less than the second predetermined average.

[0072] For example, the analysis described above reveals that if stress concentration is caused by etching depth deviation in the STI process, adjusting the etching parameters can reduce the failure rate of the next batch of wafers, while also decreasing the average dislocation density, thus improving the defect severity to a minor level. Furthermore, this evaluation logic can quickly pinpoint process problems, providing a quantitative basis for process optimization and achieving end-to-end defect prevention.

[0073] This application embodiment achieves full coverage of dislocation detection in different areas of the wafer by arranging the test structure according to the exposure unit, ensuring that the dislocation risk of the chip in each exposure unit can be accurately captured. Using zero gate voltage as a standardized test condition can eliminate the interference of gate voltage on the current signal, ensure the consistency of electrical characteristic curves, and provide a reliable benchmark for subsequent parameter comparison. The presence of dislocations is determined by comparing electrical parameters with preset thresholds, eliminating the need for wafer slicing or acid etching as in existing technologies. This achieves non-destructive qualitative and location detection, avoiding wafer scrapping, achieving zero-loss wafer monitoring, and laying the foundation for subsequent quantitative evaluation. It solves the problem of existing technologies relying on destructive methods and being unable to quantify. At the same time, the test structure is formed synchronously with the wafer device, and the detection process can be embedded in the WAT stage, compatible with online process monitoring, and can provide real-time feedback on dislocation defects, helping to optimize the process and prevent defects throughout the entire process.

[0074] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0075] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0076] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0077] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0078] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0079] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A test structure for detecting Si dislocations, characterized in that, The test structure is integrated into the dicing channel of the wafer under test and is formed synchronously with the devices in the wafer under test. The test structure includes: an isolation trench and an active region. The active region is located on both sides of the isolation trench and interconnected. Source and drain doped regions are provided in the active region. The length of the isolation trench is greater than a set value and the isolation trench is a discrete structure. A filling layer is provided in the isolation trench.

2. The test structure according to claim 1, characterized in that, The length of the isolation trench is greater than or equal to 50 μm.

3. The test structure according to claim 1, characterized in that, The test structure further includes a polysilicon gate, which, together with the active region, forms a current control path to control the on / off state of the current.

4. The test structure according to claim 3, characterized in that, The polysilicon gate is strip-shaped, and the length direction of the polysilicon gate is perpendicular to the length direction of the isolation trench.

5. The test structure according to claim 1, characterized in that, The test structure also includes a contact hole, through which the internal electrical connection of the test structure is realized, and the electrical parameters of the test structure are read in conjunction with an external dedicated measurement circuit.

6. A method for detecting Si dislocations, characterized in that, The test structure described in any one of claims 1 to 5 is used to perform Si dislocation detection on the wafer under test, the detection method comprising: The test structure is arranged in the dicing channel of the wafer under test according to the layout of the exposure units, wherein at least one test structure is arranged in each exposure unit; under the condition that the gate voltage is zero, the source-drain voltage signal is applied to the device in the test structure, and an electrical characteristic curve is output, wherein the electrical characteristic curve characterizes the change of electrical parameters with the source-drain voltage; Based on the relationship between the electrical parameter values ​​on the electrical characteristic curve and the preset parameter threshold, it is determined whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located.

7. The detection method according to claim 6, characterized in that, The electrical parameters include drain current, and the electrical characteristic curves include a first characteristic curve, which characterizes the change of drain current with source-drain voltage. The step of determining whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located based on the electrical parameter values ​​on the electrical characteristic curve includes: If the drain current on the first characteristic curve exceeds the first preset threshold, it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

8. The detection method according to claim 6, characterized in that, The electrical parameters include drain current and substrate current, and the electrical characteristic curves include a first characteristic curve and a second characteristic curve. The first characteristic curve characterizes the change of drain current with source-drain voltage, and the second characteristic curve characterizes the change of substrate current with source-drain voltage. The step of determining whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located based on the electrical parameter values ​​on the electrical characteristic curve includes: If the drain current on the first characteristic curve exceeds the first preset threshold and the substrate current on the second characteristic curve exceeds the second preset threshold, then it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

9. The detection method according to claim 6, characterized in that, The electrical parameters include drain current, substrate current, gate current, and source current. The electrical characteristic curves include a first characteristic curve, a second characteristic curve, a third characteristic curve, and a fourth characteristic curve. The first characteristic curve characterizes the change of drain current with source-drain voltage, the second characteristic curve characterizes the change of substrate current with source-drain voltage, the third characteristic curve characterizes the change of gate current with source-drain voltage, and the fourth characteristic curve characterizes the change of source current with source-drain voltage. The step of determining whether there are Si dislocations in the wafer region corresponding to the exposure unit where the test structure is located based on the electrical parameter values ​​on the electrical characteristic curve includes: If the drain current on the first characteristic curve exceeds the first preset threshold, the substrate current on the second characteristic curve exceeds the second preset threshold, the gate current on the third characteristic curve is within the normal range, and the source current on the fourth characteristic curve exceeds the third preset threshold, then it is determined that there is a Si dislocation in the wafer region corresponding to the exposure unit where the test structure is located.

10. The detection method according to claim 6, characterized in that, The detection method further includes: The number of failure test structures in the wafer under test whose electrical parameter values ​​exceed a preset parameter threshold is counted, and the failure ratio of chips in the wafer under test is calculated based on the total number of test structures on the wafer under test. Extract the abnormal values ​​of the electrical parameters for each failure test structure; Based on the pre-established mapping model between abnormal electrical parameters and dislocation density, the abnormal electrical parameters of each failure test structure are converted into the dislocation density of the corresponding exposure unit. The overall defect level of the wafer under test is evaluated based on the dislocation density of each exposure unit and the failure rate of the chip.

Images