Substrate structure and semiconductor package

Abstract

The invention provides a substrate structure and a semiconductor package. The substrate structure includes a substrate, a redistribution structure, and a pad connection layer. The substrate has a first grain region, a second grain region, and a spacer region extending between the first grain region and the second grain region. The redistribution structure is disposed on the substrate, wherein the redistribution structure includes a plurality of signal wirings and a plurality of shielding wirings. The signal wirings and the shield wirings are alternately disposed in the vertical direction and the lateral direction, and the width of the shield wirings is within a range of 3.5 to 4.6 times the width of the signal wirings. The pad connection layer is disposed on the substrate and the redistribution structure is located between the pad connection layer and the substrate, wherein the pad connection layer includes a plurality of pad connection patterns located in the first die region and the second die region.

Description

Technical Field

[0001] This invention relates to a packaging-related structure, and more particularly to a substrate structure and semiconductor packaging. Background Technology

[0002] With advancements in semiconductor manufacturing technology, the performance of chip devices is continuously improving. The industry is also demanding higher processing speeds from these devices. To achieve high-efficiency processing, technologies such as stacking chips into three-dimensional packages have been proposed, with ongoing improvements in the interface design between chips. For example, in high-density designs, crosstalk between control signals becomes a significant issue. Summary of the Invention

[0003] This invention relates to a substrate structure with ideal signal transmission performance.

[0004] This invention relates to a semiconductor package that controls crosstalk between signals within a required range.

[0005] According to an embodiment of the present invention, the substrate structure includes a substrate, a redistribution structure, and a pad connection layer. The substrate has a first die region, a second die region, and a spacing region extending between the first die region and the second die region. The redistribution structure is disposed on the substrate, wherein the redistribution structure includes multiple signal traces and multiple shielding traces. The signal traces and shielding traces are alternately arranged in the vertical and lateral directions, and the width of the shielding traces falls within the range of 3.5 to 4.6 times the width of the signal traces. The pad connection layer is disposed on the substrate, and the redistribution structure is located between the pad connection layer and the substrate, wherein the pad connection layer includes multiple pad connection patterns located in the first die region and the second die region.

[0006] In the substrate structure according to an embodiment of the present invention, the pad connection layer further includes a plurality of shielding strips extending between the first grain region and the second grain region and traversing the spacing region. The width of the shielding strip is 1.4 to 1.6 times the width of the nearest shielding wiring. The shielding strip is connected to the nearest shielding wiring through a through-hole. The substrate structure also includes a reference ground pad disposed on the pad connection layer, wherein the shielding strip and the reference ground pad are physically and electrically connected.

[0007] In the substrate structure according to an embodiment of the present invention, signal wirings and shielding wirings alternately arranged in the vertical direction are separated by a vertical distance, and signal wirings and shielding wirings alternately arranged in the lateral direction are separated by a lateral distance, wherein the lateral distance falls within the range of 1.5 to 1.8 times the vertical distance. The lateral distance is not less than 0.8 micrometers.

[0008] In the substrate structure according to an embodiment of the present invention, the redistribution structure further includes multiple bottom layer wirings. The bottom layer wirings are disposed on the substrate, and signal wirings and shielding wirings are located between the bottom layer wirings and the pad connection layer, wherein the bottom layer wirings have the same width. The bottom layer wirings also include multiple ground wirings and multiple power wirings, wherein the ground wirings and power wirings are alternately arranged in the lateral direction, and each ground wiring corresponds to one of the signal wirings in the vertical direction, and each power wiring corresponds to one of the shielding wirings in the vertical direction.

[0009] According to an embodiment of the present invention, the substrate structure includes a substrate, a redistribution structure, and a pad connection layer. The substrate has a first die region, a second die region, and a spacer region extending between the first die region and the second die region. The redistribution structure is disposed on the substrate. The pad connection layer is disposed on the substrate, and the redistribution structure is located between the pad connection layer and the substrate, wherein the pad connection layer includes a plurality of pad connection patterns located in the first die region and the second die region, and a plurality of shielding strips extending between the first die region and the second die region and traversing the spacer region.

[0010] In the substrate structure according to an embodiment of the present invention, the shielding strip is connected to the rewiring structure through a through-hole.

[0011] In the substrate structure according to an embodiment of the present invention, the substrate structure further includes a reference ground pad, which is disposed on the pad connection layer, wherein the shielding strip is physically and electrically connected to the reference ground pad.

[0012] In the substrate structure according to an embodiment of the present invention, the width of the shielding strip is greater than the width of all the wirings in the rewiring structure.

[0013] In the substrate structure according to an embodiment of the present invention, the spacing of the shielding strips is approximately twice the wiring spacing of the rewiring structure.

[0014] In the substrate structure according to an embodiment of the present invention, the width of each shielding strip is 1.4 to 1.6 times the width of the nearest shielding strip of the redistribution structure.

[0015] In the substrate structure according to an embodiment of the present invention, the redistribution structure includes multiple bottom-layer wirings disposed on the substrate, and the bottom-layer wirings having the same width. The bottom-layer wirings include multiple ground wirings and multiple power wirings, wherein the ground wirings and power wirings are alternately arranged in the lateral direction.

[0016] According to an embodiment of the present invention, a semiconductor package includes a substrate structure, a first die, and a second die. The substrate structure includes a substrate, a redistribution structure, and a pad connection layer. The substrate has a first die region, a second die region, and a spacer region extending between the first die region and the second die region. The redistribution structure is disposed on the substrate. The pad connection layer is disposed on the substrate, and the redistribution structure is located between the pad connection layer and the substrate, wherein the pad connection layer includes a plurality of pad connection patterns located in the first die region and the second die region, and a plurality of shielding strips extending between the first die region and the second die region and traversing the spacer region. The first die is bonded to the substrate structure in the first die region. The second die is bonded to the substrate structure in the second die region, wherein the first die and the second die are spaced apart by the spacer region.

[0017] In a semiconductor package according to an embodiment of the present invention, the redistribution structure includes multiple signal traces and multiple shielding traces, which are alternately arranged in the vertical and lateral directions. The width of the shielding traces falls within the range of 3.5 to 4.6 times the width of the signal traces. The width of the shielding strip is 1.4 to 1.6 times the width of the nearest shielding trace in the redistribution structure. The shielding strip is connected to the nearest shielding trace in the redistribution structure through a via. The substrate structure also includes a reference ground pad disposed on a pad connection layer, wherein the shielding strip and the reference ground pad are physically and electrically connected. The signal traces and shielding traces alternately arranged in the vertical direction are separated by a vertical distance, and the signal traces and shielding traces alternately arranged in the lateral direction are separated by a lateral distance, with the lateral distance falling within the range of 1.5 to 1.8 times the vertical distance. The lateral distance is not less than 0.8 micrometers.

[0018] In a semiconductor package according to an embodiment of the present invention, a first die and a second die each have an interface circuit disposed therein, and the interface circuit of the first die and the interface circuit of the second die are signal connected through a rewiring structure.

[0019] In a semiconductor package according to an embodiment of the present invention, the semiconductor package further includes a packaging substrate, wherein the side of the substrate structure opposite to the redistribution structure is bonded to the packaging substrate.

[0020] In a semiconductor package according to an embodiment of the present invention, the redistribution structure further includes multiple signal traces, multiple shielding traces, and multiple bottom-layer traces. The bottom-layer traces are disposed on a substrate, and the signal traces and shielding traces are located between the bottom-layer traces and the pad connection layer, wherein the bottom-layer traces have the same width. The bottom-layer traces include multiple ground traces and multiple power traces, wherein the ground traces and power traces are alternately arranged in the lateral direction, each ground trace is correspondingly arranged with one of the signal traces in the vertical direction, and each power trace is correspondingly arranged with one of the shielding traces in the vertical direction.

[0021] Based on the above, the substrate structure of this disclosure provides a shielding strip on the pad connection layer of the redistribution structure and / or provides widened shielding wiring in the signal wiring of the redistribution structure to control signal crosstalk between signal wirings within a suitable range, thereby achieving high signal processing efficiency. Since the shielding strip and the widened shielding wiring do not require additional manufacturing processes, they can be manufactured in existing processes, thus avoiding process burden. Attached Figure Description

[0022] Figure 1 This is a partial top view of a substrate structure according to an embodiment of the present disclosure;

[0023] Figure 2 for Figure 1 A cross-sectional view of the substrate structure along line II;

[0024] Figure 3 for Figure 1 A schematic cross-sectional view of the substrate structure along line II-II;

[0025] Figure 4 This is a schematic diagram of a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0026] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0027] Figure 1 This is a partial top view of a substrate structure according to an embodiment of the present disclosure. Figure 1 The substrate structure 100 includes a substrate 110 and a pad connection layer 120 disposed on the substrate 110, and Figure 1 Only a portion of the pad connection layer 120 is shown. The substrate structure 100 can be understood as an interposer in a semiconductor package, which can be used to achieve signal connections between multiple semiconductor dies, and also for signal connections between semiconductor dies and a package substrate. In other words, the substrate structure 100 can provide signal transmission / connection in the lateral direction (e.g., the X direction) and in the vertical direction (vertical direction, e.g., the Z direction). In addition, the substrate structure 100 may also include a plurality of pads 130 disposed on the pad connection layer 120. The pads 130 can be coupled with suitable connectors for bonding other components (e.g., semiconductor dies or the like) to the substrate structure 100.

[0028] In some embodiments, the substrate 110 of the substrate structure 100 may be a silicon substrate. The substrate 110 may have sufficient mechanical strength to support components such as dies disposed thereon in subsequent applications. In some embodiments, circuit components such as transistors may not be disposed on (or within) the substrate 110, but designed conductive features may be disposed on or within the substrate 110 to establish electrical transport paths between multiple components. For example, the pad connection layer 120 can be understood as an example of designed conductive features disposed on the substrate 110. The substrate 110 may be bonded to multiple semiconductor dies or similar components in practical applications, and thus may have a first die region 112 and a second die region 114. The substrate 110 may also have a spacer region 116 between the first die region 112 and the second die region 114. In some embodiments, the first die region 112 and the second die region 114 may be configured to have dimensions corresponding to the semiconductor dies or similar components to be bonded, while the spacer region 116 is an area required to be retained during the assembly of the substrate and semiconductor dies due to process factors. In other words, the spacer region 116 must not overlap with a semiconductor die or similar component.

[0029] The pad connection layer 120 may include multiple pad connection patterns 122 and multiple shielding strips 124. The pad connection layer 120 may be composed of a patterned layer of metallic material. The pad connection patterns 122 and the shielding strips 124 are of the same layer and formed by the same manufacturing process. The materials of the pad connection patterns 122 and the shielding strips 124 may include copper, gold, aluminum, nickel, their alloys, or combinations thereof. Furthermore, the pad connection layer 120 may also include a reference grounding wire 126 for connection to a ground potential. The reference grounding wire 126 may be connected to the shielding strips 124 and one or more of the pad connection patterns 122.

[0030] In some embodiments, the pad connection pattern 122 connected to the reference ground line 126 may be referred to as the reference ground pattern G122, and other pad connection patterns 122 may be used to transmit signals and are referred to as signal connection patterns S122. For clarity, Figure 1 Only schematically, a reference ground pattern G122 and a signal connection pattern S122 are marked in the pad connection pattern 122A located in the first grain region 112. Furthermore, by Figure 1 It can be seen that the shielding strip 124 and the reference grounding pattern G122 can be physically and electrically connected through the reference grounding wire 126, but this is not a limitation.

[0031] In some embodiments, the substrate structure 100 is used to mount a plurality of semiconductor chips or similar components thereon, and specifically, the semiconductor chips or similar components can be mounted via suitable bonding elements. Figure 1(Not shown, but may include microbumps or similar features) are bonded to pad 130. Depending on the location, pad 130 may include pad 130A located in the first die region 112 and pad 130B located in the second die region 114. Additionally, the pad connection pattern 122 corresponding to each individual pad 130 also includes pad connection pattern 122A located in the first die region 112 and pad connection pattern 122B located in the second die region 114. In some embodiments, the sizes of pad 130 and the corresponding pad connection pattern 122 may correspond to each other or one may be larger than the other. The number and arrangement of pads 130A and 130B are related to the design of the corresponding plurality of semiconductor dies or similar components. Therefore, the number and arrangement of pads 130A and 130B may be different or the same. For clarity of the drawings, Figure 1 Only six pads 130A and six pads 130B are shown in the figure. The number of individual features shown in the figure is for illustration only and not for limitation.

[0032] Multiple shielding strips 124 extend between the first grain region 112 and the second grain region 114 and traverse the spacer region 116. In some embodiments, the ends of each shielding strip 124 may overlap the first grain region 112 and the second grain region 114, respectively. The shielding strips 124 may be connected to a reference ground line 126, and the reference ground line 126 may be connected to a reference ground pattern G122. In some embodiments, the pads 130 corresponding to the reference ground pattern G122 may be used for grounding and are referred to as reference ground pads G130, while other pads 130 used for signal transmission may be referred to as signal pads S130. The shielding strips 124 and the reference ground pads G130 are physically and electrically connected. However, the shielding strips 124 and the signal pads S130 are physically and electrically separated and are electrically independent conductive features. Furthermore, the shielding strips 124 may be arranged substantially parallel to each other, but are not limited thereto. For clarity of the accompanying drawings, reference ground pad G130 and signal pad S130 are marked on pad 130A located in the first grain region 112, but pad 130B located in the second grain region 114 may also have a similar structure and connection relationship.

[0033] Figure 2 for Figure 1 A schematic cross-sectional view of the substrate structure along line II. (See attached diagram.) Figure 2As shown, the substrate structure 100 also includes a redistribution structure 140. The redistribution structure 140 is disposed on the substrate 110. The redistribution structure 140 includes multiple wiring layers M1 to M5 sequentially stacked between the substrate 110 and the pad connection layer 120, wherein wiring layer M1 is closest to the substrate 110, and wiring layer M5 is furthest from the substrate 110. To separate different conductive features, the redistribution structure 140 also includes an interlayer insulator 142, wherein the interlayer insulator 142 is disposed on the substrate 110 and extends between the redistribution structure 140 and the pad connection layer 120. Additionally, the substrate structure 100 includes a protective layer PS1 covering the wiring layer M5 and a protective layer PS2 covering the pad connection layer 120. Specifically, the interlayer insulator 142, the protective layer PS1, and the protective layer PS2 can separate the conductive features formed by the wiring layers M1 to M5 and the pad layer 120 to maintain the electrical conduction paths required for individual conductive features. The number of wiring layers M1 to M5 can be determined according to different designs or applications. This embodiment uses five layers to illustrate only to provide a possible example and is not intended to limit the number of wiring layers M1 to M5.

[0034] The wiring layers M1 to M5 of the redistribution structure 140 are patterned conductive metal layers, the materials of which include copper, gold, aluminum, nickel, alloys thereof, or combinations thereof. In some embodiments, the wiring layers M1 to M5 can be formed by a damascene process, such as a single damascene process, a dual damascene process, or a similar process. In some embodiments, the interlayer insulator 142 can be formed of a dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or similar oxides; silicon nitride, or similar nitrides.

[0035] The redistribution structure 140 includes multiple bottom-layer wirings 148 in the wiring layer M1 closest to the substrate 110, wherein the bottom-layer wirings 148 are disposed on the substrate 110. The bottom-layer wirings 148 may include alternating ground wirings 148A and power wirings 148B. In some embodiments, each bottom-layer wiring 148 has a substantially wide width W148. In other words, the ground wirings 148A and power wirings 148B have substantially the same width W148. In some embodiments, wiring layers M2 to M5 are used to distribute electrical conduction paths according to the required circuit design, therefore the wiring arrangement design of wiring layers M2 to M5 may differ from that of wiring layer M1.

[0036] like Figure 2As shown, the redistribution structure 140 may include multiple signal wires 144 and multiple shielding wires 146. The multiple signal wires 144 and multiple shielding wires 146 may be the wiring of wiring layers M2 to M5. The signal wires 144 and shielding wires 146 are alternately arranged in the vertical direction (e.g., the Z direction) and the lateral direction (e.g., the Y direction). For example, each of wiring layers M2 to M5 may include multiple signal wires 144 and multiple shielding wires 146. Taking wiring layer M5 as an example, in the Y direction, each signal wire 144 is adjacent to a shielding wire 146, and each shielding wire 146 is adjacent to a signal wire 144. Therefore, the signal wires 144 and shielding wires 146 in wiring layer M5 are arranged alternately along the Y direction, and there is no arrangement where two signal wires 144 are closely adjacent. Wiring layers M2 to M4 also have the same wiring arrangement.

[0037] Furthermore, in the Z-direction, the signal wiring 144 of wiring layer M5 corresponds to the shielding wiring 146 of wiring layer M4, and the shielding wiring 146 of wiring layer M5 corresponds to the signal wiring 144 of wiring layer M4. In some embodiments, in the Z-direction, one signal wiring 144 of wiring layer M5, one shielding wiring 146 of wiring layer M4, one signal wiring 144 of wiring layer M3, and one shielding wiring 146 of wiring layer M2 can be centered and aligned with each other. Similarly, in the Z-direction, one shielding wiring 146 of wiring layer M5, one signal wiring 144 of wiring layer M4, one shielding wiring 146 of wiring layer M3, and one signal wiring 144 of wiring layer M2 can be centered and aligned with each other. In addition, the signal wiring 144 and shielding wiring 146 of wiring layer M2 can be centered and aligned with the bottom wiring 148 of wiring layer M1, respectively. Furthermore, the grounding wiring 148A and power wiring 148B of wiring layer M1 are alternately arranged in the lateral direction (e.g., the Y direction), and in the vertical direction (e.g., the Z direction), each grounding wiring 148A corresponds to one of the signal wirings 144 of wiring layer M2, and each power wiring 148B corresponds to one of the shielding wirings 146 of wiring layer M2. The above arrangement is only for illustrative purposes. In other embodiments, any wiring may be selectively designed as a wiring with bends, and a section may conform to the above arrangement relationship, but it is not limited to the entire wiring conforming to the above relationship.

[0038] exist Figure 2 In this wiring arrangement, each signal wiring 144 in wiring layers M2 to M4 is adjacent to the corresponding shielding wiring 146 in both the vertical direction (Z direction) and the lateral direction (Y direction). Thus, the signal wirings 144 used for signal transmission are not arranged close together, which helps to reduce crosstalk between signal wirings 144 and achieve ideal signal transmission performance.

[0039] In some embodiments, the signal routing 144 generally has a width W144, the shielding routing 146 generally has a width W146, and the width W146 of the shielding routing 146 is greater than the width W144 of the signal routing 144. The coupling capacitance and coupling inductance between the routings can determine the total integrated proximal crosstalk (PSNEXT) of the signal routing 144. When the width W146 of the shielding routing 146 is insufficient, the total integrated proximal crosstalk may not be improved ideally. In some embodiments, the width W146 of the shielding routing 146 can fall within the range of 3.5 times to 4.6 times the width W144 of the signal routing 144. It can also be understood that 3.5×W144 < W146 < 4.6×W144. In some embodiments, the width W144 of the signal routing 144 can be determined according to the process conditions and design requirements. For example, the width W144 can be set to about 0.8 microns in some high-density applications, but not limited thereto. When the substrate structure 100 is applied to a lower-density design, the width W144 may also be greater than 0.8 microns, and when applied to a higher-density design, the width W144 may also be less than 0.8 microns.

[0040] The shielding routing 146 is, for example, a grounded routing, which can be used to shield the coupling between adjacent signal routings 144 and reduce the crosstalk between the signal routings 144. In this embodiment, in addition to the shielding routing 146 being disposed around the signal routing 144, the shielding routing 146 is widened to further improve the shielding ability and achieve high-quality electrical transmission performance. Additionally, in this embodiment, in the vertical direction (Z direction), there is a vertical distance DZ between each signal routing 144 and the adjacent shielding routing 146, and in the lateral direction (Y direction), there is a lateral distance DY between each signal routing 144 and the adjacent shielding routing 146. The vertical distance DZ and the lateral distance DY can be designed to control the load capacitance received by the signal routing 144 and the shielding effect provided by the shielding routing 146 under ideal conditions. Under fixed routing space conditions, if the vertical distance DZ and the lateral distance DY are too large, the width W146 of the shielding routing 146 becomes smaller, and its shielding effect cannot be effectively exerted. If the vertical distance DZ and the lateral distance DY are too small, the shielding routing 146 may impose an excessive load on the signal routing 144. In some embodiments, both the vertical distance DZ and the lateral distance DY can be not less than 0.8 microns. In some embodiments, the lateral distance DY can fall within the range of 1.5 times to 1.8 times the vertical distance DZ. It can also be understood that 1.5×DZ ≦ DY ≦ 1.8×DZ.

[0041] In addition, as Figure 2 shown, the shielding strip 124 of the pad connection layer 120 can be provided corresponding to the shielding routing 146 of the routing layer M5. In some embodiments, referring to Figure 1As can be seen, the extension trajectory of the shielding wiring 146 roughly follows the extension trajectory of the shielding strip 124, that is, it extends between the first grain region 112 and the second grain region 114 and crosses the spacing region 116. Referring again... Figure 2 In some embodiments, each of the shielding strips 124 is centered and aligned with the nearest wiring of the redistribution structure 140. For example, each shielding strip 124 of the pad connection layer 120 may be disposed above one of the shielded wirings 146 of the wiring layer M5, and each shielding strip 124 may be centered and aligned with one of the shielded wirings 146 in the wiring layer M5. In some embodiments, the spacing D124 between the shielding strips 124 may be greater than the width W144 of the signal wiring 144. Furthermore, the spacing P124 of the shielding strips 124 may be approximately equal to twice the wiring spacing P140 of the redistribution structure 140, but is not limited thereto.

[0042] The shielding strip 124 can be connected to the redistribution structure 140 through the through-hole V1, and specifically, it is connected to the nearest shielding wire 146 (i.e., the corresponding shielding wire 146 in the wiring layer M5) through the through-hole V1. In some embodiments, all shielding wires 146 and all shielding strips 124 are grounded. The shielding strip 124 can shield crosstalk between signal wires 144 in the wiring layer M5, so that even though there is no shielding wire 146 directly above the signal wires 144 in the wiring layer M5 (viewed in the Z direction), there will still be no significant crosstalk, thus providing ideal signal transmission performance.

[0043] In some embodiments, the shielding strip 124 has a width W124, and the width W124 of the shielding strip 124 may be greater than the width of all the wirings in the redistribution structure 140. For example, the width W124 of the shielding strip 124 is 1.4 to 1.6 times the width W146 of the nearest shielding wiring 146. Alternatively, it can be understood that 1.4 × W146 ≤ W124 ≤ 1.6 × W146. The widened shielding wiring 146 and shielding strip 124 provide enhanced shielding capabilities to enable the signal wiring 144 to achieve ideal signal transmission performance. Furthermore, the widening of the shielding wiring 146 and shielding strip 124 is configured to avoid placing an excessive load on the signal wiring 144, thereby contributing to achieving ideal signal transmission performance.

[0044] Figure 3 for Figure 1 A schematic cross-sectional view of the substrate structure along line II-II. Figure 3 The components shown are Figure 2 Since they are mostly the same, components marked with the same component symbols in the two figures can be referenced from each other. Figure 3The cross-sectional structure schematically illustrates the connection relationship between the signal pad S130 and the corresponding signal connection pattern S122, and the connection relationship between the reference ground pad G130 and the corresponding reference ground pattern G122 can also have similar characteristics. For example... Figure 3 As shown, the pad connection pattern 122 (signal connection pattern S122) in the pad connection layer 120 is connected to one of the signal wirings 144 through another through-hole V2. Additionally, a pad 130 (signal pad S130) may be disposed on the pad connection pattern 122 (signal connection pattern S122). In some embodiments, a connector 132 may be further provided on the pad 130 (signal pad S130). The connector 132 may be a microbump, and the width W132 of the connector 132 may fall within the range of approximately tens of micrometers to 30 micrometers, but is not limited thereto. Figure 3 The pad connection pattern 122 (signal connection pattern S122) and Figure 2 The shielding strip 124 is on the same layer, namely the pad connection layer 120, and is disposed on the wiring layer M5 of the redistribution structure 140. The connector 132 is connected to the pad connection pattern 122 (signal connection pattern S122) through the pad 130 (signal pad S130). The pad connection pattern 122 and the shielding strip 124 can be formed in the same manufacturing process. In other words, the fabrication of the shielding strip 124 of the pad connection layer 120 is integrated into the inherent manufacturing process of the substrate structure 100, and therefore no additional manufacturing process is required.

[0045] Figure 4 This is a schematic diagram of a semiconductor package according to an embodiment of the present disclosure. Figure 4 The semiconductor package 1000 includes at least a substrate structure 100, a first die 200A, and a second die 200B. Some features of the substrate structure 100 can be found in [reference needed]. Figure 1 and Figure 2 The substrate structure, and Figure 1 and Figure 2 The description can also be incorporated into the semiconductor package 1000 of this embodiment. For example, the substrate structure 100 may include a substrate 110, a multilayer redistribution structure 140, a bonding member 132, and a pad connection layer 120. For the sake of brevity, Figure 4 The multi-layer rewiring structure 140 and the pad connection layer 120 are only schematically shown, and the pad 130 is omitted, but the features of these components can be referred to Figures 1 to 3The relevant description is as follows. In this embodiment, the substrate 110 may have a first grain region 112, a second grain region 114, and a spacer region 116 extending between the first grain region 112 and the second grain region 114. The first grain 200A and the second grain 200B are respectively bonded to the substrate structure 100 in the first grain region 112 and the second grain region 114, and the first grain 200A and the second grain 200B are separated by the spacer region 116. Refer to Figures 1 to 4 The first die 200A can be bonded to the bonding member 132 disposed in the first die region 112, and the second die 200B can be bonded to the bonding member 132 disposed in the second die region 114. The outline of the first die 200A projected onto the substrate 110 in the vertical direction (Z direction) can define the first die region 112, and the outline of the second die 200B projected onto the substrate 110 in the vertical direction (Z direction) can define the second die region 114. The first die 200A and the second die 200B must not overlap, and at least part of the spacer region 116 must be exposed.

[0046] One of the first chip 200A and the second chip 200B can be a logic chip, which can be a Central Processing Unit (CPU) chip, a Graphics Processing Unit (GPU) chip, a Microcontroller Unit (MCU) chip, a Base Band (BB) chip, an Application Processor (AP) chip, etc. The other chip can be a memory chip, which can be a Static Random Access Memory (SRAM) chip, a Dynamic Random Access Memory (DRAM) chip, a Resistive Random Access Memory (RRAM) chip, etc. Alternatively, both the first chip 200A and the second chip 200B can be logic chips.

[0047] The first die 200A and the second die 200B can be signal-connected to each other through conductive features in the substrate structure 100. In some embodiments, the first die 200A and the second die 200B each have an interface circuit disposed therein, for example, the first die 200A has an interface circuit 210A, and the second die 200B has an interface circuit 210B. The interface circuits 210A and 210B may include Glink-3D interface circuits or UCIe interface circuits, but are not limited thereto. The interface circuit 210A can be signal-connected to a pad (not shown) on the surface of the first die 200A, and the pad on the surface of the first die 200A can be connected to a bonding member 132, thereby enabling the interface circuit 210A to be signal-connected to the redistribution structure 140 in the substrate structure 100. Similarly, the interface circuit 210B of the second die 200B can be signal-connected to the redistribution structure 140 in the substrate structure 100 through the corresponding bonding member 132. The signal wiring 144 in the rewiring structure 140 can provide a signal transmission path to enable signal communication between interface circuits 210A and 210B. In other words, the interface circuit 210A of the first die 200A and the interface circuit 210B of the second die 200B achieve signal communication between the die and the die through the rewiring structure 140.

[0048] In this embodiment, the semiconductor package 1000 further includes bonding bumps 300 and a package substrate 400. The bonding bumps 300 are disposed on the side of the substrate 110 opposite to the redistribution structure 140. In some embodiments, the bonding bumps 300 may include C4 bumps, but are not limited thereto. To transmit electrical signals from the redistribution structure 140 of the substrate structure 100 to the bonding bumps 300, the substrate structure 100 may also include a substrate via 150 penetrating the substrate 110, wherein the substrate via 150 may connect the redistribution structure 140 and the bonding bumps 300. The bonding bumps 300 are used to bond the substrate structure 100 to the package substrate 400. The package substrate 400 may include a circuit board or other substrate that may have a circuit layout. In some embodiments, the semiconductor package 1000 is a three-dimensional package structure, such as a chip-on-wafer-on-substrate (CoWoS) package, wherein the substrate structure 100 may be understood, for example, as an interposer or a similar structure, but is not limited thereto.

[0049] As the component density of semiconductor devices continues to increase, the number of signal channels in interface circuits 210A and 210B also increases. Naturally, the corresponding signal wiring 144 will inevitably increase. Within a limited wiring space, crosstalk between signal wirings 144 often leads to suboptimal signal transmission performance. In this embodiment, as... Figures 1 to 3As shown, the redistribution structure 140 provides shielded wiring 146 in wiring layers M2 to M5 corresponding to these signal wirings 144 and provides shielding strips 124 in the pad connection layer 120. The shielded wiring 146 and shielding strips 124 can effectively suppress crosstalk between signal wirings 144, thereby optimizing the signal transmission performance between the first die 200A and the second die 200B.

[0050] The wiring design of the substrate structure 100 can be applied to products with high data transmission rates, such as 4Gbps, 8Gbps, 12Gbps, 16Gbps, and 17.2Gbps. When the substrate structure 100 with shielded wiring 146 and shielding strip 124 is applied to products with high data transmission rates, the resulting eye diagram can achieve a jitter of less than 4ps and an eye width greater than 0.931UI.

[0051] In summary, the substrate structure of this disclosure provides a shielding strip in the pad connection layer and shielding wiring between the signal wiring between the pad connection layer and the substrate. The shielding strip provides shielding between the signal wiring closest to the pad connection layer, and the shielding wiring provides shielding between other signal wiring. Therefore, the substrate structure provides good signal transmission performance, which is beneficial for applications in high-transmission-rate products. The semiconductor package of this disclosure bonds multiple dies on the substrate structure and provides signal wiring for signal communication between dies in the substrate structure, thereby realizing multi-die integrated packaging. In addition, in the semiconductor package of this disclosure, the substrate structure has shielding wiring and shielding strip corresponding to the signal wiring. Therefore, the signal wiring provides good signal transmission performance, thereby meeting the requirements of high transmission rates.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A substrate structure, characterized in that, include: The substrate has a first grain region, a second grain region, and a spacer region extending between the first grain region and the second grain region; A redistribution structure is disposed on the substrate, wherein the redistribution structure includes multiple signal wirings and multiple shielding wirings, the signal wirings and the shielding wirings are alternately arranged in the vertical direction and the lateral direction, and the width of the shielding wirings falls within the range of 3.5 to 4.6 times the width of the signal wirings. as well as A pad connection layer is disposed on the substrate and the redistribution structure is located between the pad connection layer and the substrate, wherein the pad connection layer includes a plurality of pad connection patterns located in the first die region and the second die region.

2. The substrate structure according to claim 1, characterized in that, The pad connection layer also includes multiple shielding strips extending between the first grain region and the second grain region and traversing the interval region.

3. The substrate structure according to claim 2, characterized in that, The width of the shielding strip is 1.4 to 1.6 times the width of the nearest shielding wire.

4. The substrate structure according to claim 2, characterized in that, The shielding strip is connected to the nearest shielding wiring through a through hole.

5. The substrate structure according to claim 2, characterized in that, The substrate structure also includes a reference ground pad disposed on the pad connection layer, wherein the shielding strip and the reference ground pad are physically and electrically connected.

6. The substrate structure according to claim 1, characterized in that, The signal wiring and the shielding wiring are alternately arranged in the vertical direction at a vertical distance, and the signal wiring and the shielding wiring are alternately arranged in the lateral direction at a lateral distance, wherein the lateral distance falls within the range of 1.5 to 1.8 times the vertical distance.

7. The substrate structure according to claim 6, characterized in that, The lateral distance is not less than 0.8 micrometers.

8. The substrate structure according to claim 1, characterized in that, The rewiring structure also includes multiple bottom-layer wirings disposed on the substrate, and the signal wirings and the shielding wirings are located between the bottom-layer wirings and the pad connection layer, wherein the bottom-layer wirings have the same width.

9. The substrate structure according to claim 8, characterized in that, The underlying wiring also includes multiple grounding wires and multiple power wires, wherein the grounding wires and the power wires are alternately arranged in the lateral direction, and each of the grounding wires is arranged in a vertical direction corresponding to one of the signal wires, and each of the power wires is arranged in a vertical direction corresponding to one of the shielding wires.

10. A substrate structure, characterized in that, include: The substrate has a first grain region, a second grain region, and a spacer region extending between the first grain region and the second grain region; A redistribution structure is disposed on the substrate; as well as A pad connection layer is disposed on the substrate and the redistribution structure is located between the pad connection layer and the substrate, wherein the pad connection layer includes a plurality of pad connection patterns located in the first die region and the second die region and a plurality of shielding strips extending between the first die region and the second die region and traversing the spacer region.

11. The substrate structure according to claim 10, characterized in that, The shielding strip is connected to the rewiring structure through a through hole.

12. The substrate structure according to claim 10, characterized in that, The substrate structure also includes a reference ground pad disposed on the pad connection layer, wherein the shielding strip is physically and electrically connected to the reference ground pad.

13. The substrate structure according to claim 10, characterized in that, The width of the shielding strip is greater than the width of all the wiring in the rewiring structure.

14. The substrate structure according to claim 10, characterized in that, The spacing of the shielding strips is approximately twice the spacing of the wiring in the rewiring structure.

15. The substrate structure according to claim 10, characterized in that, The width of each of the shielding strips is 1.4 to 1.6 times the width of the nearest shielding strip of the redistribution structure.

16. The substrate structure according to claim 10, characterized in that, The rewiring structure includes multiple bottom-layer wirings, which are disposed on the substrate and have the same width.

17. The substrate structure according to claim 16, characterized in that, The underlying wiring includes multiple grounding wires and multiple power wires, wherein the grounding wires and the power wires are alternately arranged in the lateral direction.

18. A semiconductor package, characterized in that, include: The substrate structure includes: The substrate has a first grain region, a second grain region, and a spacer region extending between the first grain region and the second grain region; A redistribution structure is disposed on the substrate; and A pad connection layer is disposed on the substrate and the redistribution structure is located between the pad connection layer and the substrate, wherein the pad connection layer includes a plurality of pad connection patterns located in the first die region and the second die region and a plurality of shielding strips extending between the first die region and the second die region and traversing the spacer region. A first grain, bonded to the substrate structure in the first grain region; and A second grain is bonded to the substrate structure in the second grain region, wherein the first grain and the second grain are separated by the spacer region.

19. The semiconductor package according to claim 18, characterized in that, The rewiring structure includes multiple signal wires and multiple shielding wires, which are alternately arranged in the vertical and lateral directions.

20. The semiconductor package according to claim 19, characterized in that, The width of the shielding wiring falls within the range of 3.5 to 4.6 times the width of the signal wiring.

21. The semiconductor package according to claim 19, characterized in that, The width of the shielding strip is 1.4 to 1.6 times the width of the nearest shielding wire in the redistribution structure.

22. The semiconductor package according to claim 19, characterized in that, The shielding strip is connected to the nearest shielding cable in the redistribution structure through a through-hole.

23. The semiconductor package according to claim 19, characterized in that, The substrate structure also includes a reference ground pad disposed on the pad connection layer, wherein the shielding strip is physically and electrically connected to the reference ground pad.

24. The semiconductor package according to claim 19, characterized in that, The signal wiring and the shielding wiring are alternately arranged in the vertical direction at a vertical distance, and the signal wiring and the shielding wiring are alternately arranged in the lateral direction at a lateral distance, wherein the lateral distance falls within the range of 1.5 to 1.8 times the vertical distance.

25. The semiconductor package according to claim 24, characterized in that, The lateral distance is not less than 0.8 micrometers.

26. The semiconductor package according to claim 18, characterized in that, The first die and the second die each have an interface circuit disposed therein, and the interface circuit of the first die and the interface circuit of the second die are signal-connected through the rewiring structure.

27. The semiconductor package according to claim 18, characterized in that, The semiconductor package further includes a packaging substrate, wherein the side of the substrate structure opposite to the redistribution structure is bonded to the packaging substrate.

28. The semiconductor package according to claim 18, characterized in that, The rewiring structure also includes multiple signal wirings, multiple shielding wirings, and multiple bottom layer wirings. The bottom layer wirings are disposed on the substrate, and the signal wirings and the shielding wirings are located between the bottom layer wirings and the pad connection layer, wherein the bottom layer wirings have the same width.

29. The semiconductor package according to claim 28, characterized in that, The underlying wiring includes multiple grounding wires and multiple power wires, wherein the grounding wires and the power wires are alternately arranged in the lateral direction, each grounding wire is arranged in a vertical direction corresponding to one of the signal wires, and each power wire is arranged in a vertical direction corresponding to one of the shielding wires.

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