Hardware and method for enhanced wireless receiver output power

Abstract

Embodiments of the present disclosure relate to hardware and methods for enhanced wireless receiver output power. A power transfer system includes at least one wireless power transfer circuit. The first wireless power receiving circuit includes a first circuit that compares a reference voltage with a feedback voltage representing an output voltage generated from received power and delivered to an output node, and adjusts a first control terminal of a device supplying a first rectified voltage until the feedback voltage and the reference voltage are equal. The second wireless power receiving circuit includes a second circuit that modifies a control terminal of a device that sources a second rectified current to the output node based on a comparison of the reference current and a current representative of the second rectified current generated from the received power. The control circuitry adjusts the reference current until a first rectified voltage generated by the first wireless power receiving circuit and a second rectified voltage generated by the second wireless power receiving circuit are equal.

Description

[0001] This application is a divisional application of the invention patent application with application number 202110642068.X, application date June 9, 2021, and invention title "Hardware and Method for Enhancing Output Power of Wireless Receiver". Technical Field

[0002] This disclosure relates to the field of wireless power transmission, and more particularly to hardware, operating techniques and methods for increasing the amount of power that can be transmitted via wireless power transmission within a given time unit. Background Technology

[0003] Portable electronic devices such as smartphones, smartwatches, audio output devices (earbuds, headphones), and wearable devices rely on batteries for power, rather than from wired power transmitted to them through wired transmission lines and power distribution systems. Batteries used in such devices are typically rechargeable, and therefore require a method for charging such batteries.

[0004] Most portable electronic devices include a charging port, typically compliant with Micro USB or USB-C standards, into which a power cord can be plugged to charge its battery. However, such charging ports may limit the device's water resistance and make it susceptible to damage from repeated use. Furthermore, some smaller portable electronic devices (e.g., earbuds and smartwatches) lack the space available for a charging port. Additionally, some users may find it inconvenient to plug a power cord into the charging port of an electronic device to charge its battery.

[0005] Therefore, wireless power transfer has been developed to address these issues. Wireless power transfer systems utilize a coil transmitter (primary) and a coil receiver (secondary). The coil transmitter is powered by electricity from a source (usually a wired connection, but in some cases a battery). The coil transmitter generates a time-varying electric field, which induces a current in the coil receiver. The receiver hardware extracts the power transmitted to the coil receiver and supplies it to a load, such as a battery in an electronic device that integrates both the coil receiver and the receiver hardware.

[0006] Standards have been established for managing hardware and how transmitters and receivers communicate to allow for easy wireless charging in electronic devices. However, existing wireless transmission standards can only deliver a limited amount of power, which may be insufficient or undesirable in some cases where an increase in power per unit time is desired. Therefore, despite the existence of well-established and functioning wireless transmission standards, further development is needed in this area. Summary of the Invention

[0007] This document discloses a wireless power transmission system comprising at least one wireless power transmission circuit, a first wireless power receiving circuit, a second wireless power receiving circuit, and a control circuit system. Note that the first wireless power receiving circuit is the master, while the second wireless power receiving circuit is the slave, and there can be multiple slaves. However, for the sake of brevity, only one second wireless power receiving circuit (slave) is described in this abstract section.

[0008] The first wireless power receiving circuit has a first amplifier circuit configured to compare a reference voltage with a feedback voltage representing an output node voltage generated based on power received from at least one wireless power transmitting circuit, and to adjust a first transistor supplying a first rectified voltage until the feedback voltage equals the reference voltage, wherein a first rectified current is supplied to the output node.

[0009] The second wireless power receiving circuit has a second amplifier circuit configured to modify the gate bias of a second transistor that supplies the second rectified current based on a comparison of a reference current with a current representing a second rectified current generated according to power received from at least one wireless power transmission circuit, thereby modifying the second rectified current, wherein the second rectified current is supplied to an output node.

[0010] The control circuit system is configured to adjust the reference current until the first rectified voltage generated by the first wireless power receiving circuit and the second rectified voltage generated by the second wireless power receiving circuit are equal.

[0011] The first wireless power receiving circuit may further include a first capacitor, through which a first rectified voltage is formed, and the second wireless power receiving circuit may further include a second capacitor, through which a second rectified voltage is formed.

[0012] The first amplifier circuit may further include a first n-channel transistor having a drain coupled to receive a first rectified voltage, a source coupled to an output node, and a gate. The first amplifier circuit may also include a voltage divider coupled between the output node and ground, and may further include a first amplifier having a non-inverting terminal coupled to a reference voltage, an inverting terminal coupled to a tap of the voltage divider to receive a feedback voltage, and an output coupled to the gate of the first n-channel transistor.

[0013] The second amplifier circuit may include a second n-channel transistor having a drain coupled to a second rectified voltage, a source coupled to an output node, and a gate. The second amplifier circuit may also include a second amplifier having a non-inverting terminal coupled to receive a current representing the second rectified current, an inverting terminal coupled to receive a reference current, and an output coupled to the gate of the second n-channel transistor.

[0014] When the control circuit system is unable to adjust the reference current, the equalizer switch controlled by the control circuit system can selectively couple the first rectified voltage to the second rectified voltage until the feedback voltage equals the reference voltage and the current representing the second rectified current equals the reference current.

[0015] The first amplifier can be a low-dropout amplifier.

[0016] The control circuit system can adjust the reference current until the first rectified voltage and the second rectified voltage are equal by: requesting at least one power transmission circuit to transmit a portion of its transmittable power to the first wireless power receiving circuit; and adjusting the reference current until a first equilibrium point is reached where the first rectified voltage and the second rectified voltage are equal. The reference current can be adjusted until the first equilibrium point by: requesting at least one power transmission circuit to increase its transmittable power to the first wireless power receiving circuit if the first rectified voltage is greater than the output voltage at the output node and if the output voltage is greater than the second rectified voltage; increasing the magnitude of the reference current if the second rectified voltage is greater than the first rectified voltage and the first rectified voltage is greater than the output voltage; and decreasing the magnitude of the reference current if the first rectified voltage is greater than the second rectified voltage and the second rectified voltage is greater than the output voltage.

[0017] The control circuit system can further adjust the reference current until the first rectified voltage and the second rectified voltage are equal by: requesting at least one power transmission circuit to transmit a portion of the power it is capable of transmitting to the second wireless power receiving circuit; and adjusting the reference current until a second equilibrium point is reached where the first rectified voltage and the second rectified voltage are equal.

[0018] The reference current can be adjusted until a second equilibrium point is reached as follows: if the second rectified voltage is greater than the first rectified voltage and the first rectified voltage is greater than the output voltage, the magnitude of the reference current is increased; and if the first rectified voltage is greater than the second rectified voltage and the second rectified voltage is greater than the output voltage, the magnitude of the reference current is decreased.

[0019] The control circuit system can further adjust the reference current until the first rectified voltage and the second rectified voltage are equal by: requesting at least one power transmission circuit to transmit all the power it is capable of transmitting to the first and second wireless power receiving circuits; and adjusting the reference current until a third equilibrium point is reached where the first and second rectified voltages are equal. The reference current can be adjusted until the third equilibrium point is reached by: increasing the magnitude of the reference current if the second rectified voltage is greater than the first rectified voltage and the first rectified voltage is greater than the output voltage; and decreasing the magnitude of the reference current if the first rectified voltage is greater than the second rectified voltage and the second rectified voltage is greater than the output voltage. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the first wireless power transmission system disclosed in this paper, in which two transmitters transmit power to two receivers operating in parallel.

[0021] Figure 2A It is shown Figure 1 A flowchart of the operation of a wireless power transmission system;

[0022] Figure 2B It is shown Figure 2A A flowchart detailing step 115;

[0023] Figure 2C It is shown Figure 2A A flowchart detailing step 124;

[0024] Figure 2D This shows the execution Figure 2A A flowchart detailing the technology of step 102;

[0025] Figure 2E This shows the execution Figure 2A A flowchart detailing another technique in step 102;

[0026] Figure 3 This is a schematic diagram of the second wireless power transmission system disclosed in this paper, in which a single transmitter transmits power to two receivers operating in parallel. Detailed Implementation

[0027] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0028] Now for reference Figure 1An embodiment of the wireless transmission system 1 is described, wherein a first transmitter 5 and a second transmitter 7 wirelessly transmit power to a first receiver 6 and a second receiver 8 operating in parallel, respectively. First, the hardware itself will be described, followed by a description of its operation.

[0029] A. Hardware of Wireless Power Transmission System 1

[0030] Transmitter 5 includes an AC power supply 14 connected to the primary coil (schematically represented by a capacitor Cp1 connected in series with an inductor Lp1 and a resistor Rp1).

[0031] Receiver 6 includes a secondary coil (schematically represented by a capacitor Cs1 connected in series with an inductor Ls1 and a resistor Rs1) connected to rectifier 11, which rectifies the AC current Is output from the secondary coil to produce a DC output current I1. The input of rectifier 11 is connected to the secondary coil, and the output of rectifier 11 is coupled between node N1 and ground.

[0032] A current sensor 16 is coupled between nodes N1 and N2 and configured to sense the current I1 output by rectifier 11. The current sensor 16 includes a resistor R1 coupled between nodes N1 and N2, and an amplifier 12. Amplifier 12 has a non-inverting terminal coupled to node N1 and an inverting terminal coupled to node N2. The output of amplifier 12 is a first sensed current I1_s, which represents the current I1 output by rectifier 11. The output of amplifier 12 is selectively connected to the inverting terminal of amplifier 13 via a switch S2 controlled by a mode signal Mode.

[0033] The drain of the n-channel MOSFET transistor T1 is connected to node N2, its source is connected to node N3, and its gate is connected to be biased by the output of amplifier 13. The non-inverting terminal of amplifier 13 is selectively connected to either the reference voltage Vref or the reference current Iref via a switch S4 controlled by the mode signal Mode, and the inverting terminal of amplifier 13 is selectively connected to node N4 via a switch S3 controlled by the Mode signal Mode.

[0034] Resistor R2 is connected between nodes N3 and N4, and resistor R3 is connected between node N4 and ground. Load 15 (e.g., the battery of the electronic device in which receivers 6 and 8 are connected in parallel) is connected between node N3 and ground. Capacitor C1 is connected between node N2 and ground, and a first rectified voltage Vrect1 is formed across capacitor C1.

[0035] Note that switches S2, S3, and S4 in receiver 6 all operate based on the mode signal Mode, but in different ways. When the mode signal Mode indicates that receiver 6 will operate based on the output voltage control mode (hereinafter referred to as voltage feedback), the mode signal Mode is used to open switch S2, close switch S3 to receive the feedback voltage Vfbk1 from node N4, and set switch S4 to connect the non-inverting terminal of amplifier 13 to the reference voltage Vref. On the other hand, when the mode signal Mode indicates that receiver 6 will operate based on the output current control mode (hereinafter referred to as current feedback), the mode signal Mode is used to close switch S2, open switch S3, and set switch S4 to connect the non-inverting terminal of amplifier 13 to the reference current Iref.

[0036] The transmitter 7 also includes an AC power supply 24 connected to the primary coil (schematically represented by a capacitor Cp2 connected in series with an inductor Lp2 and a resistor Rp2).

[0037] Receiver 8 also includes a secondary coil (schematically represented by a capacitor Cs2 connected in series with an inductor Ls2 and a resistor Rs2) connected to rectifier 21, which rectifies the AC current Is output from the secondary coil to produce a DC output current I2. The input of rectifier 21 is connected to the secondary coil, and the output of rectifier 21 is coupled between node N5 and ground.

[0038] A current sensor 17 is coupled between nodes N5 and N6 and configured to sense the current I2 output by rectifier 21. The current sensor 17 includes a resistor R4 coupled between nodes N5 and N6, and an amplifier 22. Amplifier 22 has a non-inverting terminal coupled to node N5 and an inverting terminal coupled to node N6. The output of amplifier 22 is a second sensed current I2_s, which represents the current I2 output by rectifier 21. The output of amplifier 22 is selectively connected to the inverting terminal of amplifier 23 via a switch S7 controlled by a mode signal Mode.

[0039] The drain of the n-channel transistor T2 is connected to node N6, its source is connected to node N3, and its gate is connected to be biased by the output of amplifier 23. Note that any three-terminal device or combination of devices can be used in addition to the n-channel transistor T2.

[0040] Resistor R5 is connected between nodes N3 and N8, and resistor R6 is connected between node N8 and ground.

[0041] The non-inverting terminal of amplifier 23 is selectively connected to the reference current Iref via switch S9 controlled by the mode signal Mode, and the inverting terminal of amplifier 23 is connected via switch S7 controlled by the mode signal Mode to selectively receive current I2_s from the output of amplifier 22, or is selectively connected via switch S8 controlled by the mode signal Mode to receive feedback voltage Vfbk2 from node N8.

[0042] Capacitor C2 is connected between node N6 and ground, and a second rectified voltage Vrect2 is formed across capacitor C2.

[0043] Note that switches S7, S8, and S9 in receiver 8 all operate based on the mode signal Mode, but in different ways. When the mode signal Mode indicates that receiver 8 will operate based on voltage feedback, the mode signal Mode is used to open switch S7, close switch S8, and set switch S9 to connect the non-inverting terminal of amplifier 23 to the reference voltage Vref. On the other hand, when the mode signal Mode indicates that receiver 8 will operate based on current feedback, the mode signal Mode is used to close switch S7, open switch S8, and set switch S9 to connect the non-inverting terminal of amplifier 23 to the reference current Iref.

[0044] Those skilled in the art will note that in voltage feedback, elements 13, T1, R2, R3, S2, S3, S4 (and their corresponding counterparts 23, T2, R5, R6, S7, S8, S9) form a conventional voltage regulator configuration represented herein by an n-channel MOSFET. However, this functionality can also be implemented using a conventional p-channel LDO structure. The drain of the p-channel transistor T1 is connected to node N3, its source is connected to node N2, and its gate is connected to be biased by the output of amplifier 13, whose positive and negative inputs are swapped. The p-channel transistor structure will also be adapted for current feedback functionality. And more broadly, any receiver configured to switch between voltage control mode (conceptually a voltage source) and output current control mode (conceptually a current source) can be used to implement the disclosure herein.

[0045] Switch S1, operated by control signal Eq, is connected between nodes N2 and N6. When switch S1 is closed, Vrect1 and Vrect2 are equal.

[0046] The control unit 31 receives a reference voltage Vref, an output voltage Vout, a first rectified voltage Vrect1, a second rectified voltage Vrect2, a first rectified current I1_s, and a second rectified current I2_s, and thereby generates a reference current Iref and a control signal Eq for the switch S1.

[0047] The control unit 32 receives a reference voltage Vref, a first rectified voltage Vrect1, a second rectified voltage Vrect2, a first rectified current I1_s, and a second rectified current I2_s, and thereby generates a reference current Iref and a control signal Eq for the switch S1.

[0048] Note that only one control unit 31 or 32 may exist, or both control units 31 and 32 may exist. When both control units 31 and 32 exist, each is associated with one of the receivers 6 or 8. As explained below, one receiver 6 or 8 operates as a master, while the other receiver 8 or 6 operates as a slave. When both control units 31 and 32 exist, the control unit 31 or 32 associated with the receiver 6 or 8 designated as the master is operational, while the other control unit is idle.

[0049] The master control unit (not idle) is responsible for directly controlling the Vref of the master and the Iref of the slave and requires the power of both transmitters to increase / decrease.

[0050] In the case of in-band communication, even though the control unit is idle as a slave, the master control unit can still request to wake it up and communicate with the associated transmitter (e.g., ASK modulation in the Qi standard) to adjust the power, simply because the master control unit cannot access the physical communication link of the transmitter. This may not apply to out-of-band communication.

[0051] B. Operation of Wireless Power Transmission System 1

[0052] 1. Operation Overview

[0053] In operation, one of receivers, 6 or 8, operates as the "master" in the voltage-mode feedback loop, while the other receiver operates as the "slave" in the current-mode feedback loop. For example... Figure 1 As shown, receiver 6 operates as a master, while receiver 8 operates as a slave. Specifically, receiver 6 (operating as a master) sets and controls the rectified output voltage Vout (conceptually because a voltage source would do this), while receiver 8 (operating as a slave) increases the power delivered at that output voltage Vout (conceptually because a current source would do this).

[0054] More specifically, amplifier 13, transistor T1, and resistors R2 and R3 form a voltage regulator. Amplifier 13 compares the reference voltage Vref with the feedback voltage Vfbk1 at node N4 and modulates the bias applied to the gate of n-channel transistor T1 such that the feedback voltage Vfbk1 equals Vref. This has the effect of modulating the current I1 supplied to the load by transistor T1 to maintain the output voltage Vout at a set stable voltage.

[0055] By adding current I2 to the output current I1 of receiver 6 without changing the voltage Vout, receiver 8 operates as a "slave" in the current-mode loop. The parameters of the system are related by the following equation:

[0056] Vout=Vref and I1=Vout / Rload-Iref.

[0057] Control unit 31 monitors Vrect1 and Vrect2 and adjusts Iref such that when amplifier 23 modulates the bias voltage on the gate of n-channel transistor T2 to maintain current I2_s equal to reference current Iref, the second rectified voltage Vrect2 matches the first rectified voltage Vrect1. When Vrect1 and Vrect2 are matched, I1 and I2 are controlled by I2 = Iref and I1 = Vout / Rload - Iref, where

[0058] k1 (and corresponding k2) represent the power transfer factor from TX1 to RX1 (and correspondingly from TX2 to RX2), and α represents the ratio between the amount of power P2 supplied by TX2 and the amount of power P1 supplied by TX1, such that P2 = α.P0 and P1 = P0. For the system to reach its equilibrium point (Vrect1 = Vrect2), the total input power P1 + P2 = (1 + α)P0 should be sufficient so that Vout can be delivered at Vref. 2 / Rload simultaneously achieves Vref. When the input power is insufficient, the system adjusts the parameters Iref and Vref to match their relationship. It is important to emphasize that with k1 = k2 and α = 1, Iref = 2 x I1 = 2 x I2 = Vout / (2.R1).

[0059] Each of receivers 6 and 8 contributes to supplying power to load 15 at the output voltage Vout, thereby effectively increasing the power supplied to load 15 when only one of receivers 6 or 8 is operational.

[0060] If it is not possible, under given operating conditions (e.g., but not limited to when the incoming power is too low), to adequately adjust Iref for a given Vref such that Vrect2 is substantially equal to Vrect1, then control unit 31 may assert the equalization signal Eq and close switch S1 to short-circuit nodes N2 and N6, thereby causing Vout to move away from the target and some current to flow from Vrect1 to Vrect2 through S1 (and vice versa).

[0061] The current flowing from one of the two Vrect voltages (Vrect1, Vrect2) to the other can be read by a current sensor, and these two currents, along with Vout information (captured by Vout voltage measurement), can be used by the system to determine which parameters to use for stable operation. Ultimately, stable operation is controlled by the following formula:

[0062]

[0063] When P0, Iref, and Vref are set correctly, the current flowing through switch S1 will be zero, and the system will be able to de-equip.

[0064] If receiver 8 is reconfigured as the master, the operations performed by receiver 6 will be performed by receiver 8; conversely, if receiver 6 is reconfigured as the slave, the operations performed by receiver 8 will be performed by receiver 6.

[0065] 2. Detailed Operation Description

[0066] Now refer to another source Figure 2A-2B The flowchart below describes more details of the operation of the wireless power transmission system 1. Figure 2A-2B One potential operating technique for the wireless power transfer system 1 is shown; it should be understood that other operating techniques may also be used. To initiate wireless power transfer, receivers 6 and 8 are positioned to receive power from transmitters 5 and 7 (box 101). For example, if receivers 6 and 8 are inside a smartphone and transmitters 5 and 7 are inside a wireless charging pad, the smartphone would be placed on the wireless charging pad.

[0067] Then, perform the master / slave assignment operation (box 102). Figure 1 In the example shown, receiver 6 is configured as the master, and receiver 8 is configured as the slave. Details regarding this master / slave assignment (box 102) will be given below.

[0068] Next, transmitters 5 and 7 ping receivers 6 and 8 (box 103), causing receivers 6 and 8 to wake up. Control unit 31 sets the reference current Iref to its initial value, and the hardware within the electronics containing system 1 sets the reference voltage Vref to its initial value (box 104). Then, controller 31 sends a power request to transmitter 5 via receiver 6 using in-band or out-of-band data communication, and load 15 is connected to node N3 (box 105).

[0069] Subsequently, a first feedback loop process (block 106) is executed to find a first equilibrium point where the output voltage Vout is approximately equal to the reference voltage Vref, the current I2 is approximately equal to the reference current Iref (which is set to approximately zero), the current I1 is approximately equal to the output voltage Vout divided by the impedance of the load 15, the power transmitted from the second transmitter 7 to the second receiver 8 is approximately equal to Vout * I2, the power transmitted from the first transmitter 5 to the first receiver 6 is approximately equal to Vout * I1, and the current flowing into the load is equal to I1 + I2, with I1 providing most of the load current and I2 remaining approximately zero. The goal of the first feedback loop process is to make transmitter 5 achieve an output voltage of Vout = Vref and deliver approximately 50% of its deliverable power to receiver 6, while transmitter 7 delivers a small amount of power to bias receiver 8, and Vrect2 is effectively leveled with Vrect1. In other words, when exiting loop 106, receiver 8 receives only enough power to be energized and supplied without contributing to the load current, while receiver 6 does indeed provide 50% of its deliverable power to the load.

[0070] The first feedback loop begins with controller 31 reading the rectified voltages Vrect1 and Vrect2, and reading the output voltage Vout. If Vrect1 is greater than Vout and Vout is greater than Vrect2, considering that increasing Vrect2 as the incoming power to receiver 8 will at some point exceed the receiver's demand, which is set to a low Iref value, controller 31 requests power transfer from transmitter 7 to receiver 8 by transmitting a request from receiver 8 to transmitter 7 (box 108). After the power to transmitter 7 increases, the system will proceed to box 112 or even box 110 when the first feedback loop restarts. On the other hand, if Vrect2 is greater than Vrect1 and Vrect1 is greater than Vout (box 110), controller 31 increases Iref to change the operation of amplifier 23, causing the n-channel transistor T2 to increase by I2, resulting in a decrease in Vrect2 (box 111), and the feedback loop restarts. Conversely, if Vrect1 is greater than Vrect2 and Vrect2 is greater than Vout (box 112), controller 31 decreases Iref to change the operation of amplifier 23, causing n-channel transistor T2 to decrease I2, resulting in an increase in Vrect2 (box 113), and the first feedback loop restarts. Once Vrect1 equals Vrect2 and is greater than Vout (box 109), the first equilibrium point is reached and the first feedback loop process is complete (box 114).

[0071] After reaching the first equilibrium point, controller 31 (as the master) requests additional power to be transferred from transmitter 7 to receiver 8. In the case of in-band communication, controller 31 may not be able to control the hardware communication channel of its associated transmitter 6 to receiver 8. Therefore, controller 31 may instruct controller 32 to wake up and do so. Controller 31 accordingly ramps up the reference current Iref (box 115) to increase the power delivered to load 15. This ramp (box 115) will be described in more detail below. After the ramp, the second feedback loop process begins (box 116).

[0072] A second feedback loop is executed to find a second equilibrium point where the output voltage Vout is approximately equal to the reference voltage Vref, the current I2 is approximately equal to the reference current Iref, and the current I1 is approximately equal to the output voltage Vout divided by the load impedance Zload, where the current I2 is subtracted from the result. The power transmitted from the second transmitter 7 to the second receiver 8 is approximately equal to Vout*I2, and the power transmitted from the first transmitter 5 to the first receiver 6 is approximately equal to Vout*I1 (box 122). The goal of the second feedback loop process is for transmitters 5 and 7 to deliver approximately 50% of their respective deliverable power to receivers 6 and 8.

[0073] The second feedback loop begins when controller 31 reads the rectified voltages Vrect1 and Vrect2, and reads the output voltage Vout. If Vrect2 is greater than Vrect1 and Vrect1 is greater than Vout (box 117), controller 31 increases Iref to change the operation of amplifier 23, causing n-channel transistor T2 to increase I2, resulting in a decrease in Vrect2 (box 118), and the second feedback loop restarts. Conversely, if Vrect1 is greater than Vrect2 and Vrect2 is greater than Vout (box 120), controller 31 decreases Iref to change the operation of amplifier 23, causing n-channel transistor T2 to decrease I2, resulting in an increase in Vrect2 (box 121), and the second feedback loop restarts. Once Vrect1 equals Vrect2 and is greater than Vout (box 119), the second equilibrium point has been reached and the second feedback loop process is complete (box 122).

[0074] After reaching the second equilibrium point, controller 31 evaluates values ​​k1 and k2, where k1 is calculated as the power delivered to receiver 6 divided by the power transmitted by transmitter 5, and k2 is calculated as the power delivered to receiver 8 divided by the power transmitted by transmitter 7 (box 123). These values ​​of k1 and k2 can be stored and used in step 102 (the next time system 1 is used) to determine the master / slave assignment—receiver 6 or 8 with the higher k value can be set as the master in step 102.

[0075] Subsequently, controller 31 can instruct controller 32 to request additional power to be transmitted from transmitter 7 to receiver 8. In the case of out-of-band communication, it can also send a power request directly to either of the two transmitters. Controller 31 accordingly ramps up the reference current Iref (box 124). This ramp will be described in detail below (box 124), and this ramp is used to enable transmitters 5 and 7 to transmit 100% of their transmittable power to receivers 6 and 8. After the ramp, a third equilibrium point is reached, at which the output voltage Vout is approximately equal to the reference voltage Vref, the current I2 is approximately equal to the reference current Iref, and the current I1 is approximately equal to the output voltage Vout divided by the load impedance Zload, where the current I2 is subtracted from the result. The power transmitted from the second transmitter 7 to the second receiver 8 is approximately equal to Vout*I2, and the power transmitted from the first transmitter 5 to the first receiver 6 is approximately equal to Vout*I1 (box 125). Thereafter, each of transmitters 5 and 7 will deliver 100% of its transmittable power to receivers 6 and 8 without further adjustment. Power transfer continues until the battery in the electronic device is fully charged, or until the receivers 6 and 8 are no longer near the transmitters 5 and 7, for example, by removing the electronic device from the charging pad.

[0076] It should be understood that in some cases, currents I1 and I2 may not be balanced, so transmitters 5 and 7 may not each reach 100% of their potential power output, and receivers 6 and 8 may not each output 100% of their potential power to load 115. However, the aforementioned feedback loop will still serve to balance the rectified voltages Vrect1 and Vrect2, thereby allowing each transmitter 5 and 7 to provide different amounts of power.

[0077] 3. Detailed description of step 115

[0078] Step 115 involves three events that occur simultaneously. The load demand is adjusted to a higher value, the transmitter provides additional required power, and the control unit adjusts Iref to help ensure a smooth transition. It involves three separate hardware and time constant terms, and without proper synchronization between demand, supply, and balancing, Vrect may increase or decrease excessively. Step 115 divides this process into two phases. In the first case, power demand and Iref adjustment (supply and balancing) are performed while the virtual load is connected (steps 115a, 115b, 115c), which now allows for simultaneous processing of two hardware components (i.e., the transmitter and the receiver) and makes sequencing easier to manage, as the virtual load is part of the receiver as a device issuing instructions to the transmitter. Once the system stabilizes in the first case, in the second case (step 115d), the virtual load is disconnected and the actual load demand is set, which allows for processing of both hardware components (i.e., the receiver and its load, which could be the host, for example, in the case of a battery charger) once again.

[0079] Now refer to another source Figure 2B Further description involves the controller 31 sending a power request (box 115) to the transmitter 7, which transmits 50% of the power it is capable of delivering, to the receiver 8. First, a dummy load is connected to the receiver 8, and the controller 31 increases the reference current Iref to match the current flowing through the dummy load (box 115a).

[0080] Then, controller 31 requests (or instructs controller 32 to do so in the case of in-band communication) the second transmitter 7 to deliver additional power to the second receiver 8. Specifically, controller 31 requests the second transmitter to deliver up to 50% of the power it is capable of delivering to receiver 8 (box 115b). Controller 31 then reads the rectified voltages Vrect1 and Vrect2, and the output voltage Vout (box 115c). If Vrect1 is greater than Vrect2 (at box 115c-1, this occurs when controller 31 requests less than 50% of the power from the second transmitter 7), controller 31 again requests additional power from the second transmitter 7 (box 115b). Once Vrect1 equals Vrect2 and is greater than Vout (box 115c-2), controller 31 disconnects the dummy load after ensuring that the actual load requests the same amount of power (e.g., via I2C to the receiver hosting the transaction), causing load 15 to actually request additional current (box 115d).

[0081] 4. Detailed description of step 124

[0082] Now refer to another source Figure 2CThe power request from controller 31 to transmitters 5 and 7 to increase the power they deliver to receivers 6 and 8 is described (box 124). First, as described above, controller 31 requests transmitters 5 and 7 (directly via out-of-band communication or via controller 32) to increase the power they deliver to receivers 6 and 8 by 100%, so that they are delivering the maximum power they can provide (box 124a). Therefore, the power delivered by transmitter 5 increases by 100%, the power delivered by transmitter 7 increases by 100%, and the current I2 increases by 100% accordingly (box 124b). Afterward, the third feedback loop process is executed (box 124c).

[0083] A third feedback loop is executed to find a third equilibrium point where the output voltage Vout is approximately equal to the reference voltage Vref, the current I2 is approximately equal to the reference current Iref, and the current I1 is approximately equal to the output voltage Vout divided by the load impedance Zload, with the current I2 subtracted from the result. The power transmitted from the second transmitter 7 to the second receiver 8 is approximately equal to Vout*I2, and the power transmitted from the first transmitter 5 to the first receiver 6 is approximately equal to Vout*I1 (box 124c). The goal of the third feedback loop process is for transmitters 5 and 7 to deliver 100% of their capable power to receivers 6 and 8, respectively.

[0084] The third feedback loop begins when controller 31 reads the rectified voltages Vrect1 and Vrect2, and reads the output voltage Vout. If Vrect2 is greater than Vrect1 and Vrect1 is greater than Vout (box 124c-1), controller 31 increases Iref to change the operation of amplifier 23, causing n-channel transistor T2 to increase I2, resulting in a decrease in Vrect2 (box 124c-2), and the third feedback loop restarts. Conversely, if Vrect1 is greater than Vrect2 and Vrect2 is greater than Vout (box 124c-3), controller 31 decreases Iref to change the operation of amplifier 23, causing n-channel transistor T2 to decrease I2, resulting in an increase in Vrect2 (box 124c-4), and the third feedback loop restarts. Once Vrect1 equals Vrect2 and is greater than Vout (box 125c-5), the third equilibrium point has been reached and the third feedback loop process is complete (box 133).

[0085] 5. Detailed description of step 102

[0086] Now refer to another source Figure 2DThe master / slave assignment operation is described in detail (box 102). Initially, transmitters 5 and 7 ping receivers 6 and 8 (box 102a), and receivers 6 and 8 wake up sequentially and identify themselves to controller 31 (box 102b). Initially, the first receiver 5 starts as the master, with the reference voltage Vref set to the initial startup value, and the second receiver 7 starts as the slave, with the reference current Iref set to the initial startup value. When load 15 is not yet connected to node N3 and the controller reads the rectified voltage Vrect1 (box 102c) and stores the value of Vrect1, controller 31 requests power transfer from transmitter 5 to receiver 6. When receiver 6 is set as the master, it has the following... Figure 1 The electrical components and connections are shown. When receiver 8 is configured as a slave, it has the following characteristics: Figure 1 The electrical components and connections are shown.

[0087] Next, switch receiver 8 to master and receiver 6 to slave, then turn off receivers 6 and 8 (box 102d). Note here that by setting receiver 8 as master, receiver 8 has the same characteristics as... Figure 1 The receiver 6 shown has the same electrical components and connections, and by setting the receiver 6 as a slave, the receiver 6 has the same... Figure 1 The receiver 8 shown has the same electrical components and connections.

[0088] Now, transmitters 5 and 7 ping receivers 6 and 8 again (box 102e). Vref and Iref are reinitialized to their initial startup values. Load 15 is still not connected to node N3. Controller 31 requests power transfer from transmitter 7 to receiver 8, and controller 31 reads the rectified voltage Vrect2 (box 102f) and stores the value of Vrect2. Finally, controller 31 determines which receiver 6 or 8 will be the master and which receiver will be the slave based on whether Vrect1 or Vrect2 is higher (box 102g). Note that the receiver is turned on and off as the master / slave evaluation proceeds. Therefore, in order to be able to track master / slave assignments, the receiver should have embedded NVM capabilities or use host memory capabilities to store and retrieve information.

[0089] Now refer to another source Figure 2E The alternative techniques used for master / slave assignment operations (box 102) are described in detail. Initially, transmitters 5 and 7 ping receivers 6 and 8 (box 102a'), and receivers 6 and 8 wake up sequentially and identify themselves to controller 31 (box 102b'). Here, receivers 6 and 8 are initially both started in a slave configuration (e.g., both have...). Figure 1(The receiver 8 shown has the same electrical components and connections), load 15 is not connected to node N3, and controller 31 requests power transfer from transmitters 5 and 7 to receivers 6 and 8 while reading Vrect1 and Vrect2 and storing their values ​​(box 102c').

[0090] Subsequently, receiver 8 switches to master and receiver 7 switches to slave. Controller 31, while reading Vrect1 and storing its value, requests power transfer from transmitters 5 and 7 to receivers 6 and 8 (box 102d'). Receivers 6 and 8 then shut down. Controller 31 then determines at box 102c' which receiver 6 or 8 will be the master and which will be the slave based on whether Vrect1 or Vrect2 is higher (box 102e') and whether Vrect2 from box 102c' is higher than Vrect1 from box 102d'.

[0091] C. Replacement hardware, wireless power transmission system 1'

[0092] Now for reference Figure 3 A second embodiment of the wireless transmission system 1' is described, wherein a single transmitter 2 wirelessly transmits power to a first receiver 6 and a second receiver 8 operating in parallel. The transmitter 2 includes an AC power supply 44 connected to a primary coil (schematically represented by a capacitor Cp connected in series with an inductor Lp and a resistor Rp).

[0093] Receivers 6 and 8 are as described above.

[0094] D. Operation of Wireless Power Transmission System 1'

[0095] The operation of the wireless power transmission system 1' is the same as that of the wireless power transmission system 1 described above, except that the transmitter 2 is turned on when either the transmitter 5 or 7 is turned on and is turned off when both the transmitter 5 and 7 are turned off.

[0096] E. Other alternative hardware configurations

[0097] While the pairing of one transmitter with two receivers and two transmitters with two receivers has been shown, it should be understood that other configurations are possible. For example, there could be three or more receivers, with one receiver acting as the master (and performing the functions described above), and two or more other receivers acting as slaves (and performing the functions described above).

[0098] While this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure disclosed herein. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. A method for wireless transmission power, the method comprising: This causes at least one power transmission circuit to transmit a portion of the power that the at least one power transmission circuit is capable of transmitting to the main wireless power receiving circuit; as well as The operation of the at least one secondary wireless power receiving unit is adjusted by adjusting the operation of the at least one power transmission circuit when the first rectified voltage generated by the main wireless power receiving circuit is greater than the output voltage at the output node and the output voltage is greater than the second rectified voltage generated by the at least one secondary wireless power receiving unit, until the first rectified voltage generated by the main wireless power receiving circuit and the second rectified voltage generated by the at least one secondary wireless power receiving unit are equal. The operation of the at least one wireless power receiving circuit is adjusted by requesting the at least one power transmission circuit to modify the power transmission to the main wireless power receiving circuit until the first rectified voltage and the second rectified voltage are equal.

2. The method according to claim 1, wherein modifying the power transmission to the main wireless power receiving circuit is: increasing the power transmission to the main wireless power receiving circuit.

3. The method of claim 1, wherein the operation of the at least one wireless power receiving circuit is further adjusted by adjusting the operation of the at least one wireless power receiving circuit when the second rectified voltage is greater than the first rectified voltage and the first rectified voltage is greater than the output voltage, until the first rectified voltage and the second rectified voltage are equal.

4. The method of claim 1, wherein the operation of the at least one wireless power receiving circuit is further adjusted by adjusting the operation of the at least one wireless power receiving circuit when the first rectified voltage is greater than the second rectified voltage and the second rectified voltage is greater than the output voltage, until the first rectified voltage and the second rectified voltage are equal.

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