Bus neutral-point voltage direct-current bias elimination method of three-level converter

Abstract

The invention provides a bus neutral-point voltage direct-current bias elimination method for a three-level converter. The method comprises the following steps: acquiring the current three-phase reference voltage of the three-level converter; determining a first three-phase modulation wave according to the three-phase reference voltage and a current modulation strategy; collecting a three-phase current direction, and determining a direction signal of a bias elimination component according to the first three-phase modulation wave and the three-phase current direction; obtaining an electrolytic capacitor voltage difference between upper and lower DC buses of the three-level converter, and determining an amplitude signal of a bias elimination component according to the electrolytic capacitor voltage difference; determining a bias elimination component according to the product of the direction signal and the amplitude signal; and determining a second three-phase modulation wave according to the bias elimination component and the first three-phase modulation wave, and generating a switch tube driving signal of each bridge arm in the three-level converter. According to the invention, the direction signal and the amplitude signal of the bias elimination component are respectively calculated, the influence of the current direction on the DC bias of the neutral-point voltage of the bus is fully considered, and the stability of the converter is effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of inverter modulation technology, and in particular to a method, apparatus, storage medium, electronic device, and three-level converter for eliminating DC bias at the bus midpoint voltage of a three-level converter. Background Technology

[0002] With the rapid development of new energy industries such as photovoltaics, wind power, and energy storage, three-level converters are widely used in the new energy industry due to their advantages such as high output current and voltage power quality, low device loss, and low cost.

[0003] Three-level converters, due to their split DC buses, suffer from bus midpoint voltage imbalance, which can be divided into AC voltage fluctuations and DC voltage bias. Overall, the bus midpoint voltage imbalance is mainly caused by the modulation strategy used in the three-level converter, resulting in an imbalance of charging and discharging currents of the upper and lower bus electrolytic capacitors during the switching cycle.

[0004] For the DC bias of the bus neutral point voltage in a three-phase three-level converter, it is mainly caused by the difference in the values ​​of the electrolytic capacitors on the upper and lower buses and the accumulation of the current difference flowing through the electrolytic capacitors on the basis of the fundamental frequency. Hardware differences are unavoidable for three-phase three-level converters, so methods for suppressing the DC bias of the bus neutral point voltage mainly focus on calculating and redistributing the voltage vector to achieve suppression. Traditional methods for suppressing the DC bias of the bus neutral point voltage only consider the relationship between the voltage difference between the upper and lower buses and the output voltage vector, ignoring the fact that the direction of the output current also affects the DC bias of the bus neutral point voltage when the power factor angle changes. Furthermore, since the bus neutral point voltage in a three-phase three-level converter often experiences AC fluctuations at the third harmonic, this interferes with the PI loop of the voltage difference between the upper and lower buses, affecting the suppression effect of the DC bias of the bus neutral point voltage. Summary of the Invention

[0005] The purpose of this disclosure is to provide a method, apparatus, storage medium, electronic device, and three-level converter for eliminating DC bias of the bus midpoint voltage in a three-level converter, so as to solve the problem of DC bias of the bus midpoint voltage in the prior art.

[0006] The embodiments of this disclosure adopt the following technical solution: a method for eliminating DC bias at the bus midpoint voltage of a three-level converter, comprising: acquiring the current three-phase reference voltage of the three-level converter; determining a first three-phase modulation wave based on the three-phase reference voltage and the current modulation strategy; acquiring the three-phase current direction of the three-level converter, and determining the direction signal of the bias elimination component based on the first three-phase modulation wave and the three-phase current direction; acquiring the electrolytic capacitor voltage difference between the upper and lower DC buses of the three-level converter, and determining the amplitude signal of the bias elimination component based on the electrolytic capacitor voltage difference; determining the bias elimination component based on the product of the direction signal and the amplitude signal; determining a second three-phase modulation wave based on the bias elimination component and the first three-phase modulation wave, and generating switching transistor drive signals for each bridge arm in the three-level converter based on the second three-phase modulation wave.

[0007] This disclosure also provides a DC bias elimination device for the bus midpoint voltage of a three-level converter, comprising: an acquisition module for acquiring the current three-phase reference voltage of the three-level converter; determining a first three-phase modulation wave based on the three-phase reference voltage and the current modulation strategy; a bias elimination component calculation module for acquiring the three-phase current direction of the three-level converter and determining the direction signal of the bias elimination component based on the first three-phase modulation wave and the three-phase current direction; acquiring the electrolytic capacitor voltage difference between the upper and lower DC buses of the three-level converter and determining the amplitude signal of the bias elimination component based on the electrolytic capacitor voltage difference; determining the bias elimination component based on the product of the direction signal and the amplitude signal; and a driving module for determining a second three-phase modulation wave based on the bias elimination component and the first three-phase modulation wave, and generating switching transistor driving signals for each bridge arm in the three-level converter based on the second three-phase modulation wave.

[0008] This disclosure also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described method for eliminating DC bias at the bus midpoint voltage of a three-level converter.

[0009] This disclosure also provides an electronic device, including at least a memory and a processor. The memory stores a computer program, and when the processor executes the computer program in the memory, it implements the steps of the above-described method for eliminating DC bias at the bus midpoint voltage of a three-level converter.

[0010] This disclosure also provides a three-level converter, which includes at least the electronic equipment described above.

[0011] The beneficial effects of this embodiment are as follows: by calculating the direction signal and amplitude signal of the bias elimination component separately, the influence of the current direction on the DC bias of the bus midpoint voltage is fully considered, and the DC bias of the bus midpoint voltage is eliminated when there is a 20% capacitance difference between the upper and lower bus electrolytic capacitor values, effectively improving the stability of the converter; at the same time, there is no need to judge the voltage vector region and recalculate and allocate the voltage vector to achieve the elimination of the DC bias of the bus midpoint voltage, effectively reducing the computational load of the bus midpoint voltage DC bias elimination method. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the topology of an I-NPC three-level converter;

[0014] Figure 2 This is a flowchart of the method for eliminating DC bias at the bus midpoint voltage of a three-level converter in the first embodiment of this disclosure;

[0015] Figure 3 This is a block diagram of the constant power control of the three-level converter in the first embodiment of this disclosure;

[0016] Figure 4 This is a flowchart illustrating the process of determining the direction signal of the bias cancellation component in the first embodiment of this disclosure;

[0017] Figure 5 This is a block diagram of the bus midpoint voltage control in the first embodiment of this disclosure;

[0018] Figure 6 This is a comparison diagram showing the effect of eliminating DC bias of bus midpoint voltage using the method of this embodiment and the conventional method in the first embodiment of this disclosure;

[0019] Figure 7 This is a schematic diagram of the DC bias elimination device for the bus midpoint voltage of the three-level converter in the second embodiment of this disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0021] With the rapid development of new energy industries such as photovoltaics, wind power, and energy storage, three-level converters are widely used in the new energy industry due to their advantages such as high output current and voltage power quality, low device loss, and low cost.

[0022] Three-level converters, due to their split DC buses, suffer from bus midpoint voltage imbalance, which can be divided into AC voltage fluctuations and DC voltage bias. Overall, the bus midpoint voltage imbalance is mainly caused by the modulation strategy used in the three-level converter, resulting in an imbalance of charging and discharging currents of the upper and lower bus electrolytic capacitors during the switching cycle.

[0023] For the DC bias of the bus neutral point voltage in a three-phase three-level converter, it is mainly caused by the difference in the values ​​of the electrolytic capacitors on the upper and lower buses and the accumulation of the current difference flowing through the electrolytic capacitors on the basis of the fundamental frequency. Hardware differences are unavoidable for three-phase three-level converters, so methods for suppressing the DC bias of the bus neutral point voltage mainly focus on calculating and redistributing the voltage vector to achieve suppression. Traditional methods for suppressing the DC bias of the bus neutral point voltage only consider the relationship between the voltage difference between the upper and lower buses and the output voltage vector, ignoring the fact that the direction of the output current also affects the DC bias of the bus neutral point voltage when the power factor angle changes. Furthermore, since the bus neutral point voltage in a three-phase three-level converter often experiences AC fluctuations at the third harmonic, this interferes with the PI loop of the voltage difference between the upper and lower buses, affecting the suppression effect of the DC bias of the bus neutral point voltage.

[0024] To address the aforementioned issues, the first embodiment of this disclosure provides a method for eliminating DC bias at the bus midpoint voltage of a three-level converter. The execution entity can be the host controller of the three-level converter, which is mainly used to control the on / off switching of the bridge arm switching transistors of the three-level converter according to different modulation strategies, and finally complete the output of a three-phase sinusoidal signal.

[0025] Figure 1 A schematic diagram of the topology of an I-NPC three-level converter is shown in this embodiment. Figure 1The following explanation uses a three-level converter as an example to illustrate the method for eliminating DC bias in the bus midpoint voltage. Figure 1 As shown, each phase of the three-level converter consists of four switching transistors and two freewheeling diodes. Cap1 and Cap2 are the DC-side bus capacitors. dc S is the DC side voltage. xi Let S be the drive signal for the i-th switch in phase x, i.e., x = a, b, c; s = 1, 2, 3, 4. Let S be the drive signal for the i-th switch in phase x. xi When S is 1, the corresponding switch is turned on, and when S... xi When the value is 0, the corresponding switch is turned off. Therefore, analysis shows that each phase of the I-NPC three-phase three-level converter can output three levels: U... dc / 2, 0 and -U dc / 2, corresponding to states [P], [O], and [N] respectively. The I-NPC three-phase three-level converter is followed by an LCL filter system, which consists of three parts: inverter-side inductor L1, filter capacitor C, and grid-side inductor L2. The converter is connected to the grid through the LCL filter system.

[0026] Figure 2 The flowchart of the DC bias elimination method for the bus neutral point voltage of the three-level converter in this embodiment is shown, which mainly includes steps S10 to S60:

[0027] S10: Obtain the current three-phase reference voltage of the three-level converter.

[0028] The core function of a three-level converter is to convert the DC-side voltage into a three-phase AC voltage that meets the requirements of the load or power grid. In practical applications, the converter needs to cope with disturbances such as load fluctuations and changes in DC-side voltage. Therefore, it is necessary to dynamically adjust the three-phase reference voltage through closed-loop control (such as voltage closed-loop and current closed-loop) to ensure stable output.

[0029] Figure 3 The constant power control block diagram of the converter in this embodiment is shown. This embodiment obtains the current loop output and the grid voltage feedforward output, performs summation, inverse Park and inverse Clark transformations, and then standardizes the transformation results to obtain the three-phase reference voltage u. a ,u b ,u c Specifically, since a PI loop can follow a DC current without steady-state error, the current loop in this embodiment uses a PI loop to calculate the current command I along the dq axis based on the current grid voltage. d and I q The grid-connected current is transformed by dq and then used as the feedback value input into the current loop. At the same time, since the grid voltage fluctuates, the output of the PI loop is superimposed with the grid voltage feedforward and then normalized to obtain the three-phase reference voltage.

[0030] S20: Determine the first three-phase modulation wave based on the three-phase reference voltage and the current modulation strategy.

[0031] The three-phase modulation wave is the instantaneous waveform of the three-phase phase voltages expected to be output by the converter. It directly determines the amplitude, frequency, phase, and waveform of the output voltage and serves as the reference signal for the modulation strategy, determining the on / off timing of the switching transistors. In this embodiment, the first three-phase modulation wave can be initially determined based on the three-phase reference voltage and the current modulation strategy to serve as the basis for eliminating the DC bias of the subsequent bus midpoint voltage.

[0032] Specifically, in the modulation strategy of a three-level converter, the zero-sequence component is a "flexible adjustment tool". Its core function is to improve the performance of the converter by optimizing the three-phase reference voltage without changing the line voltage output. Therefore, in this embodiment, before determining the first three-phase modulation wave, the current zero-sequence component is calculated according to the current modulation strategy. Then, the first three-phase modulation wave is obtained by superimposing the zero-sequence component on the three-phase reference voltage.

[0033] It should be noted that the calculation method for the zero-sequence component differs for different modulation strategies. This embodiment does not describe the specific calculation process for the zero-sequence component. The calculation can be performed according to the commonly used zero-sequence component calculation method for the current modulation strategy.

[0034] S30: Acquire the direction of the three-phase current of the three-level converter, and determine the direction signal of the bias elimination component based on the first three-phase modulation wave and the direction of the three-phase current.

[0035] Under normal circumstances, the switching transistor drive signal output of the corresponding bridge arm of the converter can be generated using the first three-phase modulation wave. However, when the capacitance difference between the upper and lower bus electrolytic capacitors is too large, the current flowing through the upper and lower bus electrolytic capacitors will differ, resulting in a DC bias of the bus midpoint voltage. Therefore, in this embodiment, the direction of the DC bias of the bus midpoint voltage is determined based on the first three-phase modulation wave, combined with the real-time acquisition of the three-phase current direction of the three-level converter. This bias direction is then used to determine the direction signal of the bias elimination component used to eliminate the bias.

[0036] Specifically, after determining the first three-phase modulation wave, the intermediate value V in the first three-phase modulation wave is first determined. mid,0 Subsequently, the first current signal i corresponding to the maximum value in the first three-phase modulated wave is determined. max,0 and the second current signal i corresponding to the minimum value in the first three-phase modulated wave. min,0 Finally, based on, as follows Figure 4 The process shown determines the direction signal Sign_PI for the bias cancellation component.

[0037] Combination Figure 4 As shown, when determining Sign_PI, the intermediate value V is first detected. mid,0 Is it greater than 0; at the intermediate value V mid,0 When the value is greater than 0, detect the second current signal I. min,0 Is it greater than 0; in the second current signal I min,0 If the value is greater than 0, the direction signal Sign_PI is determined to be -1; in the second current signal I min,0 When the value is less than or equal to 0, the direction signal Sign_PI is determined to be 1; when the value is in the middle V... mid,0 When the value is less than or equal to 0, the first current signal I is detected. max,0 Is it greater than 0; in the first current signal I max,0 If the value is greater than 0, the direction signal Sign_PI is determined to be 1; in the first current signal I max,0 If the value is less than or equal to 0, the direction signal Sign_PI is determined to be -1.

[0038] S40: Obtain the voltage difference between the electrolytic capacitors of the upper and lower DC buses of the three-level converter, and determine the amplitude signal of the bias elimination component based on the voltage difference between the electrolytic capacitors.

[0039] Step S30 determines the direction signal of the bias cancellation component. Based on this, step S40 determines the amplitude signal of the bias cancellation component. Specifically, Figure 5 The diagram illustrates the bus midpoint voltage control block diagram. It shows how a PI loop is constructed to achieve closed-loop control of the voltage difference between the electrolytic capacitors of the upper and lower busbars. The PI loop generates a compensation signal to eliminate the voltage difference, ultimately achieving voltage balance between the upper and lower busbars. This embodiment utilizes the PI loop controlling the bus midpoint voltage to calculate the amplitude signal of the bias elimination component, which can be specifically described as follows:

[0040] Mid_PI.out = (U dc1 -U dc2 )×(K p +K i / s);

[0041] Where Mid_PI.out represents the amplitude signal of the bias cancellation component, U dc1 U represents the voltage of the electrolytic capacitor on the upper busbar. dc2 K represents the voltage of the electrolytic capacitor on the lower half of the bus. p K represents the proportional parameter of the PI loop controlling the bus midpoint voltage. i This represents the integral parameter of the PI loop controlling the bus midpoint voltage.

[0042] S50 determines the offset cancellation component based on the product of the direction signal and the amplitude signal.

[0043] S60: Based on the bias elimination component and the first three-phase modulation wave, determine the second three-phase modulation wave, and generate the switching transistor drive signals for each bridge arm in the three-level converter based on the second three-phase modulation wave.

[0044] After determining the direction signal Sign_PI and the amplitude signal Mid_PI.out, the bias cancellation component V can be determined by multiplying the two signals. midpoint ,Right now:

[0045] V midpoint =Sign_PI × Mid_PI.out;

[0046] The amplitude signal Mid_PI.out is used to determine the amplitude of DC bias compensation for the bus midpoint voltage, while the direction signal Sign_PI indicates the specific superposition direction of the bias elimination component during compensation.

[0047] Finally, during compensation, the bias elimination components are superimposed on the first three-phase modulated wave to obtain the second three-phase modulated wave that satisfies the DC bias elimination at the bus midpoint. That is, the second three-phase modulated wave is determined according to the following set of formulas:

[0048] u a,CB =u a +u0+V midpoint ;

[0049] u b,CB =u b +u0+V midpoint ;

[0050] u c,CB =u c +u0+V midpoint ;

[0051] Among them, u a,UCB ,u b,UCB ,u c,UCB Indicates the second and third phase modulation wave, u a +u0,u b +u0,u c +u0 represents the first three-phase modulation wave, u a ,u b ,u c This represents the three-phase reference voltage, u0 represents the current zero-sequence component, and V midpoint This indicates the bias cancellation component.

[0052] After obtaining the second and third phase modulation waves, the drive signals for the switching transistors of each bridge arm in the three-level converter can be generated based on the second and third phase modulation waves. This enables the control of the switching transistors of each phase bridge arm in the three-level converter to turn on and off based on the drive signals, generating U. dc / 2, 0 and -U dc The system employs three output levels ( / 2) to ultimately generate an output voltage containing a fundamental frequency and a high-frequency voltage signal. After the high-frequency signal is filtered out by an LCL filter, a three-phase sinusoidal signal is generated. It should be noted that the specific generation method of the drive signal for the switching transistor can be directly referenced from existing drive signal generation methods; this embodiment will not provide specific details.

[0053] Figure 6 The diagram shows a comparison of the DC bias elimination effect of the bus midpoint voltage using the method of this embodiment and the conventional method. Figure 6 It is known that when the power factor is too low, the bus midpoint voltage control strategy of the Convention Method will cause a large DC bias in the upper and lower buses. However, when switching to the Proposed Method used in this embodiment, the DC bias at the bus midpoint voltage can be basically eliminated, and only AC fluctuations exist in the bus midpoint voltage.

[0054] This embodiment calculates the direction and amplitude signals of the bias elimination component separately, fully considering the impact of current direction on the DC bias of the bus midpoint voltage. It achieves the elimination of the DC bias of the bus midpoint voltage even when there is a 20% capacitance difference between the upper and lower bus electrolytic capacitors, effectively improving the stability of the converter. At the same time, it eliminates the need to judge the voltage vector region and recalculate and distribute the voltage vector to achieve the elimination of the DC bias of the bus midpoint voltage, effectively reducing the computational load of the bus midpoint voltage DC bias elimination method.

[0055] Based on the same inventive concept, the second embodiment of this disclosure provides a DC bias elimination device for the bus midpoint voltage of a three-level converter. This device can be installed in the upper controller of the three-level converter and completes the DC bias elimination of the bus midpoint voltage of the three-level converter by acquiring the voltage and current status of the three-level converter in real time.

[0056] Figure 7The diagram illustrates the structure of the DC bias elimination device for the bus midpoint voltage of the three-level converter in this embodiment. It mainly includes: an acquisition module 10, used to acquire the current three-phase reference voltage of the three-level converter; determine the first three-phase modulation wave based on the three-phase reference voltage and the current modulation strategy; a bias elimination component calculation module 20, used to acquire the three-phase current direction of the three-level converter, and determine the direction signal of the bias elimination component based on the first three-phase modulation wave and the three-phase current direction; acquire the electrolytic capacitor voltage difference between the upper and lower DC buses of the three-level converter, and determine the amplitude signal of the bias elimination component based on the electrolytic capacitor voltage difference; determine the bias elimination component based on the product of the direction signal and the amplitude signal; and a drive module 30, used to determine the second three-phase modulation wave based on the bias elimination component and the first three-phase modulation wave, and generate the switching transistor drive signals for each bridge arm in the three-level converter based on the second three-phase modulation wave.

[0057] In some embodiments, the acquisition module 10 is specifically used to: acquire the current loop output and voltage feedforward output of the three-level converter; calculate the sum of the current loop output and voltage feedforward output; perform inverse Park transformation and inverse Clark transformation on the sum, and after standardizing the transformation results, obtain the three-phase reference voltage.

[0058] In some embodiments, the acquisition module 10 is specifically used to: determine the current zero-sequence component based on the three-phase reference voltage and the current modulation strategy; and determine the first three-phase modulation wave based on the sum of the three-phase reference voltage and the current zero-sequence component.

[0059] In some embodiments, the bias elimination component calculation module 20 is specifically used to: determine the intermediate value in the first three-phase modulated wave; determine the first current signal corresponding to the maximum value in the first three-phase modulated wave and the second current signal corresponding to the minimum value in the first three-phase modulated wave; detect whether the intermediate value is greater than 0; if the intermediate value is greater than 0, detect whether the second current signal is greater than 0; if the second current signal is greater than 0, determine the direction signal as -1; if the second current signal is less than or equal to 0, determine the direction signal as 1; if the intermediate value is less than or equal to 0, detect whether the first current signal is greater than 0; if the first current signal is greater than 0, determine the direction signal as 1; if the first current signal is less than or equal to 0, determine the direction signal as -1.

[0060] In some embodiments, the bias cancellation component calculation module 20 is specifically used to: determine the amplitude signal of the bias cancellation component according to the following formula:

[0061] Mid_PI.out = (U dc1 -U dc2 )×(K p +K i / s);

[0062] Where Mid_PI.out represents the amplitude signal of the bias cancellation component, U dc1 U represents the voltage of the electrolytic capacitor on the upper busbar. dc2 K represents the voltage of the electrolytic capacitor on the lower half of the bus. p K represents the proportional parameter of the PI loop controlling the bus midpoint voltage. i This represents the integral parameter of the PI loop controlling the bus midpoint voltage.

[0063] In some embodiments, the driving module 30 is specifically configured to: determine the second three-phase modulation wave according to the following set of formulas:

[0064] u a,CB =u a +u0+V midpoint ;

[0065] u b,CB =u b +u0+V midpoint ;

[0066] u c,CB =u c +u0+V midpoint ;

[0067] V midpoint =Sign_PI × Mid_PI.out;

[0068] Among them, u a,UCB ,u b,UCB ,u c,UCB Indicates the second and third phase modulation wave, u a +u0,u b +u0,u c +u0 represents the first three-phase modulation wave, u a ,u b ,u c This represents the three-phase reference voltage, u0 represents the current zero-sequence component, and V midpoint The offset cancellation component is represented by Sign_PI, which represents the direction signal of the offset cancellation component, and Mid_PI.out represents the amplitude signal of the offset cancellation component.

[0069] This embodiment calculates the direction and amplitude signals of the bias elimination component separately, fully considering the impact of current direction on the DC bias of the bus midpoint voltage. It achieves the elimination of the DC bias of the bus midpoint voltage even when there is a 20% capacitance difference between the upper and lower bus electrolytic capacitors, effectively improving the stability of the converter. At the same time, it eliminates the need to judge the voltage vector region and recalculate and distribute the voltage vector to achieve the elimination of the DC bias of the bus midpoint voltage, effectively reducing the computational load of the bus midpoint voltage DC bias elimination method.

[0070] Based on the same inventive concept, a third embodiment of this disclosure provides a storage medium storing a computer program. When executed by a processor, the computer program implements the steps of the DC bias elimination method for the bus midpoint voltage of the three-level converter described in the first embodiment of this disclosure. This storage medium can be installed in the host controller of the three-level converter, so that the host controller executes the computer program stored in the storage medium when driving the three-level converter.

[0071] Based on the same inventive concept, the fourth embodiment of this disclosure provides an electronic device, including at least a memory and a processor. The memory stores a computer program, and when the processor executes the computer program in the memory, it implements the steps of the method for eliminating DC bias of the bus midpoint voltage of a three-level converter as described in the first embodiment of this disclosure. This electronic device can be a host controller for a three-level converter. When driving the three-level converter, the electronic device executes the computer program stored in the memory to eliminate the DC bias of the corresponding bus midpoint voltage.

[0072] Based on the same inventive concept, the fifth embodiment of this disclosure provides a three-level converter, which includes at least the electronic equipment provided in the fourth embodiment of this disclosure. In conjunction with the conventional topology of the converter, the electronic equipment is used as a driving device to control the switching transistors of each bridge arm of the converter, thereby eliminating the DC bias of the bus midpoint voltage of the three-level converter.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for eliminating DC bias in the bus neutral point voltage of a three-level converter, characterized in that, include: Obtain the current three-phase reference voltage of the three-level converter; The first three-phase modulation wave is determined based on the three-phase reference voltage and the current modulation strategy; The direction of the three-phase current of the three-level converter is acquired, and the direction signal of the bias elimination component is determined based on the first three-phase modulation wave and the direction of the three-phase current. Obtain the voltage difference between the electrolytic capacitors of the upper and lower DC buses of the three-level converter, and determine the amplitude signal of the bias elimination component based on the voltage difference between the electrolytic capacitors. The offset cancellation component is determined based on the product of the direction signal and the amplitude signal; Based on the bias elimination component and the first three-phase modulation wave, the second three-phase modulation wave is determined, and the switching transistor drive signal of each bridge arm in the three-level converter is generated based on the second three-phase modulation wave.

2. The method for eliminating DC bias at the bus midpoint voltage according to claim 1, characterized in that, The process of obtaining the current three-phase reference voltage of the three-level converter includes: Obtain the current loop output and voltage feedforward output of the three-level converter; Calculate the sum of the current loop output and the voltage feedforward output; The sum is subjected to inverse Park and inverse Clark transformations, and the transformation results are then normalized to per-unit values ​​to obtain the three-phase reference voltage.

3. The method for eliminating DC bias at the bus midpoint voltage according to claim 1, characterized in that, The step of determining the first three-phase modulation wave based on the three-phase reference voltage and the current modulation strategy includes: The current zero-sequence component is determined based on the three-phase reference voltage and the current modulation strategy; The first three-phase modulation wave is determined based on the sum of the three-phase reference voltage and the current zero-sequence component.

4. The method for eliminating DC bias at the bus midpoint voltage according to claim 3, characterized in that, The process of acquiring the three-phase current direction of the three-level converter and determining the direction signal of the bias cancellation component based on the first three-phase modulation wave and the three-phase current direction includes: Determine the median value in the first three-phase modulated wave; Determine the first current signal corresponding to the maximum value in the first three-phase modulated wave and the second current signal corresponding to the minimum value in the first three-phase modulated wave; Detect whether the intermediate value is greater than 0; If the intermediate value is greater than 0, detect whether the second current signal is greater than 0; If the second current signal is greater than 0, the direction signal is determined to be -1; If the second current signal is less than or equal to 0, the direction signal is determined to be 1; If the intermediate value is less than or equal to 0, detect whether the first current signal is greater than 0; If the first current signal is greater than 0, the direction signal is determined to be 1; If the first current signal is less than or equal to 0, the direction signal is determined to be -1.

5. The method for eliminating DC bias in bus midpoint voltage according to claim 4, characterized in that, The step of acquiring the electrolytic capacitor voltage difference between the upper and lower DC buses of the three-level converter, and determining the amplitude signal of the bias elimination component based on the electrolytic capacitor voltage difference, includes: The amplitude signal of the bias cancellation component is determined according to the following formula: Mid_PI.out=(U dc1 -U dc2 )×(K p +K i / s); Wherein, Mid_PI.oout represents the amplitude signal of the bias cancellation component, U dc1 U represents the voltage of the electrolytic capacitor on the upper busbar. dc2 K represents the voltage of the electrolytic capacitor on the lower half of the bus. p K represents the proportional parameter of the PI loop controlling the bus midpoint voltage. i This represents the integral parameter of the PI loop controlling the bus midpoint voltage.

6. The method for eliminating DC bias at the bus midpoint voltage according to claim 5, characterized in that, The step of determining the second three-phase modulation wave based on the bias elimination component and the first three-phase modulation wave includes: The second and third phase modulation waves are determined according to the following set of formulas: u a,CB =u a +u0+V midpoint ; u b,CB =u b +u0+V midpoint ; u c,CB =u c +u0+V midpoint ; IN midpoint =Sign_PI×Mid_PI.out; Among them, u a,UCB ,u b,UCB ,u c,UCB This represents the second and third phase modulation wave, u a +u0,u b +u0,u c +u0 represents the first three-phase modulation wave, u a ,u b ,u c The three-phase reference voltage is represented by u0, and the current zero-sequence component is represented by V. midpoint The offset cancellation component is represented by Sign_PI, the direction signal of the offset cancellation component is represented by Mid_PI.out, and the amplitude signal of the offset cancellation component is represented by Mid_PI.out.

7. A device for eliminating DC bias at the bus midpoint voltage of a three-level converter, characterized in that, include: The acquisition module is used to acquire the current three-phase reference voltage of the three-level converter; The first three-phase modulation wave is determined based on the three-phase reference voltage and the current modulation strategy; The bias elimination component calculation module is used to acquire the three-phase current direction of the three-level converter, and determine the direction signal of the bias elimination component based on the first three-phase modulation wave and the three-phase current direction; acquire the electrolytic capacitor voltage difference of the upper and lower DC buses of the three-level converter, and determine the amplitude signal of the bias elimination component based on the electrolytic capacitor voltage difference; and determine the bias elimination component based on the product of the direction signal and the amplitude signal. The drive module is used to determine the second three-phase modulation wave based on the bias elimination component and the first three-phase modulation wave, and to generate the switching transistor drive signal of each bridge arm in the three-level converter based on the second three-phase modulation wave.

8. A storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for eliminating DC bias of the bus midpoint voltage of the three-level converter as described in any one of claims 1 to 6.

9. An electronic device, comprising at least a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program on the memory, it implements the steps of the method for eliminating DC bias of the bus midpoint voltage of the three-level converter as described in any one of claims 1 to 6.

10. A three-level converter, characterized in that, It includes at least the electronic device as described in claim 9.

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