Adjustable gain amplifier resistor voltage coefficient compensation circuit and electronic equipment

Abstract

This application relates to the field of integrated circuit design technology and discloses a resistor-voltage coefficient compensation circuit in an adjustable gain amplifier. The circuit includes: a polysilicon resistor disposed on an insulating layer above a well region and comprising two resistor interfaces and a well region interface; the polysilicon resistor being connected in series with a preset operational amplifier through the resistor interfaces; and a gain-adjusting operational amplifier, the input terminal of which is connected to one of the resistor interfaces, and the output terminal connected to the well region interface. The gain-adjusting operational amplifier is used to adjust the output voltage according to the input voltage, thereby changing the potential of the well region relative to the polysilicon resistor. Through capacitive coupling, it influences the internal depletion state and band structure of the polysilicon resistor in a direction perpendicular to its length, thus optimizing the resistor-voltage coefficient. This application achieves dynamic optimization of the polysilicon resistor voltage coefficient through circuit structure innovation.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and particularly relates to a resistance voltage coefficient compensation circuit in an adjustable gain amplifier and an electronic device. BACKGROUND

[0002] In the design of analog integrated circuits, adjustable gain amplifiers are widely used in signal acquisition, sensor interface and other scenarios, and the gain accuracy and linearity of the adjustable gain amplifiers directly affect the performance of the system. Polysilicon resistors are often used as key voltage dividing elements of adjustable gain amplifiers due to their easy integration and strong process compatibility. However, the voltage coefficient of resistance (VCR) of polysilicon material causes the resistance value to drift with the change of the voltage across the resistor, especially when the input voltage dynamic range is large, the nonlinear change of the resistance value will introduce signal distortion, which seriously affects the gain accuracy and linearity of the amplifier. In the prior art, the compensation methods for the resistance voltage coefficient mainly include:

[0003] 1. Fixed bias compensation: The working point of the resistor is stabilized by a preset DC bias voltage, but it cannot adapt to the dynamic change of the input voltage, and the compensation range is limited;

[0004] 2. Resistance network calibration: A calibration structure of multiple resistors in parallel or series is used, but it increases the circuit complexity and chip area, and the calibration accuracy is significantly affected by process deviation;

[0005] 3. Feedback loop compensation: The bias of the resistor is adjusted by a simple feedback circuit, but the feedback depth is insufficient, and it is difficult to effectively suppress the resistance drift in a wide voltage range.

[0006] Therefore, there is an urgent need for a circuit to solve at least one of the above problems. SUMMARY

[0007] The application provides a resistance voltage coefficient compensation circuit in an adjustable gain amplifier and an electronic device, which aims to solve the problem that the voltage coefficient of polysilicon material causes the resistance value to drift with the change of the voltage across the resistor, especially when the input voltage dynamic range is large, the nonlinear change of the resistance value will introduce signal distortion, which seriously affects the gain accuracy and linearity of the amplifier.

[0008] In a first aspect, the application provides a resistance voltage coefficient compensation circuit in an adjustable gain amplifier, comprising:

[0009] A polysilicon resistor, which is disposed on an insulating layer above a well region and includes two resistance interfaces and a well region interface, and is connected in series with a preset operational amplifier through the resistance interfaces;

[0010] A gain-adjusting operational amplifier, an input end of the gain-adjusting operational amplifier is connected with any one of the resistors, and an output end of the gain-adjusting operational amplifier is connected with the well region, for adjusting an output voltage according to an input voltage, so as to change a potential of the well region relative to the polysilicon resistor, to affect an internal depletion state and a band structure of the polysilicon resistor in a direction perpendicular to a length direction of the polysilicon resistor through capacitive coupling, and to realize optimization of a resistance voltage coefficient of the polysilicon resistor.

[0011] In some embodiments, the input end of the gain-adjusting operational amplifier is connected between the polysilicon resistor and the operational amplifier, for obtaining an input voltage signal to be amplified and applying an adjusted bias voltage to the well region of the polysilicon resistor.

[0012] In some embodiments, the length of the polysilicon resistor is greater than or equal to 18 μm; and / or, the width of the polysilicon resistor is greater than or equal to 2 μm.

[0013] In some embodiments, the gain-adjusting operational amplifier adopts a single-ended input and single-ended output structure, the single-ended input and single-ended output structure includes a gain resistor, a bias resistor, an adjustable resistor, and an inverting amplification unit; a first end of the gain resistor is connected with an input end of the gain-adjusting operational amplifier, a second end of the gain resistor is connected with an output end of the gain-adjusting operational amplifier, and the adjustable resistor is connected in series with the gain resistor; a first end of the bias resistor is connected with the inverting amplification unit and a first end of the gain resistor respectively, and a second end of the bias resistor is grounded; wherein, by adjusting a resistance value of the adjustable resistor, a corresponding closed-loop gain of the gain-adjusting operational amplifier is changed, so as to increase the well region voltage.

[0014] In some embodiments, the gain-adjusting operational amplifier further includes a mirror amplification unit corresponding to a resistance voltage coefficient compensation circuit; a first end of the gain resistor is connected with a preset input end through a first end of the mirror amplification unit; wherein, the first end of the mirror amplification unit is equivalent to an alternating current ground potential in the gain-adjusting operational amplifier, and a second end of the mirror amplification unit is equivalent to an alternating current ground potential, and common-mode noise is suppressed by mirror symmetry of the circuit.

[0015] In some embodiments, the inverting amplification unit includes a combination of an NMOS transistor and a PMOS transistor, and the mirror amplification unit includes an NMOS transistor, a plurality of PMOS transistors, and a resistor element.

[0016] In some embodiments, an adjustable resistor is further included, the adjustable resistor is connected in series with the gain resistor; wherein, by adjusting a resistance value of the adjustable resistor, a corresponding closed-loop gain of the gain-adjusting operational amplifier is changed, so as to increase the well region voltage.

[0017] In some embodiments, a preset well bias voltage calculation model is also included. The well bias voltage calculation model is used to calculate the corresponding well bias voltage based on the voltage coefficient corresponding to the polysilicon resistor, so as to adjust the resistance value of the adjustable resistor according to the well bias voltage.

[0018] In some embodiments, the method for constructing the well bias voltage calculation model includes: obtaining the material parameters of the polysilicon resistor, the preset operating voltage range, the corresponding target voltage coefficient optimization threshold, and the resistance variation characteristics of the polysilicon resistor under different bias voltages; establishing a mathematical correlation model between the well bias voltage and the vertical electric field strength inside the polysilicon resistor; determining the optimal well bias voltage adjustment strategy under different input voltage amplitudes through the mathematical correlation model; and obtaining the constructed well bias voltage calculation model.

[0019] In some embodiments, the expression for the output voltage corresponding to the output terminal of the gain-adjusting operational amplifier includes: Vout = Vin(R1 + R2) / R1; where Vout is the output voltage, Vin is the input voltage corresponding to the input terminal of the gain-adjusting operational amplifier, R1 is the resistance value corresponding to the adjustable resistor, and R2 is the resistance value corresponding to the gain resistor.

[0020] In a second aspect, this application provides an electronic device comprising: a resistor voltage coefficient compensation circuit in an adjustable gain amplifier as described in any of the first aspects above.

[0021] This application utilizes a gain-adjusting operational amplifier to adjust the well region potential in real time, and leverages capacitive coupling to alter the internal vertical electric field of the polysilicon resistor, dynamically optimizing its voltage coefficient. This significantly suppresses resistance drift caused by input voltage variations and improves amplifier gain linearity. The circuit provided in this application eliminates the need for fixed bias or complex calibration networks, enabling effective operation over a wide input voltage range, reducing reliance on external calibration circuits, and enhancing system robustness. Furthermore, the circuit is implemented using standard CMOS technology, and the capacitive coupling structure between the polysilicon resistor and the well region is easy to integrate without adding extra process steps, balancing performance improvement and cost control.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the resistor voltage coefficient compensation circuit in the adjustable gain amplifier provided in one embodiment of this application;

[0025] Figure 2 This is a schematic cross-sectional view of the polysilicon resistor provided in one embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the gain-adjusting operational amplifier provided in one embodiment of this application;

[0027] Figure 4 This is a schematic diagram of an electronic device provided in an embodiment of this application.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions of layers and regions, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] To fully understand this application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0032] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] In analog integrated circuit design, adjustable gain amplifiers are widely used in signal acquisition, sensor interfaces, and other scenarios. Their gain accuracy and linearity directly affect system performance. Polysilicon resistors are often used as key voltage divider components in adjustable gain amplifiers due to their ease of integration and strong process compatibility. However, the voltage coefficient of resistance (VCR) of polysilicon materials causes its resistance to drift with changes in the voltage across it. Especially when the input voltage dynamic range is large, the nonlinear change in resistance introduces signal distortion, severely affecting the amplifier's gain accuracy and linearity. Existing technologies for compensating for the resistor voltage coefficient mainly include:

[0034] 1. Fixed bias compensation: The operating point of the resistor is stabilized by a preset DC bias voltage, but it cannot adapt to dynamic changes in the input voltage and has a limited compensation range;

[0035] 2. Resistor network calibration: This method uses a calibration structure with multiple resistors connected in parallel or series, but it increases circuit complexity and chip area, and the calibration accuracy is significantly affected by process deviations.

[0036] 3. Feedback loop compensation: The resistor bias is adjusted by a simple feedback circuit, but the feedback depth is insufficient, making it difficult to effectively suppress resistance drift over a wide voltage range.

[0037] However, existing solutions have failed to address the core issue of "dynamically optimizing the voltage coefficient of a polycrystalline silicon resistor by controlling its internal band structure with an electric field." The voltage coefficient of a polycrystalline silicon resistor is essentially caused by the change in its internal grain boundary potential barrier with the applied electric field. Traditional methods can only passively adjust the bias and cannot actively change the electric field distribution perpendicular to the resistor's length through structural design, thus affecting the depletion state and band structure. Therefore, how to achieve dynamic optimization of the voltage coefficient of a polycrystalline silicon resistor through circuit structure innovation has become a pressing technical challenge in this field.

[0038] To solve the above problems, such as Figure 1 As shown, this application provides a resistor-voltage coefficient compensation circuit 10 in an adjustable gain amplifier, including a polysilicon resistor 11 and a gain-adjusting operational amplifier 12. The polysilicon resistor 11 is disposed on an insulating layer above the well region and includes two resistor interfaces and a well region interface. The polysilicon resistor 11 is connected in series with a preset operational amplifier 20 through the resistor interfaces. The input terminal of the gain-adjusting operational amplifier 12 is connected to any one of the resistor interfaces, and the output terminal is connected to the well region interface. It is used to adjust the output voltage according to the input voltage to change the potential of the well region relative to the polysilicon resistor 11. Through capacitive coupling, it affects the internal depletion state and band structure of the polysilicon resistor 11 in the direction perpendicular to the length of the polysilicon resistor 11, thereby optimizing the resistor-voltage coefficient of the polysilicon resistor 11.

[0039] Specifically, the provided compensation circuit mainly includes two core components: a polysilicon resistor 11 and a gain-adjusting operational amplifier 12. These two components are connected in a specific manner to optimize the resistance-voltage coefficient. The polysilicon resistor 11 is fabricated on an insulating layer above the well region (N-well), and its cross-sectional structure is shown below. Figure 2 As shown, it includes two resistor ports (A, B) and one well port (C).

[0040] The polysilicon resistor 11 is capacitively coupled to the well region through an insulating layer. The well region potential (applied through port C) affects the grain boundary barrier height and depletion region state within the polysilicon through a vertical electric field (perpendicular to the length of the resistor), thereby altering the voltage coefficient of the resistor. When the potential difference between the well region and the polysilicon changes, the vertical electric field strength changes, and the grain boundary barrier height adjusts, thus suppressing resistance fluctuations caused by excessive input voltage.

[0041] The input terminal of the gain-adjusting operational amplifier 12 is connected to one end of the polysilicon resistor 11 (such as either port B or port A), and the output terminal is connected to the well port (C), forming a closed-loop feedback. By adjusting the well voltage, the potential difference between the well and the polysilicon resistor 11 (i.e., the voltage difference across A and C) is reduced, weakening the modulation effect of the input voltage on the resistor value and improving the signal acquisition accuracy.

[0042] At the same time, if Figure 1 The circuit in the diagram does not include a gain-adjusting op-amp 12; its input-output transfer function is obtained through the virtual short and virtual open circuits of the op-amp, expressed as H(s) = (V OUTP -V OUTN ) / V IN -VIP = -Ra / Rb, where Rb is the resistance of polysilicon resistor 11, and Ra is the resistance connected to the input and output terminals of operational amplifier 20. When the input voltage amplitude is large, the longitudinal electric field reduces the height of the grain boundary barrier between grains, making it easier for charge carriers to pass through, thus reducing the resistance value. At this time, the Rb value is relatively small, resulting in a larger amplification factor and poor voltage linearity.

[0043] This application uses a polysilicon resistor 11 as the gain resistor or input resistor of a proportional amplifier, connected in series with a preset operational amplifier (such as a fully differential proportional amplifier) ​​to form a signal amplification circuit. In conventional schemes, when the input voltage amplitude is large, the potential difference between the polysilicon resistor 11 and the well region (voltage difference at terminals A and C) leads to an enhanced vertical electric field, a lower grain boundary barrier, a reduced resistance value, and an increased amplification factor error. This application uses a gain-adjusting operational amplifier 12 to increase the voltage at port C of the well region, reduce the voltage difference at terminals A and C, weaken the influence of the vertical electric field on the grain boundary barrier, stabilize the resistance value, and thus correct the amplification factor error.

[0044] The differential signal to be amplified is input to a conventional proportional amplifier, with the polysilicon resistor 11 serving as a feedback / input resistor in the signal link. The input of the gain-adjusting operational amplifier 12 acquires the voltage signal at resistor port B, calculates the output voltage through an internal amplification and feedback network, and drives the potential at port C of the well region. The output voltage is dynamically adjusted according to the input voltage, aiming to reduce the potential difference between the polysilicon resistor 11 and the well region (i.e., the voltage difference between terminals A and C). For example, when the input voltage increases, causing the potential at terminal A to rise, the operational amplifier raises the potential at terminal C, reducing the voltage difference between A and C.

[0045] The well potential is coupled to the polysilicon resistor 11 through the insulating layer capacitance, changing the electric field strength in the vertical direction, adjusting the width of the space charge region and the height of the potential barrier at the grain boundary, suppressing the resistance decrease caused by high input voltage, and stabilizing the resistor voltage coefficient. After compensation, the resistance value is stable, the transfer function of the proportional amplifier remains accurate, and the linearity of the output signal is significantly improved.

[0046] This application forms dynamic feedback by connecting a gain-adjusting operational amplifier 12 between the resistor port (B) and the well port (C), and adjusts the well potential in real time according to the input voltage. This directly addresses the resistance fluctuation problem caused by the "voltage modulation effect" and weakens the influence of the vertical electric field from a physical mechanism perspective.

[0047] The compensation circuit provided in this application does not change the core architecture of the original proportional amplifier (the virtual short and virtual open characteristics are maintained). It only adds a gain adjustment operational amplifier 12 and connects it to the well port of the polysilicon resistor 11. Without affecting the original transfer function, it specifically solves the resistance voltage coefficient problem and is suitable for scenarios such as wireless charging and motor drive that require high linearity signal acquisition.

[0048] Through the above structure, the circuit achieves dynamic optimization of the voltage coefficient of the polysilicon resistor 11, effectively suppressing the resistance change caused by excessive input voltage amplitude, and improving the signal acquisition accuracy and linearity of the signal acquisition proportional amplifier.

[0049] In some embodiments, the input terminal of the gain-adjusting operational amplifier 12 is connected between the polysilicon resistor 11 and the operational amplifier, for acquiring the input voltage signal to be amplified and applying the adjusted bias voltage to the well region of the polysilicon resistor 11.

[0050] The input terminal of the gain-adjusting operational amplifier 12 is connected between the polysilicon resistor 11 and the main operational amplifier. The input voltage signal to be amplified is obtained through this node, and a dynamically adjusted bias voltage is applied to the well region of the polysilicon resistor 11 through the output terminal of the operational amplifier to compensate for the resistor voltage coefficient.

[0051] In a traditional proportional amplifier circuit, a polysilicon resistor 11 (such as Rb) is typically connected in series as a gain resistor or input resistor in the signal link of the main operational amplifier. The input terminal of the gain-adjusting operational amplifier 12 is directly connected to the connection node between this resistor and the main operational amplifier (e.g., resistor port B) to obtain the voltage signal of this node in real time (i.e., the signal after the input voltage to be amplified is divided by the resistor).

[0052] The operational amplifier (op-amp) calculates the output voltage based on the input node voltage signal through internal amplification and feedback networks. This voltage directly acts on the well port (C-terminal) of the polysilicon resistor 11. For example, when the input voltage increases, causing the voltage difference across the resistor to increase, the op-amp output voltage raises the well potential, reducing the potential difference between the resistor and the well, thus weakening the modulation effect of the vertical electric field on the resistor. Since no current flows through the op-amp input (high input impedance characteristic), the virtual short and virtual open characteristics of the main operational amplifier are unaffected, and the transfer function of the original proportional amplifier circuit remains unchanged. Resistor voltage coefficient compensation is achieved only through dynamic adjustment of the well bias voltage.

[0053] In some embodiments, the length of the polysilicon resistor 11 is greater than or equal to 18 μm; and / or, the width of the polysilicon resistor 11 is greater than or equal to 2 μm.

[0054] By defining the geometry of the polysilicon resistor 11, requiring its length to be greater than or equal to 18 μm and / or its width to be greater than or equal to 2 μm, the voltage coefficient characteristics of the resistor are optimized.

[0055] The resistance stability of polycrystalline silicon resistor 11 is closely related to its geometric dimensions. A longer resistor length (≥18μm) can reduce the influence of edge electric field effects and reduce the non-uniformity of grain boundary potential barriers caused by voltage gradients; a wider width (≥2μm) can increase the cross-sectional area of ​​carrier transport paths and reduce the modulation sensitivity of vertical electric fields to the overall resistance.

[0056] In semiconductor manufacturing processes, when forming polycrystalline silicon resistors 11 using photolithography and ion implantation, precise control of the mask pattern dimensions is crucial to ensure that the resistor length and width meet design requirements. For example, with an 18μm length design, the resistor body extends in a single direction on the insulating layer above the well region, covering an area of ​​more than 2μm in width to enhance the symmetry of the resistor structure and the uniformity of the electric field distribution. Combined with well region bias voltage adjustment, the larger size can further suppress resistance fluctuations caused by input voltage, making the voltage coefficient of the resistor more stable under high voltage input and improving signal acquisition accuracy.

[0057] In some embodiments, the gain-adjustable operational amplifier 12 adopts a single-ended input, single-ended output structure, which includes a gain resistor, a bias resistor, an adjustable resistor, and an inverting amplifier unit. The first end of the gain resistor is connected to the input terminal of the gain-adjustable operational amplifier 12, and the second end of the gain resistor is connected to the output terminal of the gain-adjustable operational amplifier 12. The adjustable resistor is connected in series with the gain resistor. The first end of the bias resistor is connected to both the inverting amplifier unit and the first end of the gain resistor, and the second end of the bias resistor is grounded. The closed-loop gain of the gain-adjustable operational amplifier is changed by adjusting the value of the adjustable resistor, thereby increasing the well voltage.

[0058] The gain-adjustable operational amplifier 12 adopts a single-ended input and single-ended output structure, including an adjustable resistor, a gain resistor, a bias resistor, and an inverting amplifier unit. The closed-loop gain is adjusted by the cooperation of the adjustable resistor and the gain resistor to control the well voltage.

[0059] The input terminal receives a voltage signal from polysilicon resistor 11 (such as the voltage at port B) and is connected to the input node of the inverting amplifier unit (such as...). Figure 3 (Source of MP5).

[0060] The first end of the gain resistor (R2) is connected to the input terminal of the operational amplifier, and the second end is connected to the output terminal. The first end of the bias resistor (R4) is connected to the input node of the inverting amplifier unit (such as the gate of MN2) and the second end of the gain resistor, and the second end is grounded, forming a voltage parallel negative feedback.

[0061] High closed-loop gain can significantly increase the well voltage, reduce the potential difference between it and the polysilicon resistor 11, weaken the vertical electric field strength, and make the grain boundary barrier highly stable, thereby suppressing the decrease in resistance caused by the increase in input voltage.

[0062] In some embodiments, the gain-adjusting operational amplifier 12 further includes a mirror amplifier unit corresponding to the inverting amplifier unit; the first end of the gain resistor is connected to a preset input terminal via the first end of the mirror amplifier unit; wherein, the first end of the mirror amplifier unit is equivalent to AC ground potential in the gain-adjusting operational amplifier 12, and the second end of the mirror amplifier unit is equivalent to AC ground potential, and common-mode noise interference is suppressed by the mirror amplifier unit and the inverting amplifier unit, and the common-mode noise interference is suppressed by the mirror symmetry of the circuit.

[0063] The gain-adjusting operational amplifier 12 integrates a mirror amplifier unit, which works with the inverting amplifier unit to suppress common-mode noise and improve signal processing accuracy. The mirror unit is equivalent to AC ground potential in the AC path.

[0064] like Figure 3As shown, the mirror devices corresponding to the entire circuit are MP1, MP2, MP3, MP4, R3, and MN1, which suppress common-mode noise interference through the mirror symmetry of the entire circuit. Among them, MN1, MP1, MP2, and MP3 form the mirror symmetry circuit corresponding to the inverting amplifier unit, and MN1, MP1, MP2, and MP3 are PMOS and NMOS transistors, respectively.

[0065] The MP4's gate voltage and input voltage share the same common-mode noise. Due to the mirror symmetry of the entire circuit, the common-mode noise cancels out at the output, suppressing common-mode noise interference. The MP4's source is equivalent to AC ground, ensuring that the circuit's closed-loop gain is a resistor-proportional amplifier, thus improving circuit linearity.

[0066] By combining the mirror amplifier unit and the inverting amplifier unit, the op-amp becomes more sensitive to small changes in the input voltage (such as voltage fluctuations at the 11 port of the polysilicon resistor), reducing the bias voltage error at the output to the well region and ensuring the accuracy of resistor voltage coefficient compensation.

[0067] In some embodiments, the inverting amplification unit includes a combination of NMOS transistors and PMOS transistors, and the mirror amplification unit includes a plurality of PMOS transistors and resistive elements.

[0068] By clarifying the device composition of the inverting amplifier unit and the mirror amplifier unit, both the inverting amplifier unit and the mirror amplifier unit adopt a combination of NMOS and PMOS.

[0069] The inverting amplifier unit includes, for example: Figure 3 In this circuit, MN2 (NMOS transistor) is combined with MP6, MP7, and MP8 (PMOS transistors). MN2's gate receives the input signal, and its drain is connected to a PMOS load. MP6 and MP7 are current source loads, providing the required bias voltage for MP8. MN3 and MP8 form a Class-AB structure, enhancing the circuit's driving capability. This combination achieves high-gain and low-distortion signal amplification through the current amplification characteristics of complementary transistors.

[0070] The mirror magnification unit includes, for example: Figure 3 The circuit consists of MP1, MP2, MP3, MP4, R3, and MN1. MP1 and MP2 form a current source load, providing bias voltage for MP3. R3 acts as a bias resistor to set the gate potential of MN1. In the AC path, the source of MP4 is equivalent to AC ground. The gate voltage of MP4 and the input voltage have the same common-mode noise, which cancels each other out at the output, suppressing common-mode noise interference. The source of MP4 is equivalent to AC ground, ensuring that the closed-loop gain of the circuit is a resistor-based proportional gain amplifier, thus improving the circuit linearity.

[0071] The dimensions and threshold voltage of NMOS and PMOS need to be optimized according to process parameters. For example, the aspect ratio of MN2 is designed to adapt to the input signal swing, and the substrate of PMOS should be connected to its source to eliminate the body effect and ensure that it operates in the saturation region or subthreshold region.

[0072] The closed-loop gain of the gain-adjusting operational amplifier 12 is changed by adjusting the value of the adjustable resistor, thereby increasing the well voltage. By adding an adjustable resistor in series with the gain resistor in the gain-adjusting operational amplifier 12, the closed-loop gain adjustment range is expanded by adjusting the value of the adjustable resistor, further increasing the well voltage.

[0073] An adjustable resistor (such as R1) is connected in series with a gain resistor (R2) and then connected to the operational amplifier feedback loop to form a total resistance Rtotal = R1 + R2. The adjustable resistor can be a fuse-type resistor (which changes the resistance value by melting part of the resistor segment) or a programmable resistor (such as a switch-controlled resistor array).

[0074] The closed-loop gain formula then becomes Av=(R1+R2) / R1. Increasing R1 reduces the gain, while decreasing R1 increases the gain. For example, when the input voltage range is wide, the value of the adjustable resistor can be reduced by programming to make the op-amp output a higher well voltage, adapting to the compensation requirements in extreme high-voltage scenarios.

[0075] After chip manufacturing is completed, the resistance value of the adjustable resistor can be adjusted by external control signals or on-chip calibration circuits to provide personalized compensation for the voltage coefficient differences of polysilicon resistors 11 in different process batches, thereby improving circuit robustness.

[0076] In some embodiments, a preset well region bias voltage calculation model is also included. The well region bias voltage calculation model is used to calculate the corresponding well region bias voltage based on the voltage coefficient corresponding to the polysilicon resistor 11, so as to adjust the resistance value of the adjustable resistor according to the well region bias voltage.

[0077] By introducing a well region bias voltage calculation model, the optimal bias voltage is calculated in real time based on the voltage coefficient of the polysilicon resistor 11, which guides the adjustment of the adjustable resistor value.

[0078] The model input parameters include: material parameters of polysilicon resistor 11 (such as grain size and doping concentration), preset operating voltage range (such as input voltage 0-5V), target voltage coefficient optimization threshold (such as requiring resistance change rate <0.1%), and resistance change curves of resistor under different bias voltages (obtained through previous process simulation or testing).

[0079] By establishing the relationship between the well region bias voltage Vsub and the vertical electric field intensity E⊥ inside the polysilicon:

[0080] E⊥=(Vpoly-Vsub) / d (where Vpoly is the potential of polysilicon resistor 11 and d is the thickness of the insulating layer), combined with the formula for the influence of the electric field on the grain boundary barrier height, the expression for Vsub that minimizes the resistance change is derived. After the model outputs the optimal Vsub, the resistance value of the adjustable resistor (R1) is controlled by the feedback circuit to make the output voltage of the gain adjustment operational amplifier 12 approach the target value, thereby achieving adaptive compensation for the resistor voltage coefficient.

[0081] In some embodiments, the method for constructing the well bias voltage calculation model includes: obtaining the material parameters of the polysilicon resistor 11, the preset operating voltage range, the corresponding target voltage coefficient optimization threshold, and the resistance change characteristics of the polysilicon resistor 11 under different bias voltages; establishing a mathematical correlation model between the well bias voltage and the vertical electric field strength inside the polysilicon resistor 11; determining the optimal well bias voltage adjustment strategy under different input voltage amplitudes through the mathematical correlation model; and obtaining the constructed well bias voltage calculation model.

[0082] The method for constructing the well bias voltage calculation model is clearly defined, including parameter acquisition, mathematical model establishment, and adjustment strategy determination. Material parameters, such as resistivity, dielectric constant, and initial height of grain boundary barriers of polysilicon, are obtained through process documentation or testing. The operating range is defined by the chip's input voltage range (e.g., 0-10V in wireless charging scenarios) and temperature range (e.g., -40℃ to 85℃). Resistance characteristics are obtained through simulation (e.g., using TCAD tools) or actual measurements to obtain resistance-voltage curves at different Vsub values, thus determining the critical modulation voltage point.

[0083] The mathematical model is established based on semiconductor physics theory, and the relationship between the vertical electric field E⊥ and the grain boundary barrier height ΦB is established: ΦB(E⊥)=ΦB(0)-qE⊥d (q is the electron charge, which is the fundamental charge constant, representing the charge of a single electron or hole; ΦB(0) is the initial barrier height, representing the inherent barrier height of the grain boundary when there is no external vertical electric field; d is the barrier modulation width, which is used to represent the effective width of the grain boundary barrier under the action of the vertical electric field). Combining the relationship between the resistance value and the barrier height R∝eΦB / kT, the mapping model between Vsub and R is derived.

[0084] The adjustment strategy is determined by calculating the optimal Vsub for different input voltage amplitudes using a model. For example, when the input voltage Vin > 3V, the op-amp gain boosting mechanism is triggered, causing Vsub to increase with Vin at a preset slope, ensuring that resistance changes are effectively suppressed.

[0085] In some embodiments, the expression for the output voltage corresponding to the output terminal of the gain-adjusting operational amplifier 12 includes: Vout = Vin(R1 + R2) / R1; where Vout is the output voltage, Vin is the input voltage corresponding to the input terminal of the gain-adjusting operational amplifier 12, R1 is the resistance value corresponding to the adjustable resistor, and R2 is the resistance value corresponding to the gain resistor.

[0086] By giving the expression Vout=Vin(R1+R2) / R1 for the output voltage of gain-adjustable op-amp 12, the influence of adjustable resistor (R1) and gain resistor (R2) on the output voltage is clarified.

[0087] Based on the KCL equations of the operational amplifier feedback loop, assuming the operational amplifier input is virtually short (equal voltage) and virtually open (zero current), the adjustable resistor (R1) and the gain resistor (R2, i.e., R4 in Example 3) in the feedback network form a voltage divider. For a single-ended input and single-ended output structure, the output voltage Vout satisfies (Vout-Vin) / R2=Vin / R1, that is, the closed-loop gain is Av=1+R2 / R1.

[0088] Increasing the value of R1 (an adjustable resistor) reduces the gain, thus decreasing the variation of Vout with Vin, making it suitable for scenarios with small input voltage fluctuations. Conversely, decreasing the value of R1 increases the gain, significantly improving Vout, effectively increasing the well voltage, narrowing the potential difference with the polysilicon resistor 11, and suppressing resistance changes under high input voltages.

[0089] During circuit design, the target gain range is calculated in advance, the initial resistance values ​​of R1 and R2 are configured, and adjustable interfaces (such as fuses or register-controlled resistor arrays) are reserved to achieve dynamic adjustment of the parameters in the formula, ensuring that the output voltage accurately matches the resistor voltage coefficient compensation requirements.

[0090] In some embodiments, an adaptive feedback algorithm is embedded in the gain-adjusting operational amplifier 12 to dynamically adjust the resistance value of the adjustable resistor by monitoring the actual resistance value change of the polysilicon resistor 11 in real time, thereby achieving self-calibration compensation of the resistor voltage coefficient.

[0091] Resistance monitoring is used to connect a high-precision analog-to-digital converter (ADC) in parallel in the signal chain. It periodically collects the voltage (Vsub) across the polysilicon resistor 11 and the current (Isub) flowing through it. The real-time resistance is calculated using Ohm's law and compared with the preset ideal resistance to obtain the resistance deviation ΔR.

[0092] The adaptive algorithm employs a proportional-integral (PI) control algorithm, calculating the adjustment ΔG (corresponding to the op-amp closed-loop gain) based on the resistance deviation: ΔG = KpΔR + Ki∫ΔRdt; where Kp and Ki are the proportional and integral coefficients, configurable via registers. The algorithm outputs a digital signal to an adjustable resistor (such as a fuse array or MOSFET switching resistor) to dynamically correct the resistance value of R1, bringing the actual resistance value close to the preset ideal resistance value.

[0093] The closed-loop control process includes: initialization phase: the ADC collects the resistance value when unloaded and determines the preset ideal resistance value; operation phase: the ADC is triggered to sample once every 1μs, the algorithm calculates and adjusts R1 in real time, responds to changes in input voltage (such as high-frequency fluctuations of wireless charging signals), and ensures that the resistance fluctuation is suppressed to within 0.05%.

[0094] In some embodiments, by introducing an on-chip machine learning model (such as a linear regression model), the optimal well bias voltage is predicted based on multi-dimensional parameters such as input voltage amplitude, temperature, and process deviation, thereby achieving high-precision compensation across operating conditions.

[0095] By integrating temperature sensors, voltage sensors, and process deviation detection modules, environmental parameters (temperature T), input voltage (Vsub), and chip manufacturing parameters (such as polysilicon grain size deviation δ) are collected in real time and used as input features for the model.

[0096] A pre-trained linear regression model, Vsub = w1Vin + w2T + w3δ + b, is used, where the weights w1, w2, w3, and the bias b are stored in on-chip non-volatile memory (NVM). The model is obtained through offline training: optimal Vsub data under different T, V, and δ are simulated using TCAD, and the parameters are fitted using the least squares method.

[0097] Sensor data is read every 5μs and input into the model to calculate the target Vsub. The bias resistor (R1) of the gain adjustment op-amp 12 is adjusted through a digital-to-analog converter (DAC) to make the op-amp output voltage approach the predicted value. For example, when the temperature rises and causes the polysilicon grain boundary barrier to decrease, the model automatically increases Vsub to offset the resistance decrease caused by the temperature.

[0098] In some embodiments, for the nonlinear voltage coefficient characteristics of polycrystalline silicon resistor 11 under high voltage input, a lightweight neural network (such as a single-layer perceptron) is used to model the complex mapping relationship between the vertical electric field and the resistance value, so as to achieve accurate compensation in nonlinear scenarios.

[0099] The neural network architecture includes an input layer (2 neurons: voltage across the resistor Vpoly and voltage in the well region Vsub), a hidden layer (5 neurons with ReLU activation function), and an output layer (1 neuron, outputting the predicted resistance value R). The network is trained offline to fit the nonlinear relationship R=f(Vpoly,Vsub), with training data derived from measured resistance curves under high-voltage conditions.

[0100] Neuron computation is implemented using analog neural network circuits (such as transconductance amplifier arrays), and weight parameters are stored in non-volatile memory (such as Flash). Input signals Vpoly and Vsub are converted into current signals by buffers, and weighted summation is performed through a weighted resistor matrix. The ReLU activation function is implemented by a diode limiting circuit.

[0101] The compensation strategy includes: when the input voltage Vin > 4V (the threshold can also be adjusted according to actual needs), activating the neural network compensation mode: calculating the required Vsub based on real-time Vpoly, thus stabilizing Rpred at the target value. For example, at a 10V input, traditional linear compensation fails; the neural network outputs a higher Vsub through nonlinear mapping, suppressing the nonlinear decrease in resistance and reducing the amplification factor error.

[0102] In some embodiments, for scenarios where the input voltage contains high-frequency noise or transient interference, a fuzzy logic controller is designed to dynamically adjust the operational amplifier response speed according to the amplitude and frequency of resistor voltage fluctuations, achieving an adaptive balance between compensation accuracy and stability.

[0103] The design of fuzzy logic rules includes: defining input variables: resistance fluctuation amplitude E (large / medium / small), fluctuation frequency f (high / medium / low); and output variables: operational amplifier feedback loop bandwidth B (high / medium / low). A fuzzy rule base is then established, for example:

[0104] If E is large and f is low, then B is high (large deviation in fast response); if E is small and f is high, then B is low (suppression of high-frequency noise interference).

[0105] An integrated bandpass filter separates noise frequencies, a comparator detects the E threshold, and a state machine implements fuzzy rule matching. The output control signal adjusts the operational amplifier feedback capacitor (e.g., a parallel adjustable capacitor C) to change the loop bandwidth: increasing C reduces bandwidth and minimizes the impact of high-frequency noise; decreasing C increases bandwidth for faster response to large signal changes.

[0106] In high-noise environments such as motor drives, when the input voltage is detected to contain high-frequency noise above 100kHz, the fuzzy controller automatically reduces the loop bandwidth to suppress the noise interference on the sink voltage. At the same time, it restores high bandwidth compensation during noise intervals to ensure a balance between dynamic response and anti-interference capability.

[0107] In some embodiments, by adding an on-chip self-test (BIST) module, the initial voltage coefficient of the polysilicon resistor 11 is automatically calibrated when the chip is powered on, and the parameter deviations of different process batches are dynamically compensated by a programmable resistor array.

[0108] The self-test calibration process includes: after power-on reset, the BIST module applies a calibration voltage sequence (e.g., 0V, 2V, 4V, 6V) to the polysilicon resistor 11, and collects the corresponding resistance data R1, R2, R3, and R4; the resistor-voltage coefficient is fitted using the least squares method.

[0109] TC = (R4-R1) / 3R1ΔV, and the compensation coefficient Kcal is calculated by comparing it with the target threshold. Based on Kcal, the resistance value of the adjustable resistor array (such as an 8-bit programmable resistor) is configured, and the closed-loop gain of the gain adjustment op-amp 12 is corrected.

[0110] The hardware module includes a calibration voltage generator, a high-precision comparator, and a digital signal processor (DSP) core (which can be a microcontroller IP). Calibration data is stored in on-chip one-time programmable (OTP) memory. The calibration process is completed within 1ms and does not affect normal operation.

[0111] In some embodiments, under low-power scenarios, pulse width modulation (PWM) technology is used to dynamically control the duty cycle of the gain adjustment operational amplifier 12, thereby reducing static power consumption while ensuring compensation accuracy.

[0112] The PWM control strategy includes: when the input voltage change rate is below a threshold (e.g., 1V / μs), entering a low-power mode: the op-amp only operates during the high level of the PWM pulse (duty cycle D is adjustable), and is turned off during the low level to save current. The pulse frequency is matched to the input signal bandwidth (e.g., 10kHz) to ensure that the op-amp is active during the critical range of signal changes (rising / falling edges). An integrated edge detection circuit monitors the rising / falling edges of the input voltage in real time, forcing the op-amp to operate for the full cycle when an edge arrives, avoiding dynamic response lag. For example, when a rising edge of the input voltage is detected, the PWM duty cycle is temporarily increased to 100% for 500ns to ensure that the well voltage tracks changes in a timely manner.

[0113] This application uses a gain-adjusting operational amplifier 12 to adjust the well region potential in real time, and utilizes capacitive coupling to change the internal vertical electric field of the polysilicon resistor 11, dynamically optimizing its voltage coefficient. This significantly suppresses resistance drift caused by input voltage variations and improves amplifier gain linearity. The circuit provided in this application eliminates the need for fixed bias or complex calibration networks, enabling effective operation over a wide input voltage range, reducing reliance on external calibration circuits and improving system robustness. Furthermore, the circuit is implemented using standard CMOS technology, and the capacitive coupling structure between the polysilicon resistor 11 and the well region is easy to integrate without adding extra process steps, balancing performance improvement and cost control.

[0114] Please refer to the foregoing embodiments. Figure 4 This application also provides a schematic diagram of an electronic device 30. The electronic device 30 includes a resistor-voltage coefficient compensation circuit 10 in an adjustable gain amplifier provided in any embodiment of this application.

[0115] In some embodiments, the resistor-voltage coefficient compensation circuit 10 in the adjustable gain amplifier includes a polysilicon resistor 11 and a gain-adjusting operational amplifier 12. The polysilicon resistor 11 is disposed on an insulating layer above the well region and includes two resistor interfaces and a well region interface. The polysilicon resistor 11 is connected in series with a preset operational amplifier 20 through the resistor interfaces. The input terminal of the gain-adjusting operational amplifier 12 is connected to any one of the resistor interfaces, and the output terminal is connected to the well region interface. This is used to adjust the output voltage according to the input voltage to change the potential of the well region relative to the polysilicon resistor 11. Through capacitive coupling, it affects the internal depletion state and band structure of the polysilicon resistor 11 in the direction perpendicular to its length, thereby optimizing the resistor-voltage coefficient of the polysilicon resistor 11.

[0116] In some embodiments, electronic device 30 can be a high-precision measuring instrument, such as a digital multimeter, oscilloscope, spectrum analyzer, precision data acquisition card, etc.

[0117] In some embodiments, electronic device 30 may be a communication and radio frequency device, such as a wireless transceiver module (e.g., a 5G / 6G communication module), a radio frequency power amplifier, a signal modem, etc.

[0118] Because impedance matching and gain control in RF circuits require extremely high resistor stability, voltage fluctuations can introduce phase noise and gain errors due to changes in resistance. This circuit dynamically adjusts the well bias voltage to ensure that the bias resistor remains linear under the high voltage swing of RF signals (such as 28GHz millimeter waves), thereby improving modulation accuracy (e.g., reducing the error vector amplitude EVM of QAM signals).

[0119] In some embodiments, electronic device 30 may be a power management and energy conversion device, such as a DC-DC converter (e.g., a buck / boost chip), a battery management system (BMS), a wireless charging controller, a photovoltaic inverter, etc.

[0120] In power supply circuits, the stability of the bias resistor directly affects the accuracy of the output voltage. For example, in the battery voltage sampling circuit of a BMS, the voltage coefficient compensation of the polysilicon resistor can control the sampling error to within 0.1%, avoiding the risk of overcharging / over-discharging. In the power amplifier circuit of a wireless charging receiver, which has a wide input voltage range (0-20V), the circuit uses dynamic bias adjustment to suppress the decrease in resistance value under high voltage, ensuring stable power transmission efficiency.

[0121] In some embodiments, the electronic device 30 can be an industrial control and sensor interface device, such as an industrial sensor (pressure / temperature sensor signal conditioning module), a PLC control module, a motor drive controller, etc.

[0122] Due to voltage fluctuations (such as transient high voltage caused by motor start-stop) and temperature changes in industrial environments, the amplification of sensor signals (such as mV-level thermocouple signals) is easily affected by resistance stability. This circuit, through geometric optimization and adaptive gain adjustment, ensures that signal amplification errors are controlled within a preset temperature range, thereby improving the reliability of industrial automation systems.

[0123] In some embodiments, the electronic device 30 may be a high-end audio decoder (DAC), a noise-canceling headphone chip, a fitness tracker (physiological signal acquisition module), a drone flight control sensor, etc.

[0124] In audio decoding circuits, resistor stability affects the signal-to-noise ratio (SNR). This circuit can reduce total harmonic distortion (THD) and improve sound quality. In battery-powered scenarios (3.3V~5V) of portable devices, the low-power design of pulse width modulation reduces quiescent current, extends battery life, and ensures high-precision acquisition of physiological signals such as heart rate sensors (improved noise suppression ratio).

[0125] In some embodiments, the electronic device 30 may be an electrocardiograph (ECG), a blood pressure monitor, a blood glucose meter, a medical imaging device (such as an MRI signal preprocessing module), etc.

[0126] In some embodiments, the electronic device 30 may be an aviation sensor (barometric pressure / accelerometer), an automotive electronic control unit (ECU), an autonomous driving camera signal processing chip, etc.

[0127] In aerospace environments, voltage fluctuations are large (e.g., 28V±10%) and temperature ranges are wide (e.g., -55℃~125℃). This circuit, through geometric optimization and voltage coefficient model compensation, ensures the resistance change rate under extreme conditions, avoiding signal misinterpretation by the flight control system. When used as a sensor interface circuit for automotive ECUs, it can suppress common-mode noise caused by engine electromagnetic interference (EMI), improve the acquisition accuracy of key signals such as brake pressure sensors, and ensure driving safety.

[0128] Based on the numerous embodiments described above, the provided electronic device 30 can also be a scientific instrument (such as a spectrometer or chromatograph signal amplification module), a quantum computing auxiliary circuit (weak signal detection), a precision temperature control device (thermocouple signal amplification), etc. To meet the requirements of extremely low noise and high stability, an adjustable resistor combined with an adaptive algorithm achieves full-condition compensation of the resistance-voltage coefficient, satisfying the extreme accuracy requirements of cutting-edge technology fields. Therefore, this application does not limit the type of electronic device 30.

[0129] This application solves the signal amplification accuracy problem under wide voltage and complex environments by dynamically compensating the resistor voltage coefficient. It is applicable to all analog circuit systems that rely on high-precision resistor feedback, and has significant advantages in fields with stringent requirements for signal stability, such as high-precision measurement, communication, power management, industrial control, and medical equipment.

[0130] The specific principle and implementation of the electronic device 30 provided in this application embodiment are similar to the resistor voltage coefficient compensation circuit 10 in the adjustable gain amplifier of the aforementioned embodiment, and will not be repeated here.

[0131] It should be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. It should be understood that when an element or layer is referred to as “on,” “adjacent to,” “connected to,” or “coupled to” other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion.

[0132] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0133] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0134] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0135] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A resistance voltage coefficient compensation circuit in a tunable gain amplifier, characterized by, include: A polysilicon resistor is disposed on an insulating layer above a well region and includes two resistor interfaces and a well region interface. The polysilicon resistor is connected in series with a preset operational amplifier through the resistor interfaces. A gain-adjusting operational amplifier is provided, with its input terminal connected to any of the resistor interfaces and its output terminal connected to the well interface. It is used to adjust the output voltage Vout according to the input voltage Vin to change the potential of the well region relative to the polysilicon resistor. Through capacitive coupling, it affects the internal depletion state and band structure of the polysilicon resistor in the length direction perpendicular to the polysilicon resistor, thereby optimizing the resistance-voltage coefficient of the polysilicon resistor. The gain-adjustable operational amplifier includes: a gain resistor R2, bias resistors R3 and R4, an adjustable resistor R1, current sources I1 and I2, multiple PMOS transistors and multiple NMOS transistors. The PMOS transistors include MP1, MP2, MP3, MP4, MP5, MP6, MP7 and MP8, and the NMOS transistors include MN1, MN2 and MN3. The sources of MP1, MP2, MP3, MP6, MP7, and MP8 are connected to the power supply voltage VDD. The gate of MP1 is connected to the gate of MP2. The drain of MP1 is grounded via I1. The drain of MP2 is connected to the drain of MN1. The sources of MN1, MN2, and MN3 are grounded. The drain of MP4 is grounded via R3. The drain of MP5 is grounded via R4. The gate and drain of MP2 are connected. The gate of MP3 is connected to the drain of MP1. The drain of MP3 is connected to the first terminal of R1. The drain of MP3 is also connected to the source of MP4. The gate of MP4 is connected to a voltage. The common-mode voltage is VCM. The gate of MP5 is connected to the input voltage Vin. The second terminal of R1 is connected to the source of MP5. The second terminal of R1 is also connected to the first terminal of R2. The second terminal of R2 is connected to the output voltage Vout. The drains of MP8 and MN3 are also connected to Vout. The gates of MN3 and MN2 are both connected to the drain of MP5. The drain of MN2 is connected to the drain of MP6. The gate of MP6 is connected to the gate of MP7. The gate of MP6 is connected to the drain of MP6. The gate of MP8 is connected to the drain of MP7. The drain of MP7 is grounded through I2.

2. The circuit of claim 1, wherein, The input terminal of the gain-adjustable operational amplifier is connected between the polysilicon resistor and the operational amplifier, and is used to acquire the input voltage signal to be amplified and apply the adjusted bias voltage to the well region of the polysilicon resistor.

3. The circuit of claim 1, wherein, The length of the polycrystalline silicon resistor is greater than or equal to 18 μm; and / or, The width of the polycrystalline silicon resistor is greater than or equal to 2 μm.

4. The circuit of claim 1, wherein, It also includes a preset well region bias voltage calculation model, which is used to calculate the corresponding well region bias voltage based on the voltage coefficient corresponding to the polysilicon resistor, so as to adjust the resistance value of the adjustable resistor according to the well region bias voltage.

5. The circuit of claim 4, wherein, The construction method corresponding to the well region bias voltage calculation model includes: The material parameters of the polysilicon resistor, a preset working voltage range, a corresponding target voltage coefficient optimization threshold and resistance value change characteristics of the polysilicon resistor under different bias voltages are acquired, a mathematical correlation model of a well region bias voltage and an internal vertical electric field strength of the polysilicon resistor is established, an optimal well region bias voltage adjustment strategy corresponding to different input voltage amplitudes is determined through the mathematical correlation model, and a constructed well region bias voltage calculation model is acquired.

6. The circuit of claim 1, wherein, An expression of an output voltage corresponding to an output end of the gain-adjusted operational amplifier includes: Vout=Vin(R1+R2) / R1; wherein Vout is the output voltage, Vin is an input voltage corresponding to an input end of the gain-adjusted operational amplifier, R1 is a resistance value corresponding to the adjustable resistor, and R2 is a resistance value corresponding to the gain resistor.

7. An electronic device, comprising: The electronic device comprises the claim 1 6 any one of the adjustable gain amplifier in the resistance voltage coefficient compensation circuit.

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