Intelligent monitoring system for anti-interference signal decoder
The intelligent monitoring system, which integrates grounding status monitoring, dynamic compensation, and multi-source temperature monitoring, solves the grounding reliability and heat dissipation problems of the anti-interference signal decoder in industrial environments, thereby improving the system's anti-interference capability and fault location efficiency.
Patent Information
- Application Number
- CN202511185264.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-22
- Publication Date
- 2025-11-14
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Existing anti-interference signal decoders suffer from problems such as insufficient grounding reliability, contradiction between heat dissipation and anti-interference, and limitations of passive protection in industrial environments, especially near strong interference sources such as motors and frequency converters, which can lead to decoding distortion and hardware damage.
The grounding status monitoring module detects the grounding impedance in real time, the dynamic compensation control module activates the backup grounding path, and the multi-source temperature monitoring module combines a graded heat dissipation strategy with a fault tracing module to generate a failure root cause analysis report. The interface shielding monitoring unit and the shielding layer compensation unit enhance the system's anti-interference capability.
It improves the system's anti-interference stability and reliability, reduces maintenance costs, ensures hardware security and maintains stable system operation, and achieves accurate response to different interference sources and rapid fault location.
Smart Images

Figure CN120956585A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of intelligent monitoring, and more specifically to an intelligent monitoring system for an anti-interference signal decoder. Background Technology
[0002] Wired video transmission requires the compressed digital stream to be restored to a high-definition analog signal, but electromagnetic interference (EMI) can cause decoding distortion, requiring a dedicated anti-interference design.
[0003] In industrial environments, decoders are often deployed near strong interference sources such as motors and frequency converters. Traditional solutions rely on metal casing shielding and physical grounding.
[0004] The existing technology CN218679194U has insufficient grounding reliability: it relies on manually adjusting the copper plate to contact the ground, but non-conductive surfaces cannot be grounded; the grounding terminal is not linked to the interface shielding layer, and cable-induced interference is directly transmitted into the circuit.
[0005] The contradiction between heat dissipation and anti-interference: The bottom copper plate blocks the heat dissipation channel, and the heat is accumulated by relying only on the side heat dissipation holes. The high temperature deteriorates the signal-to-noise ratio of the decoding chip and aggravates the bit error rate.
[0006] Limitations of passive protection: The filter only intercepts interference in fixed frequency bands and cannot cope with transient pulse interference. The suction cup of the mounting mechanism is prone to falling off in a vibration environment, which can disrupt the grounding continuity. Therefore, an intelligent monitoring system for anti-interference signal decoders is proposed. Summary of the Invention
[0007] The present invention solves the above-mentioned technical problems through the following technical solutions, the present invention comprising: The grounding status monitoring module is used to detect grounding impedance in real time and generate impedance anomaly signals; A multi-source temperature monitoring module is used to simultaneously collect chip temperature and ambient temperature; The dynamic compensation control module is used to perform the following operations in response to impedance abnormality signals: Activate the backup grounding path to reduce grounding impedance; A tiered heat dissipation strategy is triggered based on the correlation between chip temperature and ambient temperature. The fault tracing module generates a failure root cause analysis report based on the historical trends of impedance and chip temperature. The decoding error rate monitoring unit is used to collect decoding error rate data of the decoder in real time.
[0008] Furthermore, the grounding status monitoring module includes: The frequency sweep signal unit is used to inject a wideband current signal into the grounding loop; The impedance analysis unit is used to calculate the complex form of the grounding impedance by detecting the voltage phase difference and amplitude attenuation between the injection point and the return point. The compensation execution unit is used to switch the grounding loop to a low-impedance backup path when the real part of the complex form of the grounding impedance exceeds a safety threshold.
[0009] Furthermore, the complex form of the grounding impedance is calculated using the following formula: ; Where α is the voltage attenuation coefficient, which is the ratio of the voltage amplitude at the return point to the voltage amplitude at the injection point; Δϕ is the phase difference, that is, the difference between the phase of the voltage at the injection point and the phase of the voltage at the return point, V in I is the injection point voltage. in The injected broadband current signal, j is the imaginary unit, j 2 =−1.
[0010] Furthermore, the graded heat dissipation strategy includes: Level 1 response: Increase the speed of the heat dissipation device. The trigger condition is when the difference between the chip temperature and the reference temperature (ΔT) reaches the first preset range (e.g., 5℃≤ΔT<15℃), or when the temperature rise rate is in the low rate range (e.g., ≤0.5℃ / s). Secondary response: Dynamically reduce the main frequency of the decoding chip according to the temperature rise rate. The triggering conditions are when the difference between the chip temperature and the reference temperature (ΔT) exceeds the first preset range and reaches the second preset range (e.g., 15℃≤ΔT<30℃), or when the temperature rise rate exceeds the low rate range (e.g., 0.5℃ / s<v≤2℃ / s). Level 3 response: When the rate of temperature change exceeds the critical threshold, the trigger condition is that the difference (ΔT) between the chip temperature and the reference temperature reaches the danger range (e.g., ΔT≥30℃, this range is set based on the upper limit of ΔT of 30℃ for Level 2 response). Or the rate of temperature rise (v) is in the high rate range (e.g., v > 2℃ / s, which is set based on the upper limit of the second-order response rate of 2℃ / s). Or chip temperature (T) j ) reaches the hardware failure threshold (e.g., T) j ≥85℃ (This threshold is based on the chip's rated maximum withstand temperature). The reference temperature is the normal temperature of the decoding chip under rated operating conditions.
[0011] Furthermore, the reduction in the decoding chip's main frequency in the secondary response is achieved through the following formula: ; Where κ is the temperature sensitivity coefficient, the value of which is determined according to the model and performance parameters of the decoding chip, and the value range is 0.001-0.01; ΔT is the difference between the real-time temperature and the reference temperature, the reference temperature is the normal temperature of the decoding chip under rated working conditions, and the value ranges from 25-40℃; and f0 is the rated main frequency of the decoding chip.
[0012] Furthermore, the fault tracing module performs fault tracing analysis in the following manner: Constructing a time evolution model of grounding impedance: By collecting grounding impedance data at different time points, a model is established using linear regression or exponential fitting methods to identify mechanical structure degradation or chemical corrosion characteristics; Monitoring high-frequency impedance characteristics: When the high-frequency impedance exhibits oscillating characteristics, it is determined to be an electromagnetic compatibility design defect.
[0013] Furthermore, the system also includes: An interface shielding monitoring unit is used to detect the continuity resistance between the external interface shielding layer and the grounding terminal. The shielding compensation unit is used to force the shielding layer to switch to the backup grounding path when the on-resistance is abnormal.
[0014] Furthermore, the dynamic compensation control module integrates an adaptive optimization algorithm, the specific implementation of which includes the following: Data acquisition: Continuously collect data on grounding impedance, chip temperature, and decoding error rate; Threshold adjustment: Dynamically adjust the grounding safety threshold and heat dissipation trigger threshold based on the collected data; Optimization objective: The core optimization objective is to maximize the system's anti-interference stability; Algorithm flow: First, initialize the grounding safety threshold and heat dissipation trigger threshold. Then, calculate the system status evaluation value based on the collected data. If the evaluation value is not optimal, adjust the threshold and re-collect data to calculate the evaluation value. Repeat the above process until the evaluation value reaches the optimal value.
[0015] Furthermore, the adaptive optimization algorithm calculates the system state evaluation value using the following function, as follows: ; Where, r t η1, η2, and η3 are system state evaluation values used to measure whether the current system state has reached its optimum. The higher the evaluation value, the better the system state. η1, η2, and η3 are dynamic weighting coefficients, whose values are determined according to the importance of each indicator under different system operating states, and satisfy η1 + η2 + η3 = 1. error Z represents the decoding error rate. g For grounding impedance; Z target θ(T) represents the target grounding impedance.j This is a temperature penalty term. When the chip temperature Tj exceeds the normal operating temperature range, its value increases with the temperature; when the chip temperature is within the normal range, its value is 0.
[0016] Furthermore, the multi-source temperature monitoring module calculates the chip temperature using a thermal network model: ; Where T j The temperature of the decoding chip; T s ω is the surface temperature of the decoding chip; ω is the thermal resistance parameter, the value of which is determined by the chip's package type and heat dissipation structure; P is the power consumption of the decoding chip; T a For ambient temperature; Φ(T) a ) is the ambient temperature compensation function, and its value takes the following rules: when the ambient temperature T a Within the normal range, Φ(T) a )=1; when T a When it exceeds the normal range, Φ(T) a Linear adjustments are made based on the degree of deviation.
[0017] Compared with existing technologies, this invention has the following advantages: The intelligent monitoring system for anti-interference signal decoders uses a grounding status monitoring module to detect grounding impedance in real time, and a dynamic compensation control module to activate a backup grounding path to reduce impedance when abnormal impedance occurs. Combined with the interface shielding monitoring unit's monitoring of the external interface shielding layer and the compensation mechanism for switching backup grounding paths, this solves the problem of single protection type in existing security protection systems. It enhances the overall anti-interference performance of the system from both grounding stability and shielding reliability perspectives. A multi-source temperature monitoring module simultaneously collects chip temperature and ambient temperature, and a tiered heat dissipation strategy is implemented (first level: increasing the speed of the heat dissipation device; second level: dynamically reducing the chip's main frequency; third level: cutting off the power supply and initiating emergency cooling). It can respond precisely to temperature differences and rates of change, preventing chip damage due to high temperatures, ensuring hardware safety and maintaining stable system operation. The fault tracing module can generate a failure root cause analysis report by constructing a grounding impedance time evolution model and monitoring high-frequency impedance characteristics. This helps to quickly locate problems such as mechanical structure degradation, chemical corrosion, or electromagnetic compatibility design defects, reducing maintenance costs and improving system availability. The adaptive optimization algorithm integrated into the dynamic compensation control module continuously collects grounding impedance, chip temperature, and decoding error rate data, and dynamically adjusts the grounding safety threshold and heat dissipation trigger threshold to maximize system anti-interference stability. This achieves adaptive optimization of system performance and improves overall operating efficiency.
[0018] Through multi-dimensional monitoring, dynamic compensation, precise temperature control, and intelligent optimization, the problem of single protection type and poor protection effect of existing security protection systems has been effectively solved, and the stability, reliability and anti-interference capability of anti-interference signal decoders have been significantly improved. Attached Figure Description
[0019] Figure 1 This is a system block diagram of the present invention. Detailed Implementation
[0020] The embodiments of the present invention are described in detail below. These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation processes. However, the scope of protection of the present invention is not limited to the following embodiments.
[0021] like Figure 1 As shown, this embodiment provides a technical solution: an intelligent monitoring system for anti-interference signal decoders, comprising: The grounding status monitoring module is used to detect grounding impedance in real time and generate impedance anomaly signals; A multi-source temperature monitoring module is used to simultaneously collect chip temperature and ambient temperature; The dynamic compensation control module is used to perform the following operations in response to impedance abnormality signals: Activate the backup grounding path to reduce grounding impedance; A tiered heat dissipation strategy is triggered based on the correlation between chip temperature and ambient temperature. The fault tracing module generates a failure root cause analysis report based on the historical trends of impedance and chip temperature. The decoding error rate monitoring unit is used to collect decoding error rate data of the decoder in real time.
[0022] The grounding status monitoring module includes: The frequency sweep signal unit is used to inject a wideband current signal into the grounding loop. Compared with a single frequency signal, the frequency sweep signal unit can cover the impedance characteristics of the grounding loop at different frequencies (especially in high-frequency interference scenarios), avoid monitoring blind spots caused by a single frequency, and ensure comprehensive monitoring of various frequency bands that may affect grounding performance. The impedance analysis unit is used to calculate the complex form of the grounding impedance by detecting the voltage phase difference and amplitude attenuation between the injection point and the return point. The complex impedance includes both amplitude (reflecting the magnitude of the impedance) and phase (reflecting the inductive and capacitive components) information. Compared with only monitoring the resistance value (real number), it can more realistically reflect the electrical characteristics of the grounding loop, such as changes in contact inductance / capacitance caused by corrosion or loosening, making the judgment of impedance anomalies more accurate. The compensation execution unit is used to switch the grounding loop to a low-impedance backup path when the real part of the complex-form grounding impedance exceeds a safety threshold. The unit specifies that switching to a low-impedance backup path occurs when the real part of the complex-form grounding impedance exceeds the safety threshold; the real part corresponds to the active power loss of the grounding loop, and its exceeding the threshold directly reflects a deterioration in grounding performance (such as increased impedance due to poor contact). By actively switching to the backup path, the grounding impedance can be quickly reduced, restoring the grounding system's anti-interference capability and avoiding problems such as signal interference and equipment malfunctions caused by poor grounding.
[0023] By refining the hardware components and operating logic of grounding status monitoring, the comprehensiveness, accuracy, and anomaly response speed of grounding monitoring have been significantly improved, providing a core guarantee for the anti-interference stability of the entire system.
[0024] The complex form of the grounding impedance is calculated using the following formula: ; Where α is the voltage attenuation coefficient, which is the ratio of the voltage amplitude at the return point to the voltage amplitude at the injection point; Δϕ is the phase difference, that is, the difference between the phase of the voltage at the injection point and the phase of the voltage at the return point, V in I is the injection point voltage. in The injected broadband current signal, j is the imaginary unit, j 2 =−1; formula In the middle, V in The injection point voltage (a fixed value, output by the frequency sweep unit); I in This represents the injected broadband current (a constant value to ensure comparability). α = Injection point voltage amplitude / Return point voltage amplitude (voltage attenuation coefficient, reflecting circuit loss); Δϕ represents the phase difference between the voltage at the injection point and the return point (reflecting inductive / capacitive characteristics, unit: degree).
[0025] Substitute into scenario 1: Scenario 1: Normal grounding state (no fault); Background: The grounding circuit is firmly connected, without corrosion or loosening, and the resistance is mainly purely resistive with no obvious inductance / capacitance.
[0026] Parameter settings: Injected current I in =1A (constant output); Injection point voltage V in =5V (from V=I*R, the normal resistance R0=5Ω); Since the voltage at the return point has no attenuation (consistent with the injection point), α = 5V / 5V = 1; Phase synchronization (no inductive / capacitive delay), Δϕ=0°.
[0027] Complex impedance calculation: Substitute into the formula In the calculation, ; The conclusion at this point is: real part 5Ω (normal resistance), imaginary part 0Ω (no reactance), and grounding status is normal. Scenario 2: Oxidation of grounding terminal (resistive fault); Background: Terminal oxidation forms a high-resistivity oxide layer, leading to increased grounding resistance. It is purely resistive with no change in inductance / capacitance. Parameter settings: Injected current I in =1A remains unchanged; Injection point voltage V in =5V remains unchanged (the sweep frequency unit output is constant); Oxidation causes the circuit resistance to increase to R=10Ω, which can be obtained from U=I*R. The return point voltage amplitude rises to 10V (the voltage increases with the increase of resistance), so α=10V / 5V=2. A purely resistive fault has no phase shift, Δϕ=0°.
[0028] Complex impedance calculation: ; Conclusion: When the real part increases to 10Ω, it exhibits resistive fault characteristics; the imaginary part remains 0. The system can trigger the backup grounding path if the real part exceeds the limit. Scenario 3: Loose grounding cable, inductive fault; Background: Loose cable connectors create tiny gaps, increasing the equivalent inductance.
[0029] Parameter settings: Injected current I in =1A remains unchanged; Injection point voltage V in =5V remains unchanged; The resistance remains 5Ω, but the gap causes a slight voltage drop, and the return point voltage amplitude drops to 4.5V. Therefore, α = 4.5V / 5V = 0.9. The inductance causes phase lag, with a phase difference Δϕ = 30°.
[0030] Complex impedance calculation: Substitute into the formula to calculate: ; The absolute value of the imaginary part is 2.25Ω, which increases significantly while the real part decreases slightly. The system can detect inductance abnormalities by changing the imaginary part and avoid high-frequency interference. The effect of inductance on impedance is more significant at high frequencies. This allows for a precise distinction between resistive faults (increased real part, such as 10+j0Ω in scenario 2) and inductive faults (increased absolute value of imaginary part, such as 3.897-j2.25Ω in scenario 3). All parameter settings (voltage, current, α and Δφ) conform to physical laws (such as voltage increase when resistance increases and phase lag when inductance increases), and the calculation results strictly correspond to the fault type, providing a quantitative basis for system fault judgment.
[0031] The graded heat dissipation strategy includes: Level 1 response: Increase the speed of the heat dissipation device. The trigger condition is when the difference between the chip temperature and the reference temperature (ΔT) reaches the first preset range (e.g., 5℃≤ΔT<15℃), or when the temperature rise rate is in the low rate range (e.g., ≤0.5℃ / s). Secondary response: Dynamically reduce the main frequency of the decoding chip according to the temperature rise rate. The triggering conditions are when the difference between the chip temperature and the reference temperature (ΔT) exceeds the first preset range and reaches the second preset range (e.g., 15℃≤ΔT<30℃), or when the temperature rise rate exceeds the low rate range (e.g., 0.5℃ / s<v≤2℃ / s). Level 3 response: When the rate of temperature change exceeds the critical threshold, the trigger condition is that the difference (ΔT) between the chip temperature and the reference temperature reaches the danger range (e.g., ΔT≥30℃, this range is set based on the upper limit of ΔT of 30℃ for Level 2 response). Or the rate of temperature rise (v) is in the high rate range (e.g., v > 2℃ / s, which is set based on the upper limit of the second-order response rate of 2℃ / s). Or chip temperature (T) j ) reaches the hardware failure threshold (e.g., T) j ≥85℃ (This threshold is based on the chip's rated maximum withstand temperature). The reference temperature is the normal temperature of the decoding chip under rated operating conditions. The graded heat dissipation strategy sets three response thresholds based on the difference (ΔT) between the chip temperature and the reference temperature and the temperature rise rate, such as the range of 5℃, 15℃ and 30℃ for ΔT, and the range of temperature rise rate of ≤0.5℃ / s, 0.5-2℃ / s and greater than 2℃ / s. This avoids a one-size-fits-all approach to heat dissipation control, such as relying on a single temperature threshold.
[0032] For example: With a slight temperature increase, when 5℃≤ΔT<15℃, only the heat dissipation speed is increased, i.e., first-order response, without sacrificing performance; The clock speed is reduced only when the temperature rises to a moderate level (15℃≤ΔT<30℃), which is a level 2 response, to balance heat dissipation and performance. In case of emergency heating exceeding 2℃ / s or reaching a dangerous threshold, power is immediately cut off for cooling, i.e., a level three response, prioritizing hardware safety.
[0033] This on-demand response mechanism ensures that heat dissipation measures are matched with temperature risks, avoiding over-intervention (such as frequency reduction when there is a small temperature difference) or under-response (such as failure to handle high temperatures in a timely manner).
[0034] The tiered strategy avoids the limitations of a single measure through step-by-step intervention: Level 1 response only adjusts the speed of the heat dissipation device, which is a passive heat dissipation enhancement and does not affect the operating performance of the decoding chip. It is suitable for scenarios with slight temperature abnormalities and ensures efficient system operation. The secondary response actively controls the temperature by reducing the main frequency, rather than directly cutting off the power. When the temperature rises but does not reach the dangerous value, the system continues to run with controllable performance loss. For example, high-frequency decoding tasks can temporarily reduce the frequency to maintain basic functions. Level 3 response serves as a last line of defense, activating only when a sharp increase in temperature could damage the hardware, minimizing unnecessary downtime.
[0035] The combination of these three elements enables dynamic switching between performance priority, performance and heat dissipation balance, and safety priority, taking into account both system availability and hardware protection.
[0036] Furthermore, the trigger thresholds for each level of response were clearly defined, such as the specific range of ΔT and the numerical range of the temperature rise rate, thus transforming the heat dissipation strategy from a qualitative description to quantitative execution.
[0037] For example, when the rate of temperature rise is ≤0.5℃ / s, it is determined to be a slow temperature rise, requiring only a first-order response; When the rate is greater than 2℃ / s, it is determined to be a rapid temperature rise, and a level 3 response is directly initiated.
[0038] Clear quantitative standards avoid subjective judgment errors, ensure that heat dissipation measures can be accurately triggered in different scenarios, and improve the stability and reliability of system control.
[0039] In practical applications, decoder temperature changes can be influenced by various factors such as ambient temperature and decoding load (e.g., power consumption surges during high-bandwidth signal decoding). Temperature rise patterns are diverse, ranging from slow accumulation to sudden spikes. A tiered strategy, by simultaneously monitoring both the temperature difference (reflecting cumulative temperature rise) and the rate of rise (reflecting the urgency of the temperature increase), can cover different types of temperature anomalies. For slow, cumulative temperature increases, such as a gradual rise in ambient temperature, a first- or second-order response is triggered by the ΔT threshold. For sudden spikes, such as rapid temperature rise caused by chip short circuits, a three-level response is triggered preferentially based on the rate threshold.
[0040] This multi-dimensional monitoring ensures the adaptability of the heat dissipation strategy to complex scenarios and improves the system's anti-interference ability in changing environments.
[0041] The reduction of the decoding chip's main frequency in the second-level response is achieved through the following formula: ; Where κ is the temperature sensitivity coefficient, the value of which is determined according to the model and performance parameters of the decoding chip, and the value range is 0.001-0.01; ΔT is the difference between the real-time temperature and the reference temperature, the reference temperature is the normal temperature of the decoding chip under rated working conditions, and the value ranges from 25-40℃; and f0 is the rated main frequency of the decoding chip. The formula uses the exponential relationship between the temperature sensitivity coefficient κ and the real-time temperature difference ΔT to strictly link the magnitude of the frequency reduction to the degree of temperature anomaly: When the temperature difference is small, such as ΔT close to 15℃, the frequency reduction is small because the exponential function decays slowly when ΔT is small, so as to preserve the chip performance as much as possible. When the temperature difference increases, such as when ΔT approaches 30℃, the frequency reduction increases exponentially with ΔT, the decay accelerates, and the chip power consumption is reduced rapidly. Power consumption is positively correlated with the main frequency, thus enhancing the temperature control effect.
[0042] The dynamic characteristic of more significant frequency reduction with greater temperature difference avoids the rigidity of fixed-ratio frequency reduction and achieves a balance between temperature control requirements and performance retention.
[0043] The κ value in the formula is determined based on the model and performance parameters of the decoding chip (ranging from 0.001 to 0.01), allowing for customized temperature sensitivity coefficients for different chips, such as high-power and low-power chips. For chips with poor high-temperature tolerance, such as precision decoding chips, a larger κ value can be set, such as 0.01, so that a slight increase in temperature difference will significantly reduce the frequency. For chips with strong high-temperature tolerance, a smaller κ value (such as 0.001) can be set to reduce unnecessary performance loss.
[0044] This flexibility ensures that the formula can be adapted to diverse hardware requirements, enhancing system versatility.
[0045] As a specific implementation method for the secondary response, the formula clarifies when and by how much to reduce the frequency, transforming the tiered heat dissipation strategy from a qualitative description into an executable quantitative operation. For example, when ΔT enters the 15-30℃ range, the system can directly calculate the new main frequency using the formula without manual intervention, ensuring the consistency and reliability of the heat dissipation measures. For example, a certain decoding chip has a rated main frequency f0=2GHz, a reference temperature of 30℃ (normal operating temperature), and a temperature sensitivity coefficient κ=0.005 (set for this chip model).
[0046] Case 1: ΔT = 15℃ (low range of second-order response); Real-time temperature = Base temperature + 15℃ = 45℃, substituting into the formula: ; The frequency reduction is approximately 7.2% (only a slight reduction), which retains most of the performance while controlling the temperature.
[0047] Case 2: ΔT = 25℃ (high range of second-order response); Real-time temperature = 30℃ + 25℃ = 55℃, substitute into the formula: ; The frequency reduction is about 11.8%, which is more than the frequency reduction when ΔT=15℃. By reducing the frequency more significantly, power consumption is reduced and temperature rise is quickly suppressed.
[0048] The fault tracing module performs fault tracing analysis in the following manner: Constructing a time evolution model of grounding impedance: By collecting grounding impedance data at different time points, a model is established using linear regression or exponential fitting methods to identify mechanical structure degradation or chemical corrosion characteristics; Monitoring high-frequency impedance characteristics: When oscillating characteristics are observed in the high-frequency impedance, it is determined to be an electromagnetic compatibility design defect; The fault tracing module uses two differentiated analysis methods to accurately distinguish the root causes of different types of faults: For mechanical structural degradation (such as loose grounding terminals and worn connectors) or chemical corrosion (such as metal oxidation and damp rust), the impedance changes of such faults can be identified by grounding impedance time evolution models (linear regression or exponential fitting). These faults exhibit gradual and trend-like characteristics (such as linear growth or exponential decay). The model can capture these characteristics by tracking long-term data. For example, the impedance caused by corrosion increases by 0.5Ω per month, which conforms to a linear trend. For electromagnetic compatibility design defects, such as unreasonable grounding loop wiring or high-frequency interference caused by shielding failure, the impedance of such faults can be identified by monitoring the impedance oscillation characteristics in the high-frequency band. The impedance of such faults will show periodic fluctuations or sudden changes (non-gradual) in the high-frequency band (such as radio frequency and electromagnetic pulse band), which is completely different from the trend changes of mechanical / chemical faults.
[0049] The classification and tracing mechanism avoids the problem of general attribution in traditional fault analysis, such as knowing only that the impedance is abnormal but not being able to determine whether it is a corrosion or electromagnetic compatibility problem, making fault location more accurate.
[0050] The time evolution model of grounding impedance can identify degradation trends before a fault fully occurs through long-term data acquisition and fitting analysis.
[0051] For example, if the model shows that the grounding impedance is increasing linearly at a rate of 0.1Ω / day, which is far beyond the normal loss rate, it can be determined in advance that the mechanical structure may be loose or begin to corrode, and early warning and maintenance can be carried out before the impedance reaches the safety threshold. Compared to simply monitoring real-time impedance values, which often only triggers alarms when the fault is severe, this trend prediction can significantly reduce the risk of sudden downtime and improve the system's preventative maintenance capabilities.
[0052] A clear root cause analysis report can directly guide the maintenance direction: If the problem is determined to be mechanical structural degradation, maintenance personnel can specifically check mechanical components such as connectors and fasteners, without blindly checking the circuit or shielding layer. If the problem is determined to be an electromagnetic compatibility design flaw, the grounding wiring can be optimized, the shielding layer strengthened, or the filter circuit adjusted to avoid repeated testing and ineffective mechanical maintenance.
[0053] This targeted troubleshooting setup significantly shortens troubleshooting time and reduces trial-and-error costs, such as eliminating the need to replace undamaged parts.
[0054] The system also includes: An interface shielding monitoring unit is used to detect the continuity resistance between the external interface shielding layer and the grounding terminal. The shielding compensation unit is used to force the shielding layer to switch to the backup grounding path when the on-resistance is abnormal. The external interface is the window through which the decoder connects to external devices. The grounding status of its shielding layer directly affects the anti-interference capability. If the shielding layer and the grounding terminal are not properly connected, such as if the conduction resistance is too high, the shielding will fail, and external electromagnetic interference can easily enter the system through the interface, interfering with the decoding signal.
[0055] The interface shielding monitoring unit is specifically designed to detect the continuity resistance between the shielding layer and the grounding terminal, filling the monitoring blind spot in traditional systems that only focus on the main grounding loop and ignore the interface shielding layer. This extends the system from main grounding protection to interface shielding protection, forming a closed-loop anti-interference system across the entire link.
[0056] To achieve rapid response and proactive compensation for shielding failure; When the on-resistance of the interface shielding layer becomes abnormal, such as due to poor contact caused by vibration or oxidation, the resistance increases from the normal 0.1Ω to more than 5Ω. The shielding layer compensation unit can immediately force the shielding layer to switch to the backup grounding path, quickly restore the effective connection between the shielding layer and the grounding terminal, and the on-resistance drops back to a safe range.
[0057] It achieves closed-loop response, avoiding the problem of continuous interference intrusion after the shielding layer fails. Traditional systems may not discover the shielding problem until decoding fails, at which point the interference has already caused an impact, significantly improving the real-time performance of anti-interference.
[0058] The interface is the first barrier for external signals to enter the decoder. If the shielding fails, interference signals can easily couple with the useful signals. For example, if high-frequency interference is superimposed on the decoding signal, it will directly lead to an increase in the decoding error rate.
[0059] By ensuring that the shielding layer is always effectively grounded, external interference can be blocked from entering through the interface to the greatest extent, reducing decoding errors caused by interface shielding problems. This special protection can significantly improve decoding stability, especially for decoders in high-frequency, high-interference environments.
[0060] The dynamic compensation control module integrates an adaptive optimization algorithm, the specific implementation of which includes the following: Data acquisition: Continuously collect data on grounding impedance, chip temperature, and decoding error rate; Threshold adjustment: Dynamically adjust the grounding safety threshold and heat dissipation trigger threshold based on the collected data; Optimization objective: The core optimization objective is to maximize the system's anti-interference stability; Algorithm flow: First, initialize the grounding safety threshold and heat dissipation trigger threshold. Then, calculate the system status evaluation value based on the collected data. If the evaluation value is not optimal, adjust the threshold and re-collect data to calculate the evaluation value. Repeat the above process until the evaluation value reaches the optimal value. Traditional systems often have fixed values for grounding safety thresholds and heat dissipation trigger thresholds (such as frequency reduction when ΔT≥15℃), which are difficult to adapt to changing actual working conditions (such as ambient temperature fluctuations, decoder load changes, and hardware aging after long-term use).
[0061] This case involves continuously collecting real-time data such as grounding impedance, chip temperature, and decoding error rate, and dynamically updating thresholds (e.g., increasing the ΔT threshold triggered by heat dissipation in high-temperature environments to avoid frequent frequency reduction; and reducing the grounding safety threshold after the grounding loop ages to trigger compensation in advance).
[0062] For example, in a high-temperature environment in summer, the algorithm may adjust the ΔT threshold of the first-level heat dissipation from 5℃ to 8℃. As the ambient baseline temperature rises, this avoids initiating heat dissipation with slight temperature differences, making the threshold more in line with the actual scenario and reducing ineffective intervention.
[0063] Data acquisition covers three key dimensions: grounding impedance (electrical safety), chip temperature (hardware status), and decoding error rate (core functional indicator), rather than a single indicator (such as focusing only on temperature). This multi-dimensional linkage can avoid one-sided optimization. For example, if the grounding impedance is slightly high but the decoding error rate is normal, it may be a temporary fluctuation, and the algorithm will not blindly trigger the backup grounding path. If the temperature is normal but the bit error rate suddenly increases, it may be due to grounding interference. The algorithm will prioritize adjusting the grounding threshold rather than relying solely on temperature control.
[0064] By integrating multiple data sources, the system can more accurately determine the true state of affairs, ensuring that optimization measures directly address the core issues.
[0065] The goal is to maximize anti-interference stability and achieve global optimum. The core objective is clearly to maximize the system's anti-interference stability, rather than solely pursuing heat dissipation efficiency or minimizing grounding impedance. This holistic perspective balances the conflicting needs of various modules. For example, reducing the grounding impedance may require switching to an alternative path, but the algorithm will combine the bit error rate to make a judgment. If the current bit error rate has reached the standard, it may not be necessary to reduce the impedance excessively to avoid wasting energy. If frequency reduction and temperature control lead to increased decoding latency, the algorithm may adjust the heat dissipation threshold to prioritize decoding functionality.
[0066] An iterative optimization mechanism enables performance self-improvement during long-term operation.
[0067] The adaptive optimization algorithm calculates the system state evaluation value using the following function, as follows: ; Where, r t η1, η2, and η3 are system state evaluation values used to measure whether the current system state has reached its optimum. The higher the evaluation value, the better the system state. η1, η2, and η3 are dynamic weighting coefficients, whose values are determined according to the importance of each indicator under different system operating states, and satisfy η1 + η2 + η3 = 1. error Z represents the decoding error rate. g For grounding impedance; Z target The target grounding impedance; θ(T j () represents the temperature penalty term, which applies when the chip temperature T j When the temperature exceeds the normal operating temperature range, its value increases with increasing temperature; when the chip temperature is within the normal range, its value is 0. θ(T) within the normal range j )=0: When the chip temperature T j Within the normal temperature range of rated operation, θ(T) j =0, no penalty.
[0068] When out of range θ(T) j Linear increase: When T j Exceeding the normal range (e.g., >70℃), θ(T) j The value increases linearly with increasing temperature, and the magnitude of the increase is proportional to the degree of deviation from the normal range, meaning that it is adjusted linearly according to the degree of deviation.
[0069] θ(T j The specific process of determining the numerical value: Step 1: Define the normal temperature range; Reference temperature: The normal operating temperature of the decoding chip under rated working conditions, for example, 30℃.
[0070] Upper limit of normal range: reference temperature + safety margin, combined with the three-level response trigger condition T j ≥85℃, assuming a safety margin of 40℃, then the normal range is ≤70℃.
[0071] Step 2: Calculate the temperature deviation ΔT j ; ΔT j =T j -Upper limit of normal range. Example: T j =75℃, ΔT j =5℃; T j =85℃, ΔT j =15℃ Step 3: Determine the linear adjustment coefficient k; The principle for determining the value of k is: based on the chip's tolerance and the system optimization goals, a penalty weight for unit deviation is preset.
[0072] Example values: Level 1 response range (ΔT = 5-15℃): k = 0.1 / ℃ (θ(Tj) increases by 0.1 for every 1℃ increase); Level 2 response range (ΔT=15-30℃): k=0.2 / ℃ (higher risk at high temperatures, more severe penalties); Level 3 response range (ΔT≥30℃): k=0.5 / ℃ (approaching the hardware failure threshold, strong penalty).
[0073] Step 4: Calculate θ(T) j ): θ(Tj) = k × ΔT j For example: T j =75℃, ΔT j =5℃, k=0.1, then θ(T) j )=0.5;T j =85℃, ΔT j =15℃, k=0.2, then θ(T) j )=3; Definition; Moth three-level response threshold (e.g., T) j ≥85℃), θ(T) j The linear adjustment of the temperature risk level must be matched with the temperature risk level. Mild overheating (70-85℃): The penalty increases slowly with temperature, triggering frequency reduction (secondary response); Severe overheating (≥85℃): Penalty increases sharply, triggering power outage (Level 3 response).
[0074] It also needs to be matched with the target of the adaptive optimization algorithm; formula In, θ(T) j This needs to significantly affect the assessment value rt, forcing the system to prioritize handling high-temperature risks.
[0075] For example: when T j =85℃, θ(T) j )=3, (k=0.2), if η3=0.3, then the penalty term contributes -0.9, which is much greater than the bit error rate (e.g., R). error =0.01 contributes -0.003), ensuring that the system cools down first when the temperature is high.
[0076] The above process achieves a comprehensive quantitative evaluation of multi-dimensional indicators, integrating three key metrics: decoding error rate R. error Reflects the quality of core functions and grounding impedance deviation |Z g -Z target | reflects the basic anti-interference basis and the temperature penalty term θ(T) j This reflects hardware security, and uses a negative sign to convert the smaller the indicator (the better) into an evaluation value r. t The larger the better. This multi-dimensional integration avoids the one-sidedness of evaluation based on a single indicator (such as focusing only on the bit error rate may ignore grounding risks, or focusing only on temperature may sacrifice decoding performance), making the system status assessment more comprehensive.
[0077] The weighting coefficients η1, η2, and η3 (satisfying η1+η2+η3=1) can be adjusted according to the system's operating status. In high-interference environments (such as industrial sites), η2 (grounding impedance weight) can be increased to prioritize the protection of anti-interference foundations; When decoding tasks have high priority (such as real-time signal processing), η1 (bit error rate weight) can be increased to reduce decoding errors more effectively. In high-temperature environments, η3 (temperature weight) can be increased to prioritize avoiding hardware damage.
[0078] This flexibility allows the evaluation model to adapt to diverse scenarios, ensuring that the optimization direction is consistent with actual needs.
[0079] Provide clear quantitative targets for iterative optimization; System state evaluation value r t This is the core judgment criterion of the iterative optimization process; if the evaluation value does not reach the optimal level, the threshold is adjusted. This is achieved through r... t The numerical change of r can intuitively determine whether the optimization measures are effective, avoiding blind optimization. For example, after adjusting the grounding threshold, if r t An increase in r indicates that the measure is effective; if r increases... t If the value is reduced, adjustments must be made in the opposite direction to ensure that the optimization direction is correct.
[0080] For example, under normal working conditions and in non-extreme environments, the decoding task of a certain anti-interference signal decoder has a medium priority and the weighting coefficients are set as η1=0.3 (bit error rate), η2=0.4 (grounding), and η3=0.3 (temperature). Initial state: Decoding error rate Rerror = 0.02 (2%); Grounding impedance Zg = 8Ω, target grounding impedance Z target =5Ω, therefore |Z g -Z target |=3Ω; The chip temperature is within the normal range, θ(T) j )=0.
[0081] Calculate the evaluation value: r t =−0.3×0.02−0.4×3−0.3×0=−0.006−1.2=−1.206; Optimized status: The system adjusts the grounding threshold, triggers the backup grounding path, and the grounding impedance drops to Z. g =5.5Ω (close to the target), the bit error rate slightly decreased to R error =0.015, the temperature is still normal.
[0082] Calculate the evaluation value: r t =−0.3×0.015−0.4×∣5.5−5∣−0.3×0=−0.0045−0.4×0.5=−0.0045−0.2=−0.2045; After optimization r t The significant increase from -1.206 to -0.2045 indicates a better system state and verifies the effectiveness of the grounding adjustment measures. This demonstrates that by quantifying the changes in the evaluation value, the optimization effect can be clearly judged, guiding the system to continuously iterate towards the goal of maximizing anti-interference stability.
[0083] The multi-source temperature monitoring module calculates the chip temperature using a thermal network model. ; Where T j The temperature of the decoding chip; T s ω is the surface temperature of the decoding chip; ω is the thermal resistance parameter, the value of which is determined by the chip's package type and heat dissipation structure; P is the power consumption of the decoding chip; T a For ambient temperature; Φ(T) a ) is the ambient temperature compensation function, and its value takes the following rules: when the ambient temperature T a Within the normal range, Φ(T) a )=1; when T a When it exceeds the normal range, Φ(T)a Linear adjustment is performed based on the degree of deviation; Traditional temperature monitoring often directly uses the chip surface temperature (T). s ) instead of temperature (T) j However, temperature is the key indicator determining chip performance and lifespan, and surface temperature is often lower than ambient temperature, leading to measurement bias. The thermal network model in this case uses surface temperature (T...) as the basis for its solution. s ) + Thermal resistance (ω) × Power consumption (P) × Environmental compensation (Φ(T) a The combination of these two methods can reproduce the true internal temperature T of the chip. j This avoids the failure of heat dissipation strategies due to misjudgment of surface temperature, such as when the surface temperature is normal but the temperature is too high.
[0084] Ambient temperature T a It directly affects heat dissipation efficiency. For example, in high-temperature environments, chips heat up faster for the same power consumption. The formula Φ(T)... a (Ambient temperature compensation function) incorporates environmental factors into temperature calculations through linear adjustment (when the ambient temperature exceeds the normal range): Normal environment (e.g., T) a =25℃): Φ(T) a )=1, calculated according to conventional thermal resistance; High temperature environment (such as T) a =45℃, outside the normal range): Φ(T a An increase in the value (e.g., 1.2) reflects a decrease in heat dissipation efficiency, making the calculated temperature closer to the actual temperature (avoiding underestimation of temperature due to ignoring environmental influences).
[0085] Chip temperature is directly related to power consumption (P) (the higher the power consumption, the more severe the heat generation). The model uses power consumption as the core variable (ω·P term), enabling temperature calculation to respond in real time to changes in decoding load (such as a surge in power consumption during high-bandwidth decoding, resulting in a synchronous increase in the calculated temperature value), avoiding the lag of relying solely on static temperature monitoring.
[0086] The parameters of the thermal network model of a certain decoding chip are: Surface temperature T a =50℃ (actual value); Thermal resistance parameter ω = 0.5℃ / W (determined by package type); Current decoding power consumption P=10W (high load state); The normal range of ambient temperature is 20-35℃, Φ(T) a =1; when it exceeds this value, Φ(Ta) increases by 0.02 for every 1℃ increase.
[0087] Scenario 1: Normal ambient temperature (T) a =30℃); Environmental compensation function Φ(T)a =1 (because 30℃ is within the normal range); Temperature calculation: T j =50 + 0.5 × 10 × 1 = 55℃; Conclusion: The temperature of 55℃ is within a safe range (no need for strong heat dissipation). Scenario 2: Ambient temperature is abnormally high (T) a =40℃); The ambient temperature exceeds the normal range (40℃-35℃=5℃), therefore Φ(Ta)=1+5×0.02=1.1; Temperature calculation: T j =50 + 0.5 × 10 × 1.1 = 55.5℃; Comparison: If environmental compensation is ignored (based on Φ(T) a ()=1 calculation), will yield T j The calculated temperature is 55.5℃, but the actual temperature is 55.5℃ due to reduced heat dissipation efficiency caused by high ambient temperature. The model, after being corrected using a compensation function, is closer to the actual temperature, avoiding delays in heat dissipation response due to underestimating the temperature. Ambient temperature compensation function Φ(T) a The specific process of linear adjustment based on the degree of deviation is as follows: Determine the normal range of ambient temperature: First, determine the ambient temperature T. a The normal range.
[0088] Determine T a Is it within the normal range: When T a When within the normal range, Φ(T) a The value is fixed at 1 (no compensation required); When T a When the value exceeds the normal range (including below the lower limit or above the upper limit), linear adjustment is initiated.
[0089] Calculate the degree of deviation: Calculate T a The difference from the normal range boundary, i.e., the degree of deviation: If T a The deviation is greater than the upper limit of the normal range, and the degree of deviation is equal to T. a -Upper limit of normal range; If T a If the value is below the lower limit of the normal range, the degree of deviation is equal to the lower limit of the normal range minus Ta.
[0090] Linear adjustment Φ(T) a The value of Φ(T) is adjusted linearly according to the degree of deviation, i.e. a The adjustment amount is directly proportional to the degree of deviation: The greater the deviation, the more Φ(T) aThe larger the adjustment range, for example, for every 1°C deviation from the normal range, Φ(Ta) increases or decreases by a fixed coefficient, the specific coefficient is determined by the system based on the chip's heat dissipation characteristics; Φ(T a The core of the linear adjustment is that when the ambient temperature exceeds the normal range, its value changes linearly with the degree of deviation from the normal range, so as to reflect the impact of ambient temperature on the chip's heat dissipation efficiency.
[0091] Specific examples are as follows: The ambient temperature is within the normal range: When T a When the temperature is 25℃ (within the normal range of 20℃-35℃), according to the rules: Φ(T a ) = 1 (No need to adjust, just take 1).
[0092] Ambient temperature is above the upper limit of the normal range: When T a =40℃ (exceeding the upper limit of the normal range of 35℃, the deviation is 40-35=5℃): Φ(T a As the degree of deviation increases linearly, the calculation is as follows: Φ(T a =1 + (deviation degree × adjustment coefficient) =1 + (5℃ × 0.02) =1.1.
[0093] The ambient temperature is below the lower limit of the normal range: When T a =15℃ (below the lower limit of the normal range of 20℃, deviation = 20-15=5℃): Φ(T a The efficiency increases linearly with the degree of deviation (low temperatures can also affect heat dissipation efficiency; here we assume the adjustment logic is the same as at high temperatures), and the calculation is as follows: Φ(T a =1 + (deviation degree × adjustment coefficient) =1 + (5℃ × 0.02) =1.1.
[0094] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0095] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0096] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. An intelligent monitoring system for an anti-interference signal decoder, characterized in that, include: The grounding status monitoring module is used to detect grounding impedance in real time and generate impedance anomaly signals; A multi-source temperature monitoring module is used to simultaneously collect chip temperature and ambient temperature; The dynamic compensation control module is used to perform the following operations in response to impedance abnormality signals: Activate the backup grounding path to reduce grounding impedance; A tiered heat dissipation strategy is triggered based on the correlation between chip temperature and ambient temperature. The fault tracing module generates a failure root cause analysis report based on the historical trends of impedance and chip temperature. The decoding error rate monitoring unit is used to collect decoding error rate data of the decoder in real time.
2. The intelligent monitoring system for an anti-interference signal decoder according to claim 1, characterized in that: The grounding status monitoring module includes: The frequency sweep signal unit is used to inject a wideband current signal into the grounding loop; The impedance analysis unit is used to calculate the complex form of the grounding impedance by detecting the voltage phase difference and amplitude attenuation between the injection point and the return point. The compensation execution unit is used to switch the grounding loop to a low-impedance backup path when the real part of the complex form of the grounding impedance exceeds a safety threshold.
3. The intelligent monitoring system for an anti-interference signal decoder according to claim 2, characterized in that: The complex form of the grounding impedance is calculated using the following formula: ; Where α is the voltage attenuation coefficient, which is the ratio of the voltage amplitude at the return point to the voltage amplitude at the injection point; Δϕ is the phase difference, that is, the difference between the phase of the voltage at the injection point and the phase of the voltage at the return point, V in I is the injection point voltage. in The injected broadband current signal is denoted by j, which is the imaginary unit.
4. The intelligent monitoring system for an anti-interference signal decoder according to claim 1, characterized in that: The graded heat dissipation strategy includes: Level 1 Response: Increase the speed of the heat dissipation device. The trigger condition is when the difference between the chip temperature and the reference temperature reaches the first preset range, or when the temperature rise rate is in the low rate range. Level 2 response: Dynamically reduce the main frequency of the decoding chip according to the temperature rise rate. The triggering conditions are when the difference between the chip temperature and the reference temperature exceeds the first preset range and reaches the second preset range, or when the temperature rise rate exceeds the low rate range. Level 3 response: Power is cut off and emergency cooling is initiated. The trigger condition is that the difference between the chip temperature and the reference temperature reaches the danger range. Or the rate of temperature rise is in the high-rate range; Or the chip temperature reaches the hardware damage threshold; The reference temperature is the normal temperature of the decoding chip under rated operating conditions.
5. The intelligent monitoring system for an anti-interference signal decoder according to claim 4, characterized in that: The reduction of the decoding chip's main frequency in the second-level response is achieved through the following formula: ; Where κ is the temperature sensitivity coefficient; ΔT is the difference between the real-time temperature and the reference temperature; and f0 is the rated main frequency of the decoding chip.
6. The intelligent monitoring system for an anti-interference signal decoder according to claim 1, characterized in that: The fault tracing module performs fault tracing analysis in the following manner: Constructing a time evolution model of grounding impedance: By collecting grounding impedance data at different time points, a model is established using linear regression or exponential fitting methods to identify mechanical structure degradation or chemical corrosion characteristics; Monitoring high-frequency impedance characteristics: When the high-frequency impedance exhibits oscillating characteristics, it is determined to be an electromagnetic compatibility design defect.
7. The intelligent monitoring system for an anti-interference signal decoder according to claim 1, characterized in that: The system also includes: An interface shielding monitoring unit is used to detect the continuity resistance between the external interface shielding layer and the grounding terminal. The shielding compensation unit is used to force the shielding layer to switch to the backup grounding path when the on-resistance is abnormal.
8. The intelligent monitoring system for an anti-interference signal decoder according to claim 1, characterized in that: The dynamic compensation control module integrates an adaptive optimization algorithm, the specific implementation of which includes the following: Data acquisition: Continuously collect data on grounding impedance, chip temperature, and decoding error rate; Threshold adjustment: Dynamically adjust the grounding safety threshold and heat dissipation trigger threshold based on the collected data; Optimization objective: The core optimization objective is to maximize the system's anti-interference stability; Algorithm flow: First, initialize the grounding safety threshold and heat dissipation trigger threshold. Then, calculate the system status evaluation value based on the collected data. If the evaluation value is not optimal, adjust the threshold and re-collect data to calculate the evaluation value. Repeat the above process until the evaluation value reaches the optimal value.
9. The intelligent monitoring system for an anti-interference signal decoder according to claim 8, characterized in that: The adaptive optimization algorithm calculates the system state evaluation value using the following function, as follows: ; Where, r t The system state evaluation value is used to measure whether the current system state has reached the optimal state. The higher the evaluation value, the better the system state. η1, η2, and η3 are dynamic weighting coefficients. R error Z represents the decoding error rate. g For grounding impedance; Z target θ(T) represents the target grounding impedance. j () represents the temperature penalty item.
10. The intelligent monitoring system for an anti-interference signal decoder according to claim 1, characterized in that: The multi-source temperature monitoring module calculates the chip temperature using a thermal network model. ; Where T j The temperature of the decoding chip; T s ω is the surface temperature of the decoding chip; ω is the thermal resistance parameter, the value of which is determined by the chip's package type and heat dissipation structure; P is the power consumption of the decoding chip; T a For ambient temperature; Φ(T) a ) is the ambient temperature compensation function, and its value takes the following rules: when the ambient temperature T a Within the normal range, Φ(T) a )=1; when T a When it exceeds the normal range, Φ(T) a Linear adjustments are made based on the degree of deviation.
Citation Information
Patent Citations
Anti-interference signal decoder for video decoding
CN218679194U