A descriptor information aggregation method and module, data processing unit

Abstract

The application relates to a descriptor information aggregation method and module and a data processing unit, which comprises the following steps: receiving BD information and a qid of a current BD; determining the position of the current BD in a corresponding host side memory cache line according to the qid; obtaining the number of BD information of a target queue cached in a DPU cache module; when the position is the first storage position in the corresponding host side memory cache line, if the number of BD information is not an integer multiple of 0 or n, outputting all BD information of the target queue cached in the DPU cache module to a BD update module, so that the BD update module updates a BD ring table according to the all BD information, and writes the BD information of the current BD into the DPU cache module for caching; through the application, the problems of PCIE read time delay and read conflict caused by cross cache line update of descriptors can be solved.

Description

Technical Field

[0001] This application relates to the field of Virtio technology, specifically to a descriptor information aggregation method and module, and a data processing unit. Background Technology

[0002] In the Virtio system, data interaction between the Virtio driver and Virtio network devices is achieved through a virtual queue (Virtqueue). According to the Virtio specification, a Packed queue has only one descriptor ring table. Each buffer descriptor (BD) in the descriptor ring table contains the following fields: buffer cell address, buffer cell length, buffer cell ID, and flag information (Flag). The usage status (available / used) of the BD is managed through the VRING_DESC_F_AVAIL flag and the VRING_DESC_F_USED flag in the Flag field.

[0003] The packet receiving process for the Packed queue is as follows:

[0004] (1) The Virtio driver allocates a buffer unit for receiving packets, fills the buffer unit's address, length and ID into a BD, sets the Flag field of the BD to indicate that the BD is available, and then notifies the Virtio network device.

[0005] (2) Figure 1 This diagram illustrates the typical mapping between buffers (BDs) and packets in a Virtio network device's packed queue. One packet uses one BD. When a Virtio network device detects an incoming packet, it begins the packet reception process. The Virtio network device reads an available BD and writes the packet to the buffer pointed to by the currently read BD. After the write operation is complete, the Virtio network device updates the information of the currently used BD (including the actual packet length received by the buffer pointed to by the BD, the BufferID, and the Flag) to indicate that the BD is used. Then, it sends an interrupt signal to the Virtio driver to inform the Virtio driver that the packet has been received and stored in the buffer pointed to by the used BD.

[0006] (4) After receiving the interrupt signal, the Virtio driver reads the message from the buffer pointed to by BD and performs corresponding processing, such as parsing network data packets and updating the application state.

[0007] To conserve PCIe bandwidth, Virtio network devices aggregate BD information of used buffers. When the aggregation limit is reached or the waiting timeout occurs, the BD information of used buffers is output in batches to update multiple used buffers. Then, an interrupt signal is sent to the Virtio driver to inform the Virtio driver that the message has been received and stored in the buffers pointed to by multiple used buffers.

[0008] A cacheline is typically 64 bytes, and a buffer block (BD) is typically 16 bytes, meaning a cacheline contains 4 BDs. Read / write operations are performed line-by-line. Therefore, to facilitate the Virtio driver reading packets from the buffer sent by the Virtio network device, aggregation is performed based on an integer multiple (4, 8, 12, 16, etc.) of the number of BDs contained in a cacheline. For example, taking a maximum aggregation of 4 BDs as an example... Figure 2 As shown, when the Virtio network device waits for a timeout, it only aggregates one BD0. Therefore, it outputs only one BD0 to update it initially. Subsequent times, it aggregates four BD information before timeout. In the second time, it outputs and updates BD1-BD4 in batches, and in the third time, it outputs and updates BD5-BD8 in batches. Both BD1-BD4 and BD5-BD8 cross cache lines. Since read / write operations are performed on a cache line-by-cache basis, this means that updating BD1-BD4 requires read-modify-write operations on two cache lines (Cacheline0 and Cacheline1). Furthermore, if the Virtio driver is also reading BD0 from Cacheline0 while the Virtio network device is performing read-modify-write operations on Cacheline0, a read conflict will occur, increasing PCIe read latency and ultimately significantly reducing the performance of the Virtio system. Summary of the Invention

[0009] The purpose of this application is to propose a descriptor information aggregation method and module, and a data processing unit (DPU) to solve the PCIe read latency and read conflict problems caused by updating descriptors across cache lines.

[0010] To achieve the above objectives, according to a first aspect of this application, a descriptor information aggregation method is provided, applied to a data processing unit (DPU), the method comprising:

[0011] Retrieve the descriptor information and queue identifier of the current descriptor;

[0012] Query the current entry value of the target entry corresponding to the queue identifier in the cache line position table, determine the position of the current descriptor in the corresponding host-side memory cache line based on the current entry value, and update the entry value of the target entry; wherein, if the current entry value is n, the entry value of the target entry is updated to 0, and if the current entry value is less than n, the entry value of the target entry is updated to the current entry value plus one; n is the number of descriptors cached in one cache line on the host side;

[0013] Obtain the number of descriptor information entries for the target queue corresponding to the queue identifier cached in the DPU cache module;

[0014] When the location is the first storage location in the host-side memory cache line, if the number of descriptor information is not 0 or an integer multiple of n, then all descriptor information of the target queue cached in the DPU cache module is output to the descriptor update module, so that the descriptor update module updates the descriptor ring table according to all descriptor information, and writes the descriptor information of the current descriptor into the DPU cache module for caching.

[0015] In some embodiments, the method further includes:

[0016] When the location is the first storage location in the host-side memory cache line, if the number of descriptor information is 0 or an integer multiple of n, then the descriptor information of the current descriptor is written into the DPU cache module for caching.

[0017] In some embodiments, the method further includes:

[0018] When the location is not the first storage location in the host-side memory cache line, the descriptor information of the current descriptor is written into the DPU cache module for caching. If the number of descriptor information is equal to a preset upper limit value, all descriptor information of the target queue cached in the DPU cache module is output to the descriptor update module; the preset upper limit value is an integer multiple of n.

[0019] In some embodiments, the method further includes:

[0020] When the waiting time of any queue reaches a preset timeout threshold, at least one descriptor information of any queue cached in the DPU cache module is output to the descriptor update module, so that the descriptor update module updates the descriptor ring table according to the at least one descriptor information.

[0021] In some embodiments, obtaining the number of descriptor information entries for the target queue corresponding to the queue identifier cached in the DPU cache module includes:

[0022] Determine whether the DPU cache module has a queue linked list corresponding to the queue identifier based on the queue identifier;

[0023] If a corresponding queue list exists, the number of descriptor information entries of the target queue cached in the DPU cache module is determined based on the corresponding queue list.

[0024] If no corresponding queue list exists, the number of descriptor information is determined to be 0. The DPU cache module is requested to create a queue list corresponding to the queue identifier, and the descriptor information of the current descriptor is written into the created queue list for caching.

[0025] The queue list includes a head pointer, a tail pointer, and a number of descriptor information. The head pointer points to the storage address of the first descriptor information of the queue list in the DPU cache module, and the head pointer points to the storage address of the last descriptor information of the queue list in the DPU cache module.

[0026] In some embodiments, the method further includes:

[0027] After any descriptor information is output to the descriptor update module, the DPU cache resources occupied by the descriptor information are released.

[0028] According to a second aspect of this application, a descriptor information aggregation module is provided, comprising:

[0029] The BD information receiving unit is used to obtain the descriptor information and queue identifier of the current descriptor;

[0030] A cache line position unit is used to store a cache line position table, which includes multiple entries that correspond one-to-one with multiple queue identifiers.

[0031] The DPU caching module is used to cache descriptor information.

[0032] The BD position determination unit is used to query the current entry value of the target entry corresponding to the queue identifier in the cache line position table, determine the position of the current descriptor in the corresponding host-side memory cache line based on the current entry value, and update the entry value of the target entry; wherein, if the current entry value is n, the entry value of the target entry is updated to 0, and if the current entry value is less than n, the entry value of the target entry is updated to the current entry value plus one; n is the number of descriptors cached in one cache line on the host side;

[0033] The BD information count determination unit is used to obtain the number of descriptor information of the target queue corresponding to the queue identifier cached in the DPU cache module;

[0034] The BD information processing unit is configured to, when the location is the first storage location in the host-side memory cache line, if the number of descriptor information is not 0 or an integer multiple of n, output all descriptor information of the target queue cached in the DPU cache module to the descriptor update module, so that the descriptor update module updates the descriptor ring table according to all descriptor information and writes the descriptor information of the current descriptor into the DPU cache module for caching.

[0035] In some embodiments, the BD information processing unit is further configured to, when the location is the first storage location in the host-side memory cache line, write the descriptor information of the current descriptor into the DPU cache module for caching if the number of descriptor information is 0 or an integer multiple of n;

[0036] The BD information processing unit is further configured to write the descriptor information of the current descriptor into the DPU cache module for caching when the location is not the first storage location in the host-side memory cache line; if the number of descriptor information is equal to a preset upper limit value, then output all descriptor information of the target queue cached in the DPU cache module to the descriptor update module; the preset upper limit value is an integer multiple of n.

[0037] In some embodiments, the BD information processing unit is further configured to output at least one descriptor information of any queue cached in the DPU cache module to the descriptor update module when the waiting time of any queue reaches a preset timeout threshold, so that the descriptor update module updates the descriptor ring table according to the at least one descriptor information.

[0038] According to a third aspect of this application, a data processing unit (DPU) is provided, comprising:

[0039] The message receiving module is used to receive messages;

[0040] The descriptor reading module is used to read the current descriptor from the descriptor ring table of the Packed queue;

[0041] The message uploading module is used to write the message into the buffer unit pointed to by the current descriptor;

[0042] The descriptor information aggregation module as described in the first aspect of this application;

[0043] The descriptor update module is used to update the descriptor ring table based on the descriptor information output by the descriptor information aggregation module.

[0044] The descriptor information aggregation method and module, and data processing unit (DPU) provided in this application have the following beneficial effects:

[0045] A Virtio network device is implemented based on a Data Processing Unit (DPU) to communicate with the Virtio driver. A descriptor information aggregation module is added to the DPU to aggregate used descriptor information awaiting updates. When this aggregation module receives the descriptor information and queue identifier (qid) of the current descriptor, it queries the cache line position table for the current entry value of the target entry corresponding to the queue identifier. If the current entry value is 0, it means the current descriptor needs to be written to the first storage location of its corresponding cache line. If the current entry value is not 0, it means the current descriptor needs to be written to a location other than the first storage location of its corresponding cache line. Simultaneously, if the number of descriptor information entries for the target queue corresponding to the queue identifier (qid) already cached in the DPU cache module is not 0 or an integer multiple of n, it means the descriptor information for the target queue is not updated. If aggregation continues in a cache-line aligned manner, and the aggregation limit is reached before outputting the aggregated descriptor information, the situation of "cross-cache-line" descriptor ring table updates, as disclosed in the background art, will occur. Therefore, at this time, all descriptor information of the target queue cached in the DPU cache module (i.e., non-aligned descriptor information) needs to be output to the descriptor update module. In this way, the descriptor information of the target queue can be aggregated again in a cache-line aligned manner, so that the subsequent descriptor information can be stored in a cache-line aligned manner. This application can, through the adjustment method of this application, ensure that the descriptor information aggregated in a cache-line aligned manner can be stored in the cache line in a cache line when aggregation is performed in accordance with the cache-line aligned principle but cross-cache-line occurs when writing to the cache line, thereby avoiding PCIe read latency and read conflict problems caused by subsequent cross-cache-line descriptor updates. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 The above is a flowchart of the message uploading process disclosed in the background technology.

[0048] Figure 2 This is a schematic diagram of cross-cache line update cache descriptor (BD) disclosed in the background art.

[0049] Figure 3This is a flowchart of a descriptor information aggregation method in an embodiment of this application.

[0050] Figure 4 This is a schematic diagram of the structure of a descriptor information aggregation module in an embodiment of this application.

[0051] Figure 5 This is a schematic diagram of the structure of a data processing unit in an embodiment of this application. Detailed Implementation

[0052] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0053] See Figure 3 One embodiment of this application provides a descriptor information aggregation method applied to a data processing unit (DPU), the method comprising the following steps:

[0054] Step S10: Obtain the descriptor information and queue identifier of the current descriptor;

[0055] Specifically, this embodiment implements a Virtio network device based on a DPU, which communicates with the Virtio driver. A descriptor information aggregation module is added to the DPU to aggregate used descriptor information awaiting update. The current descriptor refers to the most recently used descriptor (BD). The descriptor information of the current descriptor includes information needed by the descriptor update module to generate the descriptor, including the packet length received by the buffer pointed to by the BD and the bufferid. The bufferid is the identifier of the buffer. The BD generated by the original Virtio driver contains the buffer address, buffer length, bufferid, and flag. After the packet is written to the buffer, the buffer length needs to be modified to the actual packet length received by the buffer. The queue identifier refers to the queue ID, i.e., queue. The descriptor information aggregation module receives the descriptor information and queue identifier of the current descriptor output by the front-end module and executes the steps of the method in this embodiment. It should be noted that the descriptor information of the current descriptor output by the front-end module can be found in the existing descriptor ring table update method. In this embodiment, a queue identifier (qid) is added to facilitate the aggregation of descriptor information from different queues.

[0056] Step S20: Query the current entry value of the target entry corresponding to the queue identifier in the cache line position table, determine the position of the current descriptor in the corresponding host-side memory cache line based on the current entry value, and update the entry value of the target entry; wherein, if the current entry value is n, the entry value of the target entry is updated to 0, and if the current entry value is less than n, the entry value of the target entry is updated to the current entry value plus one; n is the number of descriptors cached in one cache line on the host side;

[0057] Specifically, the cache line position table includes multiple entries corresponding one-to-one with multiple queues. Assuming that the Virtio driver communicates with the Virtio network device through 8000 queues, the cache line position table also includes 8000 entries. The address / index of each entry is the qid of the corresponding queue, and each entry records a position value. This position value indicates the position of the received current descriptor in its corresponding host-side memory cache line. The position in the cache line is encoded starting from 0. For example, taking n=4, the relative positions of the 4 descriptors in a cache line are 0, 1, 2, and 3 respectively. Each time a descriptor is received, the entry value corresponding to qid needs to be updated to indicate the position of the next descriptor in the cache line. An entry value of 0 indicates that the current descriptor is the first storage position in the cache line, and an entry value of 3 (i.e., n-1) indicates that the current descriptor is the last storage position in the cache line.

[0058] Step S30: Obtain the number of descriptor information entries for the target queue corresponding to the queue identifier cached in the DPU cache module;

[0059] Specifically, when the current descriptor is located at the first storage location of the corresponding host-side memory cache line, it is necessary to further determine whether the BD information output condition is met, i.e., step S40.

[0060] Step S40: When the position is the first storage position in the host-side memory cache line, if the number of descriptor information is not 0 or an integer multiple of n, then all descriptor information of the target queue cached in the DPU cache module is output to the descriptor update module, so that the descriptor update module updates the descriptor ring table according to all descriptor information and writes the descriptor information of the current descriptor into the DPU cache module for caching.

[0061] Specifically, when the location is the first storage location in the host-side memory cache line, it is necessary to determine whether to adjust the BD information aggregation order. If at this time the condition "the number of descriptor information of the target queue is not 0 or an integer multiple of n" is met (which can also be understood as "the number of descriptor information of the target queue is greater than 0 and less than n") is satisfied, it indicates that the target queue descriptor information is not aggregated in a cache line alignment manner, for example... Figure 2 In the scenario shown, the first timeout triggers the output of BD information, outputting BD0 information to the descriptor update module. The descriptor update module updates BD0 of Cacheline0. Then, the target queue continues to aggregate BDs from Cacheline0. When the received current descriptor is BD4 of Cacheline1, the position of BD4 in Cacheline1 is 0. However, at this time, the number of BD information in the target queue of the DPU cache module is 3 (including BD1, BD2, and BD3 BD information). Figure 2 Assuming n=4, m=1, and 3 is greater than 0 and not an integer multiple of n, all descriptor information of the target queue cached in the DPU cache module (including information of BD1, BD2, and BD3, but excluding the current BD4) needs to be output to the descriptor update module. Then, the BD information of BD4 (the current descriptor) is written into the DPU cache module for caching. This achieves the goal of using the BD information of BD4 as the first BD information and re-aggregating the descriptor information of the target queue according to the cache line alignment. Subsequently, the BD information of BD5, BD6, BD7, and BD8 are received sequentially. When the BD information of BD8 is received, the position of BD8 in Cacheline2 is 0, and at this time, the number of BD information of the target queue in the DPU cache module is 4 (including BD4, BD5, and BD6). If the number of BD information entries (BD6 and BD7) is equal to m×n (preset upper limit), then the BD information entries of BD4, BD5, BD6, and BD7 are output to the descriptor update module. The descriptor update module generates a corresponding cache line data (containing BD4, BD5, BD6, and BD7, but excluding the current BD8) based on the BD information entries of BD4, BD5, BD6, and BD7. The cache line data is written to the descriptor ring table of the Packed queue according to the cache line alignment method, thereby updating the descriptor ring table and updating the status of BD4, BD5, BD6, and BD7 to "used". In summary, after adjustment, the PCIe read latency and read conflict problems caused by subsequent cross-cache line descriptor updates can be avoided, thus improving the performance of the Virtio system.

[0062] Based on the above description, the method in this embodiment implements a Virtio network device based on a Data Processing Unit (DPU) and communicates with the Virtio driver. A descriptor information aggregation module is added to the DPU to aggregate used descriptor information awaiting update. When this aggregation module receives the descriptor information and queue identifier (qid) of the current descriptor, it queries the current entry value of the target entry corresponding to the queue identifier in the cache line position table. If the current entry value is 0, it indicates that the current descriptor needs to be written to the first storage location of its corresponding cache line. If the current entry value is not 0, it indicates that the current descriptor needs to be written to a location other than the first storage location of its corresponding cache line. Simultaneously, if the number of descriptor information entries for the target queue corresponding to the queue identifier (qid) cached in the DPU cache module is not 0 or an integer multiple of n, it indicates that the target queue... If the descriptor information is not aggregated according to the cache line alignment, and aggregation continues until the aggregation limit is reached before outputting the aggregated descriptor information, the situation of "cross-cache line" updating the descriptor ring table descriptors, as disclosed in the background technology, will occur. Therefore, at this time, all descriptor information of the target queue cached in the DPU cache module (i.e., descriptor information that cannot be aligned) needs to be output to the descriptor update module. In this way, the descriptor information of the target queue can be aggregated again according to the cache line alignment, so that the subsequent descriptor information can be stored according to the cache line alignment. This application can, through the adjustment method of this application, ensure that the descriptor information aggregated according to the cache line can be stored in the cache line according to the cache line alignment when it is aggregated according to the cache line alignment principle but cross-cache line occurs when finally written to the cache line, thereby avoiding the PCIe read latency and read conflict problems caused by subsequent cross-cache line update descriptors.

[0063] In some embodiments, the BD information in the DPU cache module is specifically cached by queue. For example, a certain amount of storage space is allocated to each queue, the BD information is written into the storage space with the corresponding qid as the index or address, and the number of BD information in each storage space is maintained to facilitate querying the number of descriptors cached in each queue.

[0064] In some embodiments, step S40 further includes:

[0065] When the location is the first storage location in the host-side memory cache line, if the number of descriptor information is 0 or an integer multiple of n, then the descriptor information of the current descriptor is written into the DPU cache module for caching.

[0066] Specifically, when the location is the first storage location in the host-side memory cache line, the BD information output under normal aggregation conditions is not met (but BD information may need to be output due to aggregation order adjustment). If the number of descriptor information in the cached target queue is 0 or an integer multiple of n, it means that the currently received descriptor information is the first data in the corresponding cache line, and there is no situation that requires adjustment of the aggregation order. Therefore, descriptor information does not need to be output at this time, and aggregation continues until the aggregation limit is met.

[0067] In some embodiments, step S40 further includes:

[0068] When the location is not the first storage location in the host-side memory cache line, the descriptor information of the current descriptor is written into the DPU cache module for caching. If the number of descriptor information is equal to a preset upper limit value, all descriptor information of the target queue cached in the DPU cache module is output to the descriptor update module; the preset upper limit value is an integer multiple of n.

[0069] Specifically, when the location is not the first storage location in the host-side memory cache line, there is no need to adjust the aggregation order of BD information. At this time, the location can be any storage location in the host-side memory cache line other than the first storage location. The descriptor information of the current descriptor needs to be written into the DPU cache module for caching first. It is then determined whether the number of descriptor information found is equal to the preset upper limit. If it is equal to the preset upper limit, it means that the aggregation upper limit has been reached, which satisfies the BD information output under normal aggregation conditions. All descriptor information of the aggregated target queue needs to be output immediately. After the output, the number of descriptor information of the target queue is updated to 0.

[0070] In some embodiments, step S40 further includes:

[0071] When the waiting time of any queue reaches a preset timeout threshold, at least one descriptor information of any queue cached in the DPU cache module is output to the descriptor update module, so that the descriptor update module updates the descriptor ring table according to the at least one descriptor information.

[0072] Specifically, when aggregating BD information for any queue, a timer corresponding to that queue is maintained, or a timestamp is recorded. The start time of the timer or the timestamp can be the time when the first BD information of any queue is written into the DPU cache module for caching, or it can be the time when the first BD information of any queue is received. The waiting time can be obtained directly based on the timing result, or it can be obtained based on the time difference between the timestamp and the current system time. When the waiting time is greater than or equal to a preset timeout threshold, a timeout is triggered to output BD information, and at least one descriptor information of any queue cached in the DPU cache module is output to the descriptor update module.

[0073] In some embodiments, step S30 specifically includes:

[0074] Step S301: Determine whether the DPU cache module has a queue linked list corresponding to the queue identifier based on the queue identifier; wherein, the queue linked list includes a head pointer, a tail pointer and a number of descriptor information, the head pointer points to the storage address of the first descriptor information of the queue linked list in the DPU cache module, and the head pointer points to the storage address of the last descriptor information of the queue linked list in the DPU cache module.

[0075] Specifically, the method in this embodiment uses a queue linked list to aggregate, store, and manage the BD information of each queue. For a queue that has previously aggregated and stored at least one BD information, there will be a queue linked list corresponding to the qid of that queue. For a queue that has not previously aggregated and stored BD information, there will not be a queue linked list corresponding to the qid of that queue. qid is the index or name of the queue linked list. Based on the queue linked list, the storage address of the BD information of the corresponding queue in the DPU cache module can be determined. The DPU cache module not only stores each BD information, but also maintains the pointing relationship between each storage address.

[0076] Step S302: If a corresponding queue list exists, determine the number of descriptor information of the target queue cached in the DPU cache module according to the corresponding queue list;

[0077] Specifically, if a queue list corresponding to the queue identifier exists, it means that at least one BD information of the target queue has been previously gathered and stored. Then, the number of BD information that has been gathered in the target queue (excluding the BD information of the current BD) can be directly determined according to the queue list of the target queue.

[0078] Step S303: If there is no corresponding queue list, determine that the number of descriptor information is 0, request the DPU cache module to create a queue list corresponding to the queue identifier, and write the descriptor information of the current descriptor into the created queue list for caching;

[0079] Specifically, if no queue list corresponding to the queue identifier exists, it means that the target queue's BD information has not been aggregated before. The current BD information is the first BD information aggregated for the target queue. Regardless of whether the current BD's position in the cache line is 0, aggregation is required, and BD information does not need to be output. In this case, it is necessary to request the DPU cache module to create a queue list corresponding to the queue identifier, write the current BD information into the created queue list for caching, and set the head and tail pointers of the queue list according to the storage address. At this time, the head pointer is equal to the tail pointer, and the number of descriptors is set to 1. Then, when the target queue's BD information is received next time, the queue list can be queried according to the received qid. Assuming that the cache line position of the next BD is not 0, when the BD information is written into the queue list next time, only the tail pointer needs to be updated according to the storage address of the next BD information, and the head pointer does not need to be updated. The number of descriptors is updated to 2 next time.

[0080] In some embodiments, the method further includes:

[0081] After any descriptor information is output to the descriptor update module, the DPU cache resources occupied by the descriptor information are released.

[0082] Specifically, Virtio drivers and Virtio network devices typically communicate through numerous queues. Therefore, allocating fixed storage resources to each queue would require a DPU cache module with a very large storage capacity. Furthermore, since all queues do not execute tasks in parallel, this embodiment sets up each queue to share the storage resources of the DPU cache module. After outputting any BD information to the descriptor update module, the storage resources of the DPU cache module occupied by that BD information need to be released for caching other BD information, thereby reducing the resource requirements on the DPU hardware.

[0083] Please see Figure 4 Another embodiment of this application provides a descriptor information aggregation module, including:

[0084] BD information receiving unit 1 is used to obtain the descriptor information and queue identifier of the current descriptor;

[0085] Cache line position unit 2 is used to store a cache line position table. The cache line position table includes multiple entries that correspond one-to-one with multiple queue identifiers. Each entry stores an entry value, which indicates the storage position of the next descriptor to be updated in the corresponding cache line for the corresponding queue.

[0086] DPU caching module 3 is used to cache the descriptor information of each queue by queue;

[0087] BD position determination unit 4 is used to query the current entry value of the target entry corresponding to the queue identifier in the cache line position table, determine the position of the current descriptor in the corresponding host-side memory cache line based on the current entry value, and update the entry value of the target entry; wherein, if the current entry value is n, the entry value of the target entry is updated to 0, and if the current entry value is less than n, the entry value of the target entry is updated to the current entry value plus one;

[0088] BD information count determination unit 5 is used to obtain the number of descriptor information of the target queue corresponding to the queue identifier cached in the DPU cache module;

[0089] BD information processing unit 6 is used to output all descriptor information of the target queue cached in the DPU cache module to the descriptor update module when the position is the first storage position in the host-side memory cache line, if the number of descriptor information is not 0 or an integer multiple of n, so that the descriptor update module updates the descriptor ring table according to all descriptor information and writes the descriptor information of the current descriptor into the DPU cache module for caching;

[0090] Where n is the number of descriptors cached in a cache line on the host side.

[0091] In some embodiments, the BD information processing unit 6 is further configured to write the descriptor information of the current descriptor into the DPU cache module for caching when the location is the first storage location in the host-side memory cache line and the number of descriptor information is 0 or an integer multiple of n;

[0092] The BD information processing unit 6 is further configured to write the descriptor information of the current descriptor into the DPU cache module for caching when the position is not the first storage position in the host-side memory cache line; if the number of descriptor information is equal to a preset upper limit value, then output all descriptor information of the target queue cached in the DPU cache module to the descriptor update module; the preset upper limit value is an integer multiple of n.

[0093] In some embodiments, the BD information processing unit 6 is further configured to output at least one descriptor information of any queue cached in the DPU cache module to the descriptor update module when the waiting time of any queue reaches a preset timeout threshold, so that the descriptor update module updates the descriptor ring table according to the at least one descriptor information.

[0094] It should be noted that the descriptor information aggregation module in this embodiment corresponds to the method in the above embodiment. The contents of the descriptor information aggregation module in this embodiment that are not described in detail can be obtained by referring to the contents of the method in the embodiment, and will not be described again in this embodiment.

[0095] Please see Figure 5 Another embodiment of this application also provides a data processing unit (DPU), including:

[0096] Message receiving module 10 is used to receive messages;

[0097] The descriptor reading module 20 is used to read the current descriptor from the descriptor ring table of the Packed queue;

[0098] The message uploading module 30 is used to write the message into the buffer unit pointed to by the current descriptor;

[0099] Descriptor information aggregation module 40 as described in the above embodiments;

[0100] The descriptor update module 50 is used to update the descriptor ring table based on the descriptor information output by the descriptor information aggregation module.

[0101] Another embodiment of this application provides a data processing unit (DPU), including:

[0102] A communication interface used for communicating with other electronic devices;

[0103] Memory is used to store computer program instructions;

[0104] A processor is configured to execute the computer program instructions to support the data processing unit (DPU) in implementing the descriptor information aggregation method according to the above embodiments.

[0105] In this embodiment, the memory mainly includes a program storage area and a data storage area. The program storage area can store the operating device, applications required for at least one function, etc., and the data storage area can store related data, etc. Furthermore, the memory can be a high-speed random access memory, or a non-volatile memory, such as a plug-in hard disk, a smart media card (SMC), a secure digital card (SD), and a flash card, or other volatile solid-state storage devices.

[0106] The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processor can be any conventional processor. The processor is the control center of the data processing unit and uses various interfaces and lines to connect the various parts of the data processing unit.

[0107] Another embodiment of this application provides a Virtio system, including a Virtio driver and a data processing unit (DPU) as described in the above embodiments. The Virtio driver runs on the host side and is used at least to generate the current descriptor.

[0108] Another embodiment of this application provides a computer program product, including computer program instructions that instruct a computer device to perform operations corresponding to the descriptor information aggregation method described in the above embodiments.

[0109] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program. These instructions define how to perform specific operations. These instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which refer to the various steps in the descriptor information aggregation described in the above embodiments. In this way, the computer program product of this embodiment provides a complete software solution that can run on various computer devices to implement the descriptor information aggregation method of the above embodiments.

[0110] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for converging descriptor information, characterized in that, Applied to a data processing unit (DPU), the method includes: Retrieve the descriptor information and queue identifier of the current descriptor; Query the current entry value of the target entry corresponding to the queue identifier in the cache line position table, determine the position of the current descriptor in the corresponding host-side memory cache line based on the current entry value, and update the entry value of the target entry; wherein, if the current entry value is n, the entry value of the target entry is updated to 0, and if the current entry value is less than n, the entry value of the target entry is updated to the current entry value plus one; n is the number of descriptors cached in one cache line on the host side; Obtain the number of descriptor information entries for the target queue corresponding to the queue identifier cached in the DPU cache module; When the location is the first storage location in the host-side memory cache line, if the number of descriptor information is not 0 or an integer multiple of n, then all descriptor information of the target queue cached in the DPU cache module is output to the descriptor update module, so that the descriptor update module updates the descriptor ring table according to all descriptor information, and writes the descriptor information of the current descriptor into the DPU cache module for caching.

2. The method according to claim 1, characterized in that, The method further includes: When the location is the first storage location in the host-side memory cache line, if the number of descriptor information is 0 or an integer multiple of n, then the descriptor information of the current descriptor is written into the DPU cache module for caching.

3. The method according to claim 1, characterized in that, The method further includes: When the location is not the first storage location in the host-side memory cache line, the descriptor information of the current descriptor is written into the DPU cache module for caching. If the number of descriptor information is equal to a preset upper limit value, all descriptor information of the target queue cached in the DPU cache module is output to the descriptor update module; the preset upper limit value is an integer multiple of n.

4. The method according to claim 1, characterized in that, The method further includes: When the waiting time of any queue reaches a preset timeout threshold, at least one descriptor information of any queue cached in the DPU cache module is output to the descriptor update module, so that the descriptor update module updates the descriptor ring table according to the at least one descriptor information.

5. The method according to claim 1, characterized in that, The step of obtaining the number of descriptor information entries for the target queue corresponding to the queue identifier cached in the DPU cache module includes: Determine whether the DPU cache module has a queue linked list corresponding to the queue identifier based on the queue identifier; If a corresponding queue list exists, the number of descriptor information entries of the target queue cached in the DPU cache module is determined based on the corresponding queue list. If no corresponding queue list exists, the number of descriptor information is determined to be 0. The DPU cache module is requested to create a queue list corresponding to the queue identifier, and the descriptor information of the current descriptor is written into the created queue list for caching. The queue list includes a head pointer, a tail pointer, and a number of descriptor information. The head pointer points to the storage address of the first descriptor information of the queue list in the DPU cache module, and the head pointer points to the storage address of the last descriptor information of the queue list in the DPU cache module.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: After any descriptor information is output to the descriptor update module, the DPU cache resources occupied by the descriptor information are released.

7. A descriptor information aggregation module, characterized in that, include: The BD information receiving unit is used to obtain the descriptor information and queue identifier of the current descriptor; A cache line position unit is used to store a cache line position table, which includes multiple entries that correspond one-to-one with multiple queue identifiers. The DPU caching module is used to cache descriptor information. The BD position determination unit is used to query the current entry value of the target entry corresponding to the queue identifier in the cache line position table, determine the position of the current descriptor in the corresponding host-side memory cache line based on the current entry value, and update the entry value of the target entry; wherein, if the current entry value is n, the entry value of the target entry is updated to 0, and if the current entry value is less than n, the entry value of the target entry is updated to the current entry value plus one; n is the number of descriptors cached in one cache line on the host side; The BD information count determination unit is used to obtain the number of descriptor information of the target queue corresponding to the queue identifier cached in the DPU cache module; The BD information processing unit is configured to, when the location is the first storage location in the host-side memory cache line, if the number of descriptor information is not 0 or an integer multiple of n, output all descriptor information of the target queue cached in the DPU cache module to the descriptor update module, so that the descriptor update module updates the descriptor ring table according to all descriptor information and writes the descriptor information of the current descriptor into the DPU cache module for caching.

8. The descriptor information aggregation module according to claim 7, characterized in that, The BD information processing unit is also used to write the descriptor information of the current descriptor into the DPU cache module for caching when the position is the first storage position in the host-side memory cache line and the number of descriptor information is 0 or an integer multiple of n. The BD information processing unit is also used to write the descriptor information of the current descriptor into the DPU cache module for caching when the position is not the first storage position in the host-side memory cache line; if the number of descriptor information is equal to a preset upper limit value, then all descriptor information of the target queue cached in the DPU cache module is output to the descriptor update module. The preset upper limit value is an integer multiple of n.

9. The descriptor information aggregation module according to claim 7 or 8, characterized in that, The BD information processing unit is also used to output at least one descriptor information of any queue cached in the DPU cache module to the descriptor update module when the waiting time of any queue reaches a preset timeout threshold, so that the descriptor update module updates the descriptor ring table according to the at least one descriptor information.

10. A data processing unit (DPU), characterized in that, include: The message receiving module is used to receive messages; The descriptor reading module is used to read the current descriptor from the descriptor ring table of the Packed queue; The message uploading module is used to write the message into the buffer unit pointed to by the current descriptor; The descriptor information aggregation module as described in any one of claims 7 to 9; The descriptor update module is used to update the descriptor ring table based on the descriptor information output by the descriptor information aggregation module.

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