Signal layer change structure optimization method and device suitable for DDR5 printed circuit board, medium and product

Abstract

The invention discloses a signal layer change structure optimization method and device suitable for a DDR5 printed circuit board, a medium and a product, and relates to the field of signal layer change structure optimization, and the method comprises the steps: obtaining a signal layer change structure of the DDR5 printed circuit board, and target impedance values corresponding to surface layer wiring and inner layer wiring in the signal layer change structure; establishing an equivalent transmission line model according to the basic structure parameters of the signal layer change structure in the vertical direction of the printed circuit board; performing time domain reflection impedance simulation on the equivalent transmission line model in a transient solution mode to obtain an actual impedance value; and adjusting the width of a layer-changing conductor in the signal layer-changing structure and the parallel distance between the layer-changing conductor and the vertical GND reference layer according to the difference between the actual impedance value and the target impedance value to obtain an optimized signal layer-changing structure. According to the invention, the quality, stability and transmission characteristics of signal transmission can be improved.

Description

Technical Field

[0001] This application relates to the field of signal layer structure optimization, and in particular to a method, device, medium and product for optimizing the signal layer structure of DDR5 printed circuit boards. Background Technology

[0002] Signal swapping technology is widely used in printed circuit board design. Traditional signal swapping structures employ a "coaxial cable-like" principle, where signal lines are introduced from surface pads, connected to inner pads via via metal pillars, and then routed out to inner layers, thus achieving signal swapping along the transmission link. While traditional signal swapping technology simplifies component placement, interconnect design, and link optimization for engineers, the limitations of via structures can lead to capacitive and inductive effects in practical engineering applications. This can cause abrupt impedance changes in the swapping region, impacting transmission quality.

[0003] To mitigate the impact of impedance fluctuations, traditional signal layer swapping structures typically optimize the additional capacitive or inductive components by removing non-functional pads, adjusting anti-pad and via metal pillar sizes, employing back-drilling technology (to remove the influence of via residual pillars), and adding return ground vias, thereby reducing the range of impedance variations.

[0004] However, due to the presence of many highly dense signal layer switching areas in high-speed printed circuit board designs such as DDR5 (Memory Technology Overview), and the dense signal traces and tight wiring space, the aforementioned traditional layer switching structure has certain limitations, and its impedance adjustment method will also be subject to certain restrictions.

[0005] In order to meet the requirements of JEDEC relevant protocol standards (JESD-308, JESD79-5) for DDR signal impedance, and in view of the future development trend of DDR technology such as higher speed, larger capacity and smaller size, it is necessary to study the regions with severe signal link impedance abrupt changes (signal layer switching).

[0006] Therefore, based on the above problems, there is an urgent need to provide a signal layer switching structure that can improve the limitations of traditional signal vias, enabling signals to achieve lower impedance fluctuations and excellent transmission characteristics (Return Loss, Insertion Loss) in the vertical direction of the PCB, thereby enabling high-speed signal transmission with high quality. Summary of the Invention

[0007] The purpose of this application is to provide a method, device, medium, and product for optimizing the signal layer structure of DDR5 printed circuit boards, which can improve the quality, stability, and transmission characteristics of signal transmission.

[0008] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a method for optimizing the signal layer structure of a DDR5 printed circuit board, the method comprising: Obtain the signal layer swapping structure of the DDR5 printed circuit board and the target impedance values ​​of the surface layer traces and inner layer traces in the signal layer swapping structure; An equivalent transmission line model is established based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board. In transient solution mode, time-domain reflection impedance simulation is performed on the equivalent transmission line model to obtain the actual impedance value; the actual impedance value is the layer switching impedance of the surface trace to the inner trace segment. The width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure are adjusted based on the difference between the actual impedance value and the target impedance value to obtain the optimized signal swap structure.

[0009] Optionally, the basic structural parameters specifically include: the radius of the pad connecting the trace and the layer replacement conductor, the width and thickness of the layer replacement conductor, the parallel distance between the layer replacement conductor and the vertical GND reference layer, the lateral and longitudinal distances of the filling dielectric, the vertical distances from both ends of the vertical GND reference layer to the signal trace, the radius of the arcs on both sides, and the radius of the chamfered arc of the dielectric.

[0010] Optionally, establishing an equivalent transmission line model based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board specifically includes: Based on the basic structural parameters of the signal switching structure in the vertical direction of the printed circuit board, an equivalent transmission line model is established using the three-dimensional full-wave electromagnetic simulation software HFSS.

[0011] Optionally, adjusting the width of the swap conductor and the parallel distance between the swap conductor and the perpendicular GND reference layer in the signal swap structure based on the difference between the actual impedance value and the target impedance value to obtain an optimized signal swap structure specifically includes: When 0 < w / d ≤ 1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment; When w / d≥1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment; Where, ε ex The equivalent dielectric constant of each layer of filling medium in the vertical direction is given. w d represents the width of the layer-swapping conductor, and d represents the parallel distance between the layer-swapping conductor and the vertical GND reference layer.

[0012] Secondly, this application provides a signal layer switching structure optimization device suitable for DDR5 printed circuit boards, the signal layer switching structure optimization device suitable for DDR5 printed circuit boards comprising: The data acquisition module is used to acquire the signal layer switching structure of the DDR5 printed circuit board and the target impedance values ​​corresponding to the surface layer traces and inner layer traces in the signal layer switching structure. The equivalent transmission line model determination module is used to establish an equivalent transmission line model based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board. The actual impedance value determination module is used to perform time-domain reflection impedance simulation on the equivalent transmission line model in transient solution mode to obtain the actual impedance value; the actual impedance value is the layer switching impedance of the segment from the surface layer to the inner layer. The structure optimization module is used to adjust the width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure according to the difference between the actual impedance value and the target impedance value, so as to obtain the optimized signal swap structure.

[0013] Thirdly, this application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the signal layer switching structure optimization method suitable for DDR5 printed circuit boards.

[0014] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the signal layer switching structure optimization method applicable to DDR5 printed circuit boards.

[0015] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the aforementioned signal layer switching structure optimization method for DDR5 printed circuit boards.

[0016] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a method, device, medium, and product for optimizing the signal swapping structure of DDR5 printed circuit boards. By adjusting the width of the swapping conductor and the parallel distance between the swapping conductor and the vertical GND reference layer in the signal swapping structure, the target impedance value is matched, and the signal swapping structure is made more compact. This application can improve the limitations of traditional signal vias in signal swapping structures, enabling signals to achieve lower impedance fluctuations and excellent transmission characteristics in the vertical direction of the DDR5 printed circuit board, thereby enabling high-speed, high-quality signal transmission. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of a signal layer switching structure optimization method for a DDR5 printed circuit board according to an embodiment of this application; Figure 2 A schematic diagram of the basic structural parameters of the signal switching structure provided in this application; Figure 3 This is a schematic diagram of a traditional signal layer switching structure; Figure 4 This is a schematic diagram of the signal layer switching structure provided in this application; Figure 5 This is a schematic diagram of the equivalent circuit model of the signal layer switching transmission line in this application; Figure 6 This is a schematic diagram showing the TDR impedance results of the layer replacement structure provided in this application and the traditional layer replacement structure. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] In one exemplary embodiment, such as Figure 1 As shown, a method for optimizing the signal layer switching structure of a DDR5 printed circuit board is provided, comprising the following steps S101 to S104. Wherein: S101, obtain the signal layer switching structure of the DDR5 printed circuit board and the target impedance values ​​corresponding to the surface layer traces and inner layer traces in the signal layer switching structure; The signal layer swapping structure specifically includes surface layer traces (microstrip), inner layer traces (stripline), introduction pads, exit pads, other non-functional pads, layer swapping conductors, vertical GND reference layer, and dielectric layer. The surface layer trace is connected to the vicinity of the vertical GND reference layer via the introduction pad, and then connected to the exit pad via a transmission line of thickness t and width w. Finally, the inner layer traces begin from the exit pad. In the signal layer switching structure, the target impedance values ​​corresponding to the surface layer traces and inner layer traces can be directly obtained according to the JEDEC JESD308 protocol. For example, the lead-in impedance of a single-ended signal is 40Ω and the loaded impedance is 55Ω; the differential impedance corresponding to a differential signal is 54Ω. In the DDR5 printed circuit board design, the above impedance values ​​are kept fixed to reduce signal integrity issues.

[0022] S102, establish an equivalent transmission line model based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board; such as Figure 2 As shown in (a) the three-dimensional view and (b) the top view, the basic structural parameters specifically include: the radius r of the pad connecting the trace and the layer replacement conductor, the width w and thickness t of the layer replacement conductor, the parallel distance d between the layer replacement conductor and the vertical GND reference layer, the lateral distance d1 and the longitudinal distance d2 of the filling medium, the vertical distance d3 between the two ends of the vertical GND reference layer and the signal trace, as well as the radius r1 of the arc on both sides and the radius r2 of the chamfer arc of the medium.

[0023] As a specific implementation, based on the basic structural parameters of the signal layer switching structure in the vertical direction of the printed circuit board, a simulation model is established using the three-dimensional full-wave electromagnetic simulation software HFSS. The equivalent circuit model of the transmission line in the signal layer switching region is shown below. Figure 5 As shown, the equivalent transmission line model consists of a capacitor C with capacitive properties and an inductor L with inductive properties. S103, Perform time-domain reflection impedance simulation on the equivalent transmission line model in transient solution mode to obtain the actual impedance value; the actual impedance value is the layer transition impedance from the surface layer trace to the inner layer trace segment; the equivalent characteristic impedance value of the transmission line can be obtained from... Calculations show that the actual impedance of the transmission line decreases when capacitance increases, and increases when inductance increases. Therefore, impedance fluctuations can be adjusted by varying the deviation between the actual impedance value Z and the target characteristic impedance value Z0, thereby reducing signal integrity issues. S104, adjust the width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure according to the difference between the actual impedance value and the target impedance value, to obtain the optimized signal swap structure.

[0024] To match the actual impedance value Z with the target impedance value Z0, the capacitive and inductive components of the signal layer-swapping structure need to be adjusted. The "quasi-coaxial principle" in the relevant signal layer-swapping structure is converted to the "microstrip transmission line principle." According to transmission line theory, the layer-swapping impedance (actual impedance value) Z of the surface layer trace to the inner layer trace segment is calculated as follows: When 0 < w / d ≤ 1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment; When w / d≥1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment; Where, ε ex The equivalent dielectric constant of each layer of filling medium in the vertical direction is given. w d represents the width of the layer-swapping conductor, and d represents the parallel distance between the layer-swapping conductor and the vertical GND reference layer.

[0025] Since there are unused metal segments, i.e. stubs, in the vertical direction in addition to the layer-changing conductors on the layer-changing path, their response characteristics are capacitive, which will lower the overall impedance value of the signal layer-changing structure. Therefore, by designing the impedance value on the layer-changing path to be higher or removing the stub part to balance the capacitive response brought by the stub, the impedance fluctuation can be reduced.

[0026] like Figure 4 As shown in (a) a 3D view of the single-ended signal, (b) a 3D view of the differential signal, (c) a top view of the single-ended signal, and (d) a top view of the differential signal, parametric scanning simulations were performed on the width w of the switching conductor and the parallel distance d between the switching conductor and the vertical GND reference layer in the signal switching structure using the 3D full-wave electromagnetic simulation software HFSS. The variation law is as follows: when d is a fixed value, w widens, capacitance increases, inductance decreases, and its impedance value decreases; when w is fixed, d decreases, capacitance decreases, and its impedance value increases, thus easily matching the target impedance value Z0. At the same time, the remaining structural parameters (which have a smaller impact on impedance) are further optimized, thereby achieving a compact design. The differential structure is similar in principle to the single-ended structure, the difference being that the target impedance value of the single-ended signal is ~40Ω, and the target impedance value of the differential signal is ~54Ω. Using the above method, a vertical switching structure for the signal that matches the target impedance value of the system can still be achieved, reducing impedance fluctuations and enabling high-quality transmission of higher-speed signals.

[0027] A schematic diagram of a traditional signal layer switching structure is shown below. Figure 3 As shown, Figure 3 (a) represents a single-ended signal layer change, including: surface layer traces, ground return vias, via paths, inner layer traces, and anti-pads. Figure 3 (b) is a differential signal layer change, including: surface layer traces, ground return holes, inner layer traces and via piles.

[0028] Figure 6 Part (a) is a traditional single-ended signal layer-switching structure. Figure 3 ) and the layer replacement structure provided in this application ( Figure 4 The time-domain reflection (TDR) impedance comparison results show that the TDR impedance of the layer-swapping structure provided in this application deviates less from the target impedance (~40Ω) of the DDR single-ended signal. The traditional layer-swapping structure fluctuates by about 4Ω, while the layer-swapping structure provided in this application only has 0.8Ω. Figure 6 Part (b) shows the TDR impedance results of the differential signal under two different structures. Compared with the single-ended signal, the target impedance of the DDR clock differential signal is ~54Ω. As can be seen from the comparison results, the impedance fluctuation of the structure in this application (~1Ω) is significantly lower than that of the traditional junction structure (~8Ω). Using the novel layer-swapping structure provided in this application, combined with the impedance optimization method, the rise time of higher speed signals is shorter, signal integrity problems are reduced, signal transmission is stable, and the performance of high-speed devices will be greatly improved.

[0029] As a specific example, such as Figure 5 As shown, the signal input pad and output pad are equivalent to capacitors C1 and C3, respectively. The layer switching path is represented by circuits L1 and C2, and the unused layer switching conductor portion is represented by circuits L2 and C4. The impedance of the layer switching region is mainly determined by the width w of the layer switching conductor and the distance d between the conductor and the vertical GND reference layer. When the distance d is fixed, the wider the conductor width w, the smaller L1 and the larger C2, resulting in a lower impedance. When the width w is fixed, the larger the distance d, the smaller C2, resulting in a higher impedance value.

[0030] Based on the same inventive concept, this application also provides a signal layer structure optimization device for DDR5 printed circuit boards, used to implement the aforementioned signal layer structure optimization method for DDR5 printed circuit boards. The solution provided by this device is similar to the implementation described in the above method. Therefore, the specific limitations of one or more embodiments of the signal layer structure optimization device for DDR5 printed circuit boards provided below can be found in the limitations of the signal layer structure optimization method for DDR5 printed circuit boards described above, and will not be repeated here.

[0031] In one exemplary embodiment, a signal layer switching structure optimization device suitable for DDR5 printed circuit boards is provided, comprising: The data acquisition module is used to acquire the signal layer switching structure of the DDR5 printed circuit board and the target impedance values ​​corresponding to the surface layer traces and inner layer traces in the signal layer switching structure. The equivalent transmission line model determination module is used to establish an equivalent transmission line model based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board. The actual impedance value determination module is used to perform time-domain reflection impedance simulation on the equivalent transmission line model in transient solution mode to obtain the actual impedance value; the actual impedance value is the layer switching impedance of the segment from the surface layer to the inner layer. The structure optimization module is used to adjust the width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure according to the difference between the actual impedance value and the target impedance value, so as to obtain the optimized signal swap structure.

[0032] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal. The computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is connected to the system bus via the I / O interfaces. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The I / O interfaces of the computer device are used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a signal layering structure optimization method suitable for DDR5 printed circuit boards.

[0033] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0034] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0035] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0036] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0037] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0038] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0039] In this application, all actions to acquire signals, information, or data are carried out in compliance with the relevant data protection laws and policies of the country where the location is situated, and with the authorization granted by the owner of the relevant device.

[0040] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0041] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for optimizing the signal layer switching structure of a DDR5 printed circuit board, characterized in that, The signal layer switching structure optimization method applicable to DDR5 printed circuit boards includes: Obtain the signal layer swapping structure of the DDR5 printed circuit board and the target impedance values ​​of the surface layer traces and inner layer traces in the signal layer swapping structure; An equivalent transmission line model is established based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board. In transient solution mode, time-domain reflection impedance simulation is performed on the equivalent transmission line model to obtain the actual impedance value; the actual impedance value is the layer switching impedance of the surface trace to the inner trace segment. The width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure are adjusted based on the difference between the actual impedance value and the target impedance value to obtain the optimized signal swap structure.

2. The signal layer switching structure optimization method for DDR5 printed circuit boards according to claim 1, characterized in that, The basic structural parameters specifically include: the radius of the pad connecting the trace and the layer replacement conductor, the width and thickness of the layer replacement conductor, the parallel distance between the layer replacement conductor and the vertical GND reference layer, the lateral and longitudinal distances of the filling dielectric, the vertical distances from both ends of the vertical GND reference layer to the signal trace, the radius of the arcs on both sides, and the radius of the chamfered arc of the dielectric.

3. The signal layer switching structure optimization method for DDR5 printed circuit boards according to claim 1, characterized in that, The process of establishing an equivalent transmission line model based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board specifically includes: Based on the basic structural parameters of the signal switching structure in the vertical direction of the printed circuit board, an equivalent transmission line model is established using the three-dimensional full-wave electromagnetic simulation software HFSS.

4. The signal layer switching structure optimization method for DDR5 printed circuit boards according to claim 1, characterized in that, The optimized signal layer swapping structure is obtained by adjusting the width of the swapping conductor and the parallel distance between the swapping conductor and the vertical GND reference layer based on the difference between the actual impedance value and the target impedance value. Specifically, this includes: When 0 < w / d ≤ 1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment; When w / d≥1, use the formula Determine the layer switching impedance Z of the surface layer trace to the inner layer trace segment; Where, ε ex The equivalent dielectric constant of each layer of filling medium in the vertical direction is given. w d represents the width of the layer-swapping conductor, and d represents the parallel distance between the layer-swapping conductor and the vertical GND reference layer.

5. A signal layer switching structure optimization device suitable for DDR5 printed circuit boards, characterized in that, The signal layer switching structure optimization device suitable for DDR5 printed circuit boards includes: The data acquisition module is used to acquire the signal layer switching structure of the DDR5 printed circuit board and the target impedance values ​​corresponding to the surface layer traces and inner layer traces in the signal layer switching structure. The equivalent transmission line model determination module is used to establish an equivalent transmission line model based on the basic structural parameters of the signal layer structure in the vertical direction of the printed circuit board. The actual impedance value determination module is used to perform time-domain reflection impedance simulation on the equivalent transmission line model in transient solution mode to obtain the actual impedance value; the actual impedance value is the layer switching impedance of the segment from the surface layer to the inner layer. The structure optimization module is used to adjust the width of the swap conductor and the parallel distance between the swap conductor and the vertical GND reference layer in the signal swap structure according to the difference between the actual impedance value and the target impedance value, so as to obtain the optimized signal swap structure.

6. A computer device, comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that the processor executes the computer program to implement the signal layer swapping structure optimization method for DDR5 printed circuit boards according to any one of claims 1-4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the signal layer swapping structure optimization method for DDR5 printed circuit boards as described in any one of claims 1-4.

8. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the signal layer swapping structure optimization method for DDR5 printed circuit boards as described in any one of claims 1-4.

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