Method of manufacturing electronic device including memory circuit

Abstract

The invention relates to a method of manufacturing an electronic device including a memory circuit. An electronic device includes a semiconductor substrate, an insulating layer on and in contact with the semiconductor substrate, and a memory circuit including a plurality of memory cells. Each memory cell includes a bipolar select transistor disposed in and on a semiconductor substrate, each bipolar select transistor including a base region, an emitter region, and a collector region. Each bipolar select transistor includes an insulating structure made of a first dielectric material, the insulating structure including an upper portion extending vertically through the insulating layer between the base region and the emitter region and a lower portion extending vertically through the semiconductor substrate. A side of an upper portion of the insulating structure is covered by a spacer made of a second dielectric material.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application number FR2404887, filed on May 14, 2024, entitled “Procédéde fabrication d'undispositifélectronique comprenant un circuit mémoire”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This specification relates generally to electronic devices, and more specifically to electronic devices including memory circuitry. Background Technology

[0004] Electronic devices comprise both memory circuits and logic circuits. Of particular interest here are electronic devices that include memory circuits comprising memory elements arranged in an array, each memory element being associated with a bipolar selection transistor. These transistors are used to program, erase, or read each memory element individually.

[0005] The aim is to improve at least some aspects of known electronic devices. Summary of the Invention

[0006] One embodiment provides an electronic device comprising:

[0007] Semiconductor substrate;

[0008] An insulating layer covering a semiconductor substrate, situated on and in contact with the semiconductor substrate; and

[0009] A memory circuit comprising multiple memory cells, each memory cell including a bipolar selection transistor disposed in and on a semiconductor substrate, each bipolar selection transistor including a base region, an emitter region, and a collector region.

[0010] Each bipolar selection transistor includes an insulating structure made of a first dielectric material, the insulating structure including an upper portion extending vertically through an insulating layer between the base region and the emitter region and a lower portion extending vertically through a semiconductor substrate, the sides of the upper portion of the insulating structure being covered by spacers made of a second dielectric material.

[0011] According to one embodiment, the device further includes logic circuitry comprising a plurality of fin field-effect transistors disposed in and on a semiconductor substrate, each fin field-effect transistor including a source region and a drain region.

[0012] Two adjacent fin field-effect transistors are separated by an additional insulating structure made of a first dielectric material. The insulating structure includes an upper portion extending vertically through the insulating layer between the drain and source regions of the two adjacent transistors and a lower portion extending vertically through the semiconductor substrate. The sides of the upper portion of the insulating structure are covered by spacers made of a second dielectric material.

[0013] According to one embodiment, the insulation structure of the memory circuit and the insulation structure of the logic circuit have the same depth.

[0014] According to one embodiment, the insulation structure of the memory circuit and the insulation structure of the logic circuit have different depths.

[0015] According to one embodiment, each memory cell includes a memory element comprising a layer made of a phase change material.

[0016] According to one embodiment, the memory circuitry includes an interconnect stack disposed on a semiconductor substrate, the interconnect stack including a series of levels in which interconnect elements are defined.

[0017] According to one embodiment, the memory elements are arranged on an interconnect stack.

[0018] Another embodiment provides a method for manufacturing an electronic device in and on a semiconductor substrate, the electronic device including a memory circuit including a plurality of memory cells, each memory cell including a selectable bipolar transistor formed in and on the semiconductor substrate, each selectable bipolar transistor including a base region, an emitter region and a collector region, the method including the following steps:

[0019] A sacrificial gate made of sacrificial material is formed on a semiconductor substrate;

[0020] Spacers made of dielectric material are formed on the side of the sacrificial gate;

[0021] The sacrificial material in the sacrificial gate is removed, and the substrate opposite the sacrificial gate is etched to form an opening surrounded by spacers at the top and extending through the substrate at the bottom. The opening is then filled with another dielectric material to form an insulating structure made of that other dielectric material.

[0022] An insulating layer is formed on and in contact with a semiconductor substrate. The insulating structure thus includes an upper portion extending vertically through the insulating layer between the base region and the emitter region of a bipolar transistor and a lower portion extending vertically through the semiconductor substrate. The sides of the upper portion of each insulating structure are covered by spacers.

[0023] According to one embodiment, the device further includes logic circuitry comprising a plurality of fin field-effect transistors, each fin field-effect transistor including a source region and a drain region, the method comprising the following steps:

[0024] A sacrificial gate made of sacrificial material is formed on a semiconductor substrate;

[0025] Spacers made of dielectric material are formed on the side of the sacrificial gate;

[0026] The sacrificial material in the sacrificial gate is removed, and the substrate opposite the sacrificial gate is etched to form an opening surrounded by spacers at the top and extending through the substrate at the bottom. The opening is then filled with another dielectric material to form a separate insulating structure of that dielectric material.

[0027] An insulating layer is formed on and in contact with the semiconductor substrate. The additional insulating structure therefore includes an upper portion extending vertically through the insulating layer between the source and drain regions of each fin field-effect transistor and a lower portion extending vertically through the semiconductor substrate. The sides of the upper portion of the additional insulating structure are covered by spacers.

[0028] According to one embodiment, the steps for forming the insulating structure of the memory circuit and the additional insulating structure of the logic circuit are common.

[0029] In one embodiment, a method includes: forming a first sacrificial gate of a first sacrificial material on a semiconductor substrate; forming a first spacer of a first dielectric material on the side surface of the first sacrificial gate; and forming a plurality of bipolar transistors in and on the semiconductor substrate, each bipolar transistor including a base region, an emitter region, and a collector region. The method includes forming a first opening surrounded by the first spacer at its upper portion and extending through the substrate at its lower portion by removing the first sacrificial gate and etching the substrate; and forming a first insulating structure by filling the opening with a second dielectric material. The method includes an insulating layer formed on and in contact with the semiconductor substrate. The first insulating structure includes an upper portion extending vertically through the insulating layer between the base and emitter regions of the bipolar transistors and a lower portion extending vertically through the semiconductor substrate. The side surface of the upper portion of each first insulating structure is covered by the first spacer.

[0030] In one embodiment, each bipolar transistor is part of a corresponding memory cell of a memory circuit.

[0031] In one embodiment, the method includes forming a second sacrificial gate on a semiconductor substrate, forming second spacers of a first dielectric material on the sides of the second sacrificial gate, and forming a plurality of fin field-effect transistors, each fin field-effect transistor including a source region and a drain region. The method includes forming a second opening, surrounded by spacers at the top and extending through the substrate at the bottom, by removing the second sacrificial gate between the second spacers and etching the substrate. The method includes forming a second insulating structure by filling the second opening with a second dielectric material. The second insulating structure includes an upper portion extending vertically through an insulating layer between the source and drain regions of each fin field-effect transistor and a lower portion extending vertically through the semiconductor substrate. The sides of the upper portion of the second insulating structure are covered by the second spacers.

[0032] In one embodiment, the fin field-effect transistor is part of a logic circuit.

[0033] In one embodiment, the method includes simultaneously forming a first insulating structure and a second insulating structure.

[0034] In one embodiment, a method includes forming a first sacrificial gate structure on a semiconductor substrate and forming a first spacer of a first dielectric material on the sidewalls of the first sacrificial gate structure. The method also includes forming a base region and an emitter region of a bipolar transistor in the semiconductor substrate, each base region and emitter region contacting a corresponding first spacer in the first spacer, and replacing the first sacrificial gate structure with a first insulating structure of a second dielectric material extending into the semiconductor substrate.

[0035] In one embodiment, the method includes forming an insulating layer in contact with a semiconductor substrate, wherein a first insulating structure extends vertically through the insulating layer.

[0036] In one embodiment, the method includes forming a base region and an emitter region in an epitaxial growth process separate from the semiconductor substrate.

[0037] In one embodiment, the method includes forming a second sacrificial gate structure on a semiconductor substrate, forming a second spacer of a first dielectric material on the sidewalls of the second sacrificial gate structure, and forming a first source / drain region of a first fin field-effect transistor and a second source / drain region of a second fin field-effect transistor, each source / drain region contacting a corresponding second spacer in the second spacer. The method also includes replacing the second sacrificial gate structure with a second insulating structure of a second dielectric material extending into the semiconductor substrate.

[0038] In one embodiment, the method includes forming a first source region / first drain region, a second source region / second drain region, and a base region in the same first epitaxial growth process.

[0039] In one embodiment, the method includes forming an emitter region in a second epitaxial growth process.

[0040] In one embodiment, the first fin field-effect transistor and the second fin field-effect transistor are part of a logic circuit.

[0041] In one embodiment, the bipolar transistor is part of a memory cell in a memory circuit. Attached Figure Description

[0042] In the following description of specific embodiments given by way of example rather than limitation, the above-described features and advantages, as well as other features and advantages, will be described in detail with reference to the accompanying drawings, in which:

[0043] Figure 1A , Figure 1B and Figure 1C This is a schematic partial view of an example electronic device according to the first embodiment;

[0044] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B It shows the manufacturing process. Figure 1A , Figure 1B and Figure 1C A view of the steps in the example process of the electronic chip shown;

[0045] Figure 17A and Figure 17B A schematic partial view of an example electronic device according to a second embodiment; and

[0046] Figure 18A and Figure 18B This is a schematic partial view of an example electronic device according to a third embodiment. Detailed Implementation

[0047] In the various figures, similar features are indicated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0048] For clarity, only operations and elements that help to understand the embodiments described herein are shown and described in detail.

[0049] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or coupled via one or more other elements.

[0050] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as the terms “front,” “back,” “up,” “down,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or orientation qualifiers (such as “horizontal,” “vertical,” etc.), reference is made to the orientation shown in the figures.

[0051] Unless otherwise stated, “approximately,” “roughly,” “basically,” and “about” mean within 10% or 10°, and preferably within 5% or 5°.

[0052] As used herein, the source and drain terminals of a transistor may be referred to as source / drain terminals, without specifying whether a particular terminal is a source terminal or a drain terminal.

[0053] Figure 1A , Figure 1B and Figure 1C This is a schematic partial cross-sectional view of an example electronic device according to the first embodiment. More specifically, Figure 1A and Figure 1B This is a vertical cross-sectional view of the aforementioned device, and Figure 1C This is a horizontal cross-sectional view of the aforementioned device. Figure 1A Corresponding to Figure 1C The view shown is along the cutting plane AA. Figure 1B Corresponding to Figure 1C The view shown is along the cutting plane BB, while Figure 1C Corresponding to Figure 1A and Figure 1B The top view shown is along the hierarchical cutting plane CC. Note that in... Figure 1C In the image, some elements are shown in a transparent manner.

[0054] In particular, Figure 1A , Figure 1B and Figure 1CThe memory circuitry of electronic device 11 is shown. For example, electronic device 11 includes logic circuitry in portions not shown. For example, the logic and memory circuitry are manufactured concurrently on the same semiconductor substrate.

[0055] For example, device 11 is a microchip.

[0056] The device 11 includes a semiconductor substrate 13. For example, the substrate 13 is made of silicon or a silicon-based material.

[0057] For example, substrate 13 includes a semiconductor layer 15 doped with a first conductivity type (e.g., N-type) (e.g., doped with arsenic or phosphorus atoms). For example, layer 15 is located on and in contact with another semiconductor layer 17 of substrate 13, which is doped with a second conductivity type opposite to the first conductivity type, such as P-type, for example, doped with boron atoms.

[0058] For example, substrate 13 includes a semiconductor layer 25. For example, layer 25 is located on and in contact with layer 15. Therefore, layer 25 is separated from layer 17 by layer 15. For example, layer 25 is flush with the top surface of substrate 13. Semiconductor layer 25 is, for example, a layer epitaxially formed from the top surface of layer 15. For example, layer 25 is made of silicon, such as monocrystalline silicon. For example, layer 25 includes a plurality of regions 27 and a plurality of regions 29. Figures 1A to 1C In the illustrated embodiment, region 27 extends longitudinally as a line in the first direction, and region 29 extends longitudinally as a line in the same first direction. For example, regions 27 and 29 are... Figure 1B It extends in the plane direction shown. Therefore, in Figures 1A-1C In one example, substrate 13 includes a line comprising alternating regions 27 and 29 extending in a first direction.

[0059] Each region 27 or 29 preferably extends over the entire height of layer 25. Therefore, each region 27 or 29 is flush with the top surface of layer 25. For example, each region 27 or 29 contacts the bottom surface of layer 15.

[0060] For example, region 27 is doped with a second conductivity type, such as P-type. For example, region 27 includes germanium and boron atoms. For example, region 27 is more heavily doped than layer 17.

[0061] For example, region 29 is doped with a first conductivity type, such as N-type. For example, region 29 includes phosphorus atoms. For example, region 29 is more heavily doped than layer 15.

[0062] The device 11 includes a plurality of transistors 12 formed in and on a substrate 13. For example, each transistor 12 includes a single region 27 and a single region 29 on the substrate 13.

[0063] For example, transistors 12 are separated from each other and electrically insulated, for example, by insulating trenches 14. Insulating trenches 14 are, for example, shallow trench insulation (STI) trenches. For example, trenches 14 are divided into two types: trenches 14a extending longitudinally in a first direction and trenches 14b extending longitudinally in a second direction. For example, when viewed from above, insulating trenches 14a and 14b form a grid.

[0064] The insulating trench 14 extends, for example, from a surface located at an intermediate layer between the top and bottom surfaces of layer 25. Trench 14 preferably extends through a portion of layer 25, through layer 15, and through a portion of layer 17. The insulating trench 14 is, for example, filled with a dielectric material such as silicon oxide. For example, trench 14a and trench 14b have the same depth. The depth of trench 14 is, for example, between 250 nm and 400 nm.

[0065] Therefore, the transistors 12 are arranged in an array within the grid formed by the trenches 14. Thus, the substrate 13 includes rows and columns of transistors 12.

[0066] Each transistor 12 is included within a basic memory cell. Each memory cell also includes a memory element M, which is preferably formed at least partially in a line with the transistor 12, for example, in a line with region 27 of the transistor 12. Unlike region 27, region 29 is, for example, not covered by the memory element M. For example, within each memory cell, transistor 12 is a selection transistor for memory element M.

[0067] When viewed from above, for example, memory elements M are organized into an array of rows and columns. These are respectively referred to as word lines extending in the second direction (i.e., the direction of trench 14b) and bit lines extending in the first direction (i.e., the direction of trench 14a). For example, each memory element M is located at the intersection of bit lines and word lines. Figure 1B The memory element M shown is a memory element on the same word line WL, while Figure 1A The memory elements shown are memory elements on the same bit line BL. Figure 1B In the image, only six bit lines are shown, and... Figure 1A The diagram shows only three word lines. However, in practice, memory circuits can include different numbers of bit lines and word lines, such as more than six and three, respectively.

[0068] For example, each insulating trench 14b extends longitudinally in the word line direction over the entire length of the word line. For example, each insulating trench 14a extends longitudinally in the bit line direction over the entire length of the bit line. The transistor array 12 substantially corresponds to the memory element array M.

[0069] exist Figures 1A-1C In the example shown, each transistor 12 is defined by region 29, region 27, and layer 17, all coupled to layer 15. In this example, region 27 forms the emitter region of transistor 12, layer 15 forms the base region of transistor 12, region 29 forms the base access region of transistor 12, and layer 17 forms the collector region of transistor 12. For example, the collector is common to all transistors 12 in the array and is connected to ground, for example. In this example, the base region 15 is common to all transistors 12 on the same word line of the memory circuit.

[0070] Transistor 12 is, for example, a PNP bipolar select (bipolar junction transistor, BJT) transistor.

[0071] The device 11 includes an insulating layer 18 covering the top surface of the semiconductor substrate 13 and more specifically, the top surface of the layer 25. The insulating layer 18 is in contact with the top surface of the layer 25, for example. For example, the insulating layer 18 covers the entire top surface of the layer 25. The thickness of the insulating layer 18 is between 80 nm and 300 nm, for example, between 120 nm and 200 nm.

[0072] Device 11 also includes an insulating structure or trench 16. Trench 16 is, for example, a Single Diffusion Break (SDB) trench. For example, trench 16 extends through layer 25, thereby separating region 27 from region 29 of each transistor 12. In other words, regions 27 and 29 of each transistor 12 are separated by trench 16. For example, each trench 16 extends longitudinally in the direction of the word line, for example, along the entire length of the word line.

[0073] For example, each trench 16 is located between two trenches 14b. Therefore, in the bit line direction, the substrate 13 includes alternating trenches 14b and trenches 16.

[0074] Each insulating trench 16 includes an upper portion 16s extending vertically through the insulating layer 18 and a lower portion 16i extending vertically through the semiconductor substrate 13.

[0075] The upper portion 16s of each insulating trench 16 is covered by spacers 21 made of a second dielectric material. The spacers 21 are made of, for example, an electrically insulating material such as silicon nitride. For example, the upper portion 16s of each trench 16 includes a lower portion that contacts layer 25 around the sidewalls of the spacers 21, and more specifically, contacts regions 27 and 29. For example, the bottom surface of each spacer 21 is located on the top surface of layer 15, for example, between regions 27 and 29.

[0076] The lower portion 16i of the trench 16 extends from the top surface of layer 15 through layer 15. For example, the lower portion 16i of the trench 16 does not extend into layer 17.

[0077] The lower portion 16i of each insulating trench 16 is not covered by spacers on its side, and in this portion, the insulating trench 16 is in direct contact with the layer 15 of the substrate 13.

[0078] For example, the depth of trench 16 is less than that of trench 14. Trench 16 extends, for example, from a surface located at an intermediate layer between the top and bottom surfaces of layer 18. The insulating trench 16 is, for example, filled with a dielectric material such as silicon oxide. Trench 16 has a height or depth (measured between the top and bottom surfaces of trench 16) of, for example, between 50 nm and 150 nm.

[0079] For example, vias 20 and 22 pass through layer 18. For example, the bottom surfaces of vias 20 and 22 contact the top surface of layer 25, such that each region 27 and 29 is topped by either via 20 or 22. For example, via 20 contacts region 27. For example, via 22 contacts region 29. For example, vias 20 and 22 extend over the entire height of layer 18. Therefore, vias 20 and 22 extend from the top surface of layer 18 to the bottom surface of layer 18.

[0080] For example, layer 18 is covered by an interconnect stack 35. In this example, the interconnect stack 35 is formed between the substrate 13 and the memory element M. The interconnect stack 35 is formed, for example, on the top surface of the insulating layer 18 and covers, for example, the entire surface of the insulating layer 18.

[0081] The interconnect stack 35 is formed, for example, by a series of layers 36, each layer 36 including an insulating layer 37 and an insulating layer 39. The interconnect stack 35 includes, for example, a layer 36a, which includes an insulating layer 39a formed on and in contact with the top surface of the insulating layer 18. In layer 36a, the interconnect stack 35 also includes an insulating layer 37a formed on the insulating layer 39a. The insulating layer 37a is formed, for example, over the entire surface of the insulating layer 39a. For example, the bottom surface of the insulating layer 37a contacts the top surface of the insulating layer 39a.

[0082] The interconnect stack 35 may also include an additional layer formed on and in contact with layer 36a, i.e., formed on and in contact with insulating layer 37a. Figure 1A and Figure 1B In this configuration, the interconnect stack 35 includes two additional layers 36b and 36c, for example, formed by layers 37b and 39b and by layers 37c and 39c, respectively. In practice, the number of layers in the interconnect stack 35 may be different from three, for example, more than three.

[0083] For example, the thickness of the interconnect stack 35 is between 200 nm and 800 nm, such as between 250 nm and 600 nm, approximately 350 nm.

[0084] For example, insulating layers 18 and 37 are made of materials with low dielectric constants, such as materials with a dielectric constant (corresponding to the dielectric constant of the aforementioned materials relative to the vacuum dielectric constant) of less than 5, for example, less than 4. Insulating layer 37 is made of SiCN, for example. Insulating layer 39 is made of a low dielectric constant oxide, referred to as "low k" or "ultra-low k".

[0085] Each layer 36 includes a conductive via 69 and a conductive track 71, which extends within layer 39 from, for example, the top surface of layer 39, and is therefore flush with the top surface of layer 39. Preferably, the track 71 of layer 36 extends only within layer 39 of the aforementioned layer 36. The vias 69 of the layers of stack 35 extend through layers 39 and 37 of the same layer 36. More specifically, the vias 69 of the layers of stack 35 extend from the bottom surface of the track 71 of the same layer to the bottom surface of layer 37 or to the top surface of the vias 20 or 22 through layer 18.

[0086] For example, via 69 and conductive rail 71 are made of a metallic material such as copper. For example, conductive rail 71 extends laterally over a surface area between 20 nm × 20 nm and 60 nm × 60 nm (e.g., approximately 30 nm × 30 nm). For example, conductive rail 71 extends laterally over a surface area greater than or equal to the area of ​​via 69.

[0087] exist Figures 1A to 1C In the illustrated embodiment, memory element M is formed on the top surface of stack 35. For example, memory element M is separated from stack 35 by insulating layer 45. Insulating layer 45 is made of, for example, silicon nitride, SiCN, oxide, or a stack of several of these materials, such as a stack of SiCN and oxide. For example, layer 45 contacts the top surface of layer 39c via its bottom surface. Layer 45 also contacts the bottom surface of memory element M via its top surface.

[0088] For example, memory element M is a phase-change memory element. For example, each element includes a phase-change material layer 47, such as a chalcogenide material, for example, a germanium, antimony, and tellurium alloy (GeSbTe), referred to as GST. For example, the thickness of layer 47 is between 30 nm and 100 nm, for example, approximately 50 nm. For example, memory elements M on the same bit line include a common layer 47. Thus, for example, device 11 includes as many layers 47 as bit lines. Each layer 47 extends in the direction of the bit line.

[0089] In each memory element M, the phase change material is controlled, for example, by a metal resistance heating element 49 located below the phase change material. For example, element 49 is in contact with the bottom surface of layer 47 via its top surface. For example, element 49 is laterally surrounded by a heat-insulating layer 51. For example, as... Figure 1A As shown in the cut plane, each element 49 is "L"-shaped. For example, layer 51 is made of nitride. For example, the height of the heating element 49 is between 30 nm and 100 nm, for example, about 60 nm.

[0090] Layer 47 is covered, for example, by layer 53, which is made of, for example, a conductive material (such as a metallic material). More precisely, the top surface of each layer 47 is at least partially covered, for example, completely covered, by layer 53. Each layer 53 preferably extends over the entire length of layer 47 in the direction of the bit line.

[0091] For example, in each memory element M, metal element 49 and layer 53 form the bottom electrode and top electrode of memory element M, respectively, and more specifically, form the electrode of the variable resistance element formed by layer 47 made of phase change material. For example, memory elements M on the same bit line are covered by the same layer 53. In other words, the top electrodes 53 of memory elements M on the same bit line are interconnected.

[0092] For example, each memory element M is covered by an insulating layer 55 to protect layer 47, for example, made of a phase change material, from oxidation. For example, layer 55 covers the top surface of layer 53 and the sides of layers 53, 47, and 51. For example, layer 55 is made of a dielectric material. For example, insulating layer 55 is made of a nitride such as silicon nitride.

[0093] For example, memory elements M on adjacent bit lines are insulated from each other by an insulating layer 59. The insulating layer 59 is made of, for example, a material with a low dielectric constant. Alternatively, layer 59 is made of an oxide such as silicon dioxide.

[0094] Therefore, in Figures 1A to 1C In the illustrated embodiment, each memory element M is electrically connected to its associated selection transistor 12 via a conductive via 63 that passes through all layers of the interconnect stack 35. For example, the via 63 passes through all insulating layers 37 and 39 of the interconnect stack 35 located between layer 45 and layer 18.

[0095] For example, a via 63 associated with each memory element M contacts the bottom surface of the resistive heating element 49 of the memory element M via its top surface. For example, the bottom surface of via 63 contacts a conductive via 22, which itself contacts the top surface of region 27 of the transistor 12 associated with the memory element M. In other words, for each memory element M, the corresponding via 63 electrically couples the heating element 49 of the memory cell to the underlying region 27.

[0096] For example, the conductive via 63 is made of a metallic material. For example, the conductive via 63 is made of tungsten. Alternatively, the conductive via is made of cobalt or copper. For example, in... Figure 1A plane and Figure 1B In the plane, the width of the conductive via 63 is between 20nm and 100nm, for example, about 40nm.

[0097] For example, vias 69 extend below layer 47 to the outside of the memory circuit, where they can be connected to apply a potential to the word lines of the memory element M.

[0098] For example, layer 53 is connected to a conductive element via its top surface, so that a potential can be applied to the bit line of memory element M.

[0099] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B It shows the manufacturing process. Figure 1A , Figure 1B and Figure 1C A view of the steps in an example process of the electronic device shown.

[0100] More specifically, Figures 2 to 16B This illustrates methods for concurrent manufacturing or co-integration within the same integrated circuit device. Figures 1A to 1C The diagram shows a view of the process of the memory circuitry (including bipolar selection transistors) and logic circuitry (e.g., logic circuitry adjacent to the memory circuitry, including fin field-effect transistors (FinFETs)) of the chip 11. Figures 2 to 16BTwo regions a) and b) of the device are shown, in which two bipolar selection transistors and two FinFET transistors are formed, respectively. It should be understood that in practice, region a) may include more than two bipolar selection transistors, and region b) may include more than two FinFET transistors.

[0101] Figure 2 A schematic partial cross-sectional view of the initial structure including the semiconductor substrate 13 is shown. Figure 2 In the process described below, substrate 13 includes a first region a) and a second region b), wherein a FinFET transistor is formed in the first region and on the first region, and a selective bipolar transistor is formed in the second region and on the second region.

[0102] Figure 3 It shows the use of in Figure 2 A schematic partial cross-sectional view of the structure obtained at the end of the step of forming the trench 60 in the first region a) of the substrate 13 shown.

[0103] Forming trench 60 allows the fins of a FinFET transistor to be defined between trenches 60. For example, trench 60 extends in the direction of the bit line, i.e., in relation to... Figure 3 The direction of the cutting plane shown is orthogonal to the direction.

[0104] The trench 60 extends through the substrate 13, for example, from the top surface of the substrate 13.

[0105] For example, in a cross-sectional view, the trench 60 is not rectangular in shape, with its bottom and sides orthogonal. For example, in a cross-sectional view, the trench 60 is trapezoidal, where the width of the trench 60 at its top surface is greater than the width of the trench 60 at its bottom surface. For example, the trench pitch is between 20 nm and 100 nm, for example, between 30 nm and 50 nm. For example, the width of the trench 60 at the top surface of the substrate 13 is between 10 nm and 90 nm, for example, between 20 nm and 40 nm. For example, the depth to which the trench 60 extends is between 20 nm and 400 nm, for example, between 100 nm and 200 nm, for example, approximately 150 nm. The trench 60 defines a transistor fin, the width of which is, for example, between 2 nm and 30 nm, for example, between 5 nm and 15 nm, for example, between 7 nm and 8 nm.

[0106] Figure 4 It shows in Figure 3 A schematic partial cross-sectional view of the structure obtained at the end of step 62 of depositing layer 62 on the top surface of the structure shown.

[0107] More specifically, in this step, layer 62 is deposited on the top surface of substrate 13 and in trench 60. For example, in this step, layer 62 completely covers the top surface of substrate 13. For example, layer 62 is made of a dielectric material such as oxide.

[0108] Figure 5 It shows from Figure 4 A schematic partial cross-sectional view of the structure obtained at the end of step 62 of removing the upper layer of the structure shown.

[0109] More specifically, in the first stage, layer 62 is removed from the top surface of substrate 13 to expose the top surface of substrate 13. For example, this removal is performed by chemical mechanical polishing (CMP). For example, the removal of layer 62 is stopped when the top surface of substrate 13 is exposed.

[0110] In the second stage, layer 62 is removed from the upper part of trench 60, leaving only the lower part of trench 60. For example, this removal is performed to a depth between 10 nm and 100 nm, such as approximately 50 nm.

[0111] Figure 6 It shows the use of in Figure 5 A schematic partial cross-sectional view of the structure obtained at the end of the step of forming the trench 14b in the substrate 13 shown.

[0112] Trench 14b is formed in substrate 13, for example, by extending through substrate 13 from the top surface of substrate 13. For example, the depth of trench 14b is greater than the depth of trench 60. For example, trench 14b is formed in substrate 13 in a first region a) and a second region b). For example, trench 14b allows some of it to be located in memory circuitry to insulate adjacent bit lines from each other, and allows some of it to be located between logic circuitry and memory circuitry to insulate the logic circuitry from the memory circuitry.

[0113] Figure 7A , Figure 7B , Figure 7C and Figure 7D It shows the use of in Figure 6 A schematic partial view of the structure obtained at the end of the step of forming trench 14a in the substrate 13 shown. More specifically, Figure 7B , Figure 7C and Figure 7D It is a cross-sectional view, and Figure 7A It is used in Figure 6 A top view of the structure obtained at the end of the step of forming trench 14a in substrate 13 shown. Figure 7B It is based on Figure 7A The cross-sectional view of the cutting plane BB is shown below. Figure 7C It is based on Figure 7AThe cross-sectional view of the cutting plane CC is shown, and Figure 7D It is based on Figure 7B The cross-sectional view of the cutting plane DD is shown. Figure 7C It also corresponds to a cross-sectional view within the first region a) of substrate 13, and Figure 7D A cross-sectional view corresponding to the second region b) of substrate 13.

[0114] The trench 14a is formed, for example, by extending through the substrate 13 from the top surface of the substrate 13. For example, the depth of the trench 14a is greater than the depth of the trench 60. For example, the trench 14a is formed in the substrate 13 in a first region a) and a second region b). For example, the trench 14a allows adjacent word lines to be insulated. For example, the same trench 14a may extend through both the first region a) and the second region b) of the substrate 13. Alternatively, the same trench 14a may extend only through the first region a) or only through the second region b). Alternatively, the same trench 14a may extend only over a portion of the first region a) and / or only over a portion of the second region b).

[0115] For example, the formation of trench 14 includes a preliminary step of depositing a protective layer, such as one made of nitride, which allows protection of the structure in areas where trench 14 is not formed. For example, at the end of the formation of trenches 14a and 14b, they are filled, for example, with a semiconductor material. For example, trenches 14a and 14b are filled with oxide. After the step of filling trenches 14a and 14b, for example, a CMP step stops on the top surface of the aforementioned protective layer. For example, in one embodiment, after the CMP step, the protective layer is removed to expose the top surface of substrate 13.

[0116] Although this embodiment has described filling trenches 14a and 14b with dielectric material in a single step, it may be specified that prior to forming trench 14a, in Figure 6 The groove 14b is filled at the end of the steps shown.

[0117] Furthermore, although it has been described in this embodiment that trench 14b is executed before trench 14a, it can be specified that the execution order of these trenches is reversed, and trench 14a is executed before trench 14b.

[0118] As an example, although not shown, at the end of the formation of trenches 14a and 14b, the structure is covered by a layer made of a dielectric material (e.g., oxide). Thus, the oxide layer covers the top surface of substrate 13, the top surface of trenches 14a and 14b, the top surface of layer 62 in trench 60, and the side surface of trench 60 above layer 62 in the first region a) and the second region b).

[0119] Figure 8A and Figure 8B It shows in Figures 7A to 7D A schematic partial cross-sectional view of the structure obtained at the end of the step of forming layers 15 and 17 in the second region b) of the substrate 13 of the structure shown.

[0120] More specifically, Figure 8A It shows the path along with Figure 7C The cross-section shown is a cross-sectional view of the same cutting plane, that is, a cross-sectional view through region a) of the substrate 13 in which the FinFET transistor is formed;

[0121] Figure 8B It shows the path along with Figure 7D The cross-sectional view shown is of the same cutting plane, that is, the cross-section through region b) of the substrate 13 in which the selective bipolar transistor is formed.

[0122] For example, in this step, the substrate 13 is doped to form an N-type doped layer 15 on the upper part of the substrate 13 and a P-type doped layer 17 on the lower part of the substrate 13. For example, in this step, implantation is performed such that the junction between layer 15 and layer 17 is shallower than the trenches 14a and 14b.

[0123] As an example, this step is performed only in the second region b) of substrate 13. At the end of this step, the first region a) of substrate 13 does not include either layer 15 or 17.

[0124] Figure 9A and Figure 9B It shows in Figure 8A and Figure 8B A schematic partial cross-sectional view of the structure obtained when the sacrificial gate 67 is formed on the surface of the structure shown.

[0125] More specifically, in this step, a sacrificial gate 67 is formed on the top surface of the substrate 13 in the first region a) and the second region b). The gate 67 includes, for example, a so-called sacrificial material. For example, the gate 67 includes a semiconductor layer, such as polysilicon. For example, the gate 67 also includes a dielectric layer on the semiconductor layer, such as made of silicon nitride.

[0126] For example, gate 67 is formed by depositing the aforementioned layer on the entire wafer prior to etching.

[0127] Figure 10A and Figure 10B It shows in Figure 9A and Figure 9B A schematic partial cross-sectional view of the structure obtained at the end of the step of forming spacers 21 and 68 on the structure shown.

[0128] More specifically, in this step, in Figure 9A Spacers 68 are formed on the first region a) of the substrate 13 shown, and Figure 9B Spacers 21 are formed on the second region b) of the substrate 13 shown to form as shown Figure 10A The spacer 68 shown is formed as follows: Figure 10B The spacer 21 shown.

[0129] For example, through Figure 9A and Figure 9B A layer is deposited on the top surface of the structure shown, and spacers 68 and 21 are formed in the same step. In this step, the layer covers the top surface of the substrate 13 in the first region a) and the second region b), as well as the side and top surfaces of the gate 67.

[0130] Alternatively, spacers 68 and 21 are formed in two consecutive steps. For example, spacer 68 can be formed by depositing a layer on the top surface of substrate 13 while masking the second region b). Similarly, spacer 21 can be formed by depositing a layer on the top surface of substrate 13 while masking the first region a).

[0131] For example, on the top surface of substrate 13, at the end of this step, one or more layers forming spacers 68 and 21 are removed so that they remain in contact only with gate 67.

[0132] Figure 11A and Figure 11B It shows in Figure 10A and Figure 10B A schematic partial cross-sectional view of the structure obtained at the end of the formation of regions 70 and 29 on the substrate 13 of the structure shown.

[0133] More specifically, in this step, in Figure 10A Region 70 is formed in the first region a) of the substrate 13 shown, and... Figure 10B Region 29 is formed in the second region b) of the substrate 13 shown, to form as Figure 11A The area 70 shown forms a shape as described above. Figure 11B The area shown is 29.

[0134] For example, regions 70 and 29 are formed by epitaxial growth followed by implantation of N-type doped atoms. For example, the top surfaces of regions 70 and 29 are offset from the top surface of substrate 13. For example, the top surfaces of regions 70 and 29 face forward relative to the top surface of substrate 13 and are opposite to gate 67.

[0135] For example, region 70 extends longitudinally between gates 67 and between gate 67 and trench 14a. For example, region 29 extends between gate 67 and trench 14a only on one side of each gate 67.

[0136] For example, regions 70 and 29 are formed in the same step. Alternatively, regions 70 and 29 are formed in two consecutive steps.

[0137] For example, region 70 corresponds to the future source and drain regions of an NMOS FinFET transistor. In this structure, the drain of a transistor corresponds to the source of an adjacent transistor.

[0138] Figure 12A and Figure 12B It shows in Figure 11A and Figure 11B The schematic partial cross-sectional view of the structure obtained at the end of steps 72 and 27 in the structure shown.

[0139] More specifically, in this step, in Figure 11A Region 72 is formed in the first region a) of the substrate 13 shown, and in Figure 11B Region 27 is formed in the second region b) of the substrate 13 shown, to form as Figure 12A The area 72 shown is formed as follows. Figure 12B The area shown is 27.

[0140] For example, regions 72 and 27 are formed by epitaxial growth followed by implantation of P-type doped atoms. For example, the top surfaces of regions 72 and 27 are offset from the top surface of substrate 13. For example, the top surfaces of regions 72 and 27 face forward relative to the top surface of substrate 13.

[0141] For example, region 72 extends longitudinally between gates 67 and between gate 67 and trench 14a. For example, region 27 extends between gate 67 and trench 14a only on one side of each gate 67.

[0142] For example, regions 72 and 27 are formed in the same step. Alternatively, regions 72 and 27 are formed in two consecutive steps.

[0143] For example, region 72 corresponds to the future source and drain regions of a PMOS FinFET transistor. In this structure, the drain of a transistor corresponds to the source of an adjacent transistor.

[0144] For example, at the end of the steps in Figures 11 and 12, the gate 67 in the region extending between the two trenches 14a in the first region a) of substrate 13 is surrounded only by region 70, thereby forming an NMOS or N-channel metal-oxide-semiconductor transistor therein. Similarly, for example, at the end of the steps in Figures 11 and 12, the gate 67 in the region extending between the two trenches 14a in the first region a) of substrate 13 is surrounded only by region 72, thereby forming a PMOS or P-channel metal-oxide-semiconductor transistor therein.

[0145] For example, at the end of the steps shown in Figures 11 and 12, the gate 67 in the second region (b) is surrounded by region 29 on one side and region 27 on the other side.

[0146] Figure 13A and Figure 13B It shows in Figure 12A and Figure 12B A schematic partial cross-sectional view of the structure obtained at the end of the step of forming layer 74 on the top surface of the structure shown, and the step of polishing the structure thus obtained.

[0147] More specifically, in this step, in the first stage, by covering the top surface of the substrate 13 (in its first region a) and second region b), the top surfaces of regions 70, 72, 27 and 29, and the gate 67, in Figure 12A and Figure 12B Layer 74 is formed on the top surface of the structure shown.

[0148] In the second stage, the resulting structure is subjected to CMP to remove the upper portion of layer 74 and expose the top surface of gate 67. In this step, the upper portions of spacers 68 and 21 are further removed along with layer 74. At the end of this step, spacers remain only on the sides of gate 67. At the end of this step, the top surface of gate 67 is flush with the top surface of layer 74.

[0149] Figure 14A and Figure 14B It shows that from Figure 13A and Figure 13B A schematic partial cross-sectional view of the structure obtained at the end of the step of removing the sacrificial gate 67 and filling the opening formed therefrom with layer 76.

[0150] More specifically, in this step, the material constituting the gate 67 is removed in a first stage. An opening is then formed in layer 74, surrounded by spacers 68 and 21, and extends to the top surface of substrate 13. It can be considered that the gate 67 is thus "emptied".

[0151] In the second stage, layer 76 is deposited on the top surface of the structure thus formed. For example, layer 76 is deposited on the top surface of the structure such that the opening formed in place of gate 67 is filled by layer 76. For example, layer 76 is made of a metallic material, such as titanium nitride, tantalum nitride, and / or tungsten. For example, layer 76 comprises several sublayers made of one or more of the aforementioned materials. For example, prior to depositing layer 76 in the opening formed in place of gate 67, there is a step of depositing oxides and dielectric materials with high dielectric constants in these openings.

[0152] For example, at the end of this step, the structure undergoes a CMP step to expose the top surface of layer 74, so that layer 76 remains only in the opening.

[0153] At the end of this step, layer 76 corresponds to the metal gate 77 in the opening of layer 74.

[0154] Figure 15A and Figure 15B It shows in Figure 14A and Figure 14B A schematic partial cross-sectional view of the structure obtained at the end of the steps of forming grooves 16 and 78 in the structure shown.

[0155] More specifically, in this step, in Figure 14A A trench 78 is formed in the first region a) of the substrate 13 shown, opposite to the first region, in Figure 14B A trench 16 is formed in the second region b) of the substrate 13 shown, opposite to the second region, to form a trench 16 as shown in the figure. Figure 15A The groove 78 shown is formed as follows: Figure 15B The groove 16 shown.

[0156] In this step, for example, trenches 78 and 16 are formed to replace some of the metal gates 77. More specifically, for example, trenches 78 are formed in a first region a) of substrate 13 to replace only some of the metal gates 77, and trenches 16 are formed in a second region b) of substrate 13 to replace all of the metal gates 77.

[0157] For example, trenches 78 and 16 are formed by removing the metal material contained in gate 77. At the end of the removal step, the resulting openings extend, for example, deep through substrate 13 without opening into layer 17. At the end of this step, the extended openings are filled with a dielectric material, such as oxide.

[0158] For example, after the step of filling the opening with dielectric material is the CMP step so that no of the aforementioned material is left on the top surface of layer 74.

[0159] For example, at the end of this step, trenches 16 and 78 correspond to a single diffusion fracture (SDB) structure.

[0160] For example, trenches 16 and 78 have the same depth.

[0161] Alternatively, trenches 16 and 78 have different depths.

[0162] For example, in the first region a) of the substrate 13, the trench 78 will Figure 15A The two NMOS FinFET transistors on the left and Figure 15A The two PMOS FinFET transistors on the right are insulated.

[0163] Figure 16A and Figure 16B It shows that from Figure 15A and Figure 15B A schematic partial cross-sectional view of the structure obtained at the end of the steps of removing layer 74 and depositing insulating layer 18 on the structure thus formed.

[0164] In this step, for example, layer 74 is removed, and an insulating layer 18 is deposited on the top surface of the structure. For example, layer 18 is deposited opposite to the first region a) and the second region b) of the substrate 13.

[0165] Figure 17A and Figure 17B This is a schematic partial cross-sectional view of the example electronic device 211 according to the second embodiment. Figure 17A It is along Figure 17B The cross-sectional view of section AA is shown, and Figure 17B It is along Figure 17A The cross-sectional view of section BB is shown.

[0166] More specifically, Figure 17A and Figure 17B It is shown that... Figures 1A to 1C The device 11 shown is a view of a different electronic device 211, the difference being that in device 211, the trench 14a is not an STI trench, but a so-called FIN trench, which is formed similarly to the trench 60 that defines the fins of a FinFET transistor.

[0167] For example, the trench 14a of device 211 is therefore shallower than the trench 14a of device 11. Furthermore, the width of the trench 14a of device 211 is, for example, smaller than that of the trench 14a of device 11. Additionally, the trench 14a of device 211 has a repeating pitch, for example, larger than that of the trench 14a of device 11. In this embodiment, the trench defines a fin with a width between 15 nm and 50 nm, for example, between 20 nm and 30 nm, for example, approximately 25 nm. In this embodiment, the memory elements M are therefore closer together in device 211 than in device 11.

[0168] For example, device 211 has a connection with Figures 2 to 16B The manufacturing process of the described device 11 is compatible with a manufacturing process, except that the trench 14b is formed similarly to the trench 60, for example, before, after, or concurrently with the trench 60. A further difference between the manufacturing process of device 211 and the process described above is that the bonding process is omitted. Figure 6 The steps described. For example, in this embodiment, layer 15 may extend deeper than trench 14a. This means that trench 14a will not open into layer 17.

[0169] Figure 18A and Figure 18B This is a schematic partial view of an example electronic device according to the third embodiment. Figure 18A It is along Figure 18B The cross-sectional view of the cutting plane AA shown is shown. Figure 18B It is along Figure 18A The cross-sectional view of the cutting plane BB is shown.

[0170] More specifically, Figure 18A and Figure 18B This is a view showing electronic device 311, which is combined with... Figures 1A to 1C The difference in the illustrated device 11 is that, in device 311, there is no contact recovery for each memory cell track 71 and via 69. Furthermore, in this embodiment, layers 47 and 53 extend along the word line direction, and the metal element 49 extends along the bit line direction. Additionally, electronic device 311 is combined with... Figures 1A to 1C The difference in the illustrated device 11 is that the memory element M is formed between the interconnect network 35 and the substrate 13. In this embodiment, layer 25 does not include alternating regions 27 and 29, and therefore there is no trench 14b.

[0171] For example, in this embodiment, there is a groove 16 to separate two adjacent regions 27 and to separate region 27 from the adjacent region 29.

[0172] One advantage of this embodiment is that it allows FinFET transistors and bipolar selection transistors to be integrated into a single, identical electronic device while remaining compatible with conventional processes used to manufacture FinFET and bipolar selection transistors. In fact, this embodiment allows the trench 16 in the bipolar selection transistor to be formed using steps present in conventional processes for manufacturing FinFET transistors.

[0173] Many applications can benefit from the advantages of electronic device 11, so electronic device 11 can be integrated into various types of devices.

[0174] For example, electronic device 11 can be integrated into devices used in the automotive industry. The electrification of motor vehicles has led to a significant increase in the number of electronic components in vehicles. These devices include, for example, thyristors, rectifiers, voltage transient protection diodes, modules, etc., designed for integration into the aforementioned vehicles. Furthermore, driver automation or assistance systems have led to an increase in the number of electronic components in vehicles. These devices include, for example, voltage transient protection diodes, electromagnetic discharge protection, and common-mode filters to protect the devices from electrical hazards.

[0175] For example, electronic device 11 can be used in industrial applications. Specifically, it can be used to develop green energy or infrastructure electrification, such as charging stations or integrated solar power. It can also be used in the Internet of Things (IoT) or smart home applications. For example, it is designed to be implemented in circuits that power devices, including components such as 800V or 1200V thyristors, 1200V ultrafast silicon carbide diodes, transient voltage suppression diodes, and electromagnetic discharge protection. It can also be used to implement computing systems in the cloud, 5G RF communication networks, data centers, and servers. For example, it may incorporate wide-bandgap materials.

[0176] For example, electronic device 11 can be integrated into a device for personal electronic products, for example, to increase the amount of information exchanged via RF communication, in a 5G communication system, or more generally in any connected device. This device is, for example, a mobile phone or smartphone, or part of an Internet of Things (IoT) network. The device connects via, for example, 5G, WiFi, or broadband communication. For example, the device includes a high-speed interface, such as one with advanced filtering and electromagnetic discharge protection features.

[0177] For example, electronic device 11 can be integrated into a device used for communication devices or computers and peripherals. For example, the device is used in 5G infrastructure and dedicated data centers. For example, the device includes silicon carbide diodes, Schottky power transistors, electromagnetic discharge protection diodes, and transient voltage suppression diodes. The device can also be used in satellites, including integrated passive devices, for example, for RF applications.

[0178] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily conceive of them. In particular, Figure 17A and Figure 17B as well as Figure 18A and Figure 18B The second and third embodiments shown are compatible.

[0179] Furthermore, although an embodiment in which the memory element M is formed above the interconnect stack 35 has been described, the embodiments are not limited to this particular case. Alternatively, the memory element M may be formed between the interconnect stack 35 and the substrate 13.

[0180] Furthermore, although an embodiment in which regions 70 and 29 are formed in substrate 13 prior to regions 72 and 27 has been described, the formation of these regions can also be reversed. Similarly, although an embodiment in which trench 14b is formed in substrate 13 prior to trench 14a has been described, the formation of these trenches can also be reversed.

[0181] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

[0182] In one embodiment, an electronic device (11; 211; 311) includes a semiconductor substrate (13); an insulating layer (18) covering the semiconductor substrate, on and in contact with the semiconductor substrate; and a memory circuit including a plurality of memory cells, each memory cell including a bipolar selection transistor (12) disposed in and on the semiconductor substrate, each bipolar selection transistor including a base region (29, 15), an emitter region (27) and a collector region (17), wherein each bipolar selection transistor includes an insulating structure (16) made of a first dielectric material, the insulating structure including an upper portion (16s) extending vertically through the insulating layer (18) between the base region (29) and the emitter region (27) and a lower portion (16i) extending vertically through the semiconductor substrate (13), the side of the upper portion (16s) of the insulating structure (16) being covered by a first spacer (21) of a second dielectric material.

[0183] In one embodiment, the device further includes a logic circuit comprising a plurality of fin field-effect transistors disposed in and on a semiconductor substrate, each fin field-effect transistor comprising a source region (70, 72) and a drain region (70, 72), wherein two adjacent fin field-effect transistors are separated by an additional insulating structure (78) of a first dielectric material, the additional insulating structure comprising an upper portion (78s) extending vertically through an insulating layer between the drain and source regions of the two adjacent transistors and a lower portion (78i) extending vertically through the semiconductor substrate, the sides of the upper portion (78s) of the insulating structure being covered by spacers (68) of a second dielectric material.

[0184] In one embodiment, the insulating structure (16) of the memory circuit and the insulating structure (78) of the logic circuit have the same depth.

[0185] In one embodiment, the insulating structure (16) of the memory circuit and the insulating structure (78) of the logic circuit have different depths.

[0186] In one embodiment, each memory cell includes a memory element (M) comprising a layer (47) made of a phase change material.

[0187] In one embodiment, the memory circuitry includes an interconnect stack (35) disposed on a semiconductor substrate (13), the interconnect stack including a series of levels (36) in which interconnect elements (63, 69, 71) are defined.

[0188] In one embodiment, the memory element (M) is arranged above the interconnect stack (35).

[0189] In one embodiment, a process for manufacturing an electronic device in and on a semiconductor substrate (13), the electronic device including a memory circuit comprising a plurality of memory cells, each memory cell including a selectable bipolar transistor (12) formed in and on the semiconductor substrate, each selectable bipolar transistor including a base region (29, 15), an emitter region (27), and a collector region (17), the process comprising the steps of: forming a sacrificial gate (67) made of a sacrificial material on the semiconductor substrate (13); forming spacers (21) made of a dielectric material on the sidewalls of the sacrificial gate; and removing the spacers from the sacrificial gate. The sacrificial material is etched, and the substrate opposite the sacrificial gate is etched to form an opening surrounded by spacers at the top and extending through the substrate at the bottom, and the opening is filled with another dielectric material to form an insulating structure (16) made of another dielectric material; and an insulating layer (18) is formed on and in contact with the semiconductor substrate (13), the insulating structure thus including an upper portion (16s) extending vertically through the insulating layer (18) between the base region (29) and the emitter region (27) of the bipolar transistor and a lower portion (16i) extending vertically through the semiconductor substrate (13), the sides of the upper portion (16s) of each insulating structure (16) being covered by spacers (21).

[0190] In one embodiment, the device further includes logic circuitry comprising a plurality of fin field-effect transistors, each fin field-effect transistor including a source region (70, 72) and a drain region (70, 72), the process comprising the steps of: forming a sacrificial gate (67) made of sacrificial material on a semiconductor substrate (13); forming spacers (68) made of dielectric material on the sidewalls of the sacrificial gate; removing the sacrificial material from the sacrificial gate; and etching the substrate opposite the sacrificial gate to form an opening surrounded by spacers at the top and extending through the substrate at the bottom. The opening is filled with another dielectric material to form an additional insulating structure (78) made of another dielectric material; and an insulating layer (18) is formed on and in contact with the semiconductor substrate (13). The additional insulating structure thus includes an upper portion (78s) extending vertically through the insulating layer (18) between the source region (70, 72) and the drain region of each fin field-effect transistor and a lower portion (78i) extending vertically through the semiconductor substrate (13). The sides of the upper portion (78s) of the additional insulating structure (78) are covered by spacers (68).

[0191] In one embodiment, the steps of forming the insulating structure (16) of the memory circuit and the additional insulating structure (78) of the logic circuit are common.

[0192] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An electronic device comprising: Semiconductor substrate; An insulating layer covers the semiconductor substrate, is on the semiconductor substrate, and is in contact with the semiconductor substrate; as well as A memory circuit includes multiple memory cells, each memory cell including a bipolar selection transistor disposed in and on the semiconductor substrate, each bipolar selection transistor including a base region, an emitter region, and a collector region. Each bipolar selection transistor includes an insulating structure made of a first dielectric material, the insulating structure including an upper portion extending vertically through the insulating layer between the base region and the emitter region and a lower portion extending vertically through the semiconductor substrate, the side of the upper portion of the insulating structure being covered by a first spacer of a second dielectric material.

2. The apparatus of claim 1 further comprises a logic circuit, the logic circuit including a plurality of fin field-effect transistors disposed in and on the semiconductor substrate, each fin field-effect transistor including a source region and a drain region. Two adjacent fin field-effect transistors are separated by a second insulating structure of the first dielectric material. The second insulating structure includes an upper portion extending vertically through the insulating layer between the drain region and the source region of the two adjacent fin field-effect transistors and a lower portion extending vertically through the semiconductor substrate. The side of the upper portion of the insulating structure is covered by a second spacer of the second dielectric material.

3. The apparatus of claim 2, wherein the first insulating structure of the memory circuit and the second insulating structure of the logic circuit have the same depth.

4. The apparatus of claim 2, wherein the first insulating structure of the memory circuit and the second insulating structure of the logic circuit have different depths.

5. The apparatus of claim 1, wherein each memory cell includes a memory element comprising a layer made of a phase change material.

6. The apparatus of claim 1, wherein the memory circuitry includes an interconnect stack disposed on the semiconductor substrate, the interconnect stack including a series of levels in which interconnect elements are defined.

7. The apparatus of claim 6, wherein each memory includes a memory element comprising a layer made of a phase change material, the memory element being disposed above the interconnect stack.

8. A method comprising: A first sacrificial gate made of a first sacrificial material is formed on a semiconductor substrate; A first spacer of a first dielectric material is formed on the side surface of the first sacrificial gate; A plurality of bipolar transistors are formed in and on the semiconductor substrate, each bipolar transistor including a base region, an emitter region and a collector region; A first opening is formed by removing the first sacrificial gate and etching the substrate, which is surrounded by the first spacer at the top and extends through the substrate at the bottom. The first insulating structure is formed by filling the opening with a second dielectric material; as well as An insulating layer is formed on and in contact with the semiconductor substrate. The first insulating structure includes an upper portion extending vertically through the insulating layer between the base region and the emitter region of the bipolar transistor and a lower portion extending vertically through the semiconductor substrate. The side surface of the upper portion of each first insulating structure is covered by the first spacer.

9. The method of claim 8, wherein each bipolar transistor is part of a corresponding memory cell of a memory circuit.

10. The method of claim 9, further comprising: A second sacrificial gate is formed on the semiconductor substrate; A second spacer of the first dielectric material is formed on the side of the second sacrificial gate; Multiple fin field-effect transistors are formed, each of which includes a source region and a drain region; A second opening is formed by removing the second sacrificial gate from between the second spacers and etching the substrate, which is surrounded by the spacers at the top and extends through the substrate at the bottom. A second insulating structure is formed by filling the second opening with the second dielectric material. The second insulating structure includes an upper portion extending vertically through the insulating layer between the source region and the drain region of each fin field-effect transistor and a lower portion extending vertically through the semiconductor substrate. The side of the upper portion of the second insulating structure is covered by the second spacer.

11. The method of claim 10, wherein the fin field-effect transistor is part of a logic circuit.

12. The method of claim 11, further comprising simultaneously forming the first insulating structure and the second insulating structure.

13. A method comprising: A first sacrificial gate structure is formed on a semiconductor substrate; A first spacer of a first dielectric material is formed on the sidewall of the first sacrificial gate structure; A base region and an emitter region of a bipolar transistor are formed in the semiconductor substrate, and the base region and the emitter region are each in contact with a corresponding first spacer in the first spacer. as well as The first sacrificial gate structure is replaced with a first insulating structure of a second dielectric material extending into the semiconductor substrate.

14. The method of claim 13, further comprising forming an insulating layer in contact with the semiconductor substrate, wherein the first insulating structure extends vertically through the insulating layer.

15. The method of claim 13, further comprising forming the base region and the emitter region in an epitaxial growth process separate from the semiconductor substrate.

16. The method of claim 12, further comprising: A second sacrificial gate structure is formed on the semiconductor substrate; A second spacer of the first dielectric material is formed on the sidewall of the second sacrificial gate structure; A first source region / first drain region is formed in the first fin field-effect transistor and a second source region / second drain region in the second fin field-effect transistor, and each source region / drain region is in contact with a corresponding second spacer in the second spacer; as well as The second sacrificial gate structure is replaced with a second insulating structure that extends into the semiconductor substrate using the second dielectric material.

17. The method of claim 16, further comprising forming the first source region / first drain region, the second source region / second drain region, and the base region in the same first epitaxial growth process.

18. The method of claim 17, further comprising forming the emitter region in a second epitaxial growth process.

19. The method of claim 16, wherein the first fin field-effect transistor and the second fin field-effect transistor are part of a logic circuit.

20. The method of claim 13, wherein the bipolar transistor is part of a memory cell of a memory circuit.

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