Ultra-low forward high-reliability trench Schottky diode structure and manufacturing method thereof

Abstract

The invention discloses an ultra-low forward high-reliability trench Schottky diode structure and a manufacturing method thereof. The device comprises a first conductive type heavily doped substrate serving as a substrate; a lightly doped epitaxial layer of a first conductive type is arranged on the heavily doped substrate; an outer voltage dividing ring and an inner equilateral equiangular hexagonal groove are formed in the epitaxial layer; gate oxide is formed in the groove, and polycrystalline silicon is filled; filling LPTEOS as a terminal dielectric layer after polycrystalline back etching; the contact hole is formed in a masking mode through photoresist, the contact hole is covered with a barrier metal layer and an anode double-layer metal layer, and the anode metal layer is covered with a PI passivation layer. According to the invention, a larger barrier area can be achieved, and lower forward and reverse electric leakage can be obtained and kept unchanged; secondly, lower forward voltage drop can be obtained more flexibly at lower cost under the condition of ensuring that reverse electric leakage meets the requirement; and finally, the surge resistance, the ESD resistance and the reliability are higher.

Description

Technical Field

[0001] This invention relates to the field of semiconductor discrete devices, and more particularly to an ultra-low forward bias, high reliability trench Schottky diode structure and its manufacturing method. Background Technology

[0002] With the rise of solar photovoltaic in recent years, the demand for trench Schottky diodes used to protect bypass junction box circuits in photovoltaic solar cell modules has been increasing. Simultaneously, to further reduce energy consumption, trench Schottky diodes require low forward voltage drop. In existing technologies, most trench Schottky diodes typically use metals with low work function as the potential barrier. The lower the work function, the lower the barrier height, and the smaller the forward voltage drop, but inevitably, the reverse leakage current also increases. Single-metal barriers (such as titanium, nickel, and platinum with work functions ranging from low to high) or combined barriers with different metal ratios have relatively fixed barrier heights, and adjusting the latter ratio is costly. Therefore, the key to further reducing the forward voltage drop is to more flexibly obtain lower barrier metals while ensuring that the reverse leakage current meets requirements. Secondly, in chip structure design, increasing the proportion of the barrier region to the total chip area without changing the reverse leakage current can also reduce the forward voltage drop.

[0003] Therefore, how to obtain a barrier metal with a lower work function while ensuring reverse leakage current, and how to increase the barrier area without changing the reverse leakage current to obtain lower energy consumption, while ensuring its high performance and reliability, have become the technical problems that need to be solved. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides an ultra-low forward bias, high reliability trench Schottky diode structure and its manufacturing method, thereby solving at least one of the above-mentioned technical problems.

[0005] To achieve the above objectives, the present invention provides an ultra-low forward voltage and high reliability trench Schottky diode structure, characterized in that it includes a first conductivity type heavily doped substrate as a substrate, and a lightly doped epitaxial layer of the first conductivity type is disposed on the heavily doped substrate.

[0006] A trench structure is formed on the epitaxial layer, the trench structure including a pressure dividing ring and an inner equilateral hexagonal trench arranged sequentially from the outside to the inside;

[0007] A gate oxide layer is formed within the trench structure, and then filled with polysilicon.

[0008] The epitaxial layer is covered with LPTEOS as a terminal medium layer;

[0009] The terminal dielectric layer has a contact hole, and a barrier metal layer and an anode metal layer are covered above the contact hole. A PI passivation layer is covered on the anode metal layer. The barrier metal layer is located in the gap between adjacent inner equilateral hexagonal trenches. A barrier silicide is formed between the barrier metal layer and the epitaxial layer.

[0010] The bottom of the first type of conductive, heavily doped substrate is covered with a cathode metal layer.

[0011] More preferably, the thickness of the first conductive type heavily doped substrate is 220-260 μm, and the resistivity is 0.001-0.00185 ohm·cm.

[0012] More preferably, the thickness of the epitaxial layer is 5-7.5 μm and the resistivity is 0.25-0.45 ohm·cm.

[0013] More preferably, the thickness of the gate oxide layer is 1100-1400 Å.

[0014] More preferably, the thickness of the terminal dielectric layer is 4000-6000 Å.

[0015] More preferably, the thickness of the barrier silicide is 2000-4000 Å.

[0016] More preferably, the total thickness of the anode metal layer is 6-8 μm.

[0017] More preferably, the cathode metal thickness is 1-2 μm.

[0018] Another aspect of the present invention provides a method for fabricating an ultra-low forward bias, high reliability trench Schottky diode, the method comprising the following steps:

[0019] Step S1: Take a silicon substrate containing a heavily doped substrate of the first conductivity type and a lightly doped epitaxial layer of the first conductivity type. Grow a SiO2 layer of a certain thickness on the epitaxial layer using a hydrogen-oxygen synthesis oxidation method to form a masking layer. Then, use photolithography to etch the oxide layer to form a window for the trench structure. Use the retained oxide layer as a masking layer to perform trench etching to form a trench structure. The trench structure includes a voltage dividing ring and an inner equilateral hexagonal trench structure arranged sequentially from the outside to the inside.

[0020] Step S2: The retained Hardmask layer is removed using a sacrificial hydrogen-oxygen synthesis oxidation process, and a gate oxide layer is formed using a hydrogen-oxygen synthesis oxidation process. The trench is then filled using a polycrystalline deposition method.

[0021] Step S3: Use dry etching to remove the polycrystalline material on the gate oxide layer, leaving only the polycrystalline material within the trench structure.

[0022] Step S4: The terminal dielectric layer is formed by LPTEOS deposition, and the contact hole area is opened by photolithography. The oxide layer on the epitaxial layer of the hole area is completely etched away by dry etching process.

[0023] Step S5: A combination of low-barrier metal and high-barrier metal is sputtered onto the exposed epitaxial layer using a metal sputtering process, and a barrier silicide is formed by a rapid annealing process. The barrier metal on the gate oxide layer is then removed by a wet process.

[0024] Step S6: Two layers of anode metal are formed and covered with an imine layer as a PI passivation layer;

[0025] Step S7: Thin the back side of the substrate, and form a cathode metal layer on the thinned, heavily doped back side substrate using a metal evaporation process.

[0026] More preferably, the low barrier metal is titanium, chromium, or tungsten;

[0027] High barrier metals are nickel, nickel-platinum metal, or pure platinum.

[0028] Furthermore, in step S6, the two anode metal layers are an upper metal layer and a lower metal layer, which are set one above the other.

[0029] The material of the upper metal layer is AlNiAg;

[0030] The material of the lower metal layer is TiAl.

[0031] Compared with the prior art, the beneficial effects of the present invention are:

[0032] 1. Employing a hexagonal unit cell design, which has a larger barrier area, it achieves lower forward and reverse leakage current while maintaining the same level. Taking a 150mil size as an example, the performance improvement is shown in the table below:

[0033]

[0034] 2. By employing a combination of high and low barrier metal sputtering and rapid annealing processes, a lower forward voltage drop can be obtained more flexibly and at a lower cost while ensuring that the reverse leakage current meets the requirements.

[0035] 3. This double-layer anode metal and PI passivation structure provides stronger resistance to surges, ESD, and reliability. Attached Figure Description

[0036] Figure 1 This is a cross-sectional view after step S1 of the present invention;

[0037] Figure 2 This is a cross-sectional view after step S2 of the present invention;

[0038] Figure 3 This is a cross-sectional view after step S3 of the present invention;

[0039] Figure 4 This is a cross-sectional view after step S4 of the present invention;

[0040] Figure 5 This is a cross-sectional view after step S5 of the present invention;

[0041] Figure 6 This is a cross-sectional view after step S6 of the present invention;

[0042] Figure 7 This is a cross-sectional view after step S7 of the present invention;

[0043] Figure 8 This is a top view of the front of the chip of the present invention. Detailed Implementation

[0044] The present invention will now be further described with reference to the accompanying drawings.

[0045] See Figure 7 as well as Figure 8 Specific embodiment 1: An ultra-low forward, high-reliability trench Schottky diode structure includes a heavily doped substrate 1 of the first conductivity type as a substrate, a lightly doped epitaxial layer 2 of the first conductivity type disposed on the heavily doped substrate 1; a trench structure is formed on the epitaxial layer 2, the trench structure including a voltage dividing ring 5 and an inner equilateral hexagonal trench 6 arranged sequentially from the outside to the inside; a gate oxide layer 7 is formed in the trench structure and filled with polysilicon; an LPTEOS layer is covered above the epitaxial layer 2 as a terminal dielectric layer 9; a contact hole is formed on the terminal dielectric layer 9, a barrier metal layer and an anode metal layer are covered above the contact hole, a PI passivation layer is covered on the anode metal layer, the barrier metal layer is located in the gap between adjacent inner equilateral hexagonal trenches 6, and a barrier silicide 10 is formed between the barrier metal layer and the epitaxial layer 2; a cathode metal layer is covered at the bottom of the heavily doped substrate 1 of the first conductivity type.

[0046] The groove width of the outer pressure dividing ring 3 is 0.3-0.6μm, the spacing between adjacent pressure dividing rings is 0.8-1.5μm, and the depth is 2.3-2.8μm.

[0047] In all the external pressure dividing rings 5, the width of the annular groove adjacent to the inner equilateral hexagonal groove 6 is greater than the width of the other annular grooves. The terminal dielectric layer covers the outer side of the annular groove adjacent to the inner equilateral hexagonal groove 6. The barrier metal layer covers the inner side of the annular groove adjacent to the inner equilateral hexagonal groove 6.

[0048] The junction between the terminal dielectric layer and the barrier metal layer is located above the annular trench of the adjacent inner equilateral hexagonal trench 6.

[0049] The cross-section of the inner equilateral hexagonal groove is an equilateral hexagon with a side length of 0.5-0.8μm. The spacing between adjacent inner equilateral hexagonal grooves is 1.5-2.5μm, and the depth is 1.9-2.3μm.

[0050] The thickness of the first conductivity type of heavily doped substrate 1 is 220-260 μm, and the resistivity is 0.001-0.00185 ohm·cm.

[0051] The thickness of epitaxial layer 2 is 5-7.5 μm, and the resistivity is 0.25-0.45 ohm·cm.

[0052] The thickness of the gate oxide layer 7 is 1100-1400 Å.

[0053] The thickness of the terminal dielectric layer 9 is 4000-6000 Å.

[0054] The thickness of barrier silicide 10 is 2000-4000 Å.

[0055] The total thickness of the anode metal layer is 6-8 μm.

[0056] The cathode metal thickness is 1-2 μm.

[0057] See Figures 1 to 7 A method for fabricating an ultra-low forward bias, high reliability trench Schottky diode includes the following steps:

[0058] Step S1: Take a silicon substrate containing a heavily doped substrate 1 of the first conductivity type and a lightly doped epitaxial layer 2 of the first conductivity type. On the epitaxial layer 2, grow a SiO2 layer of a certain thickness using thermal oxidation to form a hardmask layer 3. Then, etch the oxide layer using photolithography to form a window 4 for the trench structure. Use the retained oxide layer as a mask layer to perform trench etching to form a trench structure. The trench structure includes voltage dividing rings 5 ​​arranged sequentially from the outside to the inside, and inner equilateral hexagonal trenches 6. See [link to previous step] Figure 1 .

[0059] A masking layer is grown on the epitaxial layer using a hydrogen-oxygen synthesis oxidation method at 950℃. The etching power for window 4 is 700-1000W, the pressure is 160-260mTorr, and the magnetic field is 40-50gauss.

[0060] The etching power for forming the trench structure is 300-600W, the pressure is 40-60mTorr, and the trench depth is generally 1.6-2.4μm.

[0061] Step S2: The retained hardmask layer is removed using a sacrificial hydrogen-oxygen synthesis oxidation process, and a gate oxide layer 7 is formed using the same process. This layer is then filled into the trenches using polycrystalline deposition. (See also...) Figure 2 Polycrystalline deposition was performed using low-pressure chemical vapor deposition at a temperature of 560°C. The sacrificial oxidation process was carried out at a temperature of 950°C. The hydrogen-oxygen synthesis oxidation process was carried out at a temperature of 1050°C.

[0062] Step S3: The polycrystalline material on the surface gate oxide layer 7 is removed using a dry etching method, leaving only the polycrystalline material 8 within the trench structure; see [link to previous step]. Figure 3 Dry etching has an etching power of 300-600W, a pressure of 100-200mTorr, and a magnetic field of 20-50gauss.

[0063] Step S4: The terminal dielectric layer 9 is formed using LPTEOS deposition, and the contact hole area is created using photolithography. A dry etching process is then used to completely etch away the oxide layer on the epitaxial layer 2 in the hole area. (See also...) Figure 4 .

[0064] The deposition temperature using LPTEOS is 650-750℃, and the pressure is 400-500 mTorr.

[0065] The etching power of the dry etching process is 900-1000W, the pressure is 100-200mTorr, and the magnetic field is 20-50gauss.

[0066] Step S5: A combination of low-barrier and high-barrier metals is sputtered onto the exposed epitaxial layer 2 using a metal sputtering process. A barrier silicide 10 is then formed using a rapid annealing process, and the barrier metal on the gate oxide layer 7 is removed using a wet process. (See also...) Figure 5 .

[0067] The temperature for metal sputtering is 130-160℃ and the power is 2-3kW.

[0068] The rapid annealing process involves a temperature of 600-750℃ and a time of 20-50 seconds.

[0069] Step S6: Two layers of anode metal are formed, and an imine layer is coated on top as a PI passivation layer 13; see also Figure 6 .

[0070] A layer of anode metal is formed by sputtering, and then another layer of anode metal is formed by evaporation.

[0071] The sputtering temperature is 250-400℃, and the power is 10-16kW. Sputtering forms a titanium-aluminum layer.

[0072] The evaporation temperature is 100-200℃. An aluminum-nickel-silver layer is formed through evaporation.

[0073] Step S7: The back side of substrate 1 is thinned, and a cathode metal layer is formed on the heavily doped back side of the thinned substrate 1 using a metal evaporation process. See [link to relevant documentation]. Figure 7 The evaporation process is carried out at a temperature of 100-200℃.

[0074] Low barrier metals are titanium, chromium, or tungsten; high barrier metals are nickel, nickel-platinum metal, or pure platinum.

[0075] In step S6, the two anode metal layers are an upper metal layer 12 and a lower metal layer 11, which are disposed one above the other; the upper metal layer 12 is made of AlNiAg; and the lower metal layer is made of TiAl. The size of the upper metal layer is 100-150 μm smaller than that of the lower metal layer. That is, the distance between the outer edge of the upper metal layer and the outer edge of the lower metal layer is 100-150 μm.

[0076] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A trench Schottky diode structure with ultra-low forward bias and high reliability, characterized in that, It includes a heavily doped substrate of the first conductivity type as a substrate, and a lightly doped epitaxial layer of the first conductivity type is disposed on the heavily doped substrate; A trench structure is formed on the epitaxial layer, the trench structure including a pressure dividing ring and an inner equilateral hexagonal trench arranged sequentially from the outside to the inside; A gate oxide layer is formed within the trench structure, and then filled with polysilicon. The epitaxial layer is covered with LPTEOS as a terminal medium layer; The terminal dielectric layer has a contact hole, and a barrier metal layer and an anode metal layer are covered above the contact hole. A PI passivation layer is covered on the anode metal layer. The barrier metal layer is located in the gap between adjacent inner equilateral hexagonal trenches. A barrier silicide is formed between the barrier metal layer and the epitaxial layer. The bottom of the first type of conductive, heavily doped substrate is covered with a cathode metal layer.

2. The ultra-low forward bias, high reliability trench Schottky diode structure according to claim 1, characterized in that: The thickness of the first conductivity type of heavily doped substrate is 220-260 μm, and the resistivity is 0.001-0.00185 ohm·cm.

3. The ultra-low forward bias, high reliability trench Schottky diode structure according to claim 1, characterized in that: The epitaxial layer has a thickness of 5-7.5 μm and a resistivity of 0.25-0.45 ohm·cm.

4. The ultra-low forward bias, high reliability trench Schottky diode structure according to claim 1, characterized in that: The thickness of the gate oxide layer is 1100-1400 Å; The thickness of the terminal dielectric layer is 4000-6000 Å; The thickness of the barrier silicide is 2000-4000 Å.

5. The ultra-low forward bias, high reliability trench Schottky diode structure according to claim 1, characterized in that: The total thickness of the anode metal layer is 6-8 μm.

6. The ultra-low forward bias, high reliability trench Schottky diode structure according to claim 1, characterized in that: The cathode metal thickness is 1-2 μm.

7. A method for fabricating an ultra-low forward bias, high reliability trench Schottky diode, characterized in that, Includes the following steps: Step S1: Take a silicon substrate containing a heavily doped substrate of the first conductivity type and a lightly doped epitaxial layer of the first conductivity type. Grow a SiO2 layer of a certain thickness on the epitaxial layer using a hydrogen-oxygen synthesis oxidation method to form a masking layer. Then, use photolithography to etch the oxide layer to form a window for the trench structure. Use the retained oxide layer as a masking layer to perform trench etching to form a trench structure. The trench structure includes a voltage dividing ring and an inner equilateral hexagonal trench structure arranged sequentially from the outside to the inside. Step S2: The retained Hardmask layer is removed using a sacrificial hydrogen-oxygen synthesis oxidation process, and a gate oxide layer is formed using a hydrogen-oxygen synthesis oxidation process. The trench is then filled using a polycrystalline deposition method. Step S3: Use dry etching to remove the polycrystalline material on the gate oxide layer, leaving only the polycrystalline material within the trench structure. Step S4: The terminal dielectric layer is formed by LPTEOS deposition, and the contact hole area is opened by photolithography. The oxide layer on the epitaxial layer of the hole area is completely etched away by dry etching process. Step S5: A combination of low-barrier metal and high-barrier metal is sputtered onto the exposed epitaxial layer using a metal sputtering process, and a barrier silicide is formed by a rapid annealing process. The barrier metal on the gate oxide layer is then removed by a wet process. Step S6: Two layers of anode metal are formed and covered with an imine layer as a PI passivation layer; Step S7: Thin the back side of the substrate, and form a cathode metal layer on the thinned, heavily doped back side substrate using a metal evaporation process.

8. The method for fabricating an ultra-low forward bias, high reliability trench Schottky diode structure according to claim 7, characterized in that: The low barrier metal is titanium, chromium, or tungsten; High barrier metals are nickel, nickel-platinum metal, or pure platinum.

9. The method for fabricating an ultra-low forward bias, high reliability trench Schottky diode structure according to claim 7, characterized in that: In step S6, the two anode metal layers are an upper metal layer and a lower metal layer, which are set one above the other. The material of the upper metal layer is AlNiAg; The material of the lower metal layer is TiAl.

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