A trench gate silicon carbide VDMOS for 2kV or above and a manufacturing method thereof

Abstract

The application provides a method for manufacturing a 2kV or above trench gate silicon carbide VDMOS, which comprises the following steps: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, ion implantation to form a current uniform layer; ion implantation to form a first well region, a shielding layer, a second well region and an N-type source region; etching and then depositing to form an isolation dielectric layer; etching the drift layer to form a second groove and then depositing metal to form a Schottky metal layer; etching and then oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a trench; depositing metal to form a gate metal layer; etching and then depositing metal to form a source metal layer, so that the device can realize small cell, high current density and low on-resistance under the condition of 2kV or above voltage resistance.

Description

Technical Field

[0001] This invention relates to a trench-gate silicon carbide VDMOS for voltages above 2kV and its fabrication method. Background Technology

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally have high withstand voltage compared to Si VDMOS devices. However, in fields such as high-voltage power transmission, the structure of traditional silicon carbide VDMOS devices cannot meet the withstand voltage requirements of devices above 2kV. This leads to increasing the withstand voltage by sacrificing device size and on-resistance, which affects device characteristics. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a trench gate silicon carbide VDMOS for voltages above 2kV and a method for its fabrication, so as to achieve small cell size, high current density and low on-resistance of the device under voltage conditions above 2kV.

[0004] In a first aspect, the present invention provides a method for fabricating trench-gate silicon carbide VDMOS with voltages above 2kV, comprising the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; grow an epitaxial layer on the upper side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form vias, and implant ions to form a uniform flow layer;

[0007] Step 3: Ion implantation to form the first well region;

[0008] Step 4: Ion implantation to form a shielding layer;

[0009] Step 5: Ion implantation to form a second well region. The P-type well region includes the first well region and the second well region.

[0010] Step 6: Ion implantation to form an N-type source region;

[0011] Step 7: Etch the drift layer to form the first trench, and then deposit it to form the isolation dielectric layer;

[0012] Step 8: Etch the drift layer to form the second trench, then deposit metal to form a Schottky metal layer;

[0013] Step 9: Etch the drift layer and shielding layer to form a third groove, and oxidize to form an insulating dielectric layer, wherein the insulating dielectric layer has grooves;

[0014] Step 10: Deposit metal to form a gate metal layer;

[0015] Step 11: Etch the drift layer to form the third trench, deposit metal, and form the source metal layer;

[0016] Before steps 3 to 11, the barrier layer from the previous step needs to be removed, and the barrier layer is etched to form a through hole.

[0017] Secondly, the present invention provides a trench gate silicon carbide VDMOS for voltages above 2kV, wherein the silicon carbide VDMOS is prepared by the preparation method of the trench gate silicon carbide VDMOS for voltages above 2kV described in the first aspect.

[0018] The advantages of this invention are:

[0019] I. This invention constructs a symmetrical structure consisting of an isolation dielectric, Schottky metal, a P-type well region, and a gate structure. The newly added isolation dielectric can achieve direct isolation between device cells, suppressing the diffusion of the electric field to the cell edge under high drain voltage conditions above 2kV, thereby increasing the cell density of silicon carbide VDMOS in trenches above 2kV.

[0020] Second, an N-type current-equalizing layer wrapped with a P-type shielding layer is constructed at the bottom of the device trench gate. While ensuring gate reliability under a withstand voltage of over 2kV, a low-resistance path from the N-type source to the JFET region is provided, thereby reducing the on-resistance of the device.

[0021] Third, to meet the withstand voltage requirements of 2kV and above, a thick P-type well region and a narrow conductive channel (the width of the N-type current sharing region distributed on both sides of the insulating medium is only 100nm) structure is adopted, thereby reducing the on-resistance of the device while ensuring the withstand voltage capability of the device.

[0022] Fourth, a Schottky metal is constructed inside the isolation medium of the device, and the constructed Schottky body diode completes the low-resistance freewheeling in the non-conducting state of the device. Attached Figure Description

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This is a schematic diagram of a trench-gate silicon carbide VDMOS for voltages above 2kV according to the present invention.

[0025] Figure 2 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 1 .

[0026] Figure 3 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 2 .

[0027] Figure 4This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 3 .

[0028] Figure 5 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 4 .

[0029] Figure 6 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 5 .

[0030] Figure 7 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 6 .

[0031] Figure 8 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 7 .

[0032] Figure 9 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 8 .

[0033] Figure 10 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 9 .

[0034] Figure 11 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 10 .

[0035] Figure 12 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 10 one.

[0036] Figure 13 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 10 two.

[0037] Figure 14 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 10 three.

[0038] Figure 15 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 10 Four.

[0039] Figure 16This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to the present invention. Figure 10 five. Detailed Implementation

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0044] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0045] like Figures 1 to 16 As shown, this application embodiment provides a method for fabricating trench-gate silicon carbide VDMOS with voltages above 2kV, comprising the following steps:

[0046] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 111; epitaxially grow on the upper side of silicon carbide substrate 101 to form drift layer 102;

[0047] Step 2: Form a barrier layer 112 above the drift layer 102, etch the barrier layer 112 to form a via, and implant ions to form a flow equalization layer 103.

[0048] Step 3: Ion implantation to form the first well region 1061;

[0049] Step 4: Ion implantation to form shielding layer 1031;

[0050] Step 5: Ion implantation to form a second well region 1062. The P-type well region 106 includes a first well region 1061 and a second well region 1062.

[0051] Step 6: Ion implantation to form N-type source region 107;

[0052] Step 7: Etch the drift layer to form the first trench 113, and then deposit it to form the isolation dielectric layer 104;

[0053] Step 8: Etch the drift layer to form the second trench 114, and then deposit metal to form the Schottky metal layer 105;

[0054] Step 9: Etch the drift layer 102 and the shielding layer 1031 to form the third groove 115, and oxidize to form an insulating dielectric layer 108, wherein the insulating dielectric layer 108 is provided with grooves 1081;

[0055] Step 10: Deposit metal to form gate metal layer 109;

[0056] Step 11: Etch the drift layer to form the third trench 116, deposit metal to form the source metal layer 110;

[0057] Before steps 3 to 11, the barrier layer 112 from the previous step needs to be removed, and the barrier layer 112 is etched to form a through hole.

[0058] In this embodiment, preferably, the doping concentration of the current equalization layer 103 is greater than the doping concentration of the drift layer 102.

[0059] In this embodiment, preferably, the doping concentration of the current equalization layer 103 is less than or equal to the doping concentration of the shielding layer 1031.

[0060] In this embodiment, preferably, the width of the shielding layer 1031 is equal to the width of the insulating dielectric layer 108.

[0061] In this embodiment, preferably, the doping concentration of the current equalization layer 103 is less than the doping concentration of the P-type well region 106.

[0062] In this embodiment, preferably, the silicon carbide substrate 101, the drift layer 102, and the current equalization layer 103 are all N-type, and the shielding layer 1031 is P-type.

[0063] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0064] Silicon carbide substrate 101,

[0065] A drift layer 102, the lower side of which is connected to the upper side of the silicon carbide substrate 101, and a first groove (not shown in the figure) is provided on the drift layer 102.

[0066] A flow equalization layer 103 is provided in a first groove at its lower part. A shielding layer 1031 and a second groove (not shown in the figure) are provided in the flow equalization layer 103. The shielding layer 1031 is located at the bottom of the second groove.

[0067] An isolation medium layer 104, the lower side of which is connected to the upper side of the drift layer 102;

[0068] Schottky metal layer 105, the lower side of which is connected to the upper side of drift layer 102, and the outer side of which is connected to the inner side of isolation medium layer 104;

[0069] P-type well region 106, the lower side of the P-type well region 106 is connected to the upper side of the drift layer 102, the outer side of the P-type well region 106 is connected to the inner side of the Schottky metal layer 105, and the inner side of the P-type well region 106 is connected to the flow equalization layer 103.

[0070] N-type source region 107, the lower side of which is connected to the upper side of P-type well region 106, and the outer side of which is connected to the inner side of Schottky metal layer 105;

[0071] An insulating dielectric layer 108 is provided at its lower part in a second groove. The outer side of the insulating dielectric layer 108 is connected to a P-type well region 106 and an N-type source region 107, respectively. A groove 1081 is provided in the insulating dielectric layer 108.

[0072] A gate metal layer 109 is disposed within the trench 1081;

[0073] Source metal layer 110, which is connected to N-type source region 107 and Schottky metal layer 105 respectively;

[0074] And a drain metal layer 111, which is connected to the lower side of the silicon carbide substrate 101.

[0075] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 102 is 6-10e15cm. -3 The doping concentration of the N-type current-averaging layer 103 is 6-10e16cm. -3 The doping concentration of the P-type shielding layer 1031 is 1-5e17cm. -3 The doping concentration of the P-type well region 106 is 6-10e17cm. -3 The material of the isolation dielectric layer 104 can be silicon dioxide, the material of the insulating dielectric layer 108 can be silicon dioxide, and the doping concentration of the N-type source region 107 is 2-8e18cm. -3 ;

[0076] The doping concentration of the N-type silicon carbide substrate 101 is designed to ensure a low-resistance ohmic contact with the drain metal layer 111, reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 represents a trade-off between the device's reverse breakdown voltage and on-resistance. The doping concentration of the N-type current sharing layer 103 is designed to reduce the device's on-resistance. Its relationship with the doping concentration of the P-type shielding layer 1031 ensures the protective effect of the P-type shielding layer 1031 on the device's gate insulating dielectric layer 108. The doping concentration of the P-type shielding layer 1031 is designed to improve the reliability of the bottom of the device's gate insulating dielectric layer 108, ensuring that the leakage current is sufficiently small during reverse breakdown, shielding the capacitance from the device's gate to the drain, and reducing the device's Miller capacitance. The doping concentration of the P-type well region 106 is designed to protect the device's source metal layer 110, ensuring its breakdown voltage capability during reverse breakdown. The doping concentration of the N-type source region 107 is designed to reduce the device's contact resistance, thereby reducing the device's on-resistance.

[0077] Since trench-gate silicon carbide VDMOS devices above 2kV require thick epitaxy, the silicon carbide substrate thickness is designed to be 1.5μm to ensure support during device fabrication. The N-type drift layer 102 has a thickness of 150-300μm, and the device withstand voltage range is 2kV-4.5kV, adjusted within this range according to different requirements for device withstand voltage characteristics. The source metal layer 110 has a thickness of 300nm and a width of 800nm, the N-type source region 107 has a thickness of 200nm and a width of 800nm, the P-type well region 106 has a maximum thickness of 1.5μm and a width of 800nm, the Schottky metal layer 105 has a thickness of 2μm and a width of 300nm, the isolation dielectric layer 104 has a thickness of 2μm and a width of 300nm, and the thickness of the P-type well region 106 is designed for withstand voltage requirements above 2kV. The design is based on a high-density cell design of the device based on the shielding structure of the isolation dielectric layer 104 and the Schottky metal layer 105. The device insulating dielectric layer 108 has a width of 1μm and a thickness of 1μm. The gate metal layer 109 has a width of 900nm and a thickness of 900nm. The bottom thickness of the insulating dielectric layer 108 is 100nm, and the thickness on the left and right sides is 50nm. The P-type shielding layer 1031 has a width of 1μm and a thickness of 300nm. This is to ensure the protection of the insulating dielectric layer 108 at the bottom of the device gate. The N-type current sharing layer 103 has a width of 1.4μm and a thickness of 1μm. This is to ensure that there is a 200nm conductive channel width on the left and right sides of the device gate control region. A low-resistance region unaffected by the P-type well region 106 is constructed at the bottom of the device P-type well region 106, which effectively reduces the on-resistance of the device.

[0078] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a 2kV and above trench-gate silicon carbide VDMOS, characterized in that: The method comprises the following steps: Step 1, depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and ion implantation to form a current uniform layer; Step 3, ion implantation to form a first well region; Step 4, ion implantation to form a shielding layer, and the current uniform layer wraps the shielding layer; Step 5, ion implantation to form a second well region, and the P-type well region comprises the first well region and the second well region, and the second well region is located on the upper surface of the first well region; Step 6, ion implantation to form an N-type source region; Step 7, etching the drift layer to form a first groove, and then depositing to form an isolation medium layer; Step 8, etching the drift layer to form a second groove, and then depositing metal to form a Schottky metal layer; Step 9, etching the drift layer and the shielding layer to form a third groove, and oxidizing to form an insulating medium layer, and the insulating medium layer is provided with a groove; Step 10, depositing metal to form a gate metal layer; Step 11, etching the drift layer to form a third groove, and depositing metal to form a source metal layer; Before steps 3 to 11, the barrier layer of the previous step needs to be removed, and a through hole is formed by etching the barrier layer; The lower side of the isolation medium layer is connected to the upper side of the drift layer; The lower side of the Schottky metal layer is connected to the upper side of the drift layer, and the outer side of the Schottky metal layer is connected to the inner side of the isolation medium layer; The lower side of the P-type well region is connected to the upper side of the drift layer, the outer side of the P-type well region is connected to the inner side of the Schottky metal layer, and the inner side of the P-type well region is connected to the current uniform layer; The lower side of the N-type source region is connected to the upper side of the P-type well region, and the outer side of the N-type source region is connected to the inner side of the Schottky metal layer.

2. The fabrication method of claim 1 for 2kV and above trench-gated silicon carbide VDMOS, characterized in that: The doping concentration of the current uniform layer is greater than the doping concentration of the drift layer.

3. The method for fabricating a trench-gate silicon carbide VDMOS with voltages above 2kV as described in claim 1, characterized in that: The doping concentration of the current uniform layer is less than or equal to the doping concentration of the shielding layer.

4. The method for fabricating a trench-gate silicon carbide VDMOS with voltages above 2kV as described in claim 1, characterized in that: The width of the shielding layer is equal to the width of the insulating medium layer.

5. The method of claim 1, wherein the trench-gate silicon carbide VDMOS is for 2 kV or more. 5 The doping concentration of the current uniform layer is less than the doping concentration of the P-type well region.

6. The method of claim 1, wherein the trench-gate silicon carbide VDMOS is for 2 kV or more. The silicon carbide substrate, the drift layer and the current uniform layer are N-type, and the shielding layer is P-type.

7. A trench-gate silicon carbide VDMOS for 2 kV and above, characterized by, The silicon carbide VDMOS is prepared by the preparation method of any one of claims 1 to 6.

Images