Method for producing coreless interposer

Abstract

An interconnect structure and a system-in-package fabrication method for the interconnect structure are disclosed, the interconnect structure configured for electrically communicating / coupling one or more integrated circuit packages / semiconductor dies to a circuit board, the method includes forming one or more electrically conductive lines, filling one or more gaps between the one or more electrically conductive lines with an electrically insulating material, removing excess electrically insulating material, thereby obtaining a first layer of the interconnect structure, and repeating the above steps to produce additional one or more layers of the interconnect structure, wherein additional one or more layers are stacked over the first layer, thereby enabling immediate formation of vertical electrical connections between the conductive lines / patterns.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more particularly to methods for manufacturing interconnect structures and electrical interfaces. Background Technology

[0002] Reducing the size of semiconductor devices improves their performance because of the reduced interconnect length, which in turn leads to increased signal transmission speed and reduced power consumption. Existing semiconductor device manufacturing methods are typically based on packaging semiconductor dies / chips and mounting them on a PCB. To allow for electrical interconnections between them, an intermediary is installed between the PCB and the package. Therefore, the intermediary should coordinate the small pads and fine-pitch interconnects of the semiconductor die / chip with the relatively large pads and coarse-pitch interconnects of the PCB.

[0003] Currently, the intermediates are made of silicon, glass, or organic cores and are equipped with vertical and horizontal electrical connections. Vertical electrical connections (through holes) are typically formed by drilling holes through the substrate and coating those holes with a conductive material, which in turn limits the aspect ratio that can be obtained.

[0004] Recent solutions for achieving shorter interconnect lengths include 2.5D or 3D mediators. However, forming electrical connections in 2.5D or 3D mediators requires drilling, leading to manufacturing difficulties, poor reliability, and limitations on the design and complexity of via patterns. Another approach is to fabricate ultrathin coreless mediators made of organic materials. However, these suffer from high warpage, via cracking, and limited line / spatial resolution. Summary of the Invention

[0005] According to some embodiments of this disclosure, aspects of this disclosure relate to semiconductor devices. More specifically, but not limited to, according to some embodiments of this disclosure, aspects of this disclosure relate to a coreless intermediary and a method of manufacturing the same.

[0006] According to some embodiments, this document provides a coreless intermediate interconnect structure comprising one or more layers, each of the one or more layers comprising: one or more electrically conductive lines (e.g., areas, patterns, pads, etc.) configured to allow electrical signals to pass through, and an electrically insulating material configured to fill the gaps between each of the one or more conductive lines. According to some embodiments, the one or more conductive lines are arranged in a predefined pattern. In some embodiments, the predefined pattern of each of the one or more layers may be different. According to some embodiments, the one or more layers are substantially vertically stacked, thereby enabling on-the-fly vertical electrical connections to be formed between conductive areas.

[0007] Advantageously, in some embodiments, the vertical electrical connections (i.e., vias) of each of the one or more layers are formed substantially simultaneously.

[0008] Advantageously, in some embodiments, the vertical electrical connections are formed without drilling and are therefore not limited by the aspect ratio (i.e., the height-to-diameter ratio) of the vertical electrical connections. Thus, in some embodiments, this facilitates and enables the formation of through-holes with high density, complex patterns, and substantially unrestricted through-hole height.

[0009] According to some embodiments, the coreless intermediary can be flexible. According to some embodiments, the coreless intermediary can be semi-rigid. According to some embodiments, the coreless intermediary can be rigid. Each possibility is a separate embodiment.

[0010] According to some embodiments, the aspect ratio of the vertical electrical connection is essentially unlimited / unrestricted.

[0011] According to some embodiments, this document provides a method for manufacturing interconnect structures (e.g., coreless interposers) for system-in-package (SIPP) fabrication, the interconnect structures being configured to electrically connect / couple one or more integrated circuit packages / semiconductor dies to a circuit board. The method includes: forming one or more conductive lines (e.g., areas, pads, patterns, etc.); filling one or more gaps between the one or more conductive lines with an electrically insulating material; removing excess electrically insulating material to obtain a first layer of the interconnect structure; and repeating the above steps to produce one or more additional layers of the interconnect structure, wherein the additional one or more layers are stacked on top of the first layer, thereby enabling the on-the-fly formation of vertical electrical connections between the conductive lines.

[0012] According to some embodiments, one or more conductive lines can be formed by photolithography.

[0013] According to some embodiments, photolithography may include forming a seed layer, applying a resist to the seed layer, irradiating and developing the resist, filling one or more gaps between the developed resist with a conductive material, removing the developed resist, and removing any residue from the seed layer, thereby forming one or more conductive lines of conductive material.

[0014] According to some embodiments, one or more conductive lines can be formed by selective laser sintering.

[0015] According to some embodiments, removing excess electrical insulation material may include planarizing using a surface planer tool / machine to form a substantially flat surface for the first layer and / or one or more additional layers of the interconnect structure.

[0016] According to some embodiments, excess electrical insulation material may be removed until a portion of the first layer and / or one or more additional layers of the interconnect structure is exposed.

[0017] According to some embodiments, the method may eliminate the drilling step. According to some embodiments, the method may eliminate the etching step.

[0018] According to some embodiments, the aspect ratio of the vertical electrical connection formed according to the disclosed method can be substantially unrestricted.

[0019] According to some embodiments, the method may include curing and / or baking the electrical insulating material. According to some embodiments, the method may include heat treating the electrical insulating material.

[0020] According to some embodiments, filling one or more gaps may include casting / spreading an electrical insulating material over one or more conductive wires and the gaps between the one or more conductive wires.

[0021] According to some embodiments, the method may include at least a first layer forming an interconnect structure on a temporary carrier.

[0022] According to some embodiments, the electrical insulating material may be a dielectric.

[0023] According to some embodiments, the electrical insulating material may include one or more polymers.

[0024] According to some embodiments, the line / spatial resolution of the conductive line structure can be at least about 5 / 5 μm.

[0025] According to some embodiments, a vertical electrical connection may include a vertical electrical connection that extends through the chip.

[0026] According to some embodiments, the interconnect structure can be configured to allow electrical coupling between conductive pads with a size of about 100 x 100 μm and conductive pads with a size of about 5 x 5 μm or smaller.

[0027] Some embodiments of this disclosure may include some, all, or none of the advantages described above. One or more other technical advantages will be apparent to those skilled in the art from the figures, description, and claims contained herein. Furthermore, while specific advantages have been listed above, various embodiments may include all, some, or none of the listed advantages.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In case of conflict, the patent specification (including definitions) shall prevail. As used herein, the indefinite articles “a” and “an” mean “at least one” or “one or more” unless the context clearly specifies otherwise. Attached Figure Description

[0029] This document describes some embodiments of the present disclosure with reference to the accompanying drawings. The description and the drawings make it clear to those skilled in the art how to practice these embodiments. The drawings are for illustrative purposes and do not attempt to show the structural details of the embodiments in more detail than is necessary for a basic understanding of the present disclosure. For clarity, some objects shown in the drawings are not drawn to scale. Furthermore, two different objects in the same drawing may be drawn at different scales. In particular, the scale of some objects may be significantly exaggerated compared to other objects in the same drawing.

[0030] In the diagram:

[0031] Figure 1A A side view of an interconnect structure according to some embodiments is schematically shown;

[0032] Figure 1B Schematic illustration of some embodiments Figure 1A A top view of the interconnect structure;

[0033] Figure 1C Schematic illustration of some embodiments Figure 1A A top view of each of one or more layers in the interconnect structure;

[0034] Figure 2 A flowchart is shown illustrating a method for manufacturing interconnect structures, such as coreless intermediaries, according to some embodiments;

[0035] Figure 3 An example of an additive fabrication method for forming conductive regions of an interconnect structure, according to some embodiments, is schematically illustrated.

[0036] Figure 4 An example of a semi-additive fabrication method for forming conductive regions of an interconnect structure according to some embodiments is illustrated schematically;

[0037] Figure 5 An example of a semi-additive manufacturing method for forming conductive regions of an interconnect structure according to some embodiments is illustrated schematically;

[0038] Figure 6Examples of methods for generating interconnect structures such as coreless intermediaries, according to some embodiments, are schematically illustrated.

[0039] Figure 7 An example cross-sectional view of a coreless intermediary with four layers, produced according to experiments based on some embodiments, is illustrated. Detailed Implementation

[0040] The principles, uses, and implementation methods taught herein can be better understood by referring to the accompanying description and figures. After reading the description and figures presented herein, those skilled in the art will be able to implement the teachings herein without much effort or experimentation.

[0041] In the specification and claims of this application, the terms “comprising” and “having” and their forms are not limited to members of the list that the terms may be associated with.

[0042] As used herein, the term "about" can be used to specify the value of a quantity or parameter (e.g., the length of an element) as a range of values ​​near (and including) a given (declared) value. According to some embodiments, "about" can specify the value of a parameter as between 80% and 120% of a given value. For example, declaring "the length of the element is about 1 m" is equivalent to declaring "the length of the element is between 0.8 m and 1.2 m." According to some embodiments, "about" can specify the value of a parameter as between 90% and 110% of a given value. According to some embodiments, "about" can specify the value of a parameter as between 95% and 105% of a given value.

[0043] As used herein, the terms “substantially” and “about” may be used interchangeably according to some embodiments.

[0044] As used herein, according to some embodiments, the terms "interface," "intermediate," and "interconnection structure" are interchangeable and refer to an electrical interface configured to enable electrical interconnection between devices or components thereof. According to some embodiments, the electrical interface may be configured to route and / or reroute electrical interconnections, for example, extending electrical interconnections between large pads to small pads. According to some embodiments, the intermediate may be configured to allow electrical interconnection between large pads formed on a printed circuit board (PCB) and small pads (e.g., having small size / diameter and / or small pitch dimensions) formed on a package, die, or any other component of an integrated circuit.

[0045] According to some embodiments, a large pad can refer to a pad with a large size, such as, but not limited to, about 500 x 500 μm or larger, about 400 x 400 μm or larger, or about 300 x 300 μm or larger. Each possibility is a separate embodiment. According to some embodiments, a large pad can refer to a pad with a large pitch size, such as, but not limited to, about 4 mm or larger, about 3 mm or larger, about 2 mm or larger, or about 1.4 mm or larger. Each possibility is a separate embodiment. According to some embodiments, a small pad can refer to a pad with a small size, such as, but not limited to, about 4 x 4 μm or smaller, about 5 x 5 μm or smaller, about 7 x 7 μm or smaller, about 10 x 10 μm or smaller, about 12 x 12 μm or smaller, about 15 x 15 μm or smaller, about 20 x 20 μm or smaller, about 25 x 25 μm or smaller, about 30 x 30 μm or smaller, about 40 x 40 μm or smaller, or about 50 x 50 μm or smaller. Each possibility is a separate embodiment. According to some embodiments, a small pad can refer to a pad with a small / fine pitch size (i.e., the distance between each conductive area / line), such as, but not limited to, about 500 μm or less, about 200 μm or less, about 100 μm or less, about 50 μm or less, about 40 μm or less, about 30 μm or less, about 20 μm or less, about 10 μm or less, about 8 μm or less, about 5 μm or less, about 4 μm or less, about 3 μm or less, or about 2.5 μm or less. Each possibility is a separate embodiment.

[0046] According to some embodiments, the intermediary can also be used in integrated circuits, among other things, to provide electrical connectivity between the integrated circuit die and the package / package substrate (such as a ball grid array (BGA) package, a multi-chip module, etc.). According to some embodiments, the intermediary can be integrated into a 3D integrated circuit die stack.

[0047] According to some embodiments, the intermediary may refer to a logic intermediary. According to some embodiments, the intermediary may refer to a logic and memory intermediary. According to some embodiments, the intermediary may refer to an image sensor intermediary, such as a complementary metal-oxide-semiconductor (CMOS) image intermediary. According to some embodiments, the intermediary may refer to a memory stack intermediary. According to some embodiments, the intermediary may refer to a power, RF, analog integrated passive intermediary. Each possibility is a separate embodiment.

[0048] As used herein, the term "coreless" can refer to a substrate-free structure, i.e., an intermediary without an intermediary substrate. According to some embodiments, the term "coreless intermediary" can refer to an intermediary without a core / substrate layer.

[0049] As used herein, the term "package" can refer to any package type that houses one or more semiconductor devices, dies, integrated circuits, memory devices, passive and / or active components, or any combination thereof.

[0050] As used herein, the terms "conductive line" and "conductive material region," "conductive region" and "contact pad," and "conductive pattern" are used interchangeably according to some embodiments and refer to any conductive portion, such as the conductive portion of a coreless intermediary. According to some embodiments, the conductive line may be made of or contain a metal, such as, but not limited to, copper, gold, silver, nickel, etc., or any combination thereof. According to some embodiments, the conductive region is configured to electrically interconnect, wire, and / or rewire integrated circuit devices and / or components such as, but not limited to, microprocessors, memory devices, chipsets, graphics devices, one or more dies, etc., or any combination thereof. According to some embodiments, the conductive line may refer to an electrical trace. Additionally or alternatively, in some embodiments, the conductive line may form a conductive path (vertical electrical connection) between one or more layers of a coreless intermediary, as further described elsewhere herein. According to some embodiments, the conductive line may form various types of vias, such as, but not limited to, through-hole vias, tent vias, blind vias, buried vias, stacked vias, etc., or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, the vias disclosed herein are formed without drilling, compared to conventionally formed vias. According to some embodiments, the vias disclosed herein are formed without etching, compared to conventionally formed vias.

[0051] According to some embodiments, reference is now made to Figure 1A , Figure 1B and Figure 1C , Figure 1A A side view of the interconnect structure 100 is schematically shown. Figure 1B A schematic top view of the interconnect structure 100 is shown, and Figure 1C A top view of each of one or more layers of the interconnect structure 100 is schematically illustrated.

[0052] According to some embodiments, the interconnect structure 100 includes a coreless intermediary 102. According to some embodiments, the coreless intermediary 102 is configured to allow electrical interconnections of packages (e.g., chip packages), modules, systems, etc., or any combination thereof. According to some embodiments, the coreless intermediary 102 can be used to electrically interconnect chip packages to printed circuit boards (PCBs) (such as motherboards, central processing units (CPUs), etc.).

[0053] Advantageously, in some embodiments, the linear / spatial resolution of the coreless intermediary 102 can be at least about 5 / 5 μm. According to some embodiments, the contact pitch (spatial spacing between the nearest vias) of the coreless intermediary 102 can be less than about 5 μm. According to some embodiments, the contact pitch (spatial spacing between the nearest vias) of the coreless intermediary 102 can be less than about 4 μm. According to some embodiments, the contact pitch (spatial spacing between the nearest vias) of the coreless intermediary 102 can be less than about 3 μm. According to some embodiments, the contact pitch (spatial spacing between the nearest vias) of the coreless intermediary 102 can be less than about 2.5 μm.

[0054] According to some embodiments, the coreless intermediary 102 has a substrate-free structure. According to some embodiments, the conductive lines of the coreless intermediary 102 are formed without drilling, etching, or otherwise penetrating them, thereby minimizing / preventing cracking or other deformation, while allowing for increased density and resolution of the conductive lines (and vias formed by the conductive lines, as further described elsewhere herein).

[0055] According to some embodiments, the coreless intermediary 102 is a three-dimensional (3D) intermediary. According to some embodiments, the coreless intermediary 102 may include a plurality of high-density conductive lines defined therein. According to some embodiments, the coreless intermediary 102 may include a plurality of ultra-thin and high-density vertical electrical interconnects formed therein. Advantageously, in some embodiments, the coreless intermediary 102 enables miniaturization of electronic devices while improving interconnects, thereby improving the performance of the electronic devices and reducing power consumption.

[0056] According to some embodiments, the interconnect structure 100 may have an ultrathin structure, for example, a thickness of about 50 μm or less. According to some embodiments, the interconnect structure 100 may have an ultrathin structure, for example, a thickness of about 40 μm or less. According to some embodiments, the interconnect structure 100 may have an ultrathin structure, for example, a thickness of about 30 μm or less. According to some embodiments, the interconnect structure 100 may have an ultrathin structure, for example, a thickness of about 20 μm or less. According to some embodiments, the interconnect structure 100 may have an ultrathin structure, for example, a thickness of about 10 μm or less. According to some embodiments, the interconnect structure 100 may have an ultrathin structure, for example, a thickness ranging from about 5 μm to about 500 μm. Each possibility is a separate embodiment. In some embodiments, the interconnect structure 100 may have any desired thickness (i.e., substantially unlimited height).

[0057] According to some embodiments, the interconnect structure 100 may have a multi-layer structure (e.g., 2, 3, 4, 5, 6, 7 or more layers). Each possibility is a separate embodiment. According to some embodiments, the thickness of each layer may be substantially the same. In some embodiments, each layer may have a different thickness.

[0058] According to some embodiments, interconnect structure 100 is configured to electrically interconnect various types of packages to the PCB, such as, but not limited to, ball grid array (BGA), planar grid array (LGA), multi-chip module (MCM), quad flat no-lead package (QFN), system-in-package (SiP), package-on-package (PoP), fan-out wafer-level package (WLP), or any other type of package.

[0059] According to some embodiments, interconnect structure 100 can be used to electrically connect a single package to a PCB. According to some embodiments, interconnect structure 100 can be used to electrically connect multiple packages to a PCB.

[0060] According to some embodiments, the interconnect structure 100 is configured to electrically interconnect a microprocessor (e.g., a single-core and / or multi-core processor), a microcontroller, a memory chip (such as volatile memory, non-volatile memory, etc.), a logic chip, an integrated circuit, any passive and / or active component or device, or any other electrical component, semiconductor device, etc., or any combination thereof.

[0061] According to some embodiments, the coreless intermediary 102 includes one or more layers. According to some embodiments, each of the one or more layers is stacked on top of a previous layer (bottom layer). According to some embodiments, each of the one or more layers includes an electrically insulating region and a conductive region.

[0062] According to some embodiments, each insulating region is positioned between each conductive region to prevent (horizontal) current flow (i.e., short circuit) between each conductive region in a particular layer of one or more layers. In other words, one or more layers are stacked substantially vertically to form a vertical electrical connection between the insulating regions, thereby allowing vertical current flow through one or more layers according to a predefined pattern / path.

[0063] Advantageously, in some embodiments, the structure of the coreless intermediary 102 allows for the instantaneous formation of vertical electrical connections between electrically insulating materials. According to some embodiments, vertical electrical connections in each of one or more layers can be formed simultaneously. Advantageously, in some embodiments, the vertical electrical connections are formed without drilling. Advantageously, in some embodiments, the vertical electrical connections are formed without etching (e.g., chemical etching). Advantageously, the vertical electrical connections can be formed in any desired pattern and / or height to facilitate the routing of electrical signals. Advantageously, in some embodiments, the aspect ratio of the vertical electrical connections of the coreless intermediary 102 can be substantially infinite / unlimited.

[0064] According to some embodiments, and as Figures 1A-1C As shown, one or more layers of the coreless intermediary 102 may include four layers. According to some embodiments, and as... Figure 1A As shown, the first layer 110 of one or more layers includes a plurality of conductive material regions 110a and a plurality of electrically insulating material regions 110b. According to some embodiments, and as... Figure 1A As shown, each of the second layer 112, the third layer 114, and the fourth layer 116 in one or more layers includes a plurality of conductive material regions 112a, 114a, and 116a and a plurality of electrically insulating material regions 112b, 114b, and 116b, respectively. It is understood that the number of the one or more layers of the coreless intermediary 102 can vary and substantially includes any desired number. According to some embodiments, the number of one or more layers may, among other things, include 3, 4, 5, 6, 7, 8, 9, 10, 15, 20, 25, 30, or more layers. According to some embodiments, there is substantially no upper limit to the number of one or more layers, such as... Figure 2 More detailed descriptions are available in the text.

[0065] According to some embodiments, and as Figures 1A-1C As shown, the plurality of conductive material regions 110a of the first layer 110 may include a plurality of first contact pads configured for electrical interconnection to a PCB. According to some embodiments, the dimensions of each of the plurality of first contact pads may be approximately 100 μm x 100 μm. According to some embodiments, the dimensions of each of the plurality of first contact pads may be in the range of approximately 100-500 μm x 100-500 μm. According to some embodiments, the dimensions of each of the plurality of first contact pads may be in the range of approximately 50-500 μm x 50-500 μm. Each possibility is a separate embodiment.

[0066] According to some embodiments, a plurality of conductive material regions 112a of the second layer 112 may be configured to form a desired pattern and / or size for vertical electrical connections. According to some embodiments, a plurality of conductive material regions 114a of the third layer 114 may optionally include a redistribution layer (RDL) and / or serve as such a redistribution layer, configured to redewire vertical electrical connections to desired locations. According to some embodiments, a plurality of conductive material regions 116a of the fourth layer 116 may include a second plurality of contact pads configured to interconnect the intermediate 102 to the package. According to some embodiments, the dimension of each contact pad in the second plurality of contact pads may be about 10 x 10 μm or less. According to some embodiments, the dimension of each contact pad in the second plurality of contact pads may be about 8 x 8 μm or less. According to some embodiments, the dimension of each contact pad in the second plurality of contact pads may be about 6 x 6 μm or less. According to some embodiments, the dimension of each contact pad in the second plurality of contact pads may be about 5 x 5 μm or less. According to some embodiments, the dimensions of each contact pad in the second plurality of contact pads may be approximately 4 x 4 μm or smaller. According to some embodiments, the dimensions of each contact pad in the second plurality of contact pads may be approximately 2.5 x 2.5 μm or smaller. Each possibility is a separate embodiment.

[0067] According to some embodiments, the lines and / or contact pads in the conductive material region may have a thickness of about 5-7 μm or 3-6 μm. According to some embodiments, the lines and / or pads may have a thickness of less than about 5 μm.

[0068] According to some embodiments, the conductive material regions 110a / 112a / 114a / 116a may include or be in the form of contact pads. According to some embodiments, the form / shape of the conductive material regions 110a / 112a / 114a / 116a may, among other things, include circles, squares, oblongs, rectangles, rounded rectangles, chamfered rectangles, octagons, rings, n-sided polygons, etc. (when viewed from above), or any combination thereof, or may be circles, squares, oblongs, rectangles, rounded rectangles, chamfered rectangles, octagons, rings, n-sided polygons, etc. (when viewed from above), or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, the conductive material regions 110a / 112a / 114a / 116a may include or be in the form of wires.

[0069] According to some embodiments, the vertical electrical connection may, among other things, be a through-hole, a tent-type through-hole, a blind through-hole, a buried through-hole, a stacked through-hole, or any combination thereof, or include through-holes, tent-type through-holes, blind through-holes, buried through-holes, stacked through-holes, or any combination thereof. Each possibility is a separate embodiment.

[0070] According to some embodiments, the coreless intermediary 102 may be flexible. According to some embodiments, the coreless intermediary 102 may be semi-rigid. According to some embodiments, the coreless intermediary 102 may be rigid. Each possibility is a separate embodiment. According to some embodiments, the rigid coreless intermediary may have a Shore D hardness value in the range of about 90D-100D. According to some embodiments, the rigid coreless intermediary may have a Shore D hardness value in the range of about 85D-96D. According to some embodiments, the flexible coreless intermediary may have a Shore D hardness value in the range of about 55D-75D. According to some embodiments, the flexible coreless intermediary may have a Shore D hardness value in the range of about 60D-70D. According to some embodiments, the semi-rigid coreless intermediary may have a combination of the Shore D hardness values ​​of rigid and flexible coreless intermediaries, i.e., it may include a combination of the rigid Shore D hardness values ​​and the flexible Shore D hardness values ​​of the coreless intermediary. As a non-limiting example, a semi-flexible coreless mediator may have regions with a Shore D hardness of about 96D and regions with a Shore D hardness of about 65D. Alternatively, in some embodiments, a semi-rigid coreless mediator may have a substantially uniform hardness, such as, but not limited to, a Shore D hardness value in the range of about 65D to 85D.

[0071] refer to Figure 2 , Figure 2 This is a flowchart 200 of a method for manufacturing interconnect structures such as coreless intermediaries according to some embodiments.

[0072] According to some embodiments, at step 202, the method may include forming one or more conductive regions. According to some embodiments, the one or more conductive regions may include one or more conductive lines, or take the form of one or more conductive lines. According to some embodiments, the one or more conductive regions may include contact pads, or take the form of contact pads. According to some embodiments, the one or more conductive regions may be configured to form vias. According to some embodiments, the one or more conductive regions may be formed according to a predefined pattern.

[0073] According to some embodiments, one or more conductive regions may be made of or contain metal. According to some embodiments, one or more conductive regions may contain copper, gold, silver, etc. Each possibility is a separate embodiment. According to some embodiments, each of the one or more layers of the intermediary may be made of or contain different materials. According to some embodiments, each of the one or more layers of the intermediary may be made of or contain the same material (e.g., made of or containing the same metal in each of the one or more layers).

[0074] According to some embodiments, one or more conductive regions may be made of or contain a mixture of conductive materials. According to some embodiments, one or more conductive wires may be made of or contain a mixture of metals.

[0075] According to some embodiments, at step 202, the method may include forming one or more conductive regions on a temporary carrier substrate. According to some embodiments, the temporary carrier substrate may be made of an inert material, such as, but not limited to, glass, stainless steel, SiC, AlN, polyimide, polyimide on glass, etc. According to some embodiments, the temporary carrier substrate may be rigid, semi-rigid, or flexible. Each possibility is a separate embodiment.

[0076] According to some embodiments, one or more conductive regions can be formed by implementing an additive manufacturing method (step 202a), such as, but not limited to, selective laser sintering. Figure 3 As described in the text.

[0077] According to some embodiments, one or more conductive regions can be formed by implementing a semi-additive manufacturing method (step 202b), such as, but not limited to, photolithography and / or electroplating, as... Figure 4 and Figure 5 This is further elaborated upon in the text.

[0078] According to some embodiments, at step 204, the method may include filling one or more gaps between one or more conductive regions with an electrically insulating material. According to some embodiments, filling may include casting / spreading the electrically insulating material over the one or more conductive regions and the one or more gaps between them.

[0079] According to some embodiments, the electrical insulating material may include a dielectric material. According to some embodiments, the electrical insulating material may include one or more polymers. According to some embodiments, the electrical insulating material may be made of or contain polyimide. According to some embodiments, the electrical insulating material may be photosensitive. As a non-limiting example, the electrical insulating material may be made of or contain photodefinable epoxy. According to some embodiments, the electrical insulating material may be non-photosensitive. According to some embodiments, the electrical insulating material may include a thickness-to-diameter ratio of at least about 5:1. According to some embodiments, the thickness of the electrical insulating material layer is in the range of about 5-30 μm. According to some embodiments, the electrical insulating material has a coefficient of thermal expansion (CTE) of about 15-20 ppm / °C.

[0080] According to some embodiments, the thermal conductivity (CTE) of the conductive region can be substantially matched with the CTE of the electrical insulating material, thereby facilitating thermal management and dissipating heat generated by the electronic device. Those skilled in the art will understand that insufficient heat transfer leads to performance degradation of the electronic device or its components. Furthermore, thermal expansion mismatch can cause increased mechanical stress, which in turn can also lead to performance degradation.

[0081] According to some embodiments, each of one or more layers of the coreless intermediary may be made of or contain different electrical insulating materials. According to some embodiments, each of one or more layers of the coreless intermediary may be made of or contain the same electrical insulating material.

[0082] According to some embodiments, at step 206, the method may optionally include heat treatment, curing, and / or polymerization of an electrically insulating material that fills one or more gaps between one or more conductive regions.

[0083] According to some embodiments, at step 208, the method may include removing excess electrical insulating material to obtain a first layer of one or more layers of an interconnect structure.

[0084] According to some embodiments, removing / scraping excess electrical insulation material may include planarizing using a surface planer / machine to form a substantially flat surface of the first layer (and / or each of one or more additional layers) of the interconnect structure. According to some embodiments, excess electrical insulation material may be removed until a portion of the conductive material region (e.g., the surface or top layer of the conductive material region) is exposed.

[0085] According to some embodiments, at step 210, the method may include repeating the above steps (e.g., steps 202-208) to produce one or more additional layers of the interconnect structure. In other words, the above steps may be repeated until the desired number of one or more layers are obtained (e.g., until the desired height / depth of the vertical electrical connection is reached).

[0086] According to some embodiments, the repetitive operation may include aligning conductive regions of a previous / bottom layer in one or more layers with additional layers in one or more layers of the interconnect structure. According to some embodiments, the alignment may be performed based on a reference / marker of the previous / bottom layer. According to some embodiments, the alignment between conductive regions of each layer in one or more layers may be about 1 μm or less. According to some embodiments, the alignment between conductive regions of each layer in one or more layers may be about 0.5 μm or less. Each possibility is a separate embodiment. In some embodiments, the methods disclosed herein allow for the fabrication of coreless interposers with mismatch losses of less than about 10% or less than about 5%.

[0087] According to some embodiments, the method may optionally include step 212 of removing temporary carriers from the interconnect structure.

[0088] According to some embodiments, the method may optionally include performing electrical measurements during and / or after the fabrication of the interconnect structure to test / verify at least a portion of one or more layers (steps not shown).

[0089] According to some embodiments, the method provides "instantaneous" formation of vertical electrical connections between electrically insulating materials.

[0090] In some embodiments, the methods disclosed herein do not involve any drilling steps. In some embodiments, the methods do not involve mechanical drilling and / or laser drilling. Advantageously, compared to methods involving through-hole drilling (which are prone to causing cracking of the medium or parts thereof), the methods disclosed herein are therefore not limited by the aspect ratio of the height to the diameter of the through-hole. In other words, in some embodiments, the aspect ratio can be essentially infinite.

[0091] Advantageously, since there are no height and diameter aspect ratio limitations, in some embodiments there is virtually no upper limit to the number of one or more layers stacked on top of each other, thereby allowing vertical electrical connections (e.g., through holes) to be formed between electrically insulating materials with virtually no height / depth limitations.

[0092] According to some embodiments, the predefined pattern of each of one or more layers can be different. According to some embodiments, complex and high-density patterns can be obtained regardless of the number of one or more layers of the coreless interposer. Advantageously, in some embodiments, the methods disclosed herein combine additive manufacturing techniques for producing coreless interposer interconnect structures, such that the interposer is produced via a semi-additive method or via an additive method (e.g., a full-additive method). Therefore, in some embodiments, a wide range of patterns (e.g., interconnect schemes) and via architectures are allowed to achieve the desired signal routing, signal integrity, and power delivery, while also facilitating thermal management. In some embodiments, complex patterns of vertical electrical connections can be substantially achieved without reducing or limiting the resolution of the interposer (i.e., the density of conductive regions). According to some embodiments, the line / spatial resolution of the interconnect structure can be at least about 5 / 5 μm.

[0093] In some embodiments, coreless mediators manufactured according to the methods disclosed herein are compatible with military standard testing involving 1,000 cycles from -45°C to +145°C. In some embodiments, coreless mediators manufactured according to the methods disclosed herein are compatible with Joint Electronic Devices Engineering Committee (JEDEC) standards, including testing involving 1,000 cycles from -25°C to +125°C.

[0094] In some embodiments, the methods disclosed herein allow the fabrication of coreless interposers with mismatch losses of less than about 10% or less than about 5%. In some embodiments, the methods disclosed herein allow the fabrication of coreless interposers with conductive material thickness variations of less than about 1 μm or less than about 0.5 μm. In some embodiments, the methods disclosed herein allow the fabrication of interlayer contact resistivity of less than about 1 x 10⁻⁶. -6 ohm / cm 2 Coreless intermediary.

[0095] refer to Figure 3 It schematically illustrates, according to some embodiments, a method for forming conductive regions (i.e., Figure 2 An example of the addition manufacturing method 302a in step 202a) is provided. According to some embodiments, the addition manufacturing method may, among others, include selective laser sintering (SLS) methods, such as, but not limited to, direct SLS, direct metal laser sintering (DMLS), selective laser melting (SLM), wire metal 3D printing, or any other addition manufacturing method. According to some embodiments, the addition manufacturing method may include any type of directional energy deposition method, powder-based melt addition manufacturing method, etc., or any combination thereof. According to some embodiments, the addition manufacturing method may include a micro-metal addition manufacturing (MMAM) method. Each possibility is a separate embodiment.

[0096] According to some embodiments, at step 302a-1, the addition manufacturing method may include cleaning the carrier 304. According to some embodiments, the carrier 304 may be a temporary carrier. Alternatively, in some embodiments, the carrier may be a non-temporary carrier.

[0097] According to some embodiments, the cleaning carrier 304 may include performing plasma surface treatment. According to some embodiments, the plasma surface treatment may be performed using atmospheric plasma. According to some embodiments, the cleaning carrier 304 may include chemical etching (i.e., wet or dry etching) of the carrier's surface. According to some embodiments, the cleaning carrier 304 may include dry etching of the carrier's surface. According to some embodiments, the cleaning carrier 304 may include ultrasonic cleaning. According to some embodiments, the cleaning carrier 304 may include ozone treatment of the carrier's surface. According to some embodiments, the cleaning carrier 304 may include any combination of the above-described cleaning methods, or any other surface treatment / cleaning.

[0098] According to some embodiments, at step 302a-2, the addition manufacturing method may include coating the surface of the carrier 304 with a conductive material. According to some embodiments, the conductive material may be made of or contain one or more metals. According to some embodiments, the conductive material may contain copper. According to some embodiments, the conductive material may contain gold, silver, etc.

[0099] According to some embodiments, at steps 302a-2, the addition manufacturing method may include spreading / coating a carrier 304 with an ink coating 308 (such as, but not limited to, a copper ink coating). According to some embodiments, the ink coating 308 may include a structural powder (i.e., a high-melting-point powder, such as a metal) and a binder / solvent (i.e., a powder with a melting point lower than the structural powder). In other words, in some embodiments, the ink coating 308 may be made from or contain a mixture of two or more powders. According to some embodiments, the ink coating 308 may contain a mixture of conductive materials (e.g., a mixture of metals). Those skilled in the art will understand that different binders and / or solvents produce metallic inks with different viscosities, thereby affecting their filling capacity. According to some embodiments, the solvent may, among others, include water, ethylene glycol, diethylene glycol monomethyl ether, etc. Each possibility is a separate embodiment.

[0100] According to some embodiments, coating the carrier 304 with a conductive material can, among other things, be performed by an ink spraying machine, a slot die coating machine, an ultrasonic rotary spraying machine, or any combination thereof. According to some embodiments, coating the carrier 304 may include blade coating to facilitate the formation of a well-defined coating thickness.

[0101] According to some embodiments, step 302a-2 may include drying the ink coating 308. According to some embodiments, drying may, among other things, be performed by a blower, an oven, or the like.

[0102] According to some embodiments, at steps 302a-3, addition fabrication may include performing selective laser sintering to form conductive regions 310a according to a predefined pattern. According to some embodiments, selective laser sintering may be performed using a direct laser writer.

[0103] According to some embodiments, at steps 302a-4, the addition manufacturing method may include cleaning or otherwise removing unsintered material (e.g., unsintered copper ink) to obtain a pattern of conductive regions 310a. According to some embodiments, the pattern may include conductive lines having desired width, length, and spacing, as substantially disclosed herein.

[0104] According to some embodiments, method 302a may not include the material reduction step.

[0105] refer to Figure 4 It schematically illustrates, according to some embodiments, a method for forming conductive regions (i.e., Figure 2 An example of the semi-additive manufacturing method 402b in step 202a).

[0106] According to some embodiments, the semi-additive method may be based on or include a lithography fabrication method. According to some embodiments, the lithography method may, among others, include a maskless lithography method. According to some embodiments, lithography may, among others, include X-ray, electron beam, and / or optical lithography (i.e., photolithography), etc. Each possibility is a separate embodiment. According to some embodiments, lithography may, among others, include nanolithography, plasma-assisted lithography, laser interferometry lithography, nanosphere lithography, etc. Each possibility is a separate embodiment.

[0107] According to some embodiments, the semi-additive manufacturing method 402b may include photolithography.

[0108] According to some embodiments, at step 404b-1, the semi-addition method may include cleaning the carrier 404. According to some embodiments, cleaning the carrier 404 may include performing a plasma surface treatment. According to some embodiments, the plasma surface treatment may be performed using atmospheric plasma. According to some embodiments, cleaning may include chemical etching (i.e., wet etching) of the surface of the carrier 404. According to some embodiments, carrier cleaning may include dry etching of the surface of the carrier 404. According to some embodiments, carrier cleaning may include ultrasonic cleaning (e.g., in different solutions such as acetone, methanol, etc.). According to some embodiments, carrier cleaning may include ozone treatment of the surface of the carrier 404. According to some embodiments, carrier cleaning may include any combination of the above-described cleaning methods, or any other surface treatment / cleaning.

[0109] According to some embodiments, at step 402b-2, the semi-addition method may include applying a radiation-sensitive compound onto the carrier 404. According to some embodiments, the radiation-sensitive compound may include a resist, such as a positive resist (i.e., the pattern formed in the positive resist is the same as the pattern on the mask) or a negative resist (i.e., the pattern formed is opposite to the mask pattern). According to some embodiments, the resist may include a photoresist 408.

[0110] According to some embodiments, carrier 404 may be held in a rotary sprayer for applying / spreading photoresist thereon. According to some embodiments, carrier 404 may be positioned on a vacuum spindle for applying / spreading photoresist 408 thereon. According to some embodiments, carrier 404 may be rotated (e.g., for about 15 seconds, about 30 seconds, about 60 seconds, etc.) to facilitate obtaining a uniform photoresist 408 coating. According to some embodiments, carrier 404 may optionally undergo a pre-patterning heat treatment (e.g., soft baking) to remove solvents from the photoresist 408 and / or enhance adhesion to carrier 404.

[0111] According to some embodiments, at step 402b-3, the semi-additive method may include pattern transfer. According to some embodiments, step 402b-3 may be performed in a cleanroom illuminated with yellow light. According to some embodiments, step 402b-3 may include exposing photoresist 408 to radiation (such as ultraviolet radiation) to transfer the desired pattern.

[0112] According to some embodiments, after pattern transfer is completed, the photoresist 408 can be removed from the unpatterned portions, thereby forming a pattern of one or more insulating regions 410b on the carrier 404. According to some embodiments, a developer solution (e.g., a metal ion-free developer solution) can be used to remove the unexposed portions of the negative photoresist and the exposed portions of the positive photoresist 408.

[0113] According to some embodiments, steps 402b-3 may include performing post-exposure baking before developing the pattern of one or more insulating regions 410b on the carrier 404.

[0114] According to some embodiments, steps 402b-3 may include performing hard baking on one or more insulating regions 410b to help cure the pattern of one or more insulating regions 410b.

[0115] According to some embodiments, step 402b-3 may include removing photoresist residue.

[0116] According to some embodiments, at steps 402b-4, the semi-additive method may include applying a conductive material between one or more gaps between one or more insulating regions 410b. According to some embodiments, the conductive material may be applied by electroplating (e.g., copper plating).

[0117] According to some embodiments, one or more gaps between one or more insulating regions 410b define the area and dimension of the conductive material on the carrier (i.e., conductive regions 410a, such as lines, pads, vias, etc.). As a non-limiting example, in a semi-additive method, the resolution of the conductive lines of the interconnect structure is defined by the resolution of the photoresist pattern obtained by a photolithography method (i.e., the smallest dimension of the resist that can be accurately transferred to the carrier).

[0118] According to some embodiments, at steps 402b-6, the semi-additive method may optionally include removing one or more insulating regions 410b. According to some embodiments, removing the photoresist may include any suitable removal method, such as wet and / or dry etching, stripping, cleaning, etc., or any combination thereof.

[0119] refer to Figure 5 It schematically illustrates, according to some embodiments, a method for obtaining conductive regions (i.e., Figure 2 An example of the semi-additive manufacturing method 502b in step 202b).

[0120] According to some embodiments, the semi-addition method 502b may be based on or include a lithography method. According to some embodiments, the lithography method may, among others, include a maskless lithography method. According to some embodiments, the lithography method may, among others, include X-ray, electron beam, and / or optical lithography (i.e., photolithography), etc. Each possibility is a separate embodiment. According to some embodiments, the lithography may, among others, include nanolithography, plasma-assisted lithography, laser interference lithography, nanosphere lithography, etc. Each possibility is a separate embodiment.

[0121] According to some embodiments, the semi-addition method 502b may include photolithography.

[0122] According to some embodiments, at step 502b-1, the semi-additive method may include providing / obtaining a carrier substrate 504. According to some embodiments, the carrier 504 may be a temporary carrier.

[0123] According to some embodiments, step 502b-1 may include cleaning the carrier 504. According to some embodiments, carrier cleaning may include performing plasma surface treatment. According to some embodiments, carrier cleaning may include chemical etching (i.e., wet etching) of the surface of the carrier 504. According to some embodiments, carrier cleaning may include dry etching of the surface of the carrier 504. According to some embodiments, carrier cleaning may include ultrasonic cleaning. According to some embodiments, carrier cleaning may include ozone treatment, plasma treatment, etc., of the surface of the carrier. According to some embodiments, carrier cleaning may include any combination of the above cleaning methods, or any other suitable surface treatment / cleaning.

[0124] According to some embodiments, at step 502b-2, the semi-addition method may include forming a seed layer 506 on the carrier 504. According to some embodiments, the seed layer 506 may be made of or contain one or more metals. According to some embodiments, the seed layer 506 may contain TiW and Cu.

[0125] According to some embodiments, the seed layer 506 can be formed by a metallization process. According to some embodiments, the seed layer 506 can be formed by a physical vapor deposition (PVD) method, such as sputtering or thermal evaporation. According to some embodiments, the seed layer 506 can be formed by a chemical vapor deposition (CVD) method, such as atomic layer deposition (ALD). Each possibility is a separate embodiment.

[0126] According to some embodiments, at steps 502b-3, the semi-addition method may include applying a radiation-sensitive compound onto the seed layer 506. According to some embodiments, the radiation-sensitive compound may include a resist, such as a positive resist (i.e., the pattern formed in the positive resist is the same as the pattern on the mask) or a negative resist (i.e., the pattern formed is opposite to the mask pattern). According to some embodiments, the resist may include a photoresist 508.

[0127] According to some embodiments, the carrier 504 may be positioned on a vacuum spindle during the application of the photoresist. According to some embodiments, the carrier 504 may then be rotated (e.g., for about 15 seconds, about 30 seconds, about 60 seconds, etc.) to facilitate a uniform coating of the photoresist 506. According to some embodiments, the coated carrier 504 may optionally undergo a pre-patterning heat treatment (e.g., baking) to remove solvents from the photoresist 508 and / or enhance the adhesion of the photoresist 508 to the seed layer 506.

[0128] According to some embodiments, at step 502b-4, the semi-additive method may include photoresist irradiation and development (pattern transfer). According to some embodiments, step 502b-4 may be performed in a cleanroom using yellow light illumination. According to some embodiments, step 502b-4 may include applying radiation (such as ultraviolet radiation) to transfer the desired pattern to photoresist 508, thereby forming one or more electrically insulating regions 510b (i.e., photoresist pattern 510b).

[0129] According to some embodiments, after pattern transfer is completed, the photoresist 508 can be removed from the unpatterned portions, thereby exposing the pattern of one or more electrically insulating regions 510 formed on the seed layer 506. According to some embodiments, the unpatterned photoresist can be removed by cleaning, acoustic treatment, etching and / or solution rinsing, plasma oxidation, etc., or any combination thereof.

[0130] According to some embodiments, after the pattern is developed on the carrier 504, a second heat treatment (e.g., post-baking) may optionally be performed. According to some embodiments, the carrier 504 and the developed pattern may be dried in the ambient environment.

[0131] According to some embodiments, at steps 502b-5, the semi-additive method may include filling one or more gaps between electrically insulating material regions 510b with a conductive material to form one or more conductive regions 510a. According to some embodiments, the one or more conductive regions 510a may be formed by electroplating. As a non-limiting example, steps 504b-5 may include copper electroplating.

[0132] According to some embodiments, at steps 502b-6, the semi-addition method may include removing the photoresist pattern 510b. According to some embodiments, the photoresist pattern 510b can be removed using wet chemical techniques. According to some embodiments, the photoresist pattern 510b can be removed using AZ 100 remover. According to some embodiments, the photoresist pattern 510b can be removed using AZ 920 remover. According to some embodiments, the photoresist pattern 510b can be removed using 1-methyl-2-pyrrolidone (NMP) remover. According to some embodiments, the photoresist pattern 510b can be removed using dimethyl sulfoxide (DMSO) (e.g., by ultrasonic cleaning).

[0133] According to some embodiments, at steps 502b-7, the semi-addition method may include removing seed layer 506 residue between one or more conductive regions 510a to prevent horizontal current flow between each of the one or more conductive regions 510a through each of the one or more layers of the interconnect structure, thereby allowing vertical current flow (i.e., between each of the one or more layers without a core medium).

[0134] According to some embodiments, the residue of seed layer 506 can be removed by etching or any other suitable removal technique.

[0135] refer to Figure 6 The illustration schematically depicts an example of a method 600 for producing a coreless intermediary according to some embodiments.

[0136] According to some embodiments, at step 602, the method may include forming a seed layer 601 on a carrier 603. According to some embodiments, step 602 may include sputtering one or more metals to obtain the seed layer 601.

[0137] According to some embodiments, at step 604, the method may include applying a photoresist 605 onto a carrier 603. According to some embodiments, the photoresist 605 may be applied using a rotary sprayer to facilitate a homogeneous coating of the photoresist 605. According to some embodiments, the coated carrier 603 may optionally be soft-baked to remove solvent from the photoresist 605 and / or enhance adhesion to the carrier 603.

[0138] According to some embodiments, at step 606, the method may include irradiation and development of the photoresist 605 (i.e., pattern transfer). According to some embodiments, after pattern transfer is completed, the photoresist 605 may be removed from its unexposed portions by, for example, washing, rinsing, and / or using a developer solution. According to some embodiments, step 606 may optionally include post-exposure baking before developing the photoresist pattern 607. According to some embodiments, step 606 may optionally include hard baking the photoresist pattern 607 to facilitate its curing. According to some embodiments, step 606 may optionally include removing any residue of the photoresist 605.

[0139] According to some embodiments, at step 608, the method may include applying a conductive material between one or more gaps in the photoresist pattern 607. According to some embodiments, the conductive material may be applied by electroplating (e.g., copper plating) to form one or more conductive regions 609.

[0140] According to some embodiments, at step 610, the method may include removing the photoresist pattern 607, for example, by rinsing, wet and / or dry etching, cleaning, or any combination thereof.

[0141] According to some embodiments, at step 612, the method may include removing seed layer 601 residues between one or more conductive regions 609.

[0142] According to some embodiments, at step 614, the method may include filling one or more gaps between one or more conductive regions with an electrically insulating material 611.

[0143] According to some embodiments, at step 616, the method may include heat-treating, curing, and / or polymerizing the electrically insulating material 611 that fills one or more gaps.

[0144] According to some embodiments, at step 618, the method may include removing excess electrical insulating material 611 to obtain a first layer of one or more layers of a coreless intermediary.

[0145] According to some embodiments, each of steps 620, 622, 624, 626, 628, 630, 632, 634 and 636 may be similar to or the same as each of steps 602, 604, 606, 608, 610, 612, 614, 616 and 618, thereby obtaining a second layer of one or more layers of a coreless intermediary.

[0146] According to some embodiments, each of steps 638, 640, 642, 644, 646, 648, 650, 652 and 654 may be similar to or the same as each of steps 602, 604, 606, 608, 610, 612, 614, 616 and 618, thereby obtaining a third layer of one or more layers of a coreless intermediary.

[0147] Similarly, according to some embodiments, each of steps 656, 658, 660, 662, 664, 666, 668, 670, and 672 may be similar to or identical to each of steps 602, 604, 606, 608, 610, 612, 614, 616, and 618, thereby obtaining a fourth layer of one or more layers of a coreless intermediary. Those skilled in the art will understand that the disclosed method allows for the manufacture of coreless intermediaries having any desired number of one or more layers.

[0148] According to some embodiments, the photoresist pattern 607 of each of the first, second, third, and fourth layers can be different.

[0149] According to some embodiments, at step 674, the method may include removing the carrier from the coreless intermediary.

[0150] Example

[0151] Example 1

[0152] According to some embodiments, a coreless intermediary 700 has been experimentally prepared by using copper to form one or more conductive lines and SU-8 (Gersteltec's GLM2060 SU8) to form one or more electrically insulating regions.

[0153] Figure 7 A cross-sectional side view of a coreless intermediate 700 manufactured according to the process disclosed herein (specifically using the semi-addition scheme disclosed herein) is shown, obtained by high-resolution scanning electron microscopy (HR-SEM) using a focused ion beam (FIB) in a dual-beam tool.

[0154] like Figure 7 As shown, the coreless intermediary 700 has four layers. The first layer 710 includes multiple conductive lines 710a and multiple electrically insulating material regions 710b. Figure 7 As shown, each of the second layer 712, the third layer 714, and the fourth layer 716 of one or more layers of the coreless intermediary 700 includes a plurality of conductive lines 712a, 714a, and 716a and a plurality of electrically insulating material regions 712b, 714b, and 716b.

[0155] like Figure 7As shown, the thickness of each of the multiple conductive lines 710a, 712a, and 714a is substantially uniform and approximately 5 μm. The thickness of the conductive line 716a in the fourth layer 716 is approximately 7 μm.

[0156] It should be recognized that certain features of this disclosure described in the context of individual embodiments for clarity may also be provided in combination in a single embodiment. Conversely, certain features of this disclosure described in the context of a single embodiment for brevity may also be provided individually, or in any suitable sub-combination, or in a suitable manner in any other embodiment of this disclosure. Any feature described in the context of an embodiment is not to be considered an essential feature of that embodiment unless so explicitly stated.

[0157] While the various stages of a method according to some embodiments may be described in a particular order, the methods of this disclosure may include some or all of the stages performed in a different order. In particular, it should be understood that the order of stages and sub-stages of any of the methods may be reordered unless the context explicitly specifies otherwise, for example, when a subsequent stage requires the output of a previous stage as input, or when subsequent stages require the product of a previous stage. The methods of this disclosure may include several or all of the stages described. No particular stage of the disclosed methods is considered a necessary stage of the method unless so explicitly stated.

[0158] While this disclosure has been described in conjunction with specific embodiments thereof, it will be apparent to those skilled in the art that various alternatives, modifications, and variations exist. Accordingly, this disclosure covers all such alternatives, modifications, and variations that fall within the scope of the appended claims. It should be understood that the application of this disclosure is not necessarily limited to the details of the arrangement and construction of the components and / or methods set forth herein. Other embodiments may be practiced and may be implemented in various ways.

[0159] The wording and terminology used herein are for descriptive purposes and should not be construed as limiting. Any references cited or indicated in this application should not be construed as an admission that such reference is prior art to this disclosure. Section headings used herein are intended to aid in understanding this specification and should not be construed as necessarily limiting.

Claims

1. A method for manufacturing a system-in-package interconnect structure, the interconnect structure being configured to electrically connect / couple one or more integrated circuit packages / semiconductor dies to a circuit board, the method comprising: Form one or more conductive lines; One or more gaps between the one or more conductive wires are filled with an electrically insulating material; Excess electrical insulating material is removed to obtain the first layer of the interconnect structure; Repeat the above steps to produce one or more additional layers of the interconnect structure, wherein the additional one or more layers are stacked on top of the first layer, thereby enabling the instantaneous formation of vertical electrical connections between conductive lines / patterns.

2. The method of claim 1, wherein the one or more conductive lines are formed by photolithography.

3. The method of claim 2, wherein the photolithography comprises: Seed layer formed; Apply a resist to the seed layer; Irradiation and development of the photoresist; Fill one or more gaps between the developed resist with a conductive material; Remove the resist after development; as well as Remove any residue from the seed layer to form one or more conductive lines of conductive material.

4. The method of claim 1, wherein the one or more conductive lines are formed by selective laser sintering.

5. The method of any one of claims 1-4, wherein removing excess electrical insulating material comprises planarizing using a surface planer tool / machine to form a substantially flat surface of the first layer and / or the additional one or more layers of the interconnect structure.

6. The method of any one of claims 1-5, wherein excess electrical insulating material is removed until a portion of the first layer and / or the additional one or more layers of the interconnect structure is exposed.

7. The method according to any one of claims 1-6, wherein the method does not include a drilling step.

8. The method of claim 7, wherein the aspect ratio of the vertical electrical connection is substantially unrestricted.

9. The method of any one of claims 1-8, wherein the method comprises curing and / or baking the electrical insulating material.

10. The method of any one of claims 1-9, wherein filling the one or more gaps comprises casting / spreading an electrical insulating material over the one or more conductive wires and the gaps between the one or more conductive wires.

11. The method according to any one of claims 1-10, wherein the electrically insulating material is a dielectric.

12. The method of claim 11, wherein the electrical insulating material comprises one or more polymers.

13. The method of any one of claims 1-12, wherein the line / space resolution of the interconnecting conductive lines is at least about 5 / 5 μm.

14. The method of any one of claims 1-13, wherein the method comprises forming at least a first layer of the interconnect structure on a temporary carrier.

15. The method of claim 14, further comprising removing the temporary carrier.

16. The method of any one of claims 1-15, wherein the vertical electrical connection comprises a vertical electrical connection through the chip.

17. The method of any one of claims 1-16, wherein the interconnect structure is configured to allow electrical coupling between conductive pads of about 100 x 100 μm in size and conductive pads of about 5 x 5 μm or smaller in size.

18. A coreless interposer interconnect structure, the interposer comprising one or more layers, each of the one or more layers comprising: One or more conductive lines configured to allow electrical signals to pass through, the one or more conductive lines being arranged in a predefined pattern; An electrical insulating material is configured to fill the gaps between each of the one or more conductive wires. Each of the one or more layers is stacked substantially vertically, thereby enabling the instantaneous formation of a vertical electrical connection between the conductive lines.

19. The coreless intermediary of claim 18, wherein each of the one or more layers has a different predefined pattern.

20. The coreless intermediary as claimed in any one of claims 18-19, wherein the electrical insulating material comprises a photodefinable epoxy resin.

21. The coreless intermediary as described in any one of claims 18-20, wherein the aspect ratio of the vertical electrical connection is substantially infinite.

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